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76 //******************************************************************************
77 //<MStar Software>
78 /******************************************************************************
79 Copyright (c) 2005 MStar Semiconductor, Inc.
80 All rights reserved.
81
82 [Module Name]: MsMcu.c
83 [Date]: 17-Aug-2005
84 [Comment]:
85 Mcu control subroutines.
86 [Reversion History]:
87 *******************************************************************************/
88 #define _MSMCU_C_
89
90 #include "mdrv_mfc_platform.h"
91 #include "mdrv_mfc.h"
92 #include "mdrv_mfc_mcu.h"
93 #include "mdrv_mfc_fb.h"
94
95
96 #if(CODESIZE_SEL == CODESIZE_ALL)
97 #if (WATCH_DOG_TIMER)
MDrv_MFC_McuWatchDogInit(U8 u8Sec)98 void MDrv_MFC_McuWatchDogInit(U8 u8Sec)
99 {
100 U16 u16Value;
101
102 u16Value = 65536-(MCU_XTAL_CLK_HZ/65536)*u8Sec;
103 MDrv_MFC_Write2Bytes(0x3C62, u16Value);
104 }
105
MDrv_MFC_McuWatchDogClear(void)106 void MDrv_MFC_McuWatchDogClear(void)
107 {
108 MDrv_MFC_WriteBit(0x3C66, 1, _BIT1); // XD_MCU1[0xC0] = 0;
109 }
110 #endif
111
MDrv_MFC_McuWatchDogCtrl(BOOL bEnable)112 void MDrv_MFC_McuWatchDogCtrl(BOOL bEnable)
113 {
114 if (bEnable)
115 {
116 MDrv_MFC_WriteByte(0x3C60, 0xaa);
117 MDrv_MFC_WriteByte(0x3C61, 0x55);
118 }
119 else // disable watch dog
120 {
121 MDrv_MFC_WriteByte(0x3C60, 0x55);
122 MDrv_MFC_WriteByte(0x3C61, 0xaa);
123 }
124 }
125
MDrv_MFC_McuICacheCtrl(BOOL bEnable)126 void MDrv_MFC_McuICacheCtrl(BOOL bEnable)
127 {
128 if (bEnable)
129 {
130 MDrv_MFC_WriteBit(0x1018, 1, _BIT3);
131 MDrv_MFC_WriteBit(0x2BA0, 0, _BIT0);
132 }
133 else
134 {
135 MDrv_MFC_WriteBit(0x1018, 0, _BIT3);
136 MDrv_MFC_WriteBit(0x2BA0, 1, _BIT0);
137 }
138 }
139
140 #if (ISR_EXT_TIMER0_INT)
MDrv_MFC_McuExtTimer0_Init(void)141 void MDrv_MFC_McuExtTimer0_Init(void)
142 {
143 // 1Hz interrupt
144 MDrv_MFC_WriteByte(0x3C80, (U8)MCU_XTAL_CLK_HZ);
145 MDrv_MFC_WriteByte(0x3C81, (U8)MCU_XTAL_CLK_HZ>>8);
146 MDrv_MFC_WriteByte(0x3C82, (U8)MCU_XTAL_CLK_HZ>>16);
147 MDrv_MFC_WriteByte(0x3C83, (U8)MCU_XTAL_CLK_HZ>>24);
148
149 MDrv_MFC_WriteByte(0x3C89, 0x03);
150 MDrv_MFC_WriteByteMask(0x2B00, 0, _BIT0); // int mask 0.0 ex_timer0
151 }
152
153 #endif
154
155 #if (ISR_EXT_TIMER1_INT)
MDrv_MFC_McuExtTimer1_Init(void)156 void MDrv_MFC_McuExtTimer1_Init(void)
157 {
158 // 1KHz interrupt
159 MDrv_MFC_WriteByte(0x3CA0, (U8)MCU_XTAL_CLK_KHZ);
160 MDrv_MFC_WriteByte(0x3CA1, (U8)MCU_XTAL_CLK_KHZ>>8);
161 MDrv_MFC_WriteByte(0x3CA2, (U8)MCU_XTAL_CLK_KHZ>>16);
162 MDrv_MFC_WriteByte(0x3CA3, (U8)MCU_XTAL_CLK_KHZ>>24);
163
164 MDrv_MFC_WriteByte(0x3CA9, 0x03);
165 MDrv_MFC_WriteByteMask(0x2B00, 0, _BIT1); // int mask 0.1 ex_timer1
166 }
167 #endif
168
MDrv_MFC_McuUsePLL(BOOL bEnable)169 void MDrv_MFC_McuUsePLL(BOOL bEnable)
170 {
171 MDrv_MFC_WriteBit(0x1E06, bEnable, _BIT5); // [0]
172 }
173
174
MDrv_MFC_SetMcuSpeed(U8 u8Speed)175 void MDrv_MFC_SetMcuSpeed(U8 u8Speed)
176 {
177 BOOL bPLLEnable;
178
179 if(u8Speed>4)
180 bPLLEnable = 0;
181 else
182 bPLLEnable = 1;
183
184 MDrv_MFC_McuUsePLL(_DISABLE); // MCU use Crystal clock
185 if(bPLLEnable)
186 {
187 MDrv_MFC_WriteByteMask(0x1E06, u8Speed<<2, (_BIT4|_BIT3|_BIT2));
188 MDrv_MFC_McuUsePLL(_ENABLE); // MCU use PLL clock
189 }
190 else
191 {
192 MDrv_MFC_WriteByteMask(0x1E06, (_BIT4|_BIT3|_BIT2), (_BIT4|_BIT3|_BIT2));
193 }
194
195 MDrv_MFC_WriteByteMask(0x2c48, u8Speed, 0x0f);
196 }
197
MDrv_MFC_SetInterrupt(BOOL bCtrl)198 void MDrv_MFC_SetInterrupt(BOOL bCtrl)
199 {
200 if (bCtrl) //Enable
201 {
202 MDrv_MFC_WriteBit(0x2401, 0, _BIT0); // Vsync change irq
203 MDrv_MFC_WriteBit(0x2406, 0, _BIT1); // OP Vsync irq
204 MDrv_MFC_WriteBit(0x2406, 0, _BIT3); // end of DE irq
205 }
206 else
207 {
208 //MDrv_MFC_WriteByte(0x2400, 0xFF); //mask int0.0~7
209 //MDrv_MFC_WriteByte(0x2401, 0xFF); // int0.8~15
210 //MDrv_MFC_WriteByte(0x2406, 0xFF); //mask int1.0~7
211 //MDrv_MFC_WriteByte(0x2407, 0xFF); // int1.8~15
212 MDrv_MFC_WriteBit(0x2401, 1, _BIT0); // Vsync change irq
213 MDrv_MFC_WriteBit(0x2406, 1, _BIT1); // OP Vsync irq
214 MDrv_MFC_WriteBit(0x2406, 1, _BIT3); // end of DE irq
215 }
216
217 }
218
219 /////////////////////////////////////////////////////////////////////////
MDrv_MFC_McuInitialize(void)220 void MDrv_MFC_McuInitialize(void)
221 {
222 MDrv_MFC_McuUsePLL(0);
223 //Reset MPLL
224 //Read the register to know is URSA version and save it to dummy bank
225 MDrv_MFC_WriteByte( 0x1E24, ((MDrv_MFC_ReadByte(0x1203)&0xC0)?0x02:0x01));
226 MDrv_MFC_WriteBit(0x1E80, 1, _BIT7); // MPLL power down
227 //msWriteBit(0x1E81, 1, _BIT0); // MPLL power on reset
228 MDrv_MFC_WriteByteMask(0x1E81, _BIT0|_BIT1, _BIT0|_BIT1); // MPLL power on reset
229 #if(CODEBASE_SEL == CODEBASE_51)
230 MDrv_MFC_Write2Bytes(0x1E86, 0x0902); // Loop divider setting
231 #else
232 MDrv_MFC_Write2Bytes(0x1E86, 0x0901);
233 #endif
234 MDrv_MFC_WriteBit(0x1E80, 0, _BIT7); // MPLL power on
235 //MDrv_MFC_WriteBit(0x1E81, 0, _BIT0); // MPLL power on reset release
236 MDrv_MFC_WriteByteMask(0x1E81, 0, _BIT0|_BIT1); // MPLL power on reset
237 mfcSleepMsNop(5);
238 MDrv_MFC_WriteByte( 0x1E80, 0x00);
239 MDrv_MFC_WriteByte( 0x1E81, 0x00);
240 MDrv_MFC_McuICacheCtrl(_ENABLE);
241
242 #if (WATCH_DOG_TIMER)
243 MDrv_MFC_McuWatchDogInit(WATCH_DOG_TIMER);
244 MDrv_MFC_McuWatchDogCtrl(_ENABLE);
245 MDrv_MFC_McuWatchDogClear();
246 #else
247 MDrv_MFC_McuWatchDogCtrl(_DISABLE);
248 #endif
249
250 MDrv_MFC_SetMcuSpeed(1); //3
251 MDrv_MFC_WriteBit(0x1E03, _ENABLE, _BIT2); // RX enable
252
253 #if (ISR_EXT_TIMER0_INT)
254 MDrv_MFC_McuExtTimer0_Init();
255 #endif
256 #if (ISR_EXT_TIMER1_INT)
257 MDrv_MFC_McuExtTimer1_Init();
258 #endif
259 MDrv_MFC_WriteByte(0x2400, 0xFF); //mask int0.0~7
260 MDrv_MFC_WriteByte(0x2401, 0xFF); // int0.8~15
261 MDrv_MFC_WriteByte(0x2404, 0xFF); //clear
262 MDrv_MFC_WriteByte(0x2405, 0xFF);
263 MDrv_MFC_WriteByte(0x2404, 0x00); //clear
264 MDrv_MFC_WriteByte(0x2405, 0x00);
265
266 MDrv_MFC_WriteByte(0x2406, 0xFF); //mask int1.0~7
267 MDrv_MFC_WriteByte(0x2407, 0xFF); // int1.8~15
268 MDrv_MFC_WriteByte(0x240A, 0xFF); //clear
269 MDrv_MFC_WriteByte(0x240B, 0xFF);
270 MDrv_MFC_WriteByte(0x240A, 0x00); //clear
271 MDrv_MFC_WriteByte(0x240B, 0x00);
272
273 MDrv_MFC_WriteBit(0x2B18, 0, _BIT0); // Scaler irq
274 MDrv_MFC_SetInterrupt(_DISABLE);
275
276 }
277 #endif
278
279