1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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19 // modification/derivatives thereof is transferred to you under Terms.
20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 #define _MSSCALERIP_C_
79 #include "mdrv_mfc_platform.h"
80 #include "mdrv_mfc.h"
81 #include "mdrv_mfc_fb.h"
82 #include "mdrv_mfc_scalerip.h"
83
84 #if(CODESIZE_SEL == CODESIZE_ALL)
85
IPM_LinePitch(U8 u8IpMode,U16 u16PnlWidth)86 U16 IPM_LinePitch(U8 u8IpMode, U16 u16PnlWidth)
87 {
88 if (u8IpMode==IP_YC_10BIT)
89 return LimitCheck(u16PnlWidth, 64);
90 else ///IP_YC_8BIT or IP_YC_10BIT_COMP
91 return LimitCheck(u16PnlWidth, 16);
92
93 }
94
Ycout_LinePitch(U8 u8IpMode,U16 u16PnlWidth)95 U16 Ycout_LinePitch(U8 u8IpMode, U16 u16PnlWidth)
96 {
97 if (u8IpMode==IP_YC_10BIT)
98 return LimitCheck(u16PnlWidth, 64)/64*10;
99 else ///IP_YC_8BIT or IP_YC_10BIT_COMP
100 return LimitCheck(u16PnlWidth, 16)/16*2;
101 }
102
103 #if ( TwoChip_Func == TwoChip_Slave )
Ycout_LinePitchDW(U8 u8IpMode,U32 u32PnlWidth)104 U32 Ycout_LinePitchDW(U8 u8IpMode, U32 u32PnlWidth)
105 {
106 if (u8IpMode==IP_YC_10BIT)
107 return LimitCheck(u32PnlWidth, 64)/64*10;
108 else ///IP_YC_8BIT or IP_YC_10BIT_COMP
109 return LimitCheck(u32PnlWidth, 16)/16*2;
110 }
111 #endif
112
FBNumber(void)113 U8 FBNumber(void)
114 {
115 return 4;///7; //frame buffer number=8(0~7)
116 }
117
MDrv_MFC_IP_SetMemMode(U8 u8IpMode)118 void MDrv_MFC_IP_SetMemMode(U8 u8IpMode)
119 {
120 if (u8IpMode==IP_YC_10BIT)
121 MDrv_MFC_WriteByte(0x2002, 0x77);
122 else if (u8IpMode==IP_YC_10BIT_COMP)
123 {
124 MDrv_MFC_WriteByte(0x2002, 0x05);
125 if(gmfcSysInfo.u8MirrorMode)
126 {
127 u8IpMode = u8IpMode | _BIT6; //victor 090617
128 MDrv_MFC_WriteBit(0x2005, 1, _BIT5);
129 }
130 }
131 else
132 MDrv_MFC_WriteByte(0x2002, 0x05);
133 MDrv_MFC_WriteByte(0x2003, (0x90 | u8IpMode)); //[7]=1 090820 suchiun for OSD color issue
134 }
135
136 /*
137 LVDS input selection:
138 0x2202[0]=1:Back-side pin sequence swap
139 0x2250[6]=1:LVDS clock input select from even
140 0x2300[7]=1:TI mode, [2]=1:10bits, [1]=1:Single
141 0x2328[7]=1:MSB/LSB swap, [6]=1:P/N swap, [4]=1:Odd/Even swap
142 0x233A[3]=1:6bits
143 */
MDrv_MFC_InitializeRx(void)144 void MDrv_MFC_InitializeRx(void)
145 {
146 #if(CODEBASE_SEL == CODEBASE_LINUX)
147 MDrv_MFC_WriteBit(0x2214, 0, _BIT2);
148 #elif(CODEBASE_SEL == CODEBASE_UTOPIA)
149 #if 0
150 if (gmfcSysInfo.u8PanelType==2)//LVDS
151 {
152 MDrv_MFC_WriteBit(0x2214, 1, _BIT2); //LVDS
153 }
154 else if(gmfcSysInfo.u8PanelType==0)//TTL
155 {
156 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL
157 }
158 #else
159 MDrv_MFC_WriteBit(0x2214, 0, _BIT2); //TTL
160 //for TTL power down RX
161 MDrv_MFC_WriteBit(0x2214, 1, _BIT3);
162 MDrv_MFC_WriteBit(0x2214, 1, _BIT5);
163
164 MDrv_MFC_WriteBit(0x2216, 1, _BIT3);
165 MDrv_MFC_WriteBit(0x2216, 1, _BIT4);
166
167 MDrv_MFC_WriteBit(0x221E, 1, _BIT3);
168 MDrv_MFC_WriteBit(0x221E, 1, _BIT4);
169
170 MDrv_MFC_WriteBit(0x228E, 1, _BIT3);
171 MDrv_MFC_WriteBit(0x228E, 1, _BIT4);
172 MDrv_MFC_WriteBit(0x228E, 1, _BIT5);
173 MDrv_MFC_WriteBit(0x228E, 1, _BIT6);
174 MDrv_MFC_WriteBit(0x228E, 1, _BIT7);
175
176 if (gmfcSysInfo.u8PanelVfreq==60)
177 {
178 MDrv_MFC_Write2Bytes(0x320A, 0x6008);
179 MDrv_MFC_Write2Bytes(0x3200, 0x0001);
180 MDrv_MFC_Write2Bytes(0x2A06, 0x0006);
181 MDrv_MFC_Write2Bytes(0x321E, 0x2200);
182 MDrv_MFC_WriteBit(0x2A83, 0, _BIT0);
183 MDrv_MFC_WriteBit(0x2A83, 1, _BIT1);
184 }
185 #endif
186 #endif
187 MDrv_MFC_WriteByte(0x22AC, 0x11);
188
189 #if(CODEBASE_SEL == CODEBASE_51)
190 #if ((BOARD_TYPE_SEL == BD_MST054C_C01A_S) )
191 MDrv_MFC_WriteByte(0x2202, 0x00);
192 #else
193 MDrv_MFC_WriteByte(0x2202, 0x01); // [0]=1: back-side pin sequence swap
194 #endif
195 #else
196 MDrv_MFC_WriteByte(0x2202, 0x01); // [0]=1: back-side pin sequence swap
197 #endif
198
199 MDrv_MFC_WriteByte(0x2250, 0x40); // [6]=1: LVDS clock input select from even
200
201 #if (CODEBASE_SEL == CODEBASE_51)
202 #if ((BOARD_TYPE_SEL == BD_MST054C_C01A_S))
203 MDrv_MFC_WriteByte(0x2300, 0x70|(gmfcSysInfo.u8LVDSTiMode?_BIT7:0)|(gmfcSysInfo.u8LVDSBitNum==_10BITS?_BIT2:0)|(gmfcSysInfo.u8LVDSChannel==_SINGLE?_BIT1:0));
204 MDrv_MFC_WriteByte(0x233A, 0xB0|(gmfcSysInfo.u8LVDSBitNum==_6BITS?_BIT3:0));
205 MDrv_MFC_WriteByte(0x2328, (gmfcSysInfo.u8LVDSSwapMsbLsb?_BIT7:0)|(gmfcSysInfo.u8LVDSSwap_P_N?_BIT6:0)|(gmfcSysInfo.u8LVDSSwapOddEven?_BIT4:0));
206 #endif
207 #endif
208 #if(CODEBASE_SEL == CODEBASE_51)
209 #if (REG_DIRECT_ACCESS_BY_I2C)
210 if (gmfcSysInfo.u8Preset == 0x01)
211 #endif
212 #endif
213 {
214 // 0x2300, [7]=1:TI mode, [2]=1:10bits, [1]=1:Single
215 MDrv_MFC_WriteByte(0x2300, (gmfcSysInfo.u8LVDSTiMode?_BIT7:0)
216 | (gmfcSysInfo.u8LVDSBitNum==_10BITS?_BIT2:0)
217 | (gmfcSysInfo.u8LVDSChannel==_SINGLE?_BIT1:0)
218 | (gmfcSysInfo.u8PanelBlankCPVC?_BIT6:0)
219 | (gmfcSysInfo.u8PanelBlankOEC?_BIT5:0)
220 | (gmfcSysInfo.u8PanelBlankTPC?_BIT4:0)
221 | (gmfcSysInfo.u8PanelBlankSTHC?_BIT3:0));
222 if(S7M) // RX TTL
223 {
224 MDrv_MFC_WriteBit(0x2301, 1, _BIT7);
225 MDrv_MFC_WriteBit(0x2301, 1, _BIT5);
226 }
227 // 0x233A, [3]=1:6bits
228 MDrv_MFC_WriteByte(0x233A, 0xB0|(gmfcSysInfo.u8LVDSBitNum==_6BITS?_BIT3:0));
229 //0x2328, [7]=1:MSB/LSB swap, [6]=1:P/N swap, [4]=1:Odd/Even swap
230 MDrv_MFC_WriteByte(0x2328, (gmfcSysInfo.u8LVDSSwapMsbLsb?_BIT7:0)|(gmfcSysInfo.u8LVDSSwap_P_N?_BIT6:0)|(gmfcSysInfo.u8LVDSSwapOddEven?_BIT4:0));
231 }
232
233 MDrv_MFC_WriteByte(0x2283, 0xc4);
234 MDrv_MFC_WriteByte(0x2285, 0xc4);
235 MDrv_MFC_WriteByteMask(0x228F, 0, 0x0F);
236
237 //printk("MDrv_MFC_InitializeRx()\n");
238 }
239
MDrv_MFC_InitializeIP_PtnGen(void)240 void MDrv_MFC_InitializeIP_PtnGen(void)
241 {
242 MDrv_MFC_WriteByte(0x20E0, 0x00);
243 MDrv_MFC_Write2Bytes(0x20E2, gmfcSysInfo.u16HTotal);
244 MDrv_MFC_Write2Bytes(0x20E4, gmfcSysInfo.u16VTotal);
245 MDrv_MFC_Write2Bytes(0x20E6, 0);
246 MDrv_MFC_Write2Bytes(0x20E8, gmfcSysInfo.u16Width);
247 MDrv_MFC_Write2Bytes(0x20EA, 0);
248 MDrv_MFC_Write2Bytes(0x20EC, gmfcSysInfo.u16Height);
249 //printk("MDrv_MFC_InitializeIP_PtnGen()\n");
250 }
251
252 code MST_MFC_RegUnitType_t tInitializeOPMAddr[]=
253 {
254 {0x2138, 0x4c},
255 {0x2139, 0x0d},
256 {0x213A, 0x00},
257 {0x213B, 0x00},
258
259 {0x213C, 0xEC},
260 {0x213D, 0xfe},
261 {0x213E, 0x04},
262 {0x213F, 0x00},
263
264 {0x2140, 0x8C},
265 {0x2141, 0xf0},
266 {0x2142, 0x09},
267 {0x2143, 0x00},
268
269 {0x2144, 0x2C},
270 {0x2145, 0xe2},
271 {0x2146, 0x0e},
272 {0x2147, 0x00},
273
274 {0x2148, 0xCC},
275 {0x2149, 0xd3},
276 {0x214A, 0x13},
277 {0x214B, 0x00},
278
279 {0x214C, 0xA9},
280 {0x214D, 0x00},
281 {0x214E, 0x20},
282 {0x214F, 0x00},
283
284 {0x2150, 0xAE},
285 {0x2151, 0x00},
286 {0x2152, 0x28},
287 {0x2153, 0x00},
288 {_END_OF_TBL_, _END_OF_TBL_},
289 };
290
291 code MST_MFC_RegUnitType_t tInitializeIP[]=
292 {
293 #if 1 // Input 60Hz
294 //======================
295 // 60Hz
296 //======================
297 //[IP]
298 {0x203E, 0x2f}, // rfifo rfifo thr
299 {0x203F, 0x1f}, // rfifo high pri thr
300 {0x2040, 0x20}, // wfifo wfifo thr
301 {0x2041, 0x40}, // wfifo high pri thr
302 {0x2042, 0x20}, // rreq_len_y
303 {0x2043, 0x08}, // rreq_len_mr
304 {0x2044, 0x40},///58 // wreq_len_ycout //Titan.sun suggestion 081027
305 {0x2045, 0x00}, // wreq_len_mr
306 #else
307 //======================
308 // 120Hz
309 //======================
310 //[IP]
311 {0x203E, 0x20}, // rfifo rfifo thr
312 {0x203F, 0x18}, // rfifo high pri thr
313 {0x2040, 0x20}, // wfifo wfifo thr
314 {0x2041, 0x28}, // wfifo high pri thr
315 {0x2042, 0x20}, // rreq_len_y
316 {0x2043, 0x08}, // rreq_len_mr
317 {0x2044, 0x50}, // wreq_len_ycout
318 {0x2045, 0x08}, // wreq_len_mr
319 #endif
320 {0x204A, 0x00}, // r_mask_num
321 {0x204B, 0x00}, // w_mask_num
322 {0x2060, 0x03}, // [1]:de_only, [0]:mode_det_en
323 {0x2061, 0x00}, //
324 {0x2062, 0x03}, // vpulse line for IP
325 {0x2063, 0x00}, // vpulse line for IP
326 {0x2064, 0x01}, // vpulse line for Frame Lock
327 {0x2065, 0x00}, // vpulse line for Frame Lock
328 {0x2066, 0x10}, // lock interrupt control, [4]:ref_h
329 {0x2068, 0xb4}, // blank_boundary (720)
330 {0x2069, 0x00}, // blank_boundary (720)
331 //{0x20D0, 0xF1}, // [7:6]:ip unstable control,[5:4]:ip no signal control,[0]:reference clock mode detection
332 {0x20D0, 0x31}, // For Demo Board Use, !!???
333 {0x20D4, 0x05},
334
335 {0x2001, 0x03}, // [1]Write request enable, [0]Read request enable
336
337 {_END_OF_TBL_, _END_OF_TBL_},
338 };
339
MDrv_MFC_SetMirrorMode(MirrorModeType ucMirrorMode)340 void MDrv_MFC_SetMirrorMode(MirrorModeType ucMirrorMode)
341 {
342 U8 i;
343 gmfcSysInfo.u8MirrorMode=ucMirrorMode;
344 MDrv_MFC_IP_SetMemMode(IP_MODE);
345
346 //IP Init
347 for (i=0; i<5; i++)
348 {
349 MDrv_MFC_Write3Bytes(0x2006+4*i, (gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*i)>>4);
350 }
351 for (i=0; i<3; i++)
352 {
353 MDrv_MFC_Write3Bytes(0x2020+4*i, (gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+5))>>4);
354 }
355
356 //OPM Setting
357 for (i=0; i<5; i++)
358 {
359 MDrv_MFC_Write3Bytes(0x2138+4*i, MDrv_MFC_Read3Bytes(0x2006+4*i));
360 }
361 for (i=0; i<3; i++)
362 {
363 MDrv_MFC_Write3Bytes(0x214C+4*i, MDrv_MFC_Read3Bytes(0x2020+4*i));
364 }
365
366 switch(ucMirrorMode)
367 {
368 case MIRROR_H_MODE:
369 //Set H mode IP address
370 for (i=0; i<5; i++)
371 {
372 MDrv_MFC_Write3Bytes(0x2006+4*i,
373 ((gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*i)>>4)
374 +Ycout_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width)-1);
375 }
376 for (i=0; i<3; i++)
377 {
378 MDrv_MFC_Write3Bytes(0x2020+4*i,
379 ((gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+5))>>4)
380 +Ycout_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width)-1);
381 }
382 //Enable OPM setting
383 MDrv_MFC_WriteByteMask(0x2136, _BIT0, _BIT0);
384 //Enable H mode
385 MDrv_MFC_WriteByteMask(0x205C, _BIT0, _BIT1|_BIT0);
386 break;
387
388 case MIRROR_V_MODE:
389 //Set V mode IP address
390 for (i=0; i<5; i++)
391 {
392 MDrv_MFC_Write3Bytes(0x2006+4*i,
393 (((gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+1))>>4)
394 -Ycout_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width)));
395 }
396 for (i=0; i<3; i++)
397 {
398 MDrv_MFC_Write3Bytes(0x2020+4*i,
399 (((gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+6))>>4)
400 -Ycout_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width)));
401 }
402 //Enable OPM setting
403 MDrv_MFC_WriteByteMask(0x2136, _BIT0, _BIT0);
404 //Enable V mode
405 MDrv_MFC_WriteByteMask(0x205C, _BIT1, _BIT1|_BIT0);
406 break;
407
408 case MIRROR_HV_MODE:
409 //Set HV mode IP address
410 for (i=0; i<5; i++)
411 {
412 MDrv_MFC_Write3Bytes(0x2006+4*i, (((gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+1))>>4)-1));
413 }
414 for (i=0; i<3; i++)
415 {
416 //MDrv_MFC_Write3Bytes(0x2006+4*i, (((gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+1))>>4)-1));
417 MDrv_MFC_Write3Bytes(0x2020+4*i, (((gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+6))>>4)-1));
418 }
419 //Enable OPM setting
420 MDrv_MFC_WriteByteMask(0x2136, _BIT0, _BIT0);
421 //Enable H mode
422 MDrv_MFC_WriteByteMask(0x205C, _BIT1|_BIT0, _BIT1|_BIT0);
423 break;
424
425 case MIRROR_OFF:
426 default:
427 //Set Original IP base Asddress
428 for (i=0; i<5; i++)
429 {
430 MDrv_MFC_Write3Bytes(0x2006+4*i, (gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*i)>>4);
431 }
432 for (i=0; i<3; i++)
433 {
434 MDrv_MFC_Write3Bytes(0x2020+4*i, (gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+5))>>4);
435 }
436 //Disable OPM setting
437 MDrv_MFC_WriteByteMask(0x2136, 0, _BIT0);
438 //Disable HV mode
439 MDrv_MFC_WriteByteMask(0x205C, 0, _BIT1|_BIT0);
440 break;
441 }
442 }
443
444
445 #if ( TwoChip_Func == TwoChip_Slave )
MDrv_MFC_SetOPMBaseAddr(void)446 void MDrv_MFC_SetOPMBaseAddr(void)
447 {
448 U32 dwOPMBase;
449 U8 i ;
450
451 //OPM Setting
452 dwOPMBase = Ycout_LinePitchDW(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width/2 -64 );
453 for (i=0; i<5; i++)
454 {
455 MDrv_MFC_Write3Bytes(0x2138+4*i, MDrv_MFC_Read3Bytes(0x2006+4*i) + dwOPMBase);
456 }
457
458 for (i=0; i<3; i++)
459 {
460 MDrv_MFC_Write3Bytes(0x214C+4*i, MDrv_MFC_Read3Bytes(0x2020+4*i) + dwOPMBase);
461 }
462 // MDrv_MFC_WriteRegsTbl(0x2100, tInitializeOPMAddr); // initialize all of bank
463 }
464 #endif
465
MDrv_MFC_InitializeIP(void)466 void MDrv_MFC_InitializeIP(void)
467 {
468 U8 i;
469
470 MDrv_MFC_IP_SetMemMode(gmfcMiuBaseAddr.u8IpMode);
471 //[Frame Buffer]
472 MDrv_MFC_WriteByte(0x2004, FBNumber());
473
474 for (i=0; i<5; i++) //j090423
475 {
476 MDrv_MFC_Write3Bytes(0x2006+4*i, (gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*i)>>4);
477 }
478
479 MDrv_MFC_WriteByte(0x201B, 0x04); //Ip to mc sel
480
481 for (i=0; i<3; i++)
482 {
483 MDrv_MFC_Write3Bytes(0x2020+4*i, (gmfcMiuBaseAddr.u32IpYcoutBase+gmfcMiuBaseAddr.u32IpYcoutSize*(i+5))>>4);
484 }
485
486 MDrv_MFC_Write2Bytes(0x2034, Ycout_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width));
487 MDrv_MFC_Write2Bytes(0x203A, Ycout_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width));
488 MDrv_MFC_Write2Bytes(0x2038, IPM_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width)>>4); //IP Linefetch
489 MDrv_MFC_Write2Bytes(0x2046, IPM_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width));
490 MDrv_MFC_Write2Bytes(0x2048, gmfcSysInfo.u16Height);
491 if(gmfcSysInfo.u8MirrorMode)
492 MDrv_MFC_SetMirrorMode(MIRROR_HV_MODE);
493
494 MDrv_MFC_WriteRegsTbl(0x2000, tInitializeIP); // initialize all of bank
495 //printk("MDrv_MFC_InitializeIP()\n");
496 }
497
MDrv_MFC_SoftwareResetIP(void)498 void MDrv_MFC_SoftwareResetIP(void)
499 {
500 MDrv_MFC_WriteByte(0x2000, 0x01); // [0]IP software reset
501 MDrv_MFC_WriteByte(0x2000, 0x00);
502 }
503
504 code MST_MFC_RegUnitType_t tInitializeOPM[]=
505 {
506 {0x210E, 0x08}, // MLB output data rest cycle number between two line //30->40 pip deep ,suchiun suggestion 080911
507 {0x2110, 0x70}, ///90 // OPM fifo normal threshold to trigger read request
508 {0x2111, 0x60}, // OPM fifo high threshold to trigger read request
509 {0x2112, 0x7f}, //0x50, ///48// Maxinum length of OPM read request
510 {0x2102, 0x01}, // Enable OPM/MLB disp
511 {_END_OF_TBL_, _END_OF_TBL_},
512 };
513
MDrv_MFC_InitializeOPM(void)514 void MDrv_MFC_InitializeOPM(void)
515 {
516 #if ( TwoChip_Func != TwoChip_OFF )
517 MDrv_MFC_Write2Bytes(0x2106, gmfcSysInfo.u16Width/2 +64);
518 #else
519 MDrv_MFC_Write2Bytes(0x2106, gmfcSysInfo.u16Width);
520 #endif
521 MDrv_MFC_Write2Bytes(0x2108, gmfcSysInfo.u16Height);
522 MDrv_MFC_WriteByte(0x2C47, gmfcSysInfo.u8PanelVfreq);
523 MDrv_MFC_Write2Bytes(0x2114, Ycout_LinePitch(gmfcMiuBaseAddr.u8IpMode, gmfcSysInfo.u16Width)*2);
524 //MDrv_MFC_Write2Bytes(0x2116, MrLinePitch(gmfcSysInfo.u16Width));
525 MDrv_MFC_WriteRegsTbl(0x2100, tInitializeOPM); // initialize all of bank
526 //printk("MDrv_MFC_InitializeOPM()\n");
527 }
MDrv_MFC_SoftwareResetOPM(void)528 void MDrv_MFC_SoftwareResetOPM(void)
529 {
530 MDrv_MFC_WriteByte(0x2103, 0x03); // [1]MLB's software reset, [0]OPM's software reset, 1:reset
531 mfcSleepMs(100);
532 MDrv_MFC_WriteByte(0x2103, 0x00); // OPM/MLB enable
533 }
534
535 #if ( TwoChip_Func == TwoChip_Master )
MDrv_MFC_SoftwareResetScaler(void)536 void MDrv_MFC_SoftwareResetScaler(void)
537 {
538 mfcSleepMsNop(0xfe);
539
540 MDrv_MFC_WriteBit(0x1E03, 1, _BIT0);
541
542 mfcSleepMsNop(0xfe);
543
544 MDrv_MFC_WriteBit(0x1E03, 0, _BIT0);
545 //putstr("\r\nReset Scaler-----");
546 }
547 #include "mpif.h"
msReset2Chip(void)548 void msReset2Chip(void)
549 {
550 U16 wStatus;
551 U8 ucCnt;
552 ucCnt=200;
553 while(ucCnt--)
554 {
555 wStatus= pifRead2Byte2A(0x2A08);
556 if(wStatus&0x0001)
557 {
558 MDrv_MFC_SoftwareResetScaler();
559 break;
560 }
561 }//while
562 }
563 #endif
564
565 code MST_MFC_RegUnitType_t tInitializeSnr[]=
566 {
567 {0x2E60, 0X03},
568 {0x2E61, 0X00},
569 {0x2E62, 0X0F},
570 {0x2E63, 0X00},
571 {0x2EA0, 0X03},
572 {0x2EA1, 0X00},
573 {0x2EA8, 0X30},
574 {0x2EA9, 0X00},
575 {0x2EAA, 0X11},
576 {0x2EAB, 0X00},
577 {_END_OF_TBL_, _END_OF_TBL_},
578 };
579
MDrv_MFC_InitializeScaler(void)580 void MDrv_MFC_InitializeScaler(void)
581 {
582 MDrv_MFC_WriteRegsTbl(0x2E00, tInitializeSnr); // initialize all of bank
583 //printk("MDrv_MFC_InitializeScaler()\n");
584 }
585
MDrv_MFC_InitializeScalerIP(void)586 void MDrv_MFC_InitializeScalerIP(void)
587 {
588 MDrv_MFC_InitializeRx();
589 MDrv_MFC_InitializeIP_PtnGen();
590 MDrv_MFC_InitializeIP();
591 MDrv_MFC_InitializeOPM();
592 MDrv_MFC_InitializeScaler();
593 //printk("MDrv_MFC_InitializeScalerIP()\n");
594 }
595
596 #if 0
597 U16 msIPGetHdeActive(void)
598 {
599 return MDrv_MFC_Read2Bytes(0x207C);
600 }
601
602 U16 msIPGetHtotal(void)
603 {
604 return MDrv_MFC_Read2Bytes(0x2078);
605 }
606 #endif
607
MDrv_MFC_SoftwareResetScalerInt(void)608 void MDrv_MFC_SoftwareResetScalerInt(void)
609 {
610 MDrv_MFC_WriteBit(0x1E03, 1, _BIT0);
611 mfcSleepMsNop(10);
612 MDrv_MFC_WriteBit(0x1E03, 0, _BIT0);
613 //putstr("\r\nReset Scaler-----");
614 }
615
616
msIPGetVtotal(void)617 U16 msIPGetVtotal(void)
618 {
619 return MDrv_MFC_Read2Bytes(0x207A);
620 }
621
msIPGetHdeCount(void)622 U16 msIPGetHdeCount(void)
623 {
624 return MDrv_MFC_Read2Bytes(0x20D8);
625 }
626
apiIPGetVfreq(void)627 U8 apiIPGetVfreq(void)
628 {
629 U16 wTemp;
630 U32 dwFreq;
631
632 // XTAL / Count = Vtotal * Vfreq
633
634 wTemp = msIPGetHdeCount();
635 //printf("\r\nHcnt[%x]", wTemp>>15);
636 if (!(wTemp&_BIT15))
637 return 0xFF;
638 wTemp &= ~_BIT15;
639 //printf(" [%d]", wTemp);
640 dwFreq = MST_CLOCK_HZ / wTemp;
641
642 wTemp = msIPGetVtotal();
643 //printf("_____Vtot[%x]", wTemp>>15);
644 #ifndef FrameVt_Change
645 if (!(wTemp&_BIT15)) //j090302 for ausu
646 return 0xFF;
647 #endif
648
649 wTemp &= ~_BIT15;
650 //printf(" [%d]", wTemp);
651 dwFreq /= wTemp;
652
653 //printf("_____ndwFreq[%d]", dwFreq);
654 return dwFreq;
655 }
656 #endif
657
658