1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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19 // modification/derivatives thereof is transferred to you under Terms.
20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 #define _MSSCALEROP_C_
79 #include "mdrv_mfc_platform.h"
80 #include "mdrv_mfc.h"
81 #include "mdrv_mfc_scalerop.h"
82 #include "mdrv_mfc_scalerip.h"
83 #include "mdrv_mfc_fb.h"
84 #include "mdrv_mfc_panel.h"
85
86 #if(CODESIZE_SEL == CODESIZE_ALL)
87
88 #ifndef MFC_ENABLE_LVDS_SSC
89 #define MFC_ENABLE_LVDS_SSC 0
90 #define MFC_LVDS_SSC_SPAN_DEFAULT 200
91 #define MFC_LVDS_SSC_STEP_DEFAULT 100
92 #endif
93 /*
94 #if(CODEBASE_SEL == CODEBASE_LINUX)
95 DECLARE_MUTEX(MFC_MUTEX);
96 #define MUTEX_LOCK() down(&MFC_MUTEX)
97 #define MUTEX_UNLOCK() up(&MFC_MUTEX)
98 #endif
99 */
100 extern U8 gLgModelType;
101
102 #define _RATIO 1 // 905,969,664
103 #define _STEP 4 // 4,294,967,295
104 #define _GAIN_P(f) (f/(_STEP))
105 #define _GAIN_I(f) (f/(_STEP*_STEP/2))
106
Panel_Dclk_Hz(U16 u16Htotal,U16 u16Vtotal,U8 u8Vfreq)107 U32 Panel_Dclk_Hz(U16 u16Htotal, U16 u16Vtotal, U8 u8Vfreq)
108 {
109 return (U32)u16Htotal*u16Vtotal*u8Vfreq;
110 }
111
FPLL_Panel_Dclk_Hz(U16 u16Htotal,U16 u16Vtotal,U8 u8Vfreq)112 U32 FPLL_Panel_Dclk_Hz(U16 u16Htotal, U16 u16Vtotal, U8 u8Vfreq)
113 {
114 return (U32)u16Htotal*u16Vtotal*u8Vfreq;
115 }
116
Panel_Dclk_Hz2(U16 u16Htotal,U16 u16Vtotal,U8 u8Vfreq)117 U32 Panel_Dclk_Hz2(U16 u16Htotal, U16 u16Vtotal, U8 u8Vfreq)
118 {
119 U32 u32Dclk=0;
120 u32Dclk = msCalculateDecimal(u16Htotal*u16Vtotal*u8Vfreq,1000000);
121 return u32Dclk;
122 }
123
FPLL_Panel_Dclk_Hz2(U16 u16Htotal,U16 u16Vtotal,U8 u8Vfreq)124 U32 FPLL_Panel_Dclk_Hz2(U16 u16Htotal, U16 u16Vtotal, U8 u8Vfreq)
125 {
126 U32 u32Dclk=0;
127 u32Dclk = msCalculateDecimal(u16Htotal*u16Vtotal*u8Vfreq,1000000);
128 return u32Dclk ;
129 }
130
MDrv_MFC_DE_XEnd(U16 u16PnlWidth)131 U16 MDrv_MFC_DE_XEnd(U16 u16PnlWidth)
132 {
133 if (IsMultipCheck(u16PnlWidth,4))
134 return (gmfcSysInfo.u16HStart/((TwoChip_Func)?2:1) +
135 gmfcSysInfo.u16Width/((TwoChip_Func)?2:1)-1);
136 else
137 return (gmfcSysInfo.u16HStart/((TwoChip_Func)?2:1)+
138 gmfcSysInfo.u16Width/((TwoChip_Func)?2:1)+1);
139 }
140
MDrv_MFC_SetGainPhase(void)141 void MDrv_MFC_SetGainPhase(void)
142 {
143 U8 i, u8Val;
144 U32 u32ClockDivider, u32Factor;
145
146 u32ClockDivider = (Panel_Dclk_Hz(gmfcSysInfo.u16HTotal, gmfcSysInfo.u16VTotal,gmfcSysInfo.u8PanelVfreq)/60*_RATIO)>>5;
147 u32Factor = (216ul*524288*8+(7ul*MST_CLOCK_MHZ*u32ClockDivider)/2)/(7ul*MST_CLOCK_MHZ*u32ClockDivider);
148
149 for (i=0; i<0x0F; i++)
150 {
151 if ((1ul<<i) >= _GAIN_P(u32Factor))
152 break;
153 }
154 u8Val = (i+1)<<4;
155 //printf("\r\n_GAIN_P[%d]", _GAIN_P);
156 //printf(" i[%d]", i);
157
158 for (i=0; i<0x0F; i++)
159 {
160 if ((1ul<<i) >= _GAIN_I(u32Factor))
161 break;
162 }
163 u8Val |= i+1;
164 //printf("\r\n_GAIN_I[%d]", _GAIN_I);
165 //printf(" i[%d]", i);
166
167 if ((gmfcSysInfo.u8PanelVfreq/60)==2)
168 i = 0x10; // {ovs_frame_div[3:0],ivs_frame_div[3:0]}
169 else
170 i = 0x00; // {ovs_frame_div[3:0],ivs_frame_div[3:0]}
171
172 MDrv_MFC_WriteByte(0x2A17, u8Val);
173 MDrv_MFC_WriteByte(0x2A19, i);
174 //printk("MDrv_MFC_SetGainPhase()\n");
175 }
176
MDrv_MFC_SetVCO(U32 u32Dclk,U8 u8Vfreq)177 U32 MDrv_MFC_SetVCO(U32 u32Dclk, U8 u8Vfreq)
178 {
179 U32 u32VCO;
180
181 if (gmfcSysInfo.u8PanelType == _MINI_LVDS || gmfcSysInfo.u8PanelType ==_MINI_LVDS_GIP || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
182 {
183 u32VCO = u32Dclk*4;
184 if(u8Vfreq==60)
185 {
186 if(u32VCO>313)
187 {
188 MDrv_MFC_WriteByteMask(0x2A06, _BIT1, _BIT2|_BIT1|_BIT0); ///2
189 MDrv_MFC_WriteByte(0x2A2C,_BIT3|_BIT2);
190 }
191 else if(u32VCO>156)
192 {
193 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
194 MDrv_MFC_WriteByte(0x2A2C,_BIT4|_BIT2);
195 }
196 else
197 {
198 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
199 MDrv_MFC_WriteByte(0x2A2C, _BIT4 | _BIT3|_BIT2);
200 }
201 }
202 else //120
203 {
204 if(u32VCO>625)
205 {
206 MDrv_MFC_WriteByteMask(0x2A06, _BIT1, _BIT2|_BIT1|_BIT0); ///2
207 MDrv_MFC_WriteByte(0x2A2C, 0);
208 }
209 else if(u32VCO>313)
210 {
211 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
212 MDrv_MFC_WriteByte(0x2A2C, _BIT3|_BIT2);
213 }
214 else
215 {
216 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
217 MDrv_MFC_WriteByte(0x2A2C, _BIT4|_BIT2);
218 }
219 }
220 }
221 else //LVDS
222 {
223 if (gmfcSysInfo.u8PanelChannel == _DUAL)
224 {
225 u32Dclk = u32Dclk/2;
226 u32VCO = u32Dclk*7;
227 if(u32VCO>625)
228 {
229 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
230 MDrv_MFC_WriteByte(0x2A2C, 0);
231 }
232 else
233 {
234 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
235 MDrv_MFC_WriteByte(0x2A2C, _BIT3|_BIT2);
236 }
237 }
238 else if (gmfcSysInfo.u8PanelChannel == _QUAD || gmfcSysInfo.u8PanelChannel == _QUAD_LR)
239 {
240 u32VCO = u32Dclk/2*7;
241 if(u32VCO>625)
242 {
243 MDrv_MFC_WriteByteMask(0x2A06,_BIT1, _BIT2|_BIT1|_BIT0); ///2
244 MDrv_MFC_WriteByte(0x2A2C, 0);
245 }
246 else if(u32VCO>313)
247 {
248 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
249 MDrv_MFC_WriteByte(0x2A2C, _BIT3|_BIT2);
250 }
251 else
252 {
253 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
254 MDrv_MFC_WriteByte(0x2A2C, _BIT4|_BIT2);
255 }
256 }
257 else if (gmfcSysInfo.u8PanelChannel == _V_BY1)
258 {
259 u32VCO = u32Dclk*10;
260 if(u32VCO>625)
261 {
262 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
263 MDrv_MFC_WriteByte(0x2A2C, 0);
264 }
265 else
266 {
267 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
268 MDrv_MFC_WriteByte(0x2A2C, _BIT3|_BIT2);
269 }
270 }
271 else //single
272 {
273 u32Dclk = u32Dclk/2;
274 u32VCO = u32Dclk*7;
275 if(u32VCO>625)
276 {
277 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
278 MDrv_MFC_WriteByte(0x2A2C, 0);
279 }
280 else
281 {
282 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
283 MDrv_MFC_WriteByte(0x2A2C, _BIT3|_BIT2);
284 }
285 }
286 }
287 #if ( TwoChip_Func != TwoChip_OFF )
288 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0);
289 #endif
290 return u32Dclk;
291 }
292
MDrv_MFC_SetLvdsSSC(U16 u16KHz,U8 u8Percent)293 void MDrv_MFC_SetLvdsSSC(U16 u16KHz, U8 u8Percent)
294 {
295 // SPAN value, recommend value is 30KHz ~ 40KHz
296 // STEP percent value, recommend is under 3%
297 U8 u8temp;
298 U16 u16Span, u16Step;
299 U32 u32Set;
300 u8temp = MDrv_MFC_ReadByte(0x2A1B);
301 if(MDrv_MFC_ReadByte(0x2C42)&_BIT5)
302 {
303 MDrv_MFC_WriteBit(0x2A1B, _ENABLE, _BIT3);
304 //Get SET
305 u8temp = MDrv_MFC_ReadByte (0x2A20);
306 u32Set = u8temp;
307 u8temp = MDrv_MFC_ReadByte (0x2A1F);
308 u32Set = (u32Set << 8) | u8temp;
309 u8temp = MDrv_MFC_ReadByte (0x2A1E);
310 u32Set = (u32Set << 8) | u8temp;
311
312 u16Span = ((131072*10*216)/(u32Set*u16KHz/1000));
313 u16Step = (u32Set*u8Percent)/((U32)u16Span*10000);
314
315 MDrv_MFC_WriteByte (0x2A2E, (U8)u16Step); //write step 10 bits
316 MDrv_MFC_WriteByteMask (0x2A2F, (U8)((u16Step&0x0300)>>8), 0x03);
317 MDrv_MFC_WriteByte (0x2A30, (U8)u16Span); //write SPAN 14 bits
318 MDrv_MFC_WriteByteMask (0x2A31, (U8)((u16Span&0x3F00)>>8), 0x3F);
319 }
320 else
321 {
322 MDrv_MFC_WriteBit(0x2A1B, _DISABLE, _BIT3);
323 }
324 //printk("MDrv_MFC_SetLvdsSSC()\n");
325 }
326
327
328 #if(CODEBASE_SEL == CODEBASE_51)
329
msSetFPLLGainPhase(void)330 void msSetFPLLGainPhase(void)
331 {
332 U8 i, u8Val;
333 U32 u32ClockDivider, u32Factor;
334
335 u32ClockDivider = (FPLL_Panel_Dclk_Hz(gmfcSysInfo.u16HTotal, gmfcSysInfo.u16VTotal,gmfcSysInfo.u8PanelVfreq)/60*_RATIO)>>5;
336 u32Factor = (216ul*524288*8+(7ul*MST_CLOCK_MHZ*u32ClockDivider)/2)/(7ul*MST_CLOCK_MHZ*u32ClockDivider);
337
338 for (i=0; i<0x0F; i++)
339 {
340 if ((1ul<<i) >= _GAIN_P(u32Factor))
341 break;
342 }
343 u8Val = (i+1)<<4;
344 //printf("\r\n_GAIN_P[%d]", _GAIN_P);
345 //printf(" i[%d]", i);
346
347 for (i=0; i<0x0F; i++)
348 {
349 if ((1ul<<i) >= _GAIN_I(u32Factor))
350 break;
351 }
352 u8Val |= i+1;
353 //printf("\r\n_GAIN_I[%d]", _GAIN_I);
354 //printf(" i[%d]", i);
355
356
357 if ((gmfcSysInfo.u8PanelVfreq/60)==2)
358 i = 0x10; // {ovs_frame_div[3:0],ivs_frame_div[3:0]}
359 else
360 i = 0x00; // {ovs_frame_div[3:0],ivs_frame_div[3:0]}
361
362 MDrv_MFC_WriteByte(0x2A17, u8Val);
363 MDrv_MFC_WriteByte(0x2A19, i);
364 }
365
msLPLL_SetVCO(U32 dwDclk,U8 ucVfreq)366 U32 msLPLL_SetVCO(U32 dwDclk, U8 ucVfreq)
367 {
368 U32 dwVCO;
369 //printf("\r\n dwDclk = %x", dwDclk);
370 //printf("\r\n ucVfreq = %x", ucVfreq);
371
372 if (gmfcSysInfo.u8PanelType == _MINI_LVDS || gmfcSysInfo.u8PanelType ==_MINI_LVDS_GIP || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
373 {
374 dwVCO = dwDclk*4;
375
376 if(ucVfreq==60)
377 {
378 if(dwVCO>313)
379 {
380 MDrv_MFC_WriteByteMask(0x2A06, _BIT1, _BIT2|_BIT1|_BIT0); ///2
381 MDrv_MFC_WriteByte(0x2A2C, _BIT3|_BIT2);
382 }
383 else if(dwVCO>156)
384 {
385 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
386 MDrv_MFC_WriteByte(0x2A2C, _BIT4|_BIT2);
387 }
388 else
389 {
390 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
391 MDrv_MFC_WriteByte(0x2A2C, _BIT4 | _BIT3|_BIT2);
392 }
393 }
394 else //120
395 {
396 if(dwVCO>625)
397 {
398 MDrv_MFC_WriteByteMask(0x2A06, _BIT1, _BIT2|_BIT1|_BIT0); ///2
399 MDrv_MFC_WriteByte(0x2A2C, 0);
400 }
401 else if(dwVCO>313)
402 {
403 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
404 MDrv_MFC_WriteByte(0x2A2C, _BIT3|_BIT2);
405 }
406 else
407 {
408 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
409 MDrv_MFC_WriteByte(0x2A2C, _BIT4|_BIT2);
410 }
411 }
412 }
413 else //LVDS
414 {
415 if (gmfcSysInfo.u8PanelChannel == _DUAL)
416 {
417 //printf("\r\nDual = %x", 0);
418
419 dwDclk = dwDclk/2;
420 dwVCO = dwDclk*7;
421 if(dwVCO>625)
422 {
423 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
424 MDrv_MFC_WriteByte(0x2A2C,0); //0
425 }
426 else
427 {
428 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
429 MDrv_MFC_WriteByte(0x2A2C,_BIT3|_BIT2); //c
430 }
431 }
432 else if (gmfcSysInfo.u8PanelChannel == _QUAD || gmfcSysInfo.u8PanelChannel == _QUAD_LR)
433 {
434 dwVCO = dwDclk*3.5;
435 if(dwVCO>625)
436 {
437 MDrv_MFC_WriteByteMask(0x2A06,_BIT1, _BIT2|_BIT1|_BIT0); ///2
438 MDrv_MFC_WriteByte(0x2A2C,0); //0
439 }
440 else if(dwVCO>313)
441 {
442 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
443 MDrv_MFC_WriteByte(0x2A2C,_BIT3|_BIT2); //c
444 }
445 else
446 {
447 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
448 MDrv_MFC_WriteByte(0x2A2C,_BIT4|_BIT2); //c
449 }
450 }
451 else if (gmfcSysInfo.u8PanelChannel == _V_BY1)
452 {
453 dwVCO = dwDclk*10;
454 if(dwVCO>625)
455 {
456 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
457 MDrv_MFC_WriteByte(0x2A2C,0); //0
458 }
459 else
460 {
461 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
462 MDrv_MFC_WriteByte(0x2A2C,_BIT3|_BIT2); //c
463 }
464 }
465 else //single
466 {
467 dwDclk = dwDclk/2;
468 dwVCO = dwDclk*7;
469 if(dwVCO>625)
470 {
471 MDrv_MFC_WriteByteMask(0x2A06, _BIT2|_BIT1, _BIT2|_BIT1|_BIT0); ///6
472 MDrv_MFC_WriteByte(0x2A2C,0); //0
473 }
474 else
475 {
476 MDrv_MFC_WriteByteMask(0x2A06, _BIT2, _BIT2|_BIT1|_BIT0); ///4
477 MDrv_MFC_WriteByte(0x2A2C,_BIT3|_BIT2); //c
478 }
479 }
480 }
481 #if ( TwoChip_Func != TwoChip_OFF )
482 MDrv_MFC_WriteBit(0x2A2C, 1, _BIT0);
483 #endif
484 return dwDclk;
485 }
486
msSetOutDClk(U8 u8Inputfreq,U8 ucVHzFrmT2,BOOL enableFPLL)487 void msSetOutDClk(U8 u8Inputfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL)
488 {
489 U16 wVTotal = gmfcSysInfo.u16VTotal;
490 U32 dwDClk ;
491 if(ucVHzFrmT2)
492 {
493 gmfcSysInfo.u8PanelVfreq = ucVHzFrmT2;
494 MDrv_MFC_SetGainPhase();
495 }
496
497 if(u8Inputfreq>45&&u8Inputfreq<55)
498 {
499 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32
500 }
501 else
502 {
503 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32
504 }
505
506 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle
507 #if(ENABLE_USER_TOTAL)
508 if (u8Inputfreq==50)
509 {
510 gmfcSysInfo.u16HTotal = USER_HT_50;
511 gmfcSysInfo.u16VTotal = USER_VT_50;
512 }
513 else //60
514 {
515 gmfcSysInfo.u16HTotal = USER_HT_60;
516 gmfcSysInfo.u16VTotal = USER_VT_60;
517 }
518 dwDClk = MDrv_MFC_SetVCO(Panel_Dclk_Hz2(gmfcSysInfo.u16HTotal, gmfcSysInfo.u16VTotal, u8Inputfreq/*u8Inputfreq*/), gmfcSysInfo.u8PanelVfreq);
519 MDrv_MFC_Write2BytesINT(REG_2F02, gmfcSysInfo.u16VTotal-1);
520 MDrv_MFC_Write2BytesINT(REG_2F04, gmfcSysInfo.u16HTotal-1);
521 #else
522 dwDClk = MDrv_MFC_SetVCO(Panel_Dclk_Hz2(gmfcSysInfo.u16HTotal, gmfcSysInfo.u16VTotal, 60/*u8Inputfreq*/), gmfcSysInfo.u8PanelVfreq);
523
524 if (u8Inputfreq==50)
525 {
526 if (gmfcSysInfo.u8PanelIncVtotalFor50Hz)
527 {
528 wVTotal = wVTotal*6/5;
529 }
530 else
531 {
532 dwDClk = dwDClk*5/6;
533 }
534 }
535 MDrv_MFC_Write2BytesINT(REG_2F02, wVTotal-1);
536 #endif
537
538 //printf("\r\nVTotal[%d]", wVTotal);
539 //printf("\r\nDClk[%x]", dwDClk>>16);
540 //printf("\r\n DClk1[%x]", dwDClk);
541 //printf("u8Inputfreq=[%x]", u8Inputfreq);
542
543 if (gmfcSysInfo.u8PanelType == _MINI_LVDS
544 || gmfcSysInfo.u8PanelType == _RSDS
545 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP
546 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
547 {
548 if(gmfcSysInfo.u8PanelVfreq == 60)
549 dwDClk = (U32)PANEL_DCLK_FACTOR_TCON_60 / dwDClk;
550 else
551 dwDClk = (U32)PANEL_DCLK_FACTOR_TCON / dwDClk;
552 }
553 else
554 dwDClk = (U32)PANEL_DCLK_FACTOR / dwDClk;
555
556 if (gmfcSysInfo.u8PanelChannel == _QUAD || gmfcSysInfo.u8PanelChannel == _QUAD_LR)
557 {
558 //putstr("\r\nmsSetOutDClk(Quad)");
559 }
560 else if(gmfcSysInfo.u8PanelChannel == _DUAL)
561 {
562 //putstr("\r\nmsSetOutDClk(Dual)");
563 dwDClk /= 2;
564 }
565
566 //printf("\r\nLPLL[%x]", dwDClk>>16);
567 //printf("[%x]", dwDClk);
568 MDrv_MFC_Write3Bytes(0x2A1E, dwDClk);
569
570 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle
571 MDrv_MFC_WriteByte(0x2A0A, 0x24);// make frame lock faster
572
573 MDrv_MFC_SetLvdsSSC(MFC_LVDS_SSC_SPAN_DEFAULT, MFC_LVDS_SSC_STEP_DEFAULT);
574 }
575
MDrv_MFC_SetLvdsSSC_INT(U16 u16KHz,U8 u8Percent)576 void MDrv_MFC_SetLvdsSSC_INT(U16 u16KHz, U8 u8Percent)
577 {
578 // SPAN value, recommend value is 30KHz ~ 40KHz
579 // STEP percent value, recommend is under 3%
580 U8 u8temp;
581 U16 u16Span, u16Step;
582 U32 u32Set;
583 u8temp = MDrv_MFC_ReadByte(0x2A1B);
584 if((MDrv_MFC_ReadByte(0x2C42)&_BIT5))
585 {
586 MDrv_MFC_WriteBitINT(0x2A1B, _ENABLE, _BIT3);
587 //Get SET
588 u8temp = MDrv_MFC_ReadByte (0x2A20);
589 u32Set = u8temp;
590 u8temp = MDrv_MFC_ReadByte (0x2A1F);
591 u32Set = (u32Set << 8) | u8temp;
592 u8temp = MDrv_MFC_ReadByte (0x2A1E);
593
594 u32Set = (u32Set << 8) | u8temp;
595 u16Span = ((131072*10*216)/(u32Set*u16KHz/1000));
596 u16Step = (u32Set*u8Percent)/((U32)u16Span*10000);
597
598 MDrv_MFC_WriteByte (0x2A2E, (U8 )u16Step); //write step 10 bits
599 MDrv_MFC_WriteByteMaskINT (0x2A2F, (U8 )((u16Step&0x0300)>>8), 0x03);
600 MDrv_MFC_WriteByte (0x2A30, (U8 )u16Span); //write SPAN 14 bits
601 MDrv_MFC_WriteByteMaskINT (0x2A31, (U8 )((u16Span&0x3F00)>>8), 0x3F);
602 }
603 else
604 {
605 MDrv_MFC_WriteBitINT(0x2A1B, _DISABLE, _BIT3);
606 }
607 }
608
609 #if 0
610 void msReportCurser(void)
611 {
612 WORD wTemp1;
613 BYTE i;
614 MDrv_MFC_WriteByte(REG_2F40, 0x4B); //10
615 MDrv_MFC_WriteByte(REG_2F41, 0x84); //81
616 MDrv_MFC_WriteByte(REG_2F42, 0x00);
617 MDrv_MFC_WriteByte(REG_2F43, 0x01);
618 MDrv_MFC_WriteBit(0x30A0, 1, _BIT1);
619
620 for(i=0;i<=0x64;i++)
621 {
622 wTemp1 = MDrv_MFC_Read2Bytes(0x30A4);
623 //printf(" \r\n data= %x", wTemp1);
624 Delay1ms_Nop(0x10) ;
625
626 if(wTemp1 != 0x00)
627 printf(" \r\n different --------= %x", wTemp1);
628
629 }
630
631 printf(" \r\n end----- %x", wTemp1);
632 }
633 #endif
634
635 XDATA BYTE OPMReset=1;
msSetFPLLOutDClk(U8 ucVfreq,U8 ucVHzFrmT2,BOOL enableFPLL)636 void msSetFPLLOutDClk(U8 ucVfreq, U8 ucVHzFrmT2/*Set panel frequence from T2*/, BOOL enableFPLL)
637 {
638 #if(PANEL_TYPE_SEL ==PNL_TVBOX_1080P_60HZ)
639 U16 wHTotal = 2200;
640 #else
641 U16 wVTotal = gmfcSysInfo.u16VTotal;
642 #endif
643 U32 dwDClk ;
644
645 MDrv_MFC_WriteByteINT(0x2C49, ucVfreq);
646
647 if(enableFPLL&&OPMReset)
648 {
649
650 MDrv_MFC_SoftwareResetScalerInt();
651 OPMReset=0;
652 }
653 if(ucVfreq>45&&ucVfreq<55)
654 {
655 MDrv_MFC_WriteBitINT(0x2080, _DISABLE, _BIT0); // disable film32
656 }
657 else
658 {
659 MDrv_MFC_WriteBitINT(0x2080, _ENABLE, _BIT0); // enable film32
660 }
661
662
663 if(ucVHzFrmT2)
664 {
665 gmfcSysInfo.u8PanelVfreq = ucVHzFrmT2;
666 msSetFPLLGainPhase();
667 }
668
669 MDrv_MFC_WriteBitINT(0x2A18, 0, _BIT3); // PLL set chnage Toggle
670
671 #if(ENABLE_USER_TOTAL)
672 if (ucVfreq==50)
673 {
674 gmfcSysInfo.u16HTotal = USER_HT_50;
675 gmfcSysInfo.u16VTotal = USER_VT_50;
676 }
677 else //60
678 {
679 gmfcSysInfo.u16HTotal = USER_HT_60;
680 gmfcSysInfo.u16VTotal = USER_VT_60;
681 }
682 dwDClk = msLPLL_SetVCO(FPLL_Panel_Dclk_Hz2(gmfcSysInfo.u16HTotal, gmfcSysInfo.u16VTotal, ucVfreq/*u8Inputfreq*/), gmfcSysInfo.u8PanelVfreq);
683 MDrv_MFC_Write2BytesINT(REG_2F02, gmfcSysInfo.u16VTotal-1);
684 MDrv_MFC_Write2BytesINT(REG_2F04, gmfcSysInfo.u16HTotal-1);
685 #else
686 dwDClk = msLPLL_SetVCO(FPLL_Panel_Dclk_Hz2(gmfcSysInfo.u16HTotal, gmfcSysInfo.u16VTotal, 60/*u8Inputfreq*/), gmfcSysInfo.u8PanelVfreq);
687
688 if (ucVfreq==50)
689 {
690 if (gmfcSysInfo.u8PanelIncVtotalFor50Hz)
691 {
692 #if(PANEL_TYPE_SEL ==PNL_TVBOX_1080P_60HZ)
693 wHTotal = 2640;
694 #else
695 wVTotal = wVTotal*6/5;
696 #endif
697
698 }
699 else
700 {
701 dwDClk = dwDClk*5/6;
702 }
703 }
704 MDrv_MFC_Write2BytesINT(REG_2F02, wVTotal-1);
705 #endif
706
707 //printf("\r\nVTotal[%d]", wVTotal);
708 //printf("\r\nDClk[%x]", dwDClk>>16);
709 //printf("\r\n DClk2[%x]", dwDClk);
710 //printf("ucVfreq=[%x]", ucVfreq);
711
712
713 if (gmfcSysInfo.u8PanelType == _MINI_LVDS
714 || gmfcSysInfo.u8PanelType == _RSDS
715 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP
716 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
717 {
718 if(gmfcSysInfo.u8PanelVfreq == 60)
719 dwDClk = (U32)PANEL_DCLK_FACTOR_TCON_60 / dwDClk;
720 else
721 dwDClk = (U32)PANEL_DCLK_FACTOR_TCON / dwDClk;
722 }
723 else
724 dwDClk = (U32)PANEL_DCLK_FACTOR / dwDClk;
725
726 if (gmfcSysInfo.u8PanelChannel == _QUAD || gmfcSysInfo.u8PanelChannel == _QUAD_LR)
727 {
728 //putstr("\r\nmsSetOutDClk(Quad)");
729 }
730 else if(gmfcSysInfo.u8PanelChannel == _DUAL)
731 {
732 //putstr("\r\nmsSetOutDClk(Dual)");
733 dwDClk /= 2;
734 }
735
736 //printf("\r\nLPLL[%x]", dwDClk>>16);
737 //printf("[%x]", dwDClk);
738 MDrv_MFC_Write3BytesINT(0x2A1E, dwDClk);
739 if(enableFPLL) MDrv_MFC_WriteBitINT(0x2A18, 1, _BIT3); // PLL set chnage Toggle
740 MDrv_MFC_WriteByte(0x2A0A, 0x24);// make frame lock faster
741
742 MDrv_MFC_SetLvdsSSC_INT(MFC_LVDS_SSC_SPAN_DEFAULT, MFC_LVDS_SSC_STEP_DEFAULT);
743 }
744
745 #else
746 // [u8Vfreq] for detected input frequence
747 // [u8VHzFrmT2] for panel frequence setting by front side
748 // [enableFPLL] FPLL enable/disable
749 U8 u8OPMReset=1;
MDrv_MFC_SetOutDClk(U16 u16InputfreqX100,BOOL enableFPLL)750 void MDrv_MFC_SetOutDClk(U16 u16InputfreqX100, BOOL enableFPLL)
751 {
752 U16 u16VTotal = gmfcSysInfo.u16VTotal;
753 U32 u32DClk ;
754
755 MDrv_MFC_WriteByte(0x2C49, (U8)(u16InputfreqX100/100));
756
757 if(enableFPLL&&u8OPMReset)
758 {
759 MDrv_MFC_SoftwareResetScalerInt();
760 u8OPMReset=0;
761 }
762
763 if(u16InputfreqX100>4500&&u16InputfreqX100<5500)
764 {
765 MDrv_MFC_WriteBit(0x2080, _DISABLE, _BIT0); // disable film32
766 }
767 else //if(u16InputfreqX100>=55&&u16InputfreqX100<65)
768 {
769 MDrv_MFC_WriteBit(0x2080, _ENABLE, _BIT0); // enable film32
770 }
771
772
773
774 // MUTEX_LOCK();
775 //printf("\n\n\n\n\nGet input freq from T2=[%d]\n\n\n\n\n", u16InputfreqX100);
776 if(!MDrv_MFC_GetInitStatus())
777 {
778 //MUTEX_UNLOCK();
779 return;
780 }
781 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle
782 u32DClk = MDrv_MFC_SetVCO(
783 CalculateDecimal(
784 Panel_Dclk_Hz(gmfcSysInfo.u16HTotal,
785 gmfcSysInfo.u16VTotal,
786 60/*u8Inputfreq*/),
787 1000000
788 ), gmfcSysInfo.u8PanelVfreq);
789 #if 0
790 if (u8Inputfreq==50)
791 {
792 if (gmfcSysInfo.u8PanelIncVtotalFor50Hz)
793 {
794 u16VTotal = u16VTotal*6/5;
795 }
796 else
797 {
798 u32DClk = u32DClk*5/6;
799 }
800 }
801 #else
802 if (gmfcSysInfo.u8PanelIncVtotalFor50Hz)
803 {
804 u16VTotal = (U16)((U32)u16VTotal*6000/u16InputfreqX100);
805 }
806 else
807 {
808 u32DClk = u32DClk*u16InputfreqX100/6000;
809 }
810 #endif
811 //MDrv_MFC_WriteByte(0x2A1A,MDrv_MFC_ReadByte(0x2A1A)|0x03);
812 MDrv_MFC_WriteBit(0x2A18, 0, _BIT3); // PLL set chnage Toggle
813 MDrv_MFC_Write2Bytes(0x2F02, u16VTotal-1);
814
815 if (gmfcSysInfo.u8PanelType == _MINI_LVDS
816 || gmfcSysInfo.u8PanelType == _RSDS
817 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP
818 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
819 {
820 if(gmfcSysInfo.u8PanelVfreq == 60)
821 u32DClk = (U32)PANEL_DCLK_FACTOR_TCON_60 / u32DClk;
822 else
823 u32DClk = (U32)PANEL_DCLK_FACTOR_TCON / u32DClk;
824 }
825 else
826 u32DClk = (U32)PANEL_DCLK_FACTOR / u32DClk;
827
828 if (gmfcSysInfo.u8PanelChannel == _QUAD || gmfcSysInfo.u8PanelChannel == _QUAD_LR)
829 {
830 //printf("\n u32DClk=%d", u32DClk);
831 }
832 else if(gmfcSysInfo.u8PanelChannel == _DUAL)
833 {
834 //printf("\nmsSetOutDClk(Dual)");
835 u32DClk /= 2;
836 }
837 MDrv_MFC_Write3Bytes(0x2A1E, u32DClk);
838 if(enableFPLL) MDrv_MFC_WriteBit(0x2A18, 1, _BIT3); // PLL set chnage Toggle
839 MDrv_MFC_WriteByte(0x2A0A, 0x24);// make frame lock faster
840
841 MDrv_MFC_SetLvdsSSC(MFC_LVDS_SSC_SPAN_DEFAULT, MFC_LVDS_SSC_STEP_DEFAULT);
842 //MUTEX_UNLOCK();
843 //printk("MDrv_MFC_SetOutDclk()\n");
844 }
845 #endif
846
847
MDrv_MFC_LPLL_Initialize(void)848 void MDrv_MFC_LPLL_Initialize(void)
849 {
850 MDrv_MFC_Write2Bytes(0x2A5C, 0xffec);
851 MDrv_MFC_WriteBit(0x2A06, 0, _BIT5); // power gating
852
853 if (gmfcSysInfo.u8PanelType == _MINI_LVDS || gmfcSysInfo.u8PanelType ==_MINI_LVDS_GIP || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
854 {
855 MDrv_MFC_WriteByte(0x2A03, 0x01); //div_2nd
856 MDrv_MFC_WriteBit(0x2A06, 0, _BIT7); //dual to quad mode
857 MDrv_MFC_WriteByte(0x2A02, 0x03); //div_1st
858 MDrv_MFC_WriteBit(0x2A04, 1, _BIT0); // mini_en
859 MDrv_MFC_WriteByteMask(0x2A56, 0, _BIT5 | _BIT4); //sel_432m // v_by1_en
860 MDrv_MFC_WriteBit(0x2A5C, 1, _BIT6); //sel_216m
861 MDrv_MFC_WriteByteMask(0x2A5A, _BIT3, _BIT3|_BIT2); //test bus = 8
862 }
863 else
864 {
865 if (gmfcSysInfo.u8PanelChannel == _DUAL)
866 {
867 MDrv_MFC_WriteByte(0x2A03, 0x04); //div_1st
868 MDrv_MFC_WriteBit(0x2A06, 0, _BIT7); //dual to quad mode
869 }
870 else if (gmfcSysInfo.u8PanelChannel == _QUAD || gmfcSysInfo.u8PanelChannel == _QUAD_LR)
871 {
872 MDrv_MFC_WriteByte(0x2A03, 0x04);
873 MDrv_MFC_WriteBit(0x2A06, (TwoChip_Func)?0:1, _BIT7); //dual to quad mode
874 }
875 else if (gmfcSysInfo.u8PanelChannel == _V_BY1)
876 {
877 MDrv_MFC_WriteByte(0x2A03, 0x01);
878 MDrv_MFC_WriteBit(0x2A06, 0, _BIT7); //dual to quad mode
879 }
880 else //single
881 {
882 MDrv_MFC_WriteByte(0x2A03, 0x04); //div_1st
883 MDrv_MFC_WriteBit(0x2A06, 0, _BIT7); //dual to quad mode
884 }
885 MDrv_MFC_WriteByte(0x2A02, 0x03);
886 MDrv_MFC_WriteBit(0x2A04, 0, _BIT0); // mini_en
887 MDrv_MFC_WriteByteMask(0x2A56, 0, _BIT5 | _BIT4); //sel_432m // v_by1_en
888 MDrv_MFC_WriteBit(0x2A5C, 1, _BIT6); //sel_216m
889 MDrv_MFC_WriteByteMask(0x2A5A, 0, _BIT3|_BIT2); //test bus = 0
890 //printk("MDrv_MFC_InitializeLPLL()\n");
891 }
892 }
893
894 code MST_MFC_RegUnitType_t tInitializeDispLpll[]=
895 {
896 {0x2A00, LPLL_INPUT_DIVIDER_1ST},
897 {0x2A01, LPLL_INPUT_DIVIDER_2ND},
898 //{0x2A03, 0x04},
899 //{0x2A06, 0x02},
900 {0x2A82,0x45}, //AuPll
901 {0x2A83,0x01}, //AuPll
902 {0x2AA8,0x10},//Bit4, AuPll Lock En
903 {0x2A0B, 0xC0}, // lock thr,
904 {0x2A0C, 0x00}, //0x01, // limit_d5d6d7
905 {0x2A0D, 0x00}, //0x80, // limit_d5d6d7
906 {0x2A0E, 0x01}, //0x06, // limit_d5d6d7
907 {0x2A0F, 0x00},
908 {0x2A12, 0x03}, // limit_d5d6d7
909 {0x2A14, 0x00},
910 {0x2A15, 0xd0},//0x80, //j090105 for Tvbox fpll lock
911 {0x2A16, 0x00}, // {p_gain_prd[3:0] ,i_gain_prd[3:0]}
912 #if(CODEBASE_SEL == CODEBASE_51)
913 {0x2A1B, 0x07}, // sel ovs as clock div
914 #else
915 {0x2A1B, 0x06}, // sel ovs as clock div (FPLL do not check no_signal flag when TTL input)
916 #endif
917 {_END_OF_TBL_, _END_OF_TBL_},
918 };
919
920 code MST_MFC_RegUnitType_t tInitializeDispTgen[]=
921 {
922 #if(PANEL_TYPE_SEL ==PNL_TVBOX_1080P_60HZ)
923 {0x2F06, 0x10},
924 #endif
925 {0x2F2E, 0x01}, // 0x07 -> test pattern
926 {_END_OF_TBL_, _END_OF_TBL_},
927 };
928
MDrv_MFC_InitializeDispTgen(void)929 void MDrv_MFC_InitializeDispTgen(void)
930 {
931 // DISP_TGEN
932 #if (CODEBASE_SEL == CODEBASE_51)
933 #if (REG_DIRECT_ACCESS_BY_I2C)
934 if (gmfcSysInfo.u8Preset == 0x01)
935 #endif
936 #endif
937 {
938 MDrv_MFC_Write2Bytes(0x2F02, gmfcSysInfo.u16VTotal-1);
939 MDrv_MFC_Write2Bytes(0x2F04, gmfcSysInfo.u16HTotal/((TwoChip_Func)?2:1)-1);
940 MDrv_MFC_Write2Bytes(0x2F14, gmfcSysInfo.u16VStart);
941 MDrv_MFC_Write2Bytes(0x2F16, gmfcSysInfo.u16VStart+gmfcSysInfo.u16Height-1);
942
943 #if ( TwoChip_Func == TwoChip_Master )
944 MDrv_MFC_Write2Bytes(0x2F18, gmfcSysInfo.u16HStart/2);
945 MDrv_MFC_Write2Bytes(0x2F1A, MDrv_MFC_DE_XEnd(gmfcSysInfo.u16Width));
946 #elif ( TwoChip_Func == TwoChip_Slave )
947 MDrv_MFC_Write2Bytes(0x2F18, gmfcSysInfo.u16HStart/2 -Cable_effect);
948 MDrv_MFC_Write2Bytes(0x2F1A, MDrv_MFC_DE_XEnd(gmfcSysInfo.u16Width) - Cable_effect );
949 #else
950 MDrv_MFC_Write2Bytes(0x2F18, gmfcSysInfo.u16HStart);
951 MDrv_MFC_Write2Bytes(0x2F1A, MDrv_MFC_DE_XEnd(gmfcSysInfo.u16Width));
952 #endif
953 }
954
955 MDrv_MFC_Write2Bytes(0x2F1C, gmfcSysInfo.u16VStart);
956 MDrv_MFC_Write2Bytes(0x2F1E, gmfcSysInfo.u16VStart+gmfcSysInfo.u16Height-1);
957
958 #if ( TwoChip_Func == TwoChip_Master )
959 MDrv_MFC_Write2Bytes(0x2F20, gmfcSysInfo.u16HStart/2);
960 MDrv_MFC_Write2Bytes(0x2F22, MDrv_MFC_DE_XEnd(gmfcSysInfo.u16Width));
961 #elif ( TwoChip_Func == TwoChip_Slave )
962 MDrv_MFC_Write2Bytes(0x2F20, gmfcSysInfo.u16HStart/2 -Cable_effect);
963 MDrv_MFC_Write2Bytes(0x2F22, 0x040d);//DE_XEnd2(gmfcSysInfo.u16Width -Cable_effect)); //j090508
964 #else
965 MDrv_MFC_Write2Bytes(0x2F20, gmfcSysInfo.u16HStart);
966 MDrv_MFC_Write2Bytes(0x2F22, MDrv_MFC_DE_XEnd(gmfcSysInfo.u16Width));
967 #endif
968
969 MDrv_MFC_WriteRegsTbl(0x2F00, tInitializeDispTgen); // initialize all of bank
970 MDrv_MFC_WriteRegsTbl(0x2A00, tInitializeDispLpll);
971 if((gmfcSysInfo.u16VStart+gmfcSysInfo.u16Height)> gmfcSysInfo.u16VTotal)
972 MDrv_MFC_Write2Bytes(0x2F06, gmfcSysInfo.u16VStart+gmfcSysInfo.u16Height -gmfcSysInfo.u16VTotal);//Vtrig_Y
973 else
974 MDrv_MFC_Write2Bytes(0x2F06, gmfcSysInfo.u16VStart+gmfcSysInfo.u16Height+31);//Vtrig_Y
975 MDrv_MFC_Write2Bytes(0x2F08, (gmfcSysInfo.u16HStart+gmfcSysInfo.u16Width+15)/((TwoChip_Func)?2:1)); //Vtrig_X
976 MDrv_MFC_LPLL_Initialize();
977 MDrv_MFC_SetGainPhase();
978
979 #if(CODEBASE_SEL == CODEBASE_51)
980 msSetOutDClk(60, 0, TRUE);
981 #else
982 MDrv_MFC_SetInitStatus(1);
983 MDrv_MFC_SetOutDClk(6000, TRUE);
984 MDrv_MFC_SetInitStatus(0);
985 #endif
986
987 #ifdef FrameVt_Change
988 MDrv_MFC_WriteBit(0x2A1A, 1, _BIT0); //
989 #endif
990
991 if (gmfcSysInfo.u8PanelType == _RSDS)
992 {
993 MDrv_MFC_WriteByte(0x1E0E, 0x04); // [3:0]od clk:[2]=1:1/2,[1]=1:inverse,[0]=1:gating; [7:4]op2 sram;
994 MDrv_MFC_WriteByteMask(0x3200, _BIT1|_BIT0, _BIT1|_BIT0); // for od path, [1]=1:od, =0:mft
995 MDrv_MFC_WriteBit(0x3201, 1, _BIT1); // [1]=1, dual/quad mode
996 //MDrv_MFC_WriteByteMask(0x2A06, _BIT7|_BIT6, _BIT7|_BIT6); // [7]=1:LPLL double; [6]=1:LPLL type for Rsds
997 }
998 else if (gmfcSysInfo.u8PanelType == _TTL)
999 {
1000 MDrv_MFC_WriteByte(0x1E0E, 0x04); // [3:0]od clk:[2]=1:1/2,[1]=1:inverse,[0]=1:gating; [7:4]op2 sram;
1001 MDrv_MFC_WriteByteMask(0x3200, _BIT1|_BIT0, _BIT1|_BIT0); // for od path, [1]=1:od, =0:mft
1002 MDrv_MFC_WriteBit(0x3201, 0, _BIT1); // [1]=1, dual/quad mode
1003 //MDrv_MFC_WriteByteMask(0x2A06, _BIT7|_BIT1|_BIT0, _BIT7|_BIT1|_BIT0); // [7]=1:LPLL double;
1004 }
1005 else
1006 {
1007 if ( (gmfcSysInfo.u8LVDSChannel==_SINGLE && gmfcSysInfo.u8PanelChannel==_SINGLE))
1008 {
1009 MDrv_MFC_WriteByte(0x1E0E, 0x04); // [3:0]od clk:[2]=1:1/2,[1]=1:inverse,[0]=1:gating; [7:4]op2 sram;
1010 MDrv_MFC_WriteByteMask(0x3200, _BIT0, _BIT1|_BIT0); // for od path, [1]=1:od, =0:mft
1011 }
1012 else
1013 {
1014 // calvin 1222, 0x00->0x02
1015 if (gmfcSysInfo.u8PanelType == _MINI_LVDS || gmfcSysInfo.u8PanelType ==_MINI_LVDS_GIP || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
1016 {
1017 MDrv_MFC_WriteByte(0x1E0E, 0x02); // [3:0]od clk:[2]=1:1/2,[1]=1:inverse,[0]=1:gating; [7:4]op2 sram;
1018 if(S7M) // for DPM
1019 {
1020 MDrv_MFC_WriteBit(0x1E22, 0, _BIT1); // DPM gpio1 enable.
1021 MDrv_MFC_WriteBit(0x1E1A, 1, _BIT1); // DPM enable.
1022 MDrv_MFC_WriteBit(0x1E22, 0, _BIT3); // gpio3 enable.
1023 MDrv_MFC_WriteBit(0x1E1A, 0, _BIT3); // gpio3 set to Low.
1024 }
1025 }
1026 else
1027 {
1028 MDrv_MFC_WriteByte(0x1E0E, 0x00); // [3:0]od clk:[2]=1:1/2,[1]=1:inverse,[0]=1:gating; [7:4]op2 sram;
1029 }
1030 MDrv_MFC_WriteByteMask(0x3200, _BIT0, _BIT1|_BIT0); // for od path, [1]=1:od, =0:mft
1031
1032 #if(PANEL_TYPE_SEL == PNL_INN26_WXGA_120HZ)
1033 MDrv_MFC_WriteByte(0x1E0E, 0x00);
1034 #endif
1035 }
1036
1037 if ((gmfcSysInfo.u8LVDSChannel==_SINGLE && gmfcSysInfo.u8PanelChannel==_DUAL)
1038 || (gmfcSysInfo.u8LVDSChannel==_DUAL && (gmfcSysInfo.u8PanelChannel==_QUAD || gmfcSysInfo.u8PanelChannel==_QUAD_LR)))
1039 {
1040 MDrv_MFC_WriteBit(0x3201, 1, _BIT1); // [1]=1, dual/quad mode
1041 // MDrv_MFC_WriteByteMask(0x2A06, _BIT7, _BIT7|_BIT6); // [7]=1:LPLL double; [6]=0:LPLL type for Lvds
1042 #if ( (PANEL_TYPE_SEL == PNL_LC320WXD_WXGA_120HZ) || (PANEL_TYPE_SEL == PNL_LC150OLED_WXGA_120HZ) || (PANEL_TYPE_SEL == PNL_LC150OLED_WXGA_60HZ) )
1043 MDrv_MFC_WriteBit(0x3201, 0, _BIT1);
1044 // MDrv_MFC_WriteByteMask(0x2A06, 0, _BIT7|_BIT6);
1045 #endif
1046 #ifdef Mst_func_3DDemo
1047 // msWriteBit(0x2A06, 0, _BIT7);
1048 #endif
1049 }
1050 else
1051 {
1052 MDrv_MFC_WriteBit(0x3201, 0, _BIT1);
1053 //MDrv_MFC_WriteByteMask(0x2A06, 0, _BIT7|_BIT6); // [7]=0:LPLL normal; [6]=0:LPLL type for Lvds
1054 }
1055
1056 if ((gmfcSysInfo.u8PanelType == _MINI_LVDS) || (gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP) ||(gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5))
1057 {
1058 MDrv_MFC_WriteByte(0x2A05, 0x28);
1059 //MDrv_MFC_WriteByte(0x2A04, 0x01);
1060 MDrv_MFC_WriteByteMask(0x3275, _BIT7 , _BIT7); //j080912 for power consumption
1061 }
1062 //else if ( (gmfcSysInfo.u8PanelType == _LVDS) || (gmfcSysInfo.u8PanelType == _TTL) )
1063 //MDrv_MFC_WriteByteMask(0x2A04, 0 , _BIT0); //j080912 for power consumption
1064 }
1065
1066 if(gmfcMiuBaseAddr.u8GammaMode == GAMMA_OFF)
1067 MDrv_MFC_WriteByteMask(0x1E0E, _BIT6, _BIT6); //disable op2_sramclk
1068
1069 //printk("MDrv_MFC_InitializeDispTgen()\n");
1070 }
1071
1072
1073 /*
1074 LVDS output selection:
1075 0x320B[6]TI mode, [5]=0:pair shift, [3]Polarity swap, [2]pair swap
1076 0x320A=0x08:8bits TI mode, 0x0C:6bits TI mode, 0x00:others
1077 0x321F:LVDS channel swap,
1078 [1:0]Aout, [3:2]Bout, [5:4]Cout, [7:6]Dout,
1079 '00b'Ain, '01b'Bin, '10b'Cin, '11b'Din
1080 */
1081 //_RSDS
1082 code MST_MFC_RegUnitType_t tInitializeScTop1[]=
1083 {
1084 {0x3205, 0x08}, // Rsds mode
1085 {0x320B, 0x20}, // lvds THine mode(h5[14]=0)
1086
1087 {0x3220, 0x55}, // set output configure to rsds data output = "01" for 26 channel
1088 {0x3221, 0x55}, // rsds clk output = "11"
1089 {0x3222, 0x57}, //
1090 {0x3223, 0x55}, //
1091 {0x3224, 0x55}, //
1092 {0x3225, 0x5d}, //
1093 {0x3226, 0x05}, //
1094 {0x3228, 0xff}, // set ttl_oe = "11" when rsds output for 26 channel
1095 {0x3229, 0xff}, //
1096 {0x322A, 0xff}, //
1097 {0x322B, 0xff}, //
1098 {0x322C, 0xff}, //
1099 {0x322D, 0xff}, //
1100 {0x322E, 0x0f}, //
1101 {0x3230, 0x00}, // reg_ext_en = 26'h0
1102 {0x3231, 0x00}, //
1103 {0x3232, 0x00}, //
1104 {0x3233, 0x00}, //
1105 {0x324E, 0x0f}, // enable mod_atop IB,CLK
1106 {0x324F, 0x10},
1107 {0x3250, 0x00}, // 0x4c,
1108 {0x3253, 0x80}, // enable da bias
1109 {_END_OF_TBL_, _END_OF_TBL_},
1110 };
1111
1112 //Pre-Emphasis setting (for Gip)
1113 code MST_MFC_RegUnitType_t tIniTconCommPreEmphasis[]=
1114 {
1115 {0x3242, 0xff},
1116 {0x3243, 0xff},
1117 {0x3244, 0xff},
1118 {0x3245, 0x03},
1119
1120 // {0x324E, 0x0f}, //enable IB, CLK
1121 // {0x324F, 0x00}, //enable IB, CLK //George recommand 090722
1122 {0x3268, 0xff},
1123 {0x3269, 0x03},
1124 {_END_OF_TBL_, _END_OF_TBL_},
1125 };
1126
1127 // _MINI_LVDS
1128 code MST_MFC_RegUnitType_t tInitializeScTop2_Comm[]=
1129 {
1130 {0x3200, 0x01}, //[9]quad mode
1131 {0x3201, 0x02},
1132 {0x3204, 0x00}, //en CRC
1133 {0x3205, 0x80},
1134 {0x320A, 0x00}, //[14]LVDS TI mode, [13]pdp10 bit
1135 {0x320B, 0x20},
1136 {0x3220, 0x55},
1137 {0x3221, 0x57},
1138 //{0x3222, 0x5D},//0x59,//[3:2]=10, use mini-lvds clock configuration for right---I-Chang 09092008 //j090210
1139 {0x3223, 0x54},
1140 {0x3224, 0x5D},
1141 //{0x3225, 0x75},//0x65,//[13:12]=10, use mini-lvds clock configuration for left---I-Chang 09092008//j090210
1142 {0x3226, 0x00},
1143 {0x3227, 0x00},
1144 {0x3228, 0xff},
1145 {0x3229, 0xff},
1146 {0x322A, 0xff},
1147 {0x322B, 0xff},
1148 {0x322C, 0xff},
1149 {0x322D, 0xff},
1150 {0x322E, 0x0f},
1151 {0x322F, 0x00},
1152 {0x3230, 0xff},
1153 {0x3231, 0xff},
1154 {0x3232, 0xff},
1155 {0x3233, 0x03},
1156
1157 {0x3242, 0xff},
1158 {0x3243, 0xff},
1159 {0x3244, 0xff},
1160 {0x3245, 0x03},
1161 {0x3246, 0x00},
1162 {0x3247, 0x00},
1163 {0x3248, 0x00},
1164 {0x3249, 0x00},
1165 {0x324E, 0x0f}, //enable IB, CLK
1166 {0x324F, 0x31}, //enable IB, CLK
1167 {0x3250, (0x48|MOD_POWER_ON_AFTER_INIT)}, //swing
1168 {0x3251, 0x00},
1169 {0x3252, 0x00}, //enable da bias
1170 {0x3253, 0x80},
1171 {0x3254, 0x04}, //ch26~35 type
1172 {0x3255, 0x00},
1173 {0x3256, 0x00}, //ch26~35 type
1174 {0x3257, 0x00},
1175 {0x3260, 0xff}, //reg_gpo_oez_ch26_35---------------------------0826_I-Chang
1176 {0x3261, 0xff},
1177 {0x3262, 0x0f}, //reg_gpo_oez_ch26_35
1178 {0x3263, 0x00},
1179 {0x3264, 0x00}, //ch26~35 extern enable
1180 {0x3265, 0x00},
1181 {0x3270, 0x80}, //[7]reg_tcon_en [4]reg_tcon_swap---------------------------0826_I-Chang
1182 {0x3271, 0x00},
1183 {0x3272, 0x00},
1184 {0x3273, 0xc6}, //[15:8]reg_mini_ch_swap
1185 {0x3276, 0xFC},
1186 {_END_OF_TBL_, _END_OF_TBL_},
1187 };
1188
1189 // _MINI_LVDS_GIP
1190 code MST_MFC_RegUnitType_t tInitializeScTop2_GIP[]=
1191 {
1192 {0x3200, 0x01}, //[9]quad mode
1193 {0x3201, 0x02},
1194 {0x3204, 0x00}, //en CRC
1195 {0x3205, 0x80},
1196 {0x320A, 0x00}, //[14]LVDS TI mode, [13]pdp10 bit
1197 {0x320B, 0x20},
1198
1199 {0x3220, 0x55},
1200 {0x3221, 0x57},
1201 {0x3222, 0x04},
1202 {0x3223, 0x54},
1203 {0x3224, 0x5d},
1204 {0x3225, 0x11},
1205 {0x3226, 0x00},
1206 {0x3227, 0x00},
1207 {0x3228, 0xff},
1208 {0x3229, 0xff},
1209 {0x322A, 0xff},
1210 {0x322B, 0xff},
1211 {0x322C, 0xff},
1212 {0x322D, 0xff},
1213 {0x322E, 0x0f},
1214 {0x322F, 0x00},
1215
1216 {0x3240, 0x10}, //[15]reg_mini [7]msb_p [6]msb_s [4]data_swap
1217 {0x3241, 0x80},
1218 {0x3246, 0x00},
1219 {0x3247, 0x00},
1220 {0x3248, 0x00},
1221 {0x3249, 0x00},
1222 //{0x324E, 0x0f}, //enable IB, CLK
1223 //{0x324F, 0x4c}, //enable IB, CLK //George recommand 090722
1224 {0x3250, (0x48|MOD_POWER_ON_AFTER_INIT)},//0x52, //swing
1225 {0x3253, 0xc0},//0x81,
1226
1227 {0x3251, 0x00},
1228 {0x3252, 0xc0}, //enable da bias //George recommand 090722
1229 {0x3254, 0x04}, //ch26~35 type
1230 {0x3255, 0x00},
1231 {0x3256, 0x00}, //ch26~35 type
1232 {0x3257, 0x00},
1233 {0x3260, 0xff}, //reg_gpo_oez_ch26_35---------------------------0826_I-Chang
1234 {0x3261, 0xff},
1235 {0x3262, 0x0f}, //reg_gpo_oez_ch26_35
1236 {0x3263, 0x00},
1237 {0x3264, 0x00}, //ch26~35 extern enable
1238 {0x3265, 0x00},
1239 //{0x3270, 0x80}, //[7]reg_tcon_en [4]reg_tcon_swap-----0826_I-Chang //j081031
1240 {0x3271, 0x00},
1241 {0x3272, 0x00},
1242 {0x3273, 0xc6}, //[15:8]reg_mini_ch_swap
1243 {_END_OF_TBL_, _END_OF_TBL_},
1244 };
1245
1246 //TTL
1247 code MST_MFC_RegUnitType_t tInitializeScTop3[]=
1248 {
1249 {0x3220, 0x00}, // set output configure to TTL output
1250 {0x3221, 0x00}, //
1251 {0x3222, 0x00}, //
1252 {0x3223, 0x00}, //
1253 {0x3224, 0x00}, //
1254 {0x3225, 0x00}, //
1255 {0x3226, 0x00}, //
1256
1257 {0x3228, 0xff}, // set ttl_oe = "11" when lvds output for 26 channel
1258 {0x3229, 0xff}, //
1259 {0x322A, 0xff}, //
1260 {0x322B, 0xff}, //
1261 {0x322C, 0xff}, //
1262 {0x322D, 0xff}, //
1263 {0x322E, 0x0f}, //
1264
1265 {0x3230, 0x00}, // reg_ext_en = 26'h0
1266 {0x3231, 0x00}, //
1267 {0x3232, 0x00}, //
1268 {0x3233, 0x00}, //
1269 {0x3234, 0xff}, // reg_ext_en = 26'h0
1270 {0x3235, 0xff}, //
1271 {0x3236, 0xff}, //
1272 {0x3237, 0x03}, //
1273
1274 {0x324E, 0x0f}, // enable mod_atop IB,CLK
1275 {0x3250, 0x4c}, // Bruce for Ursa 2 new setting; Ursa 1 is null register.
1276 {0x3253, 0x80}, // enable da bias
1277
1278 {0x3254, 0x00},
1279 {0x3255, 0x00},
1280 {0x3256, 0x00},
1281 {0x3257, 0x00},
1282 {0x3264, 0x00},
1283 {0x3265, 0x00},
1284 {0x3266, 0xFF},
1285 {0x3267, 0x03},
1286 {_END_OF_TBL_, _END_OF_TBL_},
1287 };
1288
1289 //LVDS
1290 code MST_MFC_RegUnitType_t tInitializeScTop4[]=
1291 {
1292 #if (CODEBASE_SEL == CODEBASE_51 || CODEBASE_SEL==CODEBASE_UTOPIA)
1293 {0x3220, 0x55}, // set output configure to lvds output = "01" for 26 channel
1294 {0x3221, 0x55}, //
1295 {0x3222, 0x55}, //
1296 {0x3223, 0x55}, //
1297 {0x3224, 0x55}, //
1298 {0x3225, 0x55}, //
1299 {0x3226, 0x05}, //
1300 #endif
1301 {0x3228, 0xff}, // set ttl_oe = "11" when lvds output for 26 channel
1302 {0x3229, 0xff}, //
1303 {0x322A, 0xff}, //
1304 {0x322B, 0xff}, //
1305 {0x322C, 0xff}, //
1306 {0x322D, 0xff}, //
1307 {0x322E, 0x0f}, //
1308
1309 {0x3230, 0x00}, // reg_ext_en = 26'h0
1310 {0x3231, 0x00}, //
1311 {0x3232, 0x00}, //
1312 {0x3233, 0x00}, //
1313 {0x324E, 0x0f}, // enable mod_atop IB,CLK
1314 {0x3250, (0x46|MOD_POWER_ON_AFTER_INIT)}, //swing
1315 {0x3253, 0x80}, // enable da bias
1316
1317 {0x3254, 0x55}, // Bruce for Ursa 2
1318 {0x3255, 0x55}, // Bruce for Ursa 2
1319 {0x3256, 0x05}, // Bruce for Ursa 2
1320 {_END_OF_TBL_, _END_OF_TBL_},
1321 };
1322
MDrv_MFC_InitializeScTop(void)1323 void MDrv_MFC_InitializeScTop(void)
1324 {
1325 MDrv_MFC_WriteBit(0x30BF, 1, _BIT6);
1326
1327 #if(CODEBASE_SEL == CODEBASE_LINUX)
1328 if((gmfcSysInfo.u8PanelType == _MINI_LVDS
1329 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP
1330 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
1331 && (gmfcSysInfo.u8PanelBitNum == _8BITS)
1332 )
1333 {
1334 MDrv_MFC_Write2Bytes(0x30C4, 0x0100);
1335 MDrv_MFC_Write2Bytes(0x30C6, 0x0100);
1336 MDrv_MFC_Write2Bytes(0x30C8, 0x0100);
1337 }
1338 else
1339 #endif
1340 {
1341 MDrv_MFC_Write2Bytes(0x30C4, 0x0403);
1342 MDrv_MFC_Write2Bytes(0x30C6, 0x0403);
1343 MDrv_MFC_Write2Bytes(0x30C8, 0x0403);
1344 }
1345
1346 if (gmfcSysInfo.u8PanelType == _MINI_LVDS
1347 || gmfcSysInfo.u8PanelType == _LVDS
1348 || gmfcSysInfo.u8PanelType == _TTL
1349 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP
1350 || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5)
1351 {
1352 //Auto no signal blue screen
1353 MDrv_MFC_WriteBit(0x3017, 1, _BIT3);
1354 MDrv_MFC_WriteBit(0x3017, 1, _BIT5);
1355 MDrv_MFC_WriteBit(0x3017, 1, _BIT6);
1356 if (gmfcSysInfo.u8PanelChannel == _QUAD_LR)
1357 {
1358 MDrv_MFC_Write2Bytes(0x3100, (gmfcSysInfo.u16Width+2)/4-1);
1359 MDrv_MFC_WriteBit(0x3101, 1, _BIT7);
1360 MDrv_MFC_WriteByte(0x3103, 0xa0);
1361 }
1362
1363 if (gmfcSysInfo.u8LVDSChannel==_SINGLE && gmfcSysInfo.u8PanelChannel==_SINGLE )
1364 {
1365 MDrv_MFC_WriteBit(0x3102, 1, _BIT4);
1366 MDrv_MFC_WriteByte(0x3105, 0x00); // [7]OD odd/even swap
1367 }
1368 else if(gmfcSysInfo.u8LVDSChannel!=gmfcSysInfo.u8PanelChannel)
1369 MDrv_MFC_WriteByte(0x3105, 0x00); // [7]OD odd/even swap
1370 else
1371 MDrv_MFC_WriteByte(0x3105, 0x80); // [7]OD odd/even swap
1372
1373 if ((gmfcSysInfo.u8PanelType == _MINI_LVDS) || (gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP) ||(gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5))
1374 {
1375 MDrv_MFC_WriteByte(0x3120, 0x80); //[15]oeswap [14]odd mode
1376 MDrv_MFC_WriteByte(0x3121, 0x80);
1377 #if (PANEL_TYPE_SEL == PNL_INN26_WXGA_120HZ)
1378 MDrv_MFC_WriteBit(0x3102, 0, _BIT5);//j090210
1379 #else
1380 MDrv_MFC_WriteBit(0x3102, 1, _BIT5); //LTD on
1381 #endif
1382 }
1383
1384 MDrv_MFC_WriteByte(0x320A, 0x00);
1385 if (gmfcSysInfo.u8PanelLVDSTiMode)
1386 {
1387 if (gmfcSysInfo.u8PanelBitNum==_8BITS)
1388 MDrv_MFC_WriteByte(0x320A, 0x08); // lvds TI 8bit(h5[3:2]=10)
1389 else if (gmfcSysInfo.u8PanelBitNum==_6BITS)
1390 MDrv_MFC_WriteByte(0x320A, 0x0C); // lvds TI 6bit(h5[3:2]=11)
1391 }
1392 if (gmfcSysInfo.u8PanelType == _TTL)
1393 MDrv_MFC_WriteBit(0x320A, 1, _BIT1);
1394 #if (CODEBASE_SEL == CODEBASE_51)
1395 #if (REG_DIRECT_ACCESS_BY_I2C)
1396 if (gmfcSysInfo.u8Preset == 0x01)
1397 #endif
1398 #endif
1399 {
1400 // [6]TI mode, [5]=0:pair shift, [3]Polarity swap, [2]pair swap
1401 MDrv_MFC_WriteByte(0x320B, (gmfcSysInfo.u8PanelLVDSTiMode?_BIT6:0)
1402 | (gmfcSysInfo.u8PanelLVDSShiftPair?0:_BIT5)
1403 | (gmfcSysInfo.u8PanelLVDSSwapPol?_BIT3:0)
1404 | (gmfcSysInfo.u8PanelLVDSSwapPair?_BIT2:0));
1405 MDrv_MFC_WriteByte(0x321F, gmfcSysInfo.u8PanelLVDSSwapCH); // channel swap
1406 }
1407 }
1408
1409 if(gmfcSysInfo.u8PanelType == _RSDS )
1410 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop1); //j081014
1411 else if(gmfcSysInfo.u8PanelType == _MINI_LVDS )
1412 {
1413 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_Comm);
1414 MDrv_MFC_InitializeScTop2_Bypanel();
1415 }
1416 else if(gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5 )
1417 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop2_GIP);
1418 else if(gmfcSysInfo.u8PanelType == _TTL )
1419 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop3);
1420 else //LVDS
1421 MDrv_MFC_WriteRegsTbl(0x3200, tInitializeScTop4);
1422
1423 //Pre-Emphasis setting
1424 if(gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP || gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5 )
1425 {
1426 MDrv_MFC_WriteRegsTbl(0x3200, tIniTconCommPreEmphasis);
1427
1428 if(gmfcSysInfo.u8ChipRevision==U02)
1429 {
1430 MDrv_MFC_Write2Bytes(0x324E, 0x400f);
1431 MDrv_MFC_Write2Bytes(0x3252, 0xc100);
1432 }
1433 else //U01
1434 {
1435 MDrv_MFC_Write2Bytes(0x324E, 0x4c0f);
1436 MDrv_MFC_Write2Bytes(0x3252, 0xc1c0);
1437 }
1438 }
1439 //printk("MDrv_MFC_InitializeScTop()\n");
1440 }
1441
1442 code MST_MFC_RegUnitType_t tInitializeFRC[]=
1443 {
1444 {0x307E, 0x17},
1445 {0x307F, 0x00},
1446 {0x3080, 0x23},
1447 {0x3081, 0x20},
1448 {0x3082, 0xf3},
1449 {0x3083, 0x3c},
1450 {0x3084, 0xc9},
1451 {0x3085, 0x9c},
1452 {0x3086, 0xc9},
1453 {0x3087, 0x9c},
1454 {0x3088, 0xaa},
1455 {0x3089, 0xaa},
1456 {0x308A, 0x50},
1457 {0x308B, 0x22},
1458 {0x308C, 0xd8},
1459 {0x308D, 0xd8},
1460 {0x308E, 0x72},
1461 {0x308F, 0x72},
1462 {0x3090, 0x8d},
1463 {0x3091, 0x8d},
1464 {0x3092, 0x27},
1465 {0x3093, 0xd8},
1466 {0x3094, 0x72},
1467 {0x3095, 0x8d},
1468 {_END_OF_TBL_, _END_OF_TBL_},
1469 };
1470
MDrv_MFC_InitializeOPMFC(void)1471 void MDrv_MFC_InitializeOPMFC(void)
1472 {
1473 if(gmfcSysInfo.u8PanelDither)
1474 {
1475 MDrv_MFC_WriteRegsTbl(0x3000, tInitializeFRC); // initialize all of bank
1476 }
1477 //printk("MDrv_MFC_InitializeOPMFC()\n");
1478 }
1479
MDrv_MFC_InitializeScalerOP(void)1480 void MDrv_MFC_InitializeScalerOP(void)
1481 {
1482 MDrv_MFC_InitializeDispTgen();
1483 MDrv_MFC_InitializeScTop();
1484 MDrv_MFC_WriteBit(0x2C42, MFC_ENABLE_LVDS_SSC, _BIT5); // enable ssc
1485 MDrv_MFC_SetLvdsSSC(MFC_LVDS_SSC_SPAN_DEFAULT, MFC_LVDS_SSC_STEP_DEFAULT);
1486 MDrv_MFC_InitializeOPMFC();
1487 //printk("MDrv_MFC_InitializeScalerOP()\n");
1488 }
1489
1490 #endif
1491