1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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76 //******************************************************************************
77 //<MStar Software>
78
79 #define _MHAL_MBX_INTERRUPT_C
80
81 //=============================================================================
82 // Include Files
83 //=============================================================================
84 #include "MsCommon.h"
85 #include "drvMBX.h"
86 #include "regMBXINT.h"
87 #include "halMBXINT.h"
88
89 //=============================================================================
90 // Compile options
91 //=============================================================================
92
93 //=============================================================================
94 // Local Defines
95 //=============================================================================
96
97 //=============================================================================
98 // Debug Macros
99 //=============================================================================
100 //#define MBXINT_DEBUG
101 #ifdef MBXINT_DEBUG
102 #define MBXINT_ERROR(fmt, args...) printf("[MBX INT Driver USER ERR][%06d] " fmt, __LINE__, ## args)
103 #define MBXINT_WARN(fmt, args...) printf("[MBX INT Driver WARN][%06d] " fmt, __LINE__, ## args)
104 #define MBXINT_PRINT(fmt, args...) printf("[MBX INT Driver][%06d] " fmt, __LINE__, ## args)
105 #define MBXINT_ASSERT(_cnd, _fmt, _args...) \
106 if (!(_cnd)) { \
107 MBXINT_PRINT(_fmt, ##_args); \
108 }
109 #else
110 #define MBXINT_ERROR(fmt, args...)
111 #define MBXINT_WARN(fmt, args...)
112 #define MBXINT_PRINT(fmt, args...)
113 #define MBXINT_ASSERT(_cnd, _fmt, _args...)
114 #endif
115
116 //=============================================================================
117 // Macros
118 //=============================================================================
119
120 //=============================================================================
121 // Local Variables
122 //=============================================================================
123 static MBX_MSGRECV_CB_FUNC _pMBXMsgRecvCbFunc = NULL;
124 static MS_U32 _u32RIUBaseAddrMBXINT = 0;
125
126 //=============================================================================
127 // Global Variables
128 //=============================================================================
129
130 //=============================================================================
131 // Local Function Prototypes
132 //=============================================================================
133 static void _MHAL_MBXINT_INTHandler(InterruptNum vector);
134 static MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID);
135
136 //=============================================================================
137 // Local Function
138 //=============================================================================
139
140 //-------------------------------------------------------------------------------------------------
141 /// Handle Interrupt, schedule tasklet
142 /// @param irq \b IN: interrupt number
143 /// @param dev_id \b IN: dev id
144 /// @return irqreturn_t: IRQ_HANDLED
145 /// @attention
146 /// <b>[MXLIB] <em></em></b>
147 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_INTHandler(InterruptNum eIntNum)148 void _MHAL_MBXINT_INTHandler(InterruptNum eIntNum)
149 {
150 if(NULL == _pMBXMsgRecvCbFunc)
151 {
152 return;
153 }
154
155 _pMBXMsgRecvCbFunc(eIntNum);
156
157 MsOS_EnableInterrupt(eIntNum);
158 }
159
160 //-------------------------------------------------------------------------------------------------
161 /// Set Interrupt to Host CPU ID: Enable related interrupt and attached related callback.
162 /// @param eHostCPUID \b IN: The Host CPU ID
163 /// @return E_MBX_SUCCESS
164 /// @attention
165 /// <b>[MXLIB] <em></em></b>
166 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)167 MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)
168 {
169 switch(eHostCPUID)
170 {
171 case E_MBX_CPU_PM:
172 {
173 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
174 MsOS_AttachInterrupt(E_INT_FIQ_MIPS_VPE0_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
175 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_8051);
176 MsOS_EnableInterrupt(E_INT_FIQ_MIPS_VPE0_TO_8051);
177 }
178 break;
179
180 case E_MBX_CPU_AEON:
181 {
182 MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
183 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
184 MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_AEON);
185 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_AEON);
186 }
187 break;
188
189 case E_MBX_CPU_MIPS:
190 {
191 MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_MIPS_VPE0, (InterruptCb)_MHAL_MBXINT_INTHandler);
192 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_BEON , (InterruptCb)_MHAL_MBXINT_INTHandler);
193 MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_MIPS_VPE0);
194 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_BEON);
195 }
196 break;
197
198 default:
199 return E_MBX_ERR_INVALID_CPU_ID;
200 }
201
202 return E_MBX_SUCCESS;
203 }
204
205 //=============================================================================
206 // Mailbox HAL Interrupt Driver Function
207 //=============================================================================
208
209 //-------------------------------------------------------------------------------------------------
210 /// Handle Interrupt INIT
211 /// @param eHostCPU \b IN: interrupt owner
212 /// @param pMBXRecvMsgCBFunc \b IN: callback func by driver
213 /// @param u32RIUBaseAddrMBXINT \b IN: RIU Base Addr with platform
214 /// @return E_MBX_ERR_INVALID_CPU_ID: the cpu id is wrong
215 /// @return E_MBX_UNKNOW_ERROR: request_irq failed;
216 /// @return E_MBX_SUCCESS: success;
217 /// @attention
218 /// <b>[MXLIB] <em></em></b>
219 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Init(MBX_CPU_ID eHostCPU,MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc,MS_U32 u32RIUBaseAddrMBXINT)220 MBX_Result MHAL_MBXINT_Init (MBX_CPU_ID eHostCPU, MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc, MS_U32 u32RIUBaseAddrMBXINT)
221 {
222 _pMBXMsgRecvCbFunc = pMBXRecvMsgCBFunc;
223 _u32RIUBaseAddrMBXINT = u32RIUBaseAddrMBXINT;
224
225 return _MHAL_MBXINT_SetHostCPU(eHostCPU);
226 }
227
228 //-------------------------------------------------------------------------------------------------
229 /// Handle Interrupt DeINIT
230 /// @param eHostCPU \b IN: interrupt owner
231 /// @return void;
232 /// @attention
233 /// <b>[MXLIB] <em></em></b>
234 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_DeInit(MBX_CPU_ID eHostCPU)235 void MHAL_MBXINT_DeInit (MBX_CPU_ID eHostCPU)
236 {
237 switch(eHostCPU)
238 {
239 case E_MBX_CPU_PM:
240 {
241 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_8051);
242 MsOS_DisableInterrupt(E_INT_FIQ_MIPS_VPE0_TO_8051);
243 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_8051);
244 MsOS_DetachInterrupt(E_INT_FIQ_MIPS_VPE0_TO_8051);
245 }
246 break;
247
248 case E_MBX_CPU_AEON:
249 {
250 MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_AEON);
251 MsOS_DisableInterrupt(E_INT_FIQ_MIPS_VPE0_TO_AEON);
252 MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_AEON);
253 MsOS_DetachInterrupt(E_INT_FIQ_MIPS_VPE0_TO_AEON);
254 }
255 break;
256
257 case E_MBX_CPU_MIPS:
258 {
259 MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_MIPS_VPE0);
260 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_MIPS_VPE0);
261 MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_MIPS_VPE0);
262 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_MIPS_VPE0);
263 }
264 break;
265
266 default:
267 break;
268 }
269 }
270
271 //-------------------------------------------------------------------------------------------------
272 /// Reset Host CPU for MBX Interrupt
273 /// @param ePrevCPU \b IN: previous host cpu id
274 /// @param eConfigCpu \b IN: new configed cpu id
275 /// @return E_MBX_SUCCESS: success;
276 /// @return E_MBX_INVALID_CPU_ID
277 /// @attention
278 /// <b>[MXLIB] <em></em></b>
279 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_ResetHostCPU(MBX_CPU_ID ePrevCPU,MBX_CPU_ID eConfigCpu)280 MBX_Result MHAL_MBXINT_ResetHostCPU (MBX_CPU_ID ePrevCPU, MBX_CPU_ID eConfigCpu)
281 {
282 MHAL_MBXINT_DeInit(ePrevCPU);
283
284 return _MHAL_MBXINT_SetHostCPU(eConfigCpu);
285 }
286
287 //-------------------------------------------------------------------------------------------------
288 /// Fire Interrupt
289 /// @param dstCPUID \b IN: dst cpu of interrupt
290 /// @param srcCPUID \b IN: src cpu of interrupt
291 /// @return E_MBX_SUCCESS: success;
292 /// @attention
293 /// <b>[MXLIB] <em></em></b>
294 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Fire(MBX_CPU_ID dstCPUID,MBX_CPU_ID srcCPUID)295 MBX_Result MHAL_MBXINT_Fire (MBX_CPU_ID dstCPUID, MBX_CPU_ID srcCPUID)
296 {
297 MBXINT_ASSERT((dstCPUID!=srcCPUID),"dst cpu is the same as src cpu!\n");
298
299 #if defined(MSOS_TYPE_NUTTX)
300 srcCPUID = E_MBX_CPU_AEON;
301 dstCPUID = E_MBX_CPU_MIPS;
302
303 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2;
304 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H2;
305
306 return E_MBX_SUCCESS;
307
308 #endif
309
310 switch(srcCPUID)
311 {
312 case E_MBX_CPU_PM:
313 {
314 if(dstCPUID==E_MBX_CPU_AEON)
315 {
316 //PM51-to-R2
317 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_AEON);
318 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON;
319 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON);
320 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
321 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
322 }
323 else
324 {
325 //PM51-to-ARM Core 0
326 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_H2);
327 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H2;
328 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H2);
329 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
330 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
331 }
332 }
333 break;
334
335 case E_MBX_CPU_AEON:
336 {
337 if(dstCPUID==E_MBX_CPU_PM)
338 {
339 //R2-to-PM51
340 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_PM);
341 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM;
342 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM);
343 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
344 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
345 }
346 else
347 {
348 //R2-to-ARM Core 0
349 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_H2);
350 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H2;
351 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H2);
352 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
353 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
354 }
355 }
356 break;
357
358 case E_MBX_CPU_MIPS:
359 {
360 if(dstCPUID==E_MBX_CPU_PM)
361 {
362 //ARM Core 0-to-PM51
363 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_H2_PM);
364 CPU_INT_REG(REG_INT_H2FIRE) |= INT_H2_PM;
365 CPU_INT_REG(REG_INT_H2FIRE) &= ~(INT_H2_PM);
366 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
367 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
368 }
369 else
370 {
371 //ARM Core 0-to-R2
372 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_H2_AEON);
373 CPU_INT_REG(REG_INT_H2FIRE) |= INT_H2_AEON;
374 CPU_INT_REG(REG_INT_H2FIRE) &= ~(INT_H2_AEON);
375 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
376 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
377 }
378 }
379 break;
380
381 default:
382 {
383 MBXINT_ASSERT(FALSE, "wrong src cpu!\n");
384 }
385 break;
386 }
387
388 return E_MBX_SUCCESS;
389 }
390
MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)391 MBX_Result MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)
392 {
393 if((eHKCPU == E_MBX_CPU_AEON) || \
394 (eHKCPU == E_MBX_CPU_MIPS) || \
395 (eHKCPU == E_MBX_CPU_MIPS_VPE1))
396 {
397 return E_MBX_SUCCESS;
398 }
399
400 MBXINT_ASSERT(FALSE, "[MHAL_MBXINT_CpuInit] Invalid HK CPU ID \n");
401
402 return E_MBX_ERR_INVALID_CPU_ID;
403 }
404