1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78
79 #define _MHAL_MBX_INTERRUPT_C
80
81 //=============================================================================
82 // Include Files
83 //=============================================================================
84 #include "MsCommon.h"
85 #include "drvMBX.h"
86 #include "regMBXINT.h"
87 #include "halMBXINT.h"
88 #include "ULog.h"
89
90 //=============================================================================
91 // Compile options
92 //=============================================================================
93
94 //=============================================================================
95 // Local Defines
96 //=============================================================================
97 #define TAG_MBX "MBX"
98
99 //=============================================================================
100 // Debug Macros
101 //=============================================================================
102 //#define MBXINT_DEBUG
103 #ifdef MBXINT_DEBUG
104 #define MBXINT_ERROR(fmt, args...) ULOGE(TAG_MBX, "[MBX INT Driver USER ERR][%06d] " fmt, __LINE__, ## args)
105 #define MBXINT_WARN(fmt, args...) ULOGW(TAG_MBX, "[MBX INT Driver WARN][%06d] " fmt, __LINE__, ## args)
106 #define MBXINT_PRINT(fmt, args...) ULOGD(TAG_MBX, "[MBX INT Driver][%06d] " fmt, __LINE__, ## args)
107 #define MBXINT_ASSERT(_cnd, _fmt, _args...) \
108 if (!(_cnd)) { \
109 MBXINT_PRINT(_fmt, ##_args); \
110 }
111 #else
112 #define MBXINT_ERROR(fmt, args...)
113 #define MBXINT_WARN(fmt, args...)
114 #define MBXINT_PRINT(fmt, args...)
115 #define MBXINT_ASSERT(_cnd, _fmt, _args...)
116 #endif
117
118 //=============================================================================
119 // Macros
120 //=============================================================================
121
122 //=============================================================================
123 // Local Variables
124 //=============================================================================
125 static MBX_MSGRECV_CB_FUNC _pMBXMsgRecvCbFunc = NULL;
126 static MS_VIRT _virtRIUBaseAddrMBXINT = 0;
127
128 //=============================================================================
129 // Global Variables
130 //=============================================================================
131
132 //=============================================================================
133 // Local Function Prototypes
134 //=============================================================================
135 static void _MHAL_MBXINT_INTHandler(InterruptNum vector);
136 static MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID);
137
138 //=============================================================================
139 // Local Function
140 //=============================================================================
141
142 //-------------------------------------------------------------------------------------------------
143 /// Handle Interrupt, schedule tasklet
144 /// @param irq \b IN: interrupt number
145 /// @param dev_id \b IN: dev id
146 /// @return irqreturn_t: IRQ_HANDLED
147 /// @attention
148 /// <b>[MXLIB] <em></em></b>
149 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_INTHandler(InterruptNum eIntNum)150 void _MHAL_MBXINT_INTHandler(InterruptNum eIntNum)
151 {
152 if(NULL == _pMBXMsgRecvCbFunc)
153 {
154 return;
155 }
156
157 _pMBXMsgRecvCbFunc(eIntNum);
158
159 MsOS_EnableInterrupt(eIntNum);
160 }
161
162 //-------------------------------------------------------------------------------------------------
163 /// Set Interrupt to Host CPU ID: Enable related interrupt and attached related callback.
164 /// @param eHostCPUID \b IN: The Host CPU ID
165 /// @return E_MBX_SUCCESS
166 /// @attention
167 /// <b>[MXLIB] <em></em></b>
168 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)169 MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)
170 {
171 switch(eHostCPUID)
172 {
173 case E_MBX_CPU_PM:
174 {
175 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
176 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
177 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_8051);
178 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_8051);
179 }
180 break;
181
182 case E_MBX_CPU_AEON:
183 {
184 MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
185 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
186 MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_AEON);
187 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_AEON);
188 }
189 break;
190
191 case E_MBX_CPU_MIPS:
192 {
193 MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
194 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
195 MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_BEON);
196 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_BEON);
197 }
198 break;
199
200 default:
201 return E_MBX_ERR_INVALID_CPU_ID;
202 }
203
204 return E_MBX_SUCCESS;
205 }
206
207 //=============================================================================
208 // Mailbox HAL Interrupt Driver Function
209 //=============================================================================
210
211 //-------------------------------------------------------------------------------------------------
212 /// Handle Interrupt INIT
213 /// @param eHostCPU \b IN: interrupt owner
214 /// @param pMBXRecvMsgCBFunc \b IN: callback func by driver
215 /// @param u32RIUBaseAddrMBXINT \b IN: RIU Base Addr with platform
216 /// @return E_MBX_ERR_INVALID_CPU_ID: the cpu id is wrong
217 /// @return E_MBX_UNKNOW_ERROR: request_irq failed;
218 /// @return E_MBX_SUCCESS: success;
219 /// @attention
220 /// <b>[MXLIB] <em></em></b>
221 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Init(MBX_CPU_ID eHostCPU,MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc,MS_VIRT virtRIUBaseAddrMBXINT)222 MBX_Result MHAL_MBXINT_Init (MBX_CPU_ID eHostCPU, MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc, MS_VIRT virtRIUBaseAddrMBXINT)
223 {
224 _pMBXMsgRecvCbFunc = pMBXRecvMsgCBFunc;
225 _virtRIUBaseAddrMBXINT = virtRIUBaseAddrMBXINT;
226
227 return _MHAL_MBXINT_SetHostCPU(eHostCPU);
228 }
229
230 //-------------------------------------------------------------------------------------------------
231 /// Handle Interrupt DeINIT
232 /// @param eHostCPU \b IN: interrupt owner
233 /// @return void;
234 /// @attention
235 /// <b>[MXLIB] <em></em></b>
236 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_DeInit(MBX_CPU_ID eHostCPU)237 void MHAL_MBXINT_DeInit (MBX_CPU_ID eHostCPU)
238 {
239 switch(eHostCPU)
240 {
241 case E_MBX_CPU_PM:
242 {
243 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_8051);
244 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_8051);
245 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_8051);
246 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_8051);
247 }
248 break;
249
250 case E_MBX_CPU_AEON:
251 {
252 MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_AEON);
253 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_AEON);
254 MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_AEON);
255 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_AEON);
256 }
257 break;
258
259 case E_MBX_CPU_MIPS:
260 {
261 MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_BEON);
262 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_BEON);
263 MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_BEON);
264 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_BEON);
265 }
266 break;
267
268 default:
269 break;
270 }
271 }
272
273 //-------------------------------------------------------------------------------------------------
274 /// Reset Host CPU for MBX Interrupt
275 /// @param ePrevCPU \b IN: previous host cpu id
276 /// @param eConfigCpu \b IN: new configed cpu id
277 /// @return E_MBX_SUCCESS: success;
278 /// @return E_MBX_INVALID_CPU_ID
279 /// @attention
280 /// <b>[MXLIB] <em></em></b>
281 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_ResetHostCPU(MBX_CPU_ID ePrevCPU,MBX_CPU_ID eConfigCpu)282 MBX_Result MHAL_MBXINT_ResetHostCPU (MBX_CPU_ID ePrevCPU, MBX_CPU_ID eConfigCpu)
283 {
284 MHAL_MBXINT_DeInit(ePrevCPU);
285
286 return _MHAL_MBXINT_SetHostCPU(eConfigCpu);
287 }
288
289 //-------------------------------------------------------------------------------------------------
290 /// Fire Interrupt
291 /// @param dstCPUID \b IN: dst cpu of interrupt
292 /// @param srcCPUID \b IN: src cpu of interrupt
293 /// @return E_MBX_SUCCESS: success;
294 /// @attention
295 /// <b>[MXLIB] <em></em></b>
296 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Fire(MBX_CPU_ID dstCPUID,MBX_CPU_ID srcCPUID)297 MBX_Result MHAL_MBXINT_Fire (MBX_CPU_ID dstCPUID, MBX_CPU_ID srcCPUID)
298 {
299 MBXINT_ASSERT((dstCPUID!=srcCPUID),"dst cpu is the same as src cpu!\n");
300
301 #if defined(MSOS_TYPE_NUTTX)
302 srcCPUID = E_MBX_CPU_AEON;
303 dstCPUID = E_MBX_CPU_MIPS;
304
305
306 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
307 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1;
308
309 return E_MBX_SUCCESS;
310
311 #endif
312
313 switch(srcCPUID)
314 {
315 case E_MBX_CPU_PM:
316 {
317 if(dstCPUID==E_MBX_CPU_AEON)
318 {
319 //PM51-to-R2
320 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_AEON);
321 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON;
322 //MBXINT_PRINT("[RIU ADDR] = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
323 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON);
324 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
325 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
326 }
327 else
328 {
329 //PM51-to-ARM Core 0
330 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_H3);
331 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1;
332 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1);
333 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
334 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
335 }
336 }
337 break;
338
339 case E_MBX_CPU_AEON:
340 {
341 if(dstCPUID==E_MBX_CPU_PM)
342 {
343 //R2-to-PM51
344 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_PM);
345 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM;
346 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM);
347 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
348 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
349 }
350 else
351 {
352 //R2-to-ARM Core 0
353 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_H3);
354 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
355 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1);
356 MBXINT_PRINT("FIQ [32-47] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
357 MBXINT_PRINT("FIQ [32-47] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
358 }
359 }
360 break;
361
362 case E_MBX_CPU_MIPS:
363 {
364 if(dstCPUID==E_MBX_CPU_PM)
365 {
366 //ARM Core 0-to-PM51
367 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_PM);
368 CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_PM;
369 CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_PM);
370 MBXINT_PRINT("FIQ [48-63] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
371 MBXINT_PRINT("FIQ [48-63] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
372 }
373 else
374 {
375 //ARM Core 0-to-R2
376 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_AEON);
377 CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_AEON;
378 CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_AEON);
379 MBXINT_PRINT("FIQ [48-63] Mask = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
380 MBXINT_PRINT("FIQ [48-63] Status = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
381 }
382 }
383 break;
384
385 default:
386 {
387 MBXINT_ASSERT(FALSE, "wrong src cpu!\n");
388 }
389 break;
390 }
391
392 return E_MBX_SUCCESS;
393 }
394
MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)395 MBX_Result MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)
396 {
397 if((eHKCPU == E_MBX_CPU_AEON) || \
398 (eHKCPU == E_MBX_CPU_MIPS) || \
399 (eHKCPU == E_MBX_CPU_MIPS_VPE1))
400 {
401 return E_MBX_SUCCESS;
402 }
403
404 MBXINT_ASSERT(FALSE, "[MHAL_MBXINT_CpuInit] Invalid HK CPU ID \n");
405
406 return E_MBX_ERR_INVALID_CPU_ID;
407 }
408