1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94 ///////////////////////////////////////////////////////////////////////////////////////////////////
95 ///
96 /// file halMBXINT.c
97 /// @brief MStar MailBox interrupt DDI
98 /// @author MStar Semiconductor Inc.
99 ///////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #define _MHAL_MBX_INTERRUPT_C
102
103 //=============================================================================
104 // Include Files
105 //=============================================================================
106 #include "MsCommon.h"
107 #include "drvMBX.h"
108 #include "regMBXINT.h"
109 #include "halMBXINT.h"
110
111 //=============================================================================
112 // Compile options
113 //=============================================================================
114
115
116 //=============================================================================
117 // Local Defines
118 //=============================================================================
119
120 //=============================================================================
121 // Debug Macros
122 //=============================================================================
123 //#define MBXINT_DEBUG
124 #ifdef MBXINT_DEBUG
125 #define MBXINT_ERROR(fmt, args...) printf("[MBX INT Driver USER ERR][%06d] " fmt, __LINE__, ## args)
126 #define MBXINT_WARN(fmt, args...) printf("[MBX INT Driver WARN][%06d] " fmt, __LINE__, ## args)
127 #define MBXINT_PRINT(fmt, args...) printf("[MBX INT Driver][%06d] " fmt, __LINE__, ## args)
128 #define MBXINT_ASSERT(_cnd, _fmt, _args...) \
129 if (!(_cnd)) { \
130 MBXINT_PRINT(_fmt, ##_args); \
131 }
132 #else
133 #define MBXINT_ERROR(fmt, args...)
134 #define MBXINT_WARN(fmt, args...)
135 #define MBXINT_PRINT(fmt, args...)
136 #define MBXINT_ASSERT(_cnd, _fmt, _args...)
137 #endif
138
139 //=============================================================================
140 // Macros
141 //=============================================================================
142
143 //=============================================================================
144 // Local Variables
145 //=============================================================================
146 static MBX_MSGRECV_CB_FUNC _pMBXMsgRecvCbFunc = NULL;
147 static MS_VIRT _virtRIUBaseAddrMBXINT = 0;
148
149 //=============================================================================
150 // Global Variables
151 //=============================================================================
152
153 //=============================================================================
154 // Local Function Prototypes
155 //=============================================================================
156 static void _MHAL_MBXINT_INTHandler(InterruptNum vector);
157 static MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID);
158
159 //=============================================================================
160 // Local Function
161 //=============================================================================
162
163 //-------------------------------------------------------------------------------------------------
164 /// Handle Interrupt, schedule tasklet
165 /// @param irq \b IN: interrupt number
166 /// @param dev_id \b IN: dev id
167 /// @return irqreturn_t: IRQ_HANDLED
168 /// @attention
169 /// <b>[MXLIB] <em></em></b>
170 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_INTHandler(InterruptNum eIntNum)171 void _MHAL_MBXINT_INTHandler(InterruptNum eIntNum)
172 {
173 if(NULL == _pMBXMsgRecvCbFunc)
174 {
175 return;
176 }
177
178 _pMBXMsgRecvCbFunc(eIntNum);
179
180 MsOS_EnableInterrupt(eIntNum);
181 }
182
183 //-------------------------------------------------------------------------------------------------
184 /// Set Interrupt to Host CPU ID: Enable related interrupt and attached related callback.
185 /// @param eHostCPUID \b IN: The Host CPU ID
186 /// @return E_MBX_SUCCESS
187 /// @attention
188 /// <b>[MXLIB] <em></em></b>
189 //-------------------------------------------------------------------------------------------------
_MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)190 MBX_Result _MHAL_MBXINT_SetHostCPU(MBX_CPU_ID eHostCPUID)
191 {
192 #if defined(CONFIG_FRC)//frcr2_integration###
193 switch(eHostCPUID)
194 {
195 case E_MBX_CPU_R2FRC:
196 MsOS_AttachInterrupt(E_FRCINT_FIQ_HST0_TO_HST1, (InterruptCb)_MHAL_MBXINT_INTHandler);
197 MsOS_EnableInterrupt(E_FRCINT_FIQ_HST0_TO_HST1); //enable host0(HKCPU/Non-PM Intr) to host1(frc-r2)
198 MsOS_EnableInterrupt(E_FRCINT_FIQ_HST1_TO_HST0); //enable host1(frc-r2) to host0(HKCPU/Non-PM Intr)
199 break;
200
201 default:
202 return E_MBX_ERR_INVALID_CPU_ID;
203 }
204 #else
205 switch(eHostCPUID)
206 {
207 case E_MBX_CPU_PM:
208 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
209 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_8051, (InterruptCb)_MHAL_MBXINT_INTHandler);
210 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_8051);
211 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_8051);
212 break;
213 case E_MBX_CPU_AEON:
214 //MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
215 MsOS_AttachInterrupt(E_INT_FIQ_BEON_TO_AEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
216 //MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_AEON);
217 MsOS_EnableInterrupt(E_INT_FIQ_BEON_TO_AEON);
218 break;
219 case E_MBX_CPU_MIPS:
220 MsOS_AttachInterrupt(E_INT_FIQ_8051_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
221 MsOS_AttachInterrupt(E_INT_FIQ_AEON_TO_BEON, (InterruptCb)_MHAL_MBXINT_INTHandler);
222 MsOS_AttachInterrupt(E_INT_IRQ_FRC_INT_FIQ2HST0, (InterruptCb)_MHAL_MBXINT_INTHandler);//frcr2_integration###
223
224 MsOS_EnableInterrupt(E_INT_FIQ_8051_TO_BEON);
225 MsOS_EnableInterrupt(E_INT_FIQ_AEON_TO_BEON);
226 MsOS_EnableInterrupt(E_INT_IRQ_FRC_INT_FIQ2HST0);//frcr2_integration###
227 break;
228
229 default:
230 return E_MBX_ERR_INVALID_CPU_ID;
231 }
232 #endif
233 return E_MBX_SUCCESS;
234 }
235
236 //=============================================================================
237 // Mailbox HAL Interrupt Driver Function
238 //=============================================================================
239
240 //-------------------------------------------------------------------------------------------------
241 /// Handle Interrupt INIT
242 /// @param eHostCPU \b IN: interrupt owner
243 /// @param pMBXRecvMsgCBFunc \b IN: callback func by driver
244 /// @param u32RIUBaseAddrMBXINT \b IN: RIU Base Addr with platform
245 /// @return E_MBX_ERR_INVALID_CPU_ID: the cpu id is wrong
246 /// @return E_MBX_UNKNOW_ERROR: request_irq failed;
247 /// @return E_MBX_SUCCESS: success;
248 /// @attention
249 /// <b>[MXLIB] <em></em></b>
250 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Init(MBX_CPU_ID eHostCPU,MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc,MS_VIRT virtRIUBaseAddrMBXINT)251 MBX_Result MHAL_MBXINT_Init (MBX_CPU_ID eHostCPU, MBX_MSGRECV_CB_FUNC pMBXRecvMsgCBFunc, MS_VIRT virtRIUBaseAddrMBXINT)
252 {
253 _pMBXMsgRecvCbFunc = pMBXRecvMsgCBFunc;
254 _virtRIUBaseAddrMBXINT = virtRIUBaseAddrMBXINT;
255
256 return _MHAL_MBXINT_SetHostCPU(eHostCPU);
257 }
258
259 //-------------------------------------------------------------------------------------------------
260 /// Handle Interrupt DeINIT
261 /// @param eHostCPU \b IN: interrupt owner
262 /// @return void;
263 /// @attention
264 /// <b>[MXLIB] <em></em></b>
265 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_DeInit(MBX_CPU_ID eHostCPU)266 void MHAL_MBXINT_DeInit (MBX_CPU_ID eHostCPU)
267 {
268 #if defined(CONFIG_FRC)//frcr2_integration###
269 switch(eHostCPU)
270 {
271 case E_MBX_CPU_R2FRC:
272 MsOS_DisableInterrupt(E_FRCINT_FIQ_HST1_TO_HST0); //disable host1(frc-r2) to host0(HKCPU/Non-PM Intr)
273 MsOS_DisableInterrupt(E_FRCINT_FIQ_HST0_TO_HST1); //disable host0(HKCPU/Non-PM Intr) to host1(frc-r2)
274 MsOS_DetachInterrupt(E_FRCINT_FIQ_HST0_TO_HST1);
275 break;
276
277 default:
278 break;
279 }
280 #else
281 switch(eHostCPU)
282 {
283 case E_MBX_CPU_PM:
284 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_8051);
285 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_8051);
286 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_8051);
287 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_8051);
288 break;
289 case E_MBX_CPU_AEON:
290 //MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_AEON);
291 MsOS_DisableInterrupt(E_INT_FIQ_BEON_TO_AEON);
292 //MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_AEON);
293 MsOS_DetachInterrupt(E_INT_FIQ_BEON_TO_AEON);
294 break;
295 case E_MBX_CPU_MIPS:
296 MsOS_DisableInterrupt(E_INT_FIQ_8051_TO_BEON);
297 MsOS_DisableInterrupt(E_INT_FIQ_AEON_TO_BEON);
298 MsOS_DisableInterrupt(E_INT_IRQ_FRC_INT_FIQ2HST0);//frcr2_integration###
299 MsOS_DetachInterrupt(E_INT_FIQ_8051_TO_BEON);
300 MsOS_DetachInterrupt(E_INT_FIQ_AEON_TO_BEON);
301 MsOS_DetachInterrupt(E_INT_IRQ_FRC_INT_FIQ2HST0);//frcr2_integration###
302 break;
303 default:
304 break;
305 }
306 #endif
307 }
308
309 //-------------------------------------------------------------------------------------------------
310 /// Reset Host CPU for MBX Interrupt
311 /// @param ePrevCPU \b IN: previous host cpu id
312 /// @param eConfigCpu \b IN: new configed cpu id
313 /// @return E_MBX_SUCCESS: success;
314 /// @return E_MBX_INVALID_CPU_ID
315 /// @attention
316 /// <b>[MXLIB] <em></em></b>
317 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_ResetHostCPU(MBX_CPU_ID ePrevCPU,MBX_CPU_ID eConfigCpu)318 MBX_Result MHAL_MBXINT_ResetHostCPU (MBX_CPU_ID ePrevCPU, MBX_CPU_ID eConfigCpu)
319 {
320 MHAL_MBXINT_DeInit(ePrevCPU);
321
322 return _MHAL_MBXINT_SetHostCPU(eConfigCpu);
323 }
324
325 //-------------------------------------------------------------------------------------------------
326 /// Fire Interrupt
327 /// @param dstCPUID \b IN: dst cpu of interrupt
328 /// @param srcCPUID \b IN: src cpu of interrupt
329 /// @return E_MBX_SUCCESS: success;
330 /// @attention
331 /// <b>[MXLIB] <em></em></b>
332 //-------------------------------------------------------------------------------------------------
MHAL_MBXINT_Fire(MBX_CPU_ID dstCPUID,MBX_CPU_ID srcCPUID)333 MBX_Result MHAL_MBXINT_Fire (MBX_CPU_ID dstCPUID, MBX_CPU_ID srcCPUID)
334 {
335 MBXINT_ASSERT((dstCPUID!=srcCPUID),"dst cpu is the same as src cpu!\n");
336
337 #if defined(MSOS_TYPE_NUTTX)
338 srcCPUID = E_MBX_CPU_AEON;
339 dstCPUID = E_MBX_CPU_MIPS;
340
341
342 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
343 CPU_INT_REG(REG_INT_AEONFIRE) &= ~INT_AEON_H1;
344 return E_MBX_SUCCESS;
345 #endif
346
347 #if defined(CONFIG_FRC)//frcr2_integration###
348 switch(srcCPUID)
349 {
350 case E_MBX_CPU_R2FRC:
351 if(dstCPUID==E_MBX_CPU_MIPS)
352 {
353 FRC_CPU_INT_REG(REG_FRCINT_FRCR2FIRE) |= INT_FRCR2_HKCPU;
354 FRC_CPU_INT_REG(REG_FRCINT_FRCR2FIRE) &= ~(INT_FRCR2_HKCPU);
355 MBXINT_PRINT("FIA [0-15]M = 0x%x\n", FIQ_FRCREG(REG_FRCFIQ_H0_0_15));
356 MBXINT_PRINT("FIQ [0-15]S = 0x%x\n", FIQ_FRCREG(REG_FRCFIQS_H0_0_15));
357 }
358
359 break;
360 default:
361 MBXINT_ASSERT(FALSE,"wrong src cpu!\n");
362 break;
363 }
364 return E_MBX_SUCCESS;
365
366 #endif
367
368 switch(srcCPUID)
369 {
370 case E_MBX_CPU_PM:
371 if(dstCPUID==E_MBX_CPU_AEON)
372 {
373 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_AEON);
374 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_AEON;
375 //MBXINT_PRINT("[RIU ADDR] = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
376 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_AEON);
377 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
378 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
379 }
380 else
381 { // PM 2 MIPS
382 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_PM_H3);
383 CPU_INT_REG(REG_INT_PMFIRE) |= INT_PM_H1;
384 CPU_INT_REG(REG_INT_PMFIRE) &= ~(INT_PM_H1);
385 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
386 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
387 }
388
389 break;
390 case E_MBX_CPU_AEON:
391 if(dstCPUID==E_MBX_CPU_PM)
392 {
393 // AEON 2 PM
394 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_PM);
395 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_PM;
396 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_PM);
397 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
398 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
399 }
400 else
401 {
402 // AEON 2 MIPS
403 //FIQ_REG(REG_FIQ_H1_32_47) &= ~(INT_FIQMASK_AEON_H3);
404 CPU_INT_REG(REG_INT_AEONFIRE) |= INT_AEON_H1;
405 CPU_INT_REG(REG_INT_AEONFIRE) &= ~(INT_AEON_H1);
406 MBXINT_PRINT("FIA [32-47]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_32_47));
407 MBXINT_PRINT("FIQ [32-47]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_32_47));
408 }
409
410 break;
411 case E_MBX_CPU_MIPS:
412 if(dstCPUID==E_MBX_CPU_PM)
413 {
414 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_PM);
415 CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_PM;
416 CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_PM);
417 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
418 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
419 }
420 else if(dstCPUID==E_MBX_CPU_AEON)
421 {
422 //FIQ_REG(REG_FIQ_H1_48_63) &= ~(INT_FIQMASK_H3_AEON);
423 CPU_INT_REG(REG_INT_H1FIRE) |= INT_H1_AEON;
424 CPU_INT_REG(REG_INT_H1FIRE) &= ~(INT_H1_AEON);
425 MBXINT_PRINT("FIA [48-63]M = 0x%x\n", FIQ_REG(REG_FIQ_H1_48_63));
426 MBXINT_PRINT("FIQ [48-63]S = 0x%x\n", FIQ_REG(REG_FIQS_H1_48_63));
427 }
428 #if 1//frcr2_integration###
429 else if(dstCPUID==E_MBX_CPU_R2FRC)
430 {
431 FRC_CPU_INT_REG(REG_FRCINT_HKCPUFIRE) |= INT_HKCPU_FRCR2;
432 FRC_CPU_INT_REG(REG_FRCINT_HKCPUFIRE) &= ~(INT_HKCPU_FRCR2);
433 MBXINT_PRINT("FIA [0-15]M = 0x%x\n", FIQ_FRCREG(REG_FRCFIQ_H1_0_15));
434 MBXINT_PRINT("FIQ [0-15]S = 0x%x\n", FIQ_FRCREG(REG_FRCFIQS_H1_0_15));
435 }
436 #endif
437
438 break;
439 default:
440 MBXINT_ASSERT(FALSE,"wrong src cpu!\n");
441 break;
442 }
443
444 return E_MBX_SUCCESS;
445 }
446
MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)447 MBX_Result MHAL_MBXINT_CpuInit(MBX_CPU_ID eHKCPU)
448 {
449 if((eHKCPU == E_MBX_CPU_AEON) || (eHKCPU == E_MBX_CPU_MIPS) ||
450 (eHKCPU == E_MBX_CPU_MIPS_VPE1) || (eHKCPU == E_MBX_CPU_R2FRC)) //frcr2_integration###
451 {
452 return E_MBX_SUCCESS;
453 }
454 MBXINT_ASSERT(FALSE, "[MHAL_MBXINT_CpuInit] Invalid HK CPU ID \n");
455 return E_MBX_ERR_INVALID_CPU_ID;
456 }
457