1*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
2*53ee8cc1Swenshuai.xi //
3*53ee8cc1Swenshuai.xi // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4*53ee8cc1Swenshuai.xi // All rights reserved.
5*53ee8cc1Swenshuai.xi //
6*53ee8cc1Swenshuai.xi // Unless otherwise stipulated in writing, any and all information contained
7*53ee8cc1Swenshuai.xi // herein regardless in any format shall remain the sole proprietary of
8*53ee8cc1Swenshuai.xi // MStar Semiconductor Inc. and be kept in strict confidence
9*53ee8cc1Swenshuai.xi // ("MStar Confidential Information") by the recipient.
10*53ee8cc1Swenshuai.xi // Any unauthorized act including without limitation unauthorized disclosure,
11*53ee8cc1Swenshuai.xi // copying, use, reproduction, sale, distribution, modification, disassembling,
12*53ee8cc1Swenshuai.xi // reverse engineering and compiling of the contents of MStar Confidential
13*53ee8cc1Swenshuai.xi // Information is unlawful and strictly prohibited. MStar hereby reserves the
14*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom.
15*53ee8cc1Swenshuai.xi //
16*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
17*53ee8cc1Swenshuai.xi
18*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
19*53ee8cc1Swenshuai.xi ///
20*53ee8cc1Swenshuai.xi /// file halLDM.c
21*53ee8cc1Swenshuai.xi /// @brief local dimming Driver HAL Interface
22*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
23*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
24*53ee8cc1Swenshuai.xi
25*53ee8cc1Swenshuai.xi
26*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
27*53ee8cc1Swenshuai.xi // Include Files
28*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
29*53ee8cc1Swenshuai.xi
30*53ee8cc1Swenshuai.xi #include <string.h>
31*53ee8cc1Swenshuai.xi #include "MsCommon.h"
32*53ee8cc1Swenshuai.xi #include "MsTypes.h"
33*53ee8cc1Swenshuai.xi #include "halLDM.h"
34*53ee8cc1Swenshuai.xi #include "regLDM.h"
35*53ee8cc1Swenshuai.xi
36*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
37*53ee8cc1Swenshuai.xi // Debug Functions
38*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
39*53ee8cc1Swenshuai.xi #define LD_WriteByte(reg,val) WRITE_BYTE((u32VirtLdBaseAddr + ((reg)<<2)),val)
40*53ee8cc1Swenshuai.xi
41*53ee8cc1Swenshuai.xi #define LD_Write2Byte(reg,val) WRITE_WORD((u32VirtLdBaseAddr + ((reg)<<2)),val)
42*53ee8cc1Swenshuai.xi
43*53ee8cc1Swenshuai.xi #define LD_ReadByte(reg) (READ_BYTE(u32VirtLdBaseAddr + ((reg)<<2)))
44*53ee8cc1Swenshuai.xi
45*53ee8cc1Swenshuai.xi #define LD_Read2Byte(reg) (READ_WORD(u32VirtLdBaseAddr + ((reg)<<2)))
46*53ee8cc1Swenshuai.xi
47*53ee8cc1Swenshuai.xi #define SUBBANK_LD_60HZ (0x2E) //sub bank 2E for local dimmig 60hz
48*53ee8cc1Swenshuai.xi #define SUBBANK_LD_120HZ (0xCE) //sub bank CE for local dimmig 120hz
49*53ee8cc1Swenshuai.xi #define SUBBANK_FO_BKC9 (0xC9) //sub bank c9 for data select 60/120hz
50*53ee8cc1Swenshuai.xi
51*53ee8cc1Swenshuai.xi static MS_U8 u8Subbank = SUBBANK_LD_120HZ;
52*53ee8cc1Swenshuai.xi
53*53ee8cc1Swenshuai.xi #define HAL_SUBBANKC9 LD_WriteByte(0,SUBBANK_FO_BKC9)
54*53ee8cc1Swenshuai.xi #define HAL_SUBBANKLD LD_WriteByte(0,u8Subbank)
55*53ee8cc1Swenshuai.xi #define HAL_SUBBANKOFF LD_WriteByte(0,0xFF)
56*53ee8cc1Swenshuai.xi
57*53ee8cc1Swenshuai.xi static MS_U32 u32VirtLdBaseAddr = BASEADDR_RIU + REG_LD_BASE;
58*53ee8cc1Swenshuai.xi
59*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
60*53ee8cc1Swenshuai.xi /// Description : Config LDMA MMIO base address
61*53ee8cc1Swenshuai.xi /// @param u32PMBankBaseAddr \b IN:base address of MMIO (PM domain)
62*53ee8cc1Swenshuai.xi /// @param u32NONPMRegBaseAddr \b IN :base address of MMIO
63*53ee8cc1Swenshuai.xi /// @param u8DeviceIndex \b IN: index of HW IP
64*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
HAL_LDM_MMIOConfig(MS_U32 u32NONPMRegBaseAddr,MS_U8 u8ClkHz)65*53ee8cc1Swenshuai.xi void HAL_LDM_MMIOConfig(MS_U32 u32NONPMRegBaseAddr, MS_U8 u8ClkHz)
66*53ee8cc1Swenshuai.xi {
67*53ee8cc1Swenshuai.xi u32VirtLdBaseAddr = u32NONPMRegBaseAddr + REG_LD_BASE;
68*53ee8cc1Swenshuai.xi
69*53ee8cc1Swenshuai.xi if(u8ClkHz == 60)
70*53ee8cc1Swenshuai.xi {
71*53ee8cc1Swenshuai.xi HAL_SUBBANKC9;
72*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_FO_DATA_PATH,0x0100);
73*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
74*53ee8cc1Swenshuai.xi u8Subbank = SUBBANK_LD_60HZ;
75*53ee8cc1Swenshuai.xi }
76*53ee8cc1Swenshuai.xi else if(u8ClkHz == 120)
77*53ee8cc1Swenshuai.xi {
78*53ee8cc1Swenshuai.xi //LMDA path sel
79*53ee8cc1Swenshuai.xi HAL_SUBBANKC9;
80*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_FO_DATA_PATH,0x0000);
81*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
82*53ee8cc1Swenshuai.xi u8Subbank = SUBBANK_LD_120HZ;
83*53ee8cc1Swenshuai.xi }
84*53ee8cc1Swenshuai.xi else //default set 60HZ timming
85*53ee8cc1Swenshuai.xi {
86*53ee8cc1Swenshuai.xi //LMDA path sel
87*53ee8cc1Swenshuai.xi HAL_SUBBANKC9;
88*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_FO_DATA_PATH,0x0100);
89*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
90*53ee8cc1Swenshuai.xi u8Subbank = SUBBANK_LD_60HZ;
91*53ee8cc1Swenshuai.xi }
92*53ee8cc1Swenshuai.xi return;
93*53ee8cc1Swenshuai.xi }
94*53ee8cc1Swenshuai.xi
HAL_LDM_SetLDFAddr(MS_U8 u8AddIndex,MS_U32 u32LDFAddr_l,MS_U32 u32LDFAddr_r)95*53ee8cc1Swenshuai.xi void HAL_LDM_SetLDFAddr(MS_U8 u8AddIndex, MS_U32 u32LDFAddr_l,MS_U32 u32LDFAddr_r)
96*53ee8cc1Swenshuai.xi {
97*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
98*53ee8cc1Swenshuai.xi switch(u8AddIndex)
99*53ee8cc1Swenshuai.xi {
100*53ee8cc1Swenshuai.xi case 0:
101*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR0_LOW_L,u32LDFAddr_l&0xFFFF);
102*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR0_HIGH_L,u32LDFAddr_l >> 16);
103*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR0_LOW_R,u32LDFAddr_r&0xFFFF);
104*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR0_HIGH_R,u32LDFAddr_r >> 16);
105*53ee8cc1Swenshuai.xi break;
106*53ee8cc1Swenshuai.xi case 1:
107*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR1_LOW_L,u32LDFAddr_l&0xFFFF);
108*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR1_HIGH_L,u32LDFAddr_l >> 16);
109*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR1_LOW_R,u32LDFAddr_r&0xFFFF);
110*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDF_BASEADDR1_HIGH_R,u32LDFAddr_r >> 16);
111*53ee8cc1Swenshuai.xi break;
112*53ee8cc1Swenshuai.xi default:
113*53ee8cc1Swenshuai.xi break;
114*53ee8cc1Swenshuai.xi }
115*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
116*53ee8cc1Swenshuai.xi return ;
117*53ee8cc1Swenshuai.xi }
118*53ee8cc1Swenshuai.xi
HAL_LDM_SetEdge2DAddr(MS_U32 u32Edge2DAddr)119*53ee8cc1Swenshuai.xi void HAL_LDM_SetEdge2DAddr(MS_U32 u32Edge2DAddr)
120*53ee8cc1Swenshuai.xi {
121*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
122*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_EDGE_2D_BASEADDR_LOW,u32Edge2DAddr&0xFFFF);
123*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_EDGE_2D_BASEADDR_HIGH,u32Edge2DAddr >> 16);
124*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
125*53ee8cc1Swenshuai.xi return ;
126*53ee8cc1Swenshuai.xi }
127*53ee8cc1Swenshuai.xi
HAL_LDM_SetLDBAddr(MS_U8 u8AddIndex,MS_U32 u32LDBAddr_l,MS_U32 u32LDBAddr_r)128*53ee8cc1Swenshuai.xi void HAL_LDM_SetLDBAddr(MS_U8 u8AddIndex, MS_U32 u32LDBAddr_l,MS_U32 u32LDBAddr_r)
129*53ee8cc1Swenshuai.xi {
130*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
131*53ee8cc1Swenshuai.xi switch(u8AddIndex)
132*53ee8cc1Swenshuai.xi {
133*53ee8cc1Swenshuai.xi case 0:
134*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR0_LOW_L,u32LDBAddr_l&0xFFFF);
135*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR0_HIGH_L,u32LDBAddr_l >> 16);
136*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR0_LOW_R,u32LDBAddr_r&0xFFFF);
137*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR0_HIGH_R,u32LDBAddr_r >> 16);
138*53ee8cc1Swenshuai.xi break;
139*53ee8cc1Swenshuai.xi case 1:
140*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR1_LOW_L,u32LDBAddr_l&0xFFFF);
141*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR1_HIGH_L,u32LDBAddr_l >> 16);
142*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR1_LOW_R,u32LDBAddr_r&0xFFFF);
143*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LDB_BASEADDR1_HIGH_R,u32LDBAddr_r >> 16);
144*53ee8cc1Swenshuai.xi break;
145*53ee8cc1Swenshuai.xi default:
146*53ee8cc1Swenshuai.xi break;
147*53ee8cc1Swenshuai.xi }
148*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
149*53ee8cc1Swenshuai.xi return ;
150*53ee8cc1Swenshuai.xi }
151*53ee8cc1Swenshuai.xi
HAL_LDM_SetMIUPackOffset(MS_U8 u8Channel,MS_U8 u8PackOffset)152*53ee8cc1Swenshuai.xi void HAL_LDM_SetMIUPackOffset(MS_U8 u8Channel,MS_U8 u8PackOffset )
153*53ee8cc1Swenshuai.xi {
154*53ee8cc1Swenshuai.xi if(u8PackOffset > 0x1F) //bit 0 ~bit4
155*53ee8cc1Swenshuai.xi {
156*53ee8cc1Swenshuai.xi printf("fun:%s @@error:Set MIU PackOffset Outof Range!!!\n",__FUNCTION__);
157*53ee8cc1Swenshuai.xi return ;
158*53ee8cc1Swenshuai.xi }
159*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
160*53ee8cc1Swenshuai.xi switch(u8Channel)
161*53ee8cc1Swenshuai.xi {
162*53ee8cc1Swenshuai.xi case LDMA0: //DMA0
163*53ee8cc1Swenshuai.xi LD_WriteByte(REG_PACK_OFFSET0,u8PackOffset);
164*53ee8cc1Swenshuai.xi break;
165*53ee8cc1Swenshuai.xi case LDMA1: //DMA1
166*53ee8cc1Swenshuai.xi LD_WriteByte(REG_PACK_OFFSET1,u8PackOffset);
167*53ee8cc1Swenshuai.xi break;
168*53ee8cc1Swenshuai.xi default:
169*53ee8cc1Swenshuai.xi break;
170*53ee8cc1Swenshuai.xi }
171*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
172*53ee8cc1Swenshuai.xi return ;
173*53ee8cc1Swenshuai.xi }
HAL_LDM_SetMIUPackLength(MS_U8 u8Channel,MS_U8 u8PackLength)174*53ee8cc1Swenshuai.xi void HAL_LDM_SetMIUPackLength(MS_U8 u8Channel,MS_U8 u8PackLength)
175*53ee8cc1Swenshuai.xi {
176*53ee8cc1Swenshuai.xi if(u8PackLength > 0x1F) //bit 0 ~bit4
177*53ee8cc1Swenshuai.xi {
178*53ee8cc1Swenshuai.xi printf("fun:%s @@error:Set MIU PackLength Outof Range!!!\n",__FUNCTION__);
179*53ee8cc1Swenshuai.xi return ;
180*53ee8cc1Swenshuai.xi }
181*53ee8cc1Swenshuai.xi
182*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
183*53ee8cc1Swenshuai.xi switch(u8Channel)
184*53ee8cc1Swenshuai.xi {
185*53ee8cc1Swenshuai.xi case LDMA0: //DMA0
186*53ee8cc1Swenshuai.xi LD_WriteByte(REG_PACK_LENGTH0,(LD_Read2Byte(REG_PACK_LENGTH0)&(~0x1F))|u8PackLength);
187*53ee8cc1Swenshuai.xi break;
188*53ee8cc1Swenshuai.xi case LDMA1: //DMA1
189*53ee8cc1Swenshuai.xi LD_WriteByte(REG_PACK_LENGTH1,(LD_Read2Byte(REG_PACK_LENGTH1)&(~0x1F))|u8PackLength);
190*53ee8cc1Swenshuai.xi break;
191*53ee8cc1Swenshuai.xi default:
192*53ee8cc1Swenshuai.xi break;
193*53ee8cc1Swenshuai.xi }
194*53ee8cc1Swenshuai.xi
195*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
196*53ee8cc1Swenshuai.xi return ;
197*53ee8cc1Swenshuai.xi }
HAL_LDM_SetYoffEnd(MS_U8 u8Channel,MS_U8 u8YoffEnd)198*53ee8cc1Swenshuai.xi void HAL_LDM_SetYoffEnd(MS_U8 u8Channel,MS_U8 u8YoffEnd)
199*53ee8cc1Swenshuai.xi {
200*53ee8cc1Swenshuai.xi if(u8YoffEnd > 0x3F) //bit 0~bit5
201*53ee8cc1Swenshuai.xi {
202*53ee8cc1Swenshuai.xi printf("fun:%s @@error:Set YoffEnd Outof Range!!!\n",__FUNCTION__);
203*53ee8cc1Swenshuai.xi return ;
204*53ee8cc1Swenshuai.xi }
205*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
206*53ee8cc1Swenshuai.xi switch(u8Channel)
207*53ee8cc1Swenshuai.xi {
208*53ee8cc1Swenshuai.xi case LDMA0: //DMA0
209*53ee8cc1Swenshuai.xi LD_WriteByte(REG_DMA_YOFF_END_0,u8YoffEnd);
210*53ee8cc1Swenshuai.xi break;
211*53ee8cc1Swenshuai.xi case LDMA1: //DMA1
212*53ee8cc1Swenshuai.xi LD_WriteByte(REG_DMA_YOFF_END_1,u8YoffEnd);
213*53ee8cc1Swenshuai.xi break;
214*53ee8cc1Swenshuai.xi default:
215*53ee8cc1Swenshuai.xi break;
216*53ee8cc1Swenshuai.xi }
217*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
218*53ee8cc1Swenshuai.xi return ;
219*53ee8cc1Swenshuai.xi }
HAL_LDM_SetDmaEnable(MS_U8 u8Channel,MS_BOOL Enable)220*53ee8cc1Swenshuai.xi void HAL_LDM_SetDmaEnable(MS_U8 u8Channel, MS_BOOL Enable)
221*53ee8cc1Swenshuai.xi {
222*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
223*53ee8cc1Swenshuai.xi switch(u8Channel)
224*53ee8cc1Swenshuai.xi {
225*53ee8cc1Swenshuai.xi case LDMA0: //DMA0
226*53ee8cc1Swenshuai.xi if(Enable)
227*53ee8cc1Swenshuai.xi {
228*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_PACK_LENGTH0,LD_Read2Byte(REG_PACK_LENGTH0)|REG_DMA0_ENABLE_BIT);
229*53ee8cc1Swenshuai.xi }
230*53ee8cc1Swenshuai.xi else
231*53ee8cc1Swenshuai.xi {
232*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_PACK_LENGTH1,LD_Read2Byte(REG_PACK_LENGTH1)&(~REG_DMA1_ENABLE_BIT));
233*53ee8cc1Swenshuai.xi }
234*53ee8cc1Swenshuai.xi break;
235*53ee8cc1Swenshuai.xi case LDMA1: //DMA1
236*53ee8cc1Swenshuai.xi if(Enable)
237*53ee8cc1Swenshuai.xi {
238*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_PACK_LENGTH1,LD_Read2Byte(REG_PACK_LENGTH1)|REG_DMA0_ENABLE_BIT);
239*53ee8cc1Swenshuai.xi }
240*53ee8cc1Swenshuai.xi else
241*53ee8cc1Swenshuai.xi {
242*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_PACK_LENGTH1,LD_Read2Byte(REG_PACK_LENGTH1)&(~REG_DMA0_ENABLE_BIT));
243*53ee8cc1Swenshuai.xi }
244*53ee8cc1Swenshuai.xi break;
245*53ee8cc1Swenshuai.xi default:
246*53ee8cc1Swenshuai.xi break;
247*53ee8cc1Swenshuai.xi }
248*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
249*53ee8cc1Swenshuai.xi return ;
250*53ee8cc1Swenshuai.xi }
251*53ee8cc1Swenshuai.xi
HAL_LDM_SetBlHeightDMA(MS_U8 u8Height)252*53ee8cc1Swenshuai.xi void HAL_LDM_SetBlHeightDMA(MS_U8 u8Height)
253*53ee8cc1Swenshuai.xi {
254*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
255*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_BL_WIDTH_DMA,(LD_Read2Byte(REG_BL_WIDTH_DMA)&(0xC0FF))|(u8Height<<8));
256*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
257*53ee8cc1Swenshuai.xi return ;
258*53ee8cc1Swenshuai.xi }
HAL_LDM_SetBlWidthDMA(MS_U8 u8Width)259*53ee8cc1Swenshuai.xi void HAL_LDM_SetBlWidthDMA(MS_U8 u8Width)
260*53ee8cc1Swenshuai.xi {
261*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
262*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_BL_WIDTH_DMA,(LD_Read2Byte(REG_BL_WIDTH_DMA)&(0xFFC0))|u8Width);
263*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
264*53ee8cc1Swenshuai.xi return ;
265*53ee8cc1Swenshuai.xi }
266*53ee8cc1Swenshuai.xi
HAL_LDM_SetLEDBufBaseOffset(MS_U32 u32DataOffset)267*53ee8cc1Swenshuai.xi void HAL_LDM_SetLEDBufBaseOffset(MS_U32 u32DataOffset)
268*53ee8cc1Swenshuai.xi {
269*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
270*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_BASEADDR_OFFSET,u32DataOffset&0xFFFF);
271*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_BASEADDR_OFFSET+1,u32DataOffset >> 16);
272*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
273*53ee8cc1Swenshuai.xi return ;
274*53ee8cc1Swenshuai.xi }
275*53ee8cc1Swenshuai.xi
276*53ee8cc1Swenshuai.xi //step6: enable local dimming
HAL_LDM_Enable(MS_BOOL Enable)277*53ee8cc1Swenshuai.xi void HAL_LDM_Enable(MS_BOOL Enable)
278*53ee8cc1Swenshuai.xi {
279*53ee8cc1Swenshuai.xi HAL_SUBBANKLD;
280*53ee8cc1Swenshuai.xi if(Enable)
281*53ee8cc1Swenshuai.xi {
282*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LD_ENABLE,0x0001);
283*53ee8cc1Swenshuai.xi }
284*53ee8cc1Swenshuai.xi else
285*53ee8cc1Swenshuai.xi {
286*53ee8cc1Swenshuai.xi LD_Write2Byte(REG_LD_ENABLE,0x0000);
287*53ee8cc1Swenshuai.xi }
288*53ee8cc1Swenshuai.xi HAL_SUBBANKOFF;
289*53ee8cc1Swenshuai.xi return ;
290*53ee8cc1Swenshuai.xi }
291