1*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
2*53ee8cc1Swenshuai.xi //
3*53ee8cc1Swenshuai.xi // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4*53ee8cc1Swenshuai.xi // All rights reserved.
5*53ee8cc1Swenshuai.xi //
6*53ee8cc1Swenshuai.xi // Unless otherwise stipulated in writing, any and all information contained
7*53ee8cc1Swenshuai.xi // herein regardless in any format shall remain the sole proprietary of
8*53ee8cc1Swenshuai.xi // MStar Semiconductor Inc. and be kept in strict confidence
9*53ee8cc1Swenshuai.xi // ("MStar Confidential Information") by the recipient.
10*53ee8cc1Swenshuai.xi // Any unauthorized act including without limitation unauthorized disclosure,
11*53ee8cc1Swenshuai.xi // copying, use, reproduction, sale, distribution, modification, disassembling,
12*53ee8cc1Swenshuai.xi // reverse engineering and compiling of the contents of MStar Confidential
13*53ee8cc1Swenshuai.xi // Information is unlawful and strictly prohibited. MStar hereby reserves the
14*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom.
15*53ee8cc1Swenshuai.xi //
16*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
17*53ee8cc1Swenshuai.xi
18*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
19*53ee8cc1Swenshuai.xi ///
20*53ee8cc1Swenshuai.xi /// file drvMSPI.c
21*53ee8cc1Swenshuai.xi /// @brief Master SPI Driver Interface
22*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
23*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
24*53ee8cc1Swenshuai.xi
25*53ee8cc1Swenshuai.xi
26*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
27*53ee8cc1Swenshuai.xi // Include Files
28*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
29*53ee8cc1Swenshuai.xi #include <string.h>
30*53ee8cc1Swenshuai.xi // Common Definition
31*53ee8cc1Swenshuai.xi #include "MsCommon.h"
32*53ee8cc1Swenshuai.xi #include "MsVersion.h"
33*53ee8cc1Swenshuai.xi #include "drvLDMA.h"
34*53ee8cc1Swenshuai.xi #include "MsOS.h"
35*53ee8cc1Swenshuai.xi #include "ULog.h"
36*53ee8cc1Swenshuai.xi
37*53ee8cc1Swenshuai.xi // Internal Definition
38*53ee8cc1Swenshuai.xi #include "regLDMA.h"
39*53ee8cc1Swenshuai.xi #include "halLDMA.h"
40*53ee8cc1Swenshuai.xi #include "drvMMIO.h"
41*53ee8cc1Swenshuai.xi #include "utopia.h"
42*53ee8cc1Swenshuai.xi
43*53ee8cc1Swenshuai.xi #define TAG_LDMA "LDMA"
44*53ee8cc1Swenshuai.xi
45*53ee8cc1Swenshuai.xi static MS_S32 _gs32LDMA_Mutex;
46*53ee8cc1Swenshuai.xi //DMA0 DMA1
47*53ee8cc1Swenshuai.xi static MS_BOOL bInited[2]= {false,false};
48*53ee8cc1Swenshuai.xi MS_U8 _u8LDMADbgLevel;
49*53ee8cc1Swenshuai.xi
50*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
51*53ee8cc1Swenshuai.xi // Debug Functions
52*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
53*53ee8cc1Swenshuai.xi #define DEBUG_LDMA(debug_level, x) do { if (_u8LDMADbgLevel >= (debug_level)) (x); } while(0)
54*53ee8cc1Swenshuai.xi
55*53ee8cc1Swenshuai.xi
56*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
57*53ee8cc1Swenshuai.xi /// Description : Set detailed level of LDMA driver debug message
58*53ee8cc1Swenshuai.xi /// @param u8DbgLevel \b IN debug level for local dimming LDMA
59*53ee8cc1Swenshuai.xi /// @return TRUE : succeed
60*53ee8cc1Swenshuai.xi /// @return FALSE : failed to set the debug level
61*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------
MDrv_LDMA_SetDbgLevel(MS_U8 u8DbgLevel)62*53ee8cc1Swenshuai.xi MS_BOOL MDrv_LDMA_SetDbgLevel(MS_U8 u8DbgLevel)
63*53ee8cc1Swenshuai.xi {
64*53ee8cc1Swenshuai.xi _u8LDMADbgLevel = u8DbgLevel;
65*53ee8cc1Swenshuai.xi
66*53ee8cc1Swenshuai.xi return TRUE;
67*53ee8cc1Swenshuai.xi }
68*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
69*53ee8cc1Swenshuai.xi /// Description : Set Menuload Number [if need transfer 100 data, then u32MenuldNum =100 ]
70*53ee8cc1Swenshuai.xi /// @param u8HWNum \b IN: LDMA Hw number index
71*53ee8cc1Swenshuai.xi /// @param u32MenuldNum \b IN: set Dma load to mspi data number
72*53ee8cc1Swenshuai.xi /// @return DRVAESDMA_OK : Success
73*53ee8cc1Swenshuai.xi /// @return Others : Fail
74*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_LDMA_SetMenuloadNumber(MS_U8 u8HWNum,MS_U32 u32MenuldNum)75*53ee8cc1Swenshuai.xi MS_S8 MDrv_LDMA_SetMenuloadNumber(MS_U8 u8HWNum, MS_U32 u32MenuldNum )
76*53ee8cc1Swenshuai.xi {
77*53ee8cc1Swenshuai.xi if(bInited[u8HWNum] == false)
78*53ee8cc1Swenshuai.xi {
79*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"LDMA Channel %d has not initiated, please check init first!\n",u8HWNum));
80*53ee8cc1Swenshuai.xi return -1;
81*53ee8cc1Swenshuai.xi }
82*53ee8cc1Swenshuai.xi return HAL_LDMA_SetMenuloadNumber(u8HWNum, u32MenuldNum);
83*53ee8cc1Swenshuai.xi }
84*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
85*53ee8cc1Swenshuai.xi /// Description : Set MSPI Command Format
86*53ee8cc1Swenshuai.xi /// @param u8HWNum \b IN: LDMA Hw number index
87*53ee8cc1Swenshuai.xi /// @param u8CmdLen \b IN: set mspi spec cmd length
88*53ee8cc1Swenshuai.xi /// @param pu16CmdBuf \b IN: mspi spec cmds
89*53ee8cc1Swenshuai.xi /// @return DRVAESDMA_OK : Success
90*53ee8cc1Swenshuai.xi /// @return Others : Fail
91*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_LDMA_SetSPICommandFormat(MS_U8 u8HWNum,MS_U8 u8CmdLen,MS_U16 * pu16CmdBuf)92*53ee8cc1Swenshuai.xi MS_S8 MDrv_LDMA_SetSPICommandFormat( MS_U8 u8HWNum,MS_U8 u8CmdLen, MS_U16* pu16CmdBuf )
93*53ee8cc1Swenshuai.xi {
94*53ee8cc1Swenshuai.xi if(bInited[u8HWNum] == false)
95*53ee8cc1Swenshuai.xi {
96*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"LDMA Channel %d has not initiated, please check init first!\n",u8HWNum));
97*53ee8cc1Swenshuai.xi return -1;
98*53ee8cc1Swenshuai.xi }
99*53ee8cc1Swenshuai.xi
100*53ee8cc1Swenshuai.xi return HAL_LDMA_SetSPICommandFormat(u8HWNum, u8CmdLen, pu16CmdBuf );
101*53ee8cc1Swenshuai.xi }
102*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
103*53ee8cc1Swenshuai.xi /// Description : Set MSPI check sum mode
104*53ee8cc1Swenshuai.xi /// @param u8HWNum \b IN: LDMA Hw number index
105*53ee8cc1Swenshuai.xi /// @param u8SumMode \b IN: set spi data check summode [000: All (start + command + data) 001: Command + data 010: Data only]
106*53ee8cc1Swenshuai.xi /// @return DRVAESDMA_OK : Success
107*53ee8cc1Swenshuai.xi /// @return Others : Fail
108*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_LDMA_SetCheckSumMode(MS_U8 u8HWNum,MS_U8 u8SumMode)109*53ee8cc1Swenshuai.xi MS_S8 MDrv_LDMA_SetCheckSumMode(MS_U8 u8HWNum,MS_U8 u8SumMode)
110*53ee8cc1Swenshuai.xi {
111*53ee8cc1Swenshuai.xi if(bInited[u8HWNum] == false)
112*53ee8cc1Swenshuai.xi {
113*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"LDMA Channel %d has not initiated, please check init first!\n",u8HWNum));
114*53ee8cc1Swenshuai.xi return -1;
115*53ee8cc1Swenshuai.xi }
116*53ee8cc1Swenshuai.xi
117*53ee8cc1Swenshuai.xi return HAL_LDMA_SetCheckSumMode(u8HWNum, u8SumMode);
118*53ee8cc1Swenshuai.xi }
119*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
120*53ee8cc1Swenshuai.xi /// Description : Set MSPI trigger mode
121*53ee8cc1Swenshuai.xi /// @param u8HWNum \b IN: LDMA Hw number index
122*53ee8cc1Swenshuai.xi /// @param u8TriggerMode \b IN: set DMA trigger mspi mode [0:trigger stop 1: one shot real time trigger 2: HW real time trigger]
123*53ee8cc1Swenshuai.xi /// @return DRVAESDMA_OK : Success
124*53ee8cc1Swenshuai.xi /// @return Others : Fail
125*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_LDMA_SetSpiTriggerMode(MS_U8 u8HWNum,MS_U8 u8TriggerMode)126*53ee8cc1Swenshuai.xi MS_S8 MDrv_LDMA_SetSpiTriggerMode( MS_U8 u8HWNum, MS_U8 u8TriggerMode )
127*53ee8cc1Swenshuai.xi {
128*53ee8cc1Swenshuai.xi if(bInited[u8HWNum] == false)
129*53ee8cc1Swenshuai.xi {
130*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"LDMA Channel %d has not initiated, please check init first!\n",u8HWNum));
131*53ee8cc1Swenshuai.xi return -1;
132*53ee8cc1Swenshuai.xi }
133*53ee8cc1Swenshuai.xi
134*53ee8cc1Swenshuai.xi return HAL_LDMA_SetSPITriggerMode(u8HWNum, u8TriggerMode);
135*53ee8cc1Swenshuai.xi }
136*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
137*53ee8cc1Swenshuai.xi /// Description : Set MSPI Trigger delay time
138*53ee8cc1Swenshuai.xi /// @param u8HWNum \b IN: LDMA Hw number index
139*53ee8cc1Swenshuai.xi /// @param pu16TrigDelay \b IN: set spi clk delay time while trigger done
140*53ee8cc1Swenshuai.xi /// @return DRVAESDMA_OK : Success
141*53ee8cc1Swenshuai.xi /// @return Others : Fail
142*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_LDMA_SetTrigDelay(MS_U8 u8HWNum,MS_U16 * pu16TrigDelay)143*53ee8cc1Swenshuai.xi MS_S8 MDrv_LDMA_SetTrigDelay(MS_U8 u8HWNum,MS_U16 *pu16TrigDelay)
144*53ee8cc1Swenshuai.xi {
145*53ee8cc1Swenshuai.xi if(bInited[u8HWNum] == false ||(pu16TrigDelay == NULL))
146*53ee8cc1Swenshuai.xi {
147*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"LDMA Channel %d has not initiated, please check init first!\n",u8HWNum));
148*53ee8cc1Swenshuai.xi return -1;
149*53ee8cc1Swenshuai.xi }
150*53ee8cc1Swenshuai.xi
151*53ee8cc1Swenshuai.xi return HAL_LDMA_SetTrigDelayCnt(u8HWNum, pu16TrigDelay);
152*53ee8cc1Swenshuai.xi }
153*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
154*53ee8cc1Swenshuai.xi /// Description : Enable ldma cs
155*53ee8cc1Swenshuai.xi /// @param u8HWNum \b IN: LDMA Hw number index
156*53ee8cc1Swenshuai.xi /// @param bEnable \b IN: set DMA for local dimming enable or disable cs
157*53ee8cc1Swenshuai.xi /// @return DRVAESDMA_OK : Success
158*53ee8cc1Swenshuai.xi /// @return Others : Fail
159*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_LDMA_EnableCS(MS_U8 u8HWNum,MS_BOOL bEnable)160*53ee8cc1Swenshuai.xi MS_S8 MDrv_LDMA_EnableCS(MS_U8 u8HWNum, MS_BOOL bEnable)
161*53ee8cc1Swenshuai.xi {
162*53ee8cc1Swenshuai.xi if(bInited[u8HWNum] == false)
163*53ee8cc1Swenshuai.xi {
164*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"LDMA Channel %d has not initiated, please check init first!\n",u8HWNum));
165*53ee8cc1Swenshuai.xi return -1;
166*53ee8cc1Swenshuai.xi }
167*53ee8cc1Swenshuai.xi
168*53ee8cc1Swenshuai.xi return HAL_LDMA_EnableCS(u8HWNum, bEnable);
169*53ee8cc1Swenshuai.xi }
170*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
171*53ee8cc1Swenshuai.xi /// Description : LDMA Init function to set iobase [should call first]
172*53ee8cc1Swenshuai.xi /// @param u8HWNum \b IN: LDMA Hw number index
173*53ee8cc1Swenshuai.xi /// @param u8ClkHz \b IN: select local dimming period for control LD bank
174*53ee8cc1Swenshuai.xi /// @return DRVAESDMA_OK : Success
175*53ee8cc1Swenshuai.xi /// @return Others : Fail
176*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_LDMA_Init(MS_U8 u8HWNum,MS_U8 u8ClkHz)177*53ee8cc1Swenshuai.xi MS_S8 MDrv_LDMA_Init(MS_U8 u8HWNum,MS_U8 u8ClkHz)
178*53ee8cc1Swenshuai.xi {
179*53ee8cc1Swenshuai.xi MS_S8 ret = 0;
180*53ee8cc1Swenshuai.xi MS_VIRT VirtNONPMBank = 0;
181*53ee8cc1Swenshuai.xi MS_PHY u32NONPMBankSize = 0;
182*53ee8cc1Swenshuai.xi
183*53ee8cc1Swenshuai.xi if(bInited[u8HWNum])
184*53ee8cc1Swenshuai.xi {
185*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"LDMA Channel %d has been initiated \n",u8HWNum));
186*53ee8cc1Swenshuai.xi return -1;
187*53ee8cc1Swenshuai.xi }
188*53ee8cc1Swenshuai.xi //config LDM_DMA register base
189*53ee8cc1Swenshuai.xi _gs32LDMA_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, "Mutex LDMA", MSOS_PROCESS_SHARED);
190*53ee8cc1Swenshuai.xi MS_ASSERT(_gs32LDMA_Mutex >= 0);
191*53ee8cc1Swenshuai.xi
192*53ee8cc1Swenshuai.xi if (!MDrv_MMIO_GetBASE( &VirtNONPMBank, &u32NONPMBankSize, MS_MODULE_HW))
193*53ee8cc1Swenshuai.xi {
194*53ee8cc1Swenshuai.xi DEBUG_LDMA(E_LDMA_DBGLV_ERR,ULOGE(TAG_LDMA,"IOMap failure to get DRV_MMIO_NONPM_BANK\n"));
195*53ee8cc1Swenshuai.xi return -1;
196*53ee8cc1Swenshuai.xi }
197*53ee8cc1Swenshuai.xi
198*53ee8cc1Swenshuai.xi HAL_LDMA_MMIOConfig(VirtNONPMBank,u8HWNum);
199*53ee8cc1Swenshuai.xi
200*53ee8cc1Swenshuai.xi bInited[u8HWNum] = true;
201*53ee8cc1Swenshuai.xi
202*53ee8cc1Swenshuai.xi return ret;
203*53ee8cc1Swenshuai.xi }
204