1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
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31 // third party.
32 //
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34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
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43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
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46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
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51 // ("Services").
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53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
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61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
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64 //
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66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #if defined(MSOS_TYPE_NOS) || defined(MSOS_TYPE_NUTTX)
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 #include "MsCommon.h"
101 #include "MsOS.h"
102 #include "halIRQTBL.h"
103 #include "regCHIP.h"
104 #include "drvIRQ.h"
105 #include "halIRQ.h"
106 #include "regIRQ.h"
107
108 #if defined(MSOS_TYPE_NUTTX)
109 #include "debug.h"
110 #endif
111
112 #define MST_MACRO_START do {
113 #define MST_MACRO_END } while (0)
114
115 #if defined (__mips__)
116 #define mtspr(spr, value) printf("[NIY] mtspr in line:%s %d\n",__FILE__, __LINE__);
117 #define mfspr(spr) printf("[NIY] mfspr in line:%s %d\n",__FILE__, __LINE__);
118
__mhal_lsbit_index(MS_U32 _value_)119 inline MS_U32 __mhal_lsbit_index(MS_U32 _value_)
120 {
121 MS_U32 index = 1;
122
123 while((_value_&0x01) == 0x00)
124 {
125 _value_ = (_value_ >> 1);
126 index++;
127 if(index == 32)
128 {
129 index = 0;
130 break;
131 }
132 }
133
134 return index;
135 //printf(const char * fmt, ...)("[NIY] __mhal_lsbit_index in line: %s %d\n",__FILE__, __LINE__);
136 }
137
138
139 #define __mhal_interrupt_disable(_old_) (_old_=_old_)
140
141 #define __mhal_interrupt_restore(_old_) (_old_=_old_)
142
143 #elif defined (__arm__) || defined(__aarch64__)
144 #define mtspr(spr, value) printf("[NIY] mtspr in line:%s %d\n",__FILE__, __LINE__);
145 #define mfspr(spr) printf("[NIY] mfspr in line:%s %d\n",__FILE__, __LINE__);
146
__mhal_lsbit_index(MS_U32 _value_)147 inline MS_U32 __mhal_lsbit_index(MS_U32 _value_)
148 {
149 MS_U32 index = 1;
150
151 while((_value_&0x01) == 0x00)
152 {
153 _value_ = (_value_ >> 1);
154 index++;
155 if(index == 32)
156 {
157 index = 0;
158 break;
159 }
160 }
161
162 return index;
163 //printf(const char * fmt, ...)("[NIY] __mhal_lsbit_index in line: %s %d\n",__FILE__, __LINE__);
164 }
165
166
167 #define __mhal_interrupt_disable(_old_) (_old_=_old_)
168
169 #define __mhal_interrupt_restore(_old_) (_old_=_old_)
170 #else
171 #define mtspr(spr, value) \
172 __asm__ __volatile__ ("l.mtspr\t\t%0,%1,0" : : "r" (spr), "r" (value))
173
174 #define mfspr(spr) \
175 ({ \
176 unsigned long value; \
177 __asm__ __volatile__ ("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr) : "memory"); \
178 value; \
179 })
180
181 #define __mhal_lsbit_index(_value_) \
182 ({ \
183 unsigned long _index_; \
184 __asm__ __volatile__ ("l.ff1\t\t%0,%1" : "=r" (_index_) : "r" (_value_));\
185 _index_; \
186 })
187
188
189 #define GRP_BITS (11)
190 #define SPR_SR ((0 << GRP_BITS) + 17)
191 #define SPR_SR_TEE 0x00000002 // Tick timer Exception Enable
192 #define SPR_SR_IEE 0x00000004 // Interrupt Exception Enable
193
194 #define __mhal_interrupt_disable(_old_) \
195 MST_MACRO_START \
196 _old_ = mfspr(SPR_SR); \
197 mtspr(SPR_SR, (_old_) & ~(SPR_SR_IEE | SPR_SR_TEE)); \
198 MST_MACRO_END
199
200 #define __mhal_interrupt_restore(_old_) \
201 mtspr(SPR_SR, (~(SPR_SR_IEE|SPR_SR_TEE) & mfspr(SPR_SR) ) | \
202 ( (SPR_SR_IEE|SPR_SR_TEE) & (_old_) ))
203 #endif
204
205
206 //-------------------------------------------------------------------------------------------------
207 // Driver Compiler Options
208 //-------------------------------------------------------------------------------------------------
209
210
211 //-------------------------------------------------------------------------------------------------
212 // Local Defines
213 //-------------------------------------------------------------------------------------------------
214 #define COUNTOF( array ) (sizeof(array) / sizeof((array)[0]))
215 //#define E_INTERRUPT_FIQ E_INTERRUPT_02
216 //#define E_INTERRUPT_IRQ E_INTERRUPT_03
217
218 //-------------------------------------------------------------------------------------------------
219 // Local Structures
220 //-------------------------------------------------------------------------------------------------
221 typedef void (*IRQCb)(MS_U32 u32Vector);
222
223 //-------------------------------------------------------------------------------------------------
224 // Global Variables
225 //-------------------------------------------------------------------------------------------------
226
227
228 //-------------------------------------------------------------------------------------------------
229 // Local Variables
230 //-------------------------------------------------------------------------------------------------
231 static IRQCb irq_table[E_IRQ_FIQ_ALL] = {0};
232 // static MS_U32 _u32FIQ, _u32IRQ, _u32FIQExp, _u32IRQExp, _u32MIO_MapBase = 0;
233 static MS_U32 _u32FIQ_Msk, _u32IRQ_Msk, _u32FIQExp_Msk, _u32IRQExp_Msk;
234
235 #if defined(MCU_AEON)
236 static MS_U32 _u32MIO_MapBase = 0xfa200000;
237 #elif defined(__arm__) || defined(__aarch64__)
238 #ifdef CONFIG_MBOOT
239 static MS_U32 _u32MIO_MapBase = 0x1f200000;
240 #else
241 static MS_U32 _u32MIO_MapBase = 0xfd200000;
242 #endif
243 #else
244 static MS_U32 _u32MIO_MapBase= 0xbf200000;
245 #endif
246
247 static MS_BOOL _bInIRQ = FALSE;
248 static MS_BOOL _bInFIQ = FALSE;
249
250 //-------------------------------------------------------------------------------------------------
251 // External Functions
252 //-------------------------------------------------------------------------------------------------
253
254 #define REG16_R(u32RegAddr) ((*((volatile MS_U16*)(_u32MIO_MapBase+ ((u32RegAddr)<< 1)))) & 0xFFFF)
255 #define REG16_W(u32RegAddr, u32Value) (*((volatile MS_U32*)(_u32MIO_MapBase+ ((u32RegAddr)<< 1))))= ((u32Value) & 0xFFFF)
256
257 /*
258 static MS_U16 REG16_R(MS_U32 u32RegAddr_in)
259 {
260 MS_U32 u32RegAddr1 = (u32RegAddr_in << 1);
261 MS_U32 u32RegAddr = (_u32MIO_MapBase+ (u32RegAddr1));
262 MS_U16 u16RegValue = (*((volatile MS_U16*)(u32RegAddr)) & 0xFFFF);
263
264 printf("[%s][%d] 0x%08x, 0x%08x\n", __FUNCTION__, __LINE__, u32RegAddr, u16RegValue);
265 return u16RegValue;
266 }
267
268 static MS_U16 REG16_W(MS_U32 u32RegAddr_in, MS_U32 u32Value)
269 {
270 MS_U32 u32RegAddr1 = (u32RegAddr_in << 1);
271 MS_U32 u32RegAddr = (_u32MIO_MapBase+ (u32RegAddr1));
272 *((volatile MS_U16*)(u32RegAddr)) = ((u32Value) & 0xFFFF);
273
274 // printf("[%s][%d] 0x%08x, 0x%08x\n", __FUNCTION__, __LINE__, u32RegAddr, u32Value);
275 // REG16_R(u32RegAddr_in);
276 }
277 */
278
279 //-------------------------------------------------------------------------------------------------
280 // Local Functions
281 //-------------------------------------------------------------------------------------------------
282 static void _HAL_IRQ_Enable(MS_U32 u32Vector, int enable);
283
_IRQ_Read2Byte(MS_U32 u32RegAddr)284 static MS_U16 _IRQ_Read2Byte(MS_U32 u32RegAddr)
285 {
286 return REG16_R(u32RegAddr);
287 }
288
_IRQ_Read4Byte(MS_U32 u32RegAddr)289 static MS_U32 _IRQ_Read4Byte(MS_U32 u32RegAddr)
290 {
291 return (_IRQ_Read2Byte(u32RegAddr) | _IRQ_Read2Byte(u32RegAddr+2) << 16);
292 }
293
294 #if 0
295 static void _IRQ_WriteByte(MS_U32 u32RegAddr, MS_U8 u8Val)
296 {
297 if (u32RegAddr & 1)
298 {
299 REG16_W(u32RegAddr, (REG16_R(u32RegAddr) & ~(0xFF00))| (u8Val<< 8));
300 }
301 else
302 {
303 REG16_W(u32RegAddr, (REG16_R(u32RegAddr) & ~(0x00FF))| (u8Val));
304 }
305 }
306 #endif
307
_IRQ_Write2Byte(MS_U32 u32RegAddr,MS_U16 u16Val)308 static void _IRQ_Write2Byte(MS_U32 u32RegAddr, MS_U16 u16Val)
309 {
310 REG16_W(u32RegAddr, u16Val);
311 }
312
_IRQ_Write4Byte(MS_U32 u32RegAddr,MS_U32 u32Val)313 static void _IRQ_Write4Byte(MS_U32 u32RegAddr, MS_U32 u32Val)
314 {
315 _IRQ_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF);
316 _IRQ_Write2Byte(u32RegAddr+2, u32Val >> 16);
317 }
318
319 #if defined(__arm__) || defined(__aarch64__)
_HAL_IRQ_FIQHnd(void)320 static void _HAL_IRQ_FIQHnd(void)
321 #else
322 static void _HAL_IRQ_FIQHnd(MHAL_SavedRegisters *pHalReg, MS_U32 u32Vector)
323 #endif
324 {
325 MS_U32 status;
326 MS_U32 index;
327
328 _bInFIQ = TRUE;
329 status = _IRQ_Read4Byte(REG_FIQ_FINAL_STATUS);
330
331 index = __mhal_lsbit_index(status);
332 if (index)
333 {
334
335 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, status);
336 _IRQ_Write4Byte(REG_C_FIQ_CLR + 0, 0);
337
338 do
339 {
340 status &= ~(1 << --index);
341 index += (MS_U32)E_FIQL_START;
342 if (irq_table[index])
343 {
344 _HAL_IRQ_Enable(index, DISABLE);
345 irq_table[index](HWIdx2IntEnum[index]);
346 }
347 index = __mhal_lsbit_index(status);
348 } while (index);
349 }
350
351 status = _IRQ_Read4Byte(REG_C_FIQ_EXP_FINAL_STATUS);
352
353 index = __mhal_lsbit_index(status);
354 if (index)
355 {
356 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, status);
357 _IRQ_Write4Byte(REG_C_FIQ_EXP_CLR, 0);
358 do {
359 status &= ~(1 << --index);
360 index += (MS_U32)E_FIQEXPL_START;
361 if (irq_table[index])
362 {
363 _HAL_IRQ_Enable(index, DISABLE);
364 irq_table[index](HWIdx2IntEnum[index]);
365 }
366 index = __mhal_lsbit_index(status);
367 } while (index);
368 }
369 _bInFIQ = FALSE;
370 }
371
372 #if defined(__arm__) || defined(__aarch64__)
_HAL_IRQ_IRQHnd(void)373 static void _HAL_IRQ_IRQHnd(void)
374 #else
375 static void _HAL_IRQ_IRQHnd(MHAL_SavedRegisters *pHalReg, MS_U32 u32Vector)
376 #endif
377 {
378 MS_U32 status;
379 MS_U32 index;
380
381 _bInIRQ = TRUE;
382 status = _IRQ_Read4Byte(REG_IRQ_FINAL_STATUS);
383 index = __mhal_lsbit_index(status);
384 if (index)
385 {
386 do {
387 status &= ~(1 << --index);
388 index += (MS_U32)E_IRQL_START;
389 if (irq_table[index])
390 {
391 _HAL_IRQ_Enable(index, DISABLE);
392 //fix Uart Rx interrupt can't work
393 irq_table[index](HWIdx2IntEnum[index]);
394 }
395 index = __mhal_lsbit_index(status);
396 } while (index);
397 }
398
399 status = _IRQ_Read4Byte(REG_C_IRQ_EXP_FINAL_STATUS);
400 index = __mhal_lsbit_index(status);
401 if (index)
402 {
403 do {
404 status &= ~(1 << --index);
405 index += (MS_U32)E_IRQEXPL_START;
406 if (irq_table[index])
407 {
408 _HAL_IRQ_Enable(index, DISABLE);
409 irq_table[index](HWIdx2IntEnum[index]);
410 }
411 index = __mhal_lsbit_index(status);
412 } while (index);
413 }
414 _bInIRQ = FALSE;
415 }
416
_HAL_IRQ_Enable(MS_U32 u32Vector,int enable)417 static void _HAL_IRQ_Enable(MS_U32 u32Vector, int enable)
418 {
419 MS_U32 reg = E_IRQ_FIQ_INVALID;
420 MS_U32 mask;
421 MS_U32 old = 0;
422
423 if ((MS_U32)u32Vector <= COUNTOF(irq_table))
424 {
425 if ( (u32Vector >= E_IRQL_START) && (u32Vector <= E_IRQH_END) )
426 {
427 u32Vector -= E_IRQL_START;
428 reg = REG_C_IRQ_MASK;
429 }
430 else if ( (u32Vector >= E_FIQL_START) && (u32Vector <= E_FIQH_END) )
431 {
432 u32Vector -= E_FIQL_START;
433 reg = REG_C_FIQ_MASK;
434 }
435 else if ( (u32Vector >= E_IRQEXPL_START) && (u32Vector <= E_IRQEXPH_END) )
436 {
437 u32Vector -= E_IRQEXPL_START;
438 reg = REG_C_IRQ_EXP_MASK;
439 }
440 else if ( (u32Vector >= E_FIQEXPL_START) && (u32Vector <= E_FIQEXPH_END) )
441 {
442 u32Vector -= E_FIQEXPL_START;
443 reg = REG_C_FIQ_EXP_MASK;
444 }
445
446 if( E_IRQ_FIQ_INVALID == reg )
447 {
448 //printf("_HAL_IRQ_Enable: unknow vector\n");
449 return;
450 }
451
452 __mhal_interrupt_disable(old);
453 mask = _IRQ_Read4Byte(reg);
454 u32Vector = (1 << u32Vector);
455
456 if (enable)
457 mask &= ~u32Vector;
458 else
459 mask |= u32Vector;
460
461 _IRQ_Write4Byte(reg, mask);
462 __mhal_interrupt_restore(old);
463
464 }
465 }
466
467 //-------------------------------------------------------------------------------------------------
468 // Global Functions
469 //-------------------------------------------------------------------------------------------------
HAL_IRQ_Set_IOMap(MS_U32 u32Base)470 void HAL_IRQ_Set_IOMap(MS_U32 u32Base)
471 {
472 _u32MIO_MapBase = u32Base;
473 }
474
475 #if defined(MSOS_TYPE_NUTTX)
_HAL_IRQ_FIQHnd_Nuttx(int irq,void * context)476 int _HAL_IRQ_FIQHnd_Nuttx(int irq, void *context)
477 {
478 _HAL_IRQ_FIQHnd((MHAL_SavedRegisters *)context, irq);
479 return 1;
480 }
481
_HAL_IRQ_IRQHnd_Nuttx(int irq,void * context)482 int _HAL_IRQ_IRQHnd_Nuttx(int irq, void *context)
483 {
484 _HAL_IRQ_IRQHnd((MHAL_SavedRegisters *)context, irq);
485 return 1;
486 }
487 #endif
488
HAL_IRQ_Init(void)489 void HAL_IRQ_Init(void)
490 {
491 HAL_InitIrqTable();
492 #if defined(__arm__) || defined(__aarch64__)
493 MsOS_CPU_AttachInterrupt(E_INTERRUPT_FIQ, _HAL_IRQ_FIQHnd, E_INTERRUPT_FIQ);
494 MsOS_CPU_AttachInterrupt(E_INTERRUPT_IRQ, _HAL_IRQ_IRQHnd, E_INTERRUPT_IRQ);
495 #else
496 #if defined(MSOS_TYPE_NUTTX)
497 MsOS_CPU_AttachInterrupt(E_INTERRUPT_FIQ, _HAL_IRQ_FIQHnd_Nuttx, E_INTERRUPT_FIQ);
498 MsOS_CPU_AttachInterrupt(E_INTERRUPT_IRQ, _HAL_IRQ_IRQHnd_Nuttx, E_INTERRUPT_IRQ);
499 MsOS_CPU_UnMaskInterrupt(E_INTERRUPT_FIQ);
500 MsOS_CPU_UnMaskInterrupt(E_INTERRUPT_IRQ);
501 #else
502 MsOS_CPU_AttachInterrupt(E_INTERRUPT_FIQ, (mhal_isr_t) _HAL_IRQ_FIQHnd, E_INTERRUPT_FIQ);
503 MsOS_CPU_AttachInterrupt(E_INTERRUPT_IRQ, (mhal_isr_t) _HAL_IRQ_IRQHnd, E_INTERRUPT_IRQ);
504 #endif
505 #endif
506 HAL_IRQ_DetechAll();
507 }
508
HAL_IRQ_Attach(MS_U32 u32Vector,void * pIntCb)509 void HAL_IRQ_Attach(MS_U32 u32Vector, void *pIntCb)
510 {
511 MS_U32 u32VectorIndex = 0;
512
513 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
514
515 if ((MS_U32)u32VectorIndex <= COUNTOF(irq_table))
516 irq_table[u32VectorIndex] = (IRQCb)pIntCb;
517 else
518 printf("%s error vector: %x\n", __FUNCTION__, (unsigned int)u32VectorIndex);
519 }
520
HAL_IRQ_DetechAll()521 void HAL_IRQ_DetechAll()
522 {
523 MS_U16 u16Cnt= 0;
524 for (; u16Cnt <= COUNTOF(irq_table); u16Cnt++)
525 irq_table[u16Cnt] = 0;
526 }
527
HAL_IRQ_Detech(MS_U32 u32Vector)528 void HAL_IRQ_Detech(MS_U32 u32Vector)
529 {
530 MS_U32 u32VectorIndex = 0;
531
532 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
533
534 if ((MS_U32)u32VectorIndex <= COUNTOF(irq_table))
535 irq_table[u32VectorIndex] = 0;
536 else
537 printf("%s error vector: %x\n", __FUNCTION__, (unsigned int)u32Vector);
538 }
539
HAL_IRQ_MaskAll(MS_BOOL bMask)540 void HAL_IRQ_MaskAll(MS_BOOL bMask)
541 {
542 if (bMask)
543 {
544 _u32FIQ_Msk = _IRQ_Read4Byte(REG_C_FIQ_MASK);
545 _u32IRQ_Msk = _IRQ_Read4Byte(REG_C_IRQ_MASK);
546 _u32FIQExp_Msk = _IRQ_Read4Byte(REG_C_FIQ_EXP_MASK);
547 _u32IRQExp_Msk = _IRQ_Read4Byte(REG_C_IRQ_EXP_MASK);
548 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0xFFFFFFFF);
549 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0xFFFFFFFF);
550 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0xFFFFFFFF);
551 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0xFFFFFFFF);
552 }
553 else
554 {
555 _IRQ_Write4Byte(REG_C_FIQ_MASK, 0);
556 _IRQ_Write4Byte(REG_C_IRQ_MASK, 0);
557 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, 0);
558 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, 0);
559 }
560 }
561
HAL_IRQ_Restore()562 void HAL_IRQ_Restore()
563 {
564 _IRQ_Write4Byte(REG_C_FIQ_MASK, _u32FIQ_Msk);
565 _IRQ_Write4Byte(REG_C_IRQ_MASK, _u32IRQ_Msk);
566 _IRQ_Write4Byte(REG_C_FIQ_EXP_MASK, _u32FIQExp_Msk);
567 _IRQ_Write4Byte(REG_C_IRQ_EXP_MASK, _u32IRQExp_Msk);
568 }
569
HAL_IRQ_Mask(MS_U32 u32Vector)570 void HAL_IRQ_Mask(MS_U32 u32Vector)
571 {
572 MS_U32 u32VectorIndex = 0;
573
574 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
575 _HAL_IRQ_Enable(u32VectorIndex, DISABLE);
576 }
577
HAL_IRQ_UnMask(MS_U32 u32Vector)578 void HAL_IRQ_UnMask(MS_U32 u32Vector)
579 {
580 MS_U32 u32VectorIndex = 0;
581
582 u32VectorIndex = (MS_U32)IntEnum2HWIdx[u32Vector];
583 _HAL_IRQ_Enable(u32VectorIndex, ENABLE);
584 }
585
HAL_IRQ_NotifyCpu(IRQ_CPU_TYPE type)586 void HAL_IRQ_NotifyCpu(IRQ_CPU_TYPE type)
587 {
588 type = type;
589 printf("[%s][%d] has not implemented yet\n", __FUNCTION__, __LINE__);
590 #if 0
591 switch (type)
592 {
593 case E_IRQ_CPU0_2_CPU1:
594 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, BIT(0));
595 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, 0);
596 break;
597 case E_IRQ_CPU0_2_CPU2:
598 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, BIT(1));
599 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU0, 0);
600 break;
601 case E_IRQ_CPU1_2_CPU0:
602 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, BIT(0));
603 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, 0);
604 break;
605 case E_IRQ_CPU1_2_CPU2:
606 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, BIT(1));
607 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU1, 0);
608 break;
609 case E_IRQ_CPU2_2_CPU0:
610 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, BIT(0));
611 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, 0);
612 break;
613 case E_IRQ_CPU2_2_CPU1:
614 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, BIT(1));
615 _IRQ_WriteByte(REG_SEND_IRQ_FROM_CPU2, 0);
616 break;
617 default:
618 break;
619 }
620 #endif
621 }
622
HAL_IRQ_InISR()623 MS_BOOL HAL_IRQ_InISR()
624 {
625 return (_bInIRQ || _bInFIQ);
626 }
627
628 #endif // #if defined (MSOS_TYPE_NOS)
629