1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 // File Name: mhal_CEC.c
94 // Description: For CEC functions.
95 ////////////////////////////////////////////////////////////////////////////////
96
97
98 #define _MHAL_CEC_C_
99
100 #include <string.h>
101 #include "MsCommon.h"
102 #include "cec_hwreg_utility2.h"
103 #include "cec_Analog_Reg.h"
104 #include "MsOS.h"
105 #include "apiCEC.h"
106 #include "MsIRQ.h"
107 #include "mhal_CEC.h"
108 #include "asmCPU.h"
109
110 extern MS_U32 CEC_RIU_BASE;
111 extern InterruptNum gCECIRQ;
112 extern MS_U8 g_u8CecVendorID[3];
113 extern MS_U8 g_u8RetryCnt;
114
115 #define CEC_DPUTSTR(str) //printf(str)
116 #define CEC_DPRINTF(str, x) //printf(str, x)
117
118 #define PM_REG_WRITE MDrv_WriteByte
119 #define PM_REG_READ MDrv_ReadByte
120
121
122 #define MST_XTAL_CLOCK_HZ (12000000UL) /* Temp define */
123
124 #define _NOP_ MAsm_CPU_Nop();
125
mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)126 void mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)
127 {
128
129 }
130
mhal_CEC_init_riu_base(MS_U32 u32riu_base,MS_U32 u32PMriu_base)131 void mhal_CEC_init_riu_base(MS_U32 u32riu_base, MS_U32 u32PMriu_base)
132 {
133 CEC_RIU_BASE = u32PMriu_base;
134 }
135
136
mhal_CEC_HeaderSwap(MS_U8 value)137 MS_U8 mhal_CEC_HeaderSwap(MS_U8 value)
138 {
139 return(((value&0x0f)<<4)+((value&0xf0)>>4));
140 }
141
mhal_CEC_SendFrame(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)142 MS_U8 mhal_CEC_SendFrame(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
143 {
144 MS_U8 i, cnt, *ptr, res;
145 MS_U8 u8waitcnt;
146
147 // clear CEC TX INT status
148 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
149 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
150 PM_REG_WRITE( L_BK_CEC(0x18), header );
151 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
152
153 CEC_DPUTSTR("\r\n/******** CEC Tx **********/\r\n");
154 CEC_DPRINTF("CEC Tx FIFO= 0x%x", (MS_U8)header);
155 CEC_DPRINTF(" 0x%x", (MS_U8)opcode);
156
157 if(len > 0)
158 {
159 ptr=operand;
160 for(i=0;i<len;i++)
161 {
162 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
163 CEC_DPRINTF(" 0x%x", *(operand+i));
164 }
165 CEC_DPUTSTR("\r\n/**************************/\r\n");
166 }
167
168
169 // CEC transmit length
170 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
171 if((opcode==0x00)&&(len==0))
172 {
173 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
174 u8waitcnt = 5;
175 }
176 else
177 {
178 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
179 u8waitcnt = 4 * (len+2);
180 }
181
182 //The total time,
183 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
184 // = 28.5 ms (1), or 52.5 ms (2), ....
185 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
186 // = 28.5 + 35.2 * 3 = 133.6 ms
187
188 cnt=0;
189 MsOS_DelayTask(20);
190
191 do
192 {
193 MsOS_DelayTask(10);
194 if(cnt++>=u8waitcnt)
195 break;
196 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
197 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
198
199 if(cnt>=u8waitcnt)
200 res |= E_CEC_SYSTEM_BUSY;
201
202 // clear CEC TX INT status
203 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
204 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
205
206 return res;
207 }
208
mhal_CEC_SendFramex(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)209 MS_U8 mhal_CEC_SendFramex(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
210 {
211 MS_U8 i, cnt, *ptr, res;
212 MS_U8 u8waitcnt;
213 volatile MS_U16 k, m;
214 // clear CEC TX INT status
215 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
216 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
217 PM_REG_WRITE( L_BK_CEC(0x18), header );
218 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
219
220 CEC_DPUTSTR("\r\n/******** CEC Tx **********/\r\n");
221 CEC_DPRINTF("CEC Tx FIFO= 0x%x", (MS_U8)header);
222 CEC_DPRINTF(" 0x%x", (MS_U8)opcode);
223
224 if(len > 0)
225 {
226 ptr=operand;
227 for(i=0;i<len;i++)
228 {
229 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
230 CEC_DPRINTF(" 0x%x", *(operand+i));
231 }
232 CEC_DPUTSTR("\r\n/**************************/\r\n");
233 }
234
235
236 // CEC transmit length
237 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
238 if((opcode==0x00)&&(len==0))
239 {
240 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
241 u8waitcnt = 5;
242 }
243 else
244 {
245 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
246 u8waitcnt = 30;
247 }
248
249 //The total time,
250 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
251 // = 28.5 ms (1), or 52.5 ms (2), ....
252 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
253 // = 28.5 + 35.2 * 3 = 133.6 ms
254
255
256 cnt=0;
257 //MsOS_DelayTask(20);
258 for(k = 0; k< 20000; k++)
259 {
260 _NOP_
261 _NOP_
262 _NOP_
263 }
264
265
266 do
267 {
268 //MsOS_DelayTask(10);
269 for(k = 0; k< 20000; k++)
270 {
271 for(m=0;m<50;m++)
272 {
273 _NOP_
274 _NOP_
275 _NOP_
276 _NOP_
277 _NOP_
278 }
279 }
280 if(cnt++>=u8waitcnt)
281 break;
282 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
283
284 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
285
286 if(cnt>=u8waitcnt)
287 res |= E_CEC_SYSTEM_BUSY;
288
289 // clear CEC TX INT status
290 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
291 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
292
293 return res;
294 }
295
296
mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)297 void mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)
298 {
299 PM_REG_WRITE(L_BK_CEC(0x02), (PM_REG_READ(L_BK_CEC(0x02)) & 0x0F) |(mylogicaladdress<<4));
300 }
301
mhal_CEC_INTEn(MS_BOOL bflag)302 void mhal_CEC_INTEn(MS_BOOL bflag)
303 {
304 if(bflag) // unmask
305 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E); //REG_HDMI_INT_MASK
306
307 else // Mask CEC interrupt
308 #if ENABLE_CEC_MULTIPLE
309 PM_REG_WRITE(L_BK_CEC(0x13), 0x7F); //REG_HDMI_INT_MASK
310 #else
311 PM_REG_WRITE(L_BK_CEC(0x13), 0x1F); //REG_HDMI_INT_MASK
312 #endif
313
314 }
315
316
mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz)317 void mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz)
318 {
319 MS_U16 reg_val0, reg_val1;
320
321 #if ENABLE_CEC_INT
322
323 // CEC irq clear
324 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F);
325 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
326 // CEC irq mask control -only enable CEC rx irq
327 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E);
328 // CEC interrupt mask for PM/normal function
329 PM_REG_WRITE(L_BK_CEC(0x30), 0x08); // 11_30[3] = 1 Interrupt clear type select (Level), clear by itself
330
331 gCECIRQ = E_INT_IRQ_CEC; // IRQ52
332 #endif
333
334 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
335 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
336 PM_REG_WRITE(H_BK_CEC(0x00),0x10|RETRY_CNT); // retry times
337 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
338 PM_REG_WRITE(H_BK_CEC(0x01),(BusFreeTime<<4)|(ReTxInterval)); // CNT1=ReTxInterval; CNT2=BusFreeTime;
339 PM_REG_WRITE(L_BK_CEC(0x02),(E_LA_TV<<4)|(FrameInterval)); // CNT3=FrameInterval; [7:4]=logical address: TV
340 #if ENABLE_CEC_MULTIPLE
341 PM_REG_WRITE(L_BK_CEC(0x30),PM_REG_READ(L_BK_CEC(0x30))|BIT(0)); // enable CEC multiple function
342 #endif
343 reg_val0=(MST_XTAL_CLOCK_HZ%100000l)*0.00016+0.5;
344 PM_REG_WRITE(H_BK_CEC(0x02),(MST_XTAL_CLOCK_HZ/100000l)); // CEC time unit by Xtal(integer)
345 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
346 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
347
348 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF); // clear CEC status
349
350
351 }
352
mhal_CEC_IsMessageReceived(void)353 MS_BOOL mhal_CEC_IsMessageReceived(void)
354 {
355 return (PM_REG_READ(H_BK_CEC(0x11))& 0x01 ? TRUE : FALSE);
356 }
357
mhal_CEC_ReceivedMessageLen(void)358 MS_U8 mhal_CEC_ReceivedMessageLen(void)
359 {
360 return ((PM_REG_READ(L_BK_CEC(0x04)) & 0x1F) + 1);
361 }
362
mhal_CEC_GetMessageByte(MS_U8 idx)363 MS_U8 mhal_CEC_GetMessageByte(MS_U8 idx)
364 {
365 return (PM_REG_READ(L_BK_CEC(0x20) + idx));
366 }
367
mhal_CEC_ClearRxStatus(void)368 void mhal_CEC_ClearRxStatus(void)
369 {
370 // clear RX INT status
371 PM_REG_WRITE(H_BK_CEC(0x12), 0x11);
372 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
373 // clear RX NACK status
374 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF);
375 }
376
377 /***************************************************************************************/
378 /// config cec wake up
379 /***************************************************************************************/
380
mhal_CEC_ConfigWakeUp(void)381 void mhal_CEC_ConfigWakeUp(void)
382 {
383 MS_U16 reg_val0, reg_val1;
384 CEC_DPUTSTR("\r\n Here do the PM config cec wakeup \r\n");
385
386 //XBYTE[0x250C] &= ~BIT0;
387 MDrv_WriteByte( REG_COMBO_PHY0_P0_0C_H, MDrv_ReadByte(REG_COMBO_PHY0_P0_0C_H) &(~ BIT(4)));
388
389
390 //(1) enable chiptop clk_mcu & clk_pram
391 #if 0
392 XBYTE[0x0E00] = 0x03;
393 //enable PM_Sleep's clk_mcu and _pram
394 Drv_WriteByte(L_BK_PMSLP(0x00), 0x03);
395 XBYTE[0x0E01] = 0x0F;
396 //0x0C; Ken 20080916 for calibration to 1Mz
397 MDrv_WriteByte(H_BK_PMSLP(0x00), 0x0F);
398 #endif
399
400
401 //(2) HDMI CEC settings
402 PM_REG_WRITE(H_BK_CEC(0x00),0x10|g_u8RetryCnt); // retry times
403 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
404 PM_REG_WRITE(H_BK_CEC(0x01),0x63); // CNT1=3; CNT2 = 6;
405 PM_REG_WRITE(L_BK_CEC(0x02),0x07); // CNT3=7; logical address: TV
406
407 reg_val0=(MST_XTAL_CLOCK_HZ%100000l)*0.00016+0.5;
408 PM_REG_WRITE(H_BK_CEC(0x02),(MST_XTAL_CLOCK_HZ/100000l)); // CEC time unit by Xtal(integer)
409
410 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
411 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
412
413
414 //(3) PM Sleep: wakeup enable sources
415 //PM_REG_WRITE(L_BK_PMMCU(0x00),0x01); // reg_cec_enw
416
417
418 //(4) PM CEC power down controller settings
419 // Mask CEC interrupt in standby mode
420 PM_REG_WRITE(L_BK_CEC(0x13),0xFF);
421 // select power down SW CEC controller
422 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
423 PM_REG_WRITE(L_BK_CEC(0x01),0x00); // [5]:CEC clock no gate; [7]: Disable CEC controller
424 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
425 #if 0//ENABLE_SW_CEC_WAKEUP
426 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
427 #else
428 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))|(BIT(4))); // [4]: sleep mode;
429 #endif
430
431
432 //(5) PM CEC wakeup opcode settings
433 // OPCODE0: 0x04(Image view on)
434 // OPCODE1: 0x0D(Text view on)
435 // OPCODE2: 0x44 0x40(Power)
436 // 0x44 0x6D(Power ON Function)
437 // OPCODE3: N/A
438 // OPCODE4: 0x82(Active source) length = 2
439 PM_REG_WRITE(L_BK_CEC(0x07), 0x37); // Enable OP0~2 and OP4
440 PM_REG_WRITE(H_BK_CEC(0x07), 0x24); // Eanble OPCODE2's operand
441
442 PM_REG_WRITE(L_BK_CEC(0x08), E_MSG_OTP_IMAGE_VIEW_ON); // OPCODE0: Image View On
443 PM_REG_WRITE(H_BK_CEC(0x08), E_MSG_OTP_TEXT_VIEW_ON); // OPCODE1: Text View ON
444
445 PM_REG_WRITE(L_BK_CEC(0x09), E_MSG_UI_PRESS); // OPCODE2: E_MSG_UI_PRESS
446 PM_REG_WRITE(H_BK_CEC(0x0B), E_MSG_UI_POWER); // OPCODE2 operand: Power
447 PM_REG_WRITE(L_BK_CEC(0x0C), E_MSG_UI_POWER_ON_FUN); // OPCODE2 operand: Power ON
448
449 PM_REG_WRITE(L_BK_CEC(0x0A), E_MSG_ACTIVE_SOURCE); // OPCODE4: Active source
450
451 // [2:0]: CEC version 1.4; [7]: OP4 is broadcast message
452 PM_REG_WRITE(H_BK_CEC(0x0D), 0x80 | HDMI_CEC_VERSION);
453
454
455 //(6) Device(TV) Vendor ID for customer (Big Endian)
456 // It depends end-customer's vendor ID
457 MS_DEBUG_MSG(printf("!!!!!!!!!!!!!!!!!!!Change this Vendor ID according to customer!!!!!!!!!!!!!!!!\n"));
458 PM_REG_WRITE(L_BK_CEC(0x0F), g_u8CecVendorID[0]); // Device Vendor ID
459 PM_REG_WRITE(H_BK_CEC(0x0F), g_u8CecVendorID[1]); // Device Vendor ID
460 PM_REG_WRITE(L_BK_CEC(0x10), g_u8CecVendorID[2]); // Device Vendor ID
461
462 // [2:0]: Feature abort reason - "Not in correct mode to respond"
463 PM_REG_WRITE(H_BK_CEC(0x10), E_MSG_AR_CANNOTRESPOND );
464
465
466 //(7) Device Physical address: default is 0x00 0x00 0x00
467 PM_REG_WRITE(L_BK_CEC(0x0E), 0x00); // Physical address 0.0
468 PM_REG_WRITE(H_BK_CEC(0x0E), 0x00); // Physical address 0.0
469 PM_REG_WRITE(H_BK_CEC(0x14), 0x00); // Device type: TV
470
471
472 //(8) Clear CEC status
473 PM_REG_WRITE(L_BK_CEC(0x11), 0x7F); // Clear CEC wakeup status
474 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F); // Clear RX/TX/RF/LA/NACK status status
475 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
476 }
477
mhal_CEC_Enabled(MS_BOOL bEnableFlag)478 void mhal_CEC_Enabled(MS_BOOL bEnableFlag)
479 {
480 if(bEnableFlag)
481 PM_REG_WRITE(L_BK_CEC(0x01),0x80); //Enable PM CEC controller
482 else
483 PM_REG_WRITE(L_BK_CEC(0x01),0x00); //Disable PM CEC controller
484 }
485
mhal_CEC_TxStatus(void)486 MS_U8 mhal_CEC_TxStatus(void)
487 {
488 return (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
489 }
490
mhal_CEC_Device_Is_Tx(void)491 MS_BOOL mhal_CEC_Device_Is_Tx(void)
492 {
493 return CEC_DEVICE_IS_SOURCE;
494 }
495