1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. 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If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2006-2008 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // (��MStar Confidential Information��) by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 // Scaler register serpead define 96 #define SCALER_REGISTER_SPREAD 1UL 97 98 //PM 99 #define REG_PM_SLP_BASE 0x000E00UL 100 #define REG_CEC_BASE 0x001100UL 101 #define REG_PM_MCU_BASE 0x001000UL 102 103 //NONPM 104 #define REG_MIU0_BASE 0x101200UL 105 #define REG_MIU1_BASE 0x100600UL 106 #define REG_CHIPTOP_BASE 0x101E00UL // 0x1E00 - 0x1EFF 107 #define REG_UHC0_BASE 0x102400UL 108 #define REG_ADC_ATOP_BASE 0x102500UL // 0x2500 - 0x25FF 109 #define REG_ADC_DTOP_BASE 0x102600UL // 0x2600 - 0x26EF 110 #define REG_IPMUX_BASE 0x102E00UL 111 #if SCALER_REGISTER_SPREAD 112 #define REG_SCALER_BASE 0x130000UL 113 #else 114 #define REG_SCALER_BASE 0x102F00UL 115 #endif 116 #define REG_LPLL_BASE 0x103100UL 117 #define REG_MOD_BASE 0x103200UL 118 119 #define REG_HDMI_BASE 0x102700UL // 0x2700 - 0x27FF 120 #define REG_HDMI2_BASE 0x101A00UL 121 #define REG_DVI_ATOP_BASE 0x110900UL 122 #define REG_DVI_DTOP_BASE 0x110A00UL 123 #define REG_DVI_EQ_BASE 0x110A80UL // EQ started from 0x80 124 #define REG_HDCP_BASE 0x110AC0UL // HDCP started from 0xC0 125 #define REG_DVI_ATOP1_BASE 0x113200UL 126 #define REG_DVI_DTOP1_BASE 0x113300UL 127 #define REG_DVI_EQ1_BASE 0x113380UL // EQ started from 0x80 128 #define REG_HDCP1_BASE 0x1133C0UL // HDCP started from 0xC0 129 #define REG_DVI_ATOP2_BASE 0x113400UL 130 #define REG_DVI_DTOP2_BASE 0x113500UL 131 #define REG_DVI_EQ2_BASE 0x113580UL // EQ started from 0x80 132 #define REG_HDCP2_BASE 0x1135C0UL // HDCP started from 0xC0 133 #define REG_DVI_PS_BASE 0x113600UL // DVI power saving 134 #define REG_DVI_DTOP3_BASE 0x113700UL 135 #define REG_DVI_EQ3_BASE 0x113780UL // EQ started from 0x80 136 #define REG_HDCP3_BASE 0x1137C0UL // HDCP started from 0xC0 137 #define REG_MHL_TMDS_BASE 0x122700UL 138 139 #define REG_COMBO_PHY0_P0_BASE 0x170200UL 140 141 142 #define REG_DVI_ATOP_06_L (REG_DVI_ATOP_BASE + 0x0C) 143 #define REG_DVI_ATOP_70_H (REG_DVI_ATOP_BASE + 0xE1) 144 #define REG_DVI_ATOP_71_H (REG_DVI_ATOP_BASE + 0xE3) 145 #define REG_DVI_ATOP_72_H (REG_DVI_ATOP_BASE + 0xE4) 146 #define REG_DVI_ATOP_73_H (REG_DVI_ATOP_BASE + 0xE6) 147 #define REG_DVI_ATOP1_06_L (REG_DVI_ATOP1_BASE + 0x0C) 148 #define REG_DVI_ATOP1_70_H (REG_DVI_ATOP1_BASE + 0xE1) 149 #define REG_DVI_ATOP1_71_H (REG_DVI_ATOP1_BASE + 0xE3) 150 #define REG_DVI_ATOP2_06_L (REG_DVI_ATOP2_BASE + 0x0C) 151 #define REG_DVI_ATOP2_70_H (REG_DVI_ATOP2_BASE + 0xE1) 152 #define REG_DVI_ATOP2_71_H (REG_DVI_ATOP2_BASE + 0xE3) 153 #define REG_DVI_EQ_00_L (REG_DVI_EQ_BASE + 0x00) 154 #define REG_DVI_EQ_00_H (REG_DVI_EQ_BASE + 0x01) 155 #define REG_DVI_EQ1_00_L (REG_DVI_EQ1_BASE + 0x00) 156 #define REG_DVI_EQ1_00_H (REG_DVI_EQ1_BASE + 0x01) 157 #define REG_DVI_EQ2_00_L (REG_DVI_EQ2_BASE + 0x00) 158 #define REG_DVI_EQ2_00_H (REG_DVI_EQ2_BASE + 0x01) 159 #define REG_DVI_EQ3_00_L (REG_DVI_EQ3_BASE + 0x00) 160 #define REG_DVI_EQ3_00_H (REG_DVI_EQ3_BASE + 0x01) 161 #define REG_HDCP_01_H (REG_HDCP_BASE + 0x02) 162 #define REG_HDCP_15_L (REG_HDCP_BASE + 0x2A) 163 #define REG_HDCP_15_H (REG_HDCP_BASE + 0x2B) 164 #define REG_HDCP1_01_H (REG_HDCP1_BASE + 0x02) 165 #define REG_HDCP1_15_L (REG_HDCP1_BASE + 0x2A) 166 #define REG_HDCP1_15_H (REG_HDCP1_BASE + 0x2B) 167 #define REG_HDCP2_01_H (REG_HDCP2_BASE + 0x02) 168 #define REG_HDCP2_15_L (REG_HDCP2_BASE + 0x2A) 169 #define REG_HDCP2_15_H (REG_HDCP2_BASE + 0x2B) 170 #define REG_HDCP3_01_H (REG_HDCP3_BASE + 0x02) 171 #define REG_HDCP3_15_L (REG_HDCP3_BASE + 0x2A) 172 #define REG_HDCP3_15_H (REG_HDCP3_BASE + 0x2B) 173 #define REG_HDMI2_26_L (REG_HDMI2_BASE + 0x4C) 174 #define REG_HDMI2_26_H (REG_HDMI2_BASE + 0x4D) 175 #define REG_HDMI2_27_L (REG_HDMI2_BASE + 0x4E) 176 #define REG_HDMI2_27_H (REG_HDMI2_BASE + 0x4F) 177 #define REG_MHL_TMDS_60_L (REG_MHL_TMDS_BASE + 0xC0) 178 #define REG_MHL_TMDS_60_H (REG_MHL_TMDS_BASE + 0xC1) 179 #define REG_MHL_TMDS_63_L (REG_MHL_TMDS_BASE + 0xC6) 180 #define REG_MHL_TMDS_63_H (REG_MHL_TMDS_BASE + 0xC7) 181 182 #define REG_COMBO_PHY0_P0_0C_H (REG_COMBO_PHY0_P0_BASE + 0x19) 183 184