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76 //******************************************************************************
77 //<MStar Software>
78 ///////////////////////////////////////////////////////////////////////////////////////////////////
79 ///
80 /// file mhal_mhl.c
81 /// @author MStar Semiconductor Inc.
82 /// @brief MHL driver Function
83 ///////////////////////////////////////////////////////////////////////////////////////////////////
84
85 #ifndef _MHAL_MHL_C_
86 #define _MHAL_MHL_C_
87
88 //-------------------------------------------------------------------------------------------------
89 // Include Files
90 //-------------------------------------------------------------------------------------------------
91 // Common Definition
92 #include "MsCommon.h"
93 #include "MsVersion.h"
94 #ifdef MSOS_TYPE_LINUX_KERNEL
95 #include <linux/string.h>
96 #else
97 #include <string.h>
98 #endif
99 #include "MsIRQ.h"
100 #include "MsOS.h"
101 #include "mhal_xc_chip_config.h"
102 #include "mhl_hwreg_utility2.h"
103 #include "hwreg_pm_sleep.h"
104 #include "hwreg_hdmi.h"
105 #include "hwreg_hdcp.h"
106 #include "hwregMHL.h"
107 #include "mdrv_mhl_st.h"
108 #include "halMHL.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Local Defines
112 //-------------------------------------------------------------------------------------------------
113 #define msg_mhl(x) x
114
115 #define DMHLInit 0
116
117 //-------------------------------------------------------------------------------------------------
118 // Local Structures
119 //-------------------------------------------------------------------------------------------------
120 typedef struct
121 {
122 MS_U32 addr;
123 MS_U16 mask;
124 MS_U16 databuf;
125 } msLoadTbl_S;
126
127 //-------------------------------------------------------------------------------------------------
128 // Global Variables
129 //-------------------------------------------------------------------------------------------------
130 MS_BOOL bMHLSignalStable = FALSE;
131 MS_U8 ucMHLSupportPort = E_MUX_NOT_SUPPORT_MHL;
132 MS_U8 ucIControlValue = MHL_ICONTROL_VALUE;
133 MS_U8 ucImpedanceValue = MHL_IMPEDANCE_VALUE;
134 MS_U8 ucChipIDValue = MHL_CHIP_ID_MUNICH;
135
136 //-------------------------------------------------------------------------------------------------
137 // MHL initial table
138 //-------------------------------------------------------------------------------------------------
139 static msLoadTbl_S tMHL_INITIAL_TABLE[] =
140 {
141 // Set accepted discover pulse high pulse width to ignore USB pulse
142 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
143 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
144 // CTS 4.3.7.1
145 {REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitration
146 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
147
148 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
149
150 // For CTS 6.3.10.7
151 {REG_MHL_CBUS_59, BMASK(15:0), 0xADB0}, // timeout for a device receiving a packet within a command
152 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 110ms
153
154 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
155
156 #if(MHL_CBUS_OPERATION_MODE >= MHL_CBUS_HW_ISR_MODE)
157 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_devcap request
158 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
159 {REG_MHL_CBUS_71, BMASK(15:14), BMASK(15:14)},
160 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
161 #else
162 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
163 {REG_MHL_CBUS_6D, BMASK(11:0), 0}, // Enable MHL HW mode
164 {REG_MHL_CBUS_71, BMASK(15:14), 0},
165 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
166 #endif
167
168 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
169 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
170 #endif
171
172 #if DMHL_INT_ENABLE
173 // Mask unused interrupt events
174 {REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_state_chg_int mask
175 {REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confirm_int mask, [5]: wakeup_pul_confirm_int mask, [1]: cbus_stuck_to_low_int mask.
176 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
177 {REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
178 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
179 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
180 {REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1]: send ddc error interrupt mask
181 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
182 {REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: client_wrt_ddc_ram interrupt mask
183 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
184 {REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int mask, [5]: receive nack pkt int_mask, [1]: receive abort pkt int mask
185 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
186 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
187 {REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mask, [5]: snd_pkt_msc_hw_int mask, [1]: msc sw send complete interrupt mask
188 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
189 {REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5]: rcv_data_err_int mask, [1]: rcv_sync_err_int mask
190 {REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
191 #endif
192 };
193
194 //-------------------------------------------------------------------------------------------------
195 // MHL power on table
196 //-------------------------------------------------------------------------------------------------
197 static msLoadTbl_S tMHL_POWER_ON_TABLE[] =
198 {
199 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
200 };
201
202 //-------------------------------------------------------------------------------------------------
203 // MHL power down table
204 //-------------------------------------------------------------------------------------------------
205 static msLoadTbl_S tMHL_POWER_DOWN_TABLE[] =
206 {
207 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
208 };
209
210 //-------------------------------------------------------------------------------------------------
211 // MHL power saving table
212 //-------------------------------------------------------------------------------------------------
213 static msLoadTbl_S tMHL_POWER_SAVING_TABLE[] =
214 {
215 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
216 };
217
218 //-------------------------------------------------------------------------------------------------
219 // Local Functions
220 //-------------------------------------------------------------------------------------------------
221
222 //**************************************************************************
223 // [Function Name]:
224 // _mhal_mhl_IsCbusBusy()
225 // [Description]
226 //
227 // [Arguments]:
228 //
229 // [Return]:
230 //
231 //**************************************************************************
_mhal_mhl_IsCbusBusy(void)232 MS_BOOL _mhal_mhl_IsCbusBusy(void)
233 {
234 return ((R2BYTE(REG_MHL_CBUS_5D) & 0x00F0) != 0 ? TRUE : FALSE);
235 }
236
237 //**************************************************************************
238 // [Function Name]:
239 // _mhal_mhl_DviAutoEQSwitch()
240 // [Description]
241 //
242 // [Arguments]:
243 //
244 // [Return]:
245 //
246 //**************************************************************************
_mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)247 void _mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
248 {
249 static MS_BOOL bAutoEQFlag = FALSE;
250
251 switch(ucCbusSelect)
252 {
253 #if(MHL_FUNCTION_SUPPORT_PORTA)
254 case MHL_CBUS_SELECT_PORTA:
255 if(GET_MHL_PATH_SUPPORT_PORTA())
256 {
257 if(!bAutoEQFlag)
258 {
259 if((R2BYTE(REG_DVI_DTOP_2F_L) &BIT(0)) == BIT(0))
260 {
261 bAutoEQFlag = TRUE;
262 }
263 }
264
265 if(bAutoEQFlag)
266 {
267 if(bFlag)
268 {
269 W2BYTEMSK(REG_DVI_DTOP_00_L, BIT(4), BIT(4)); // enable EQ new mode
270 W2BYTEMSK(REG_DVI_DTOP_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
271 }
272 else
273 {
274 W2BYTEMSK(REG_DVI_DTOP_00_L, 0, BIT(4)); // disable EQ new mode
275 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BIT(0)); // disable autoEQ controller
276 }
277 }
278 }
279
280 break;
281 #endif
282
283 #if(MHL_FUNCTION_SUPPORT_PORTB)
284 case MHL_CBUS_SELECT_PORTB:
285 if(GET_MHL_PATH_SUPPORT_PORTB())
286 {
287 if(!bAutoEQFlag)
288 {
289 if((R2BYTE(REG_DVI_DTOP1_2F_L) &BIT(0)) == BIT(0))
290 {
291 bAutoEQFlag = TRUE;
292 }
293 }
294
295 if(bAutoEQFlag)
296 {
297 if(bFlag)
298 {
299 W2BYTEMSK(REG_DVI_DTOP1_00_L, BIT(4), BIT(4)); // enable EQ new mode
300 W2BYTEMSK(REG_DVI_DTOP1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
301 }
302 else
303 {
304 W2BYTEMSK(REG_DVI_DTOP1_00_L, 0, BIT(4)); // disable EQ new mode
305 W2BYTEMSK(REG_DVI_DTOP1_2F_L, 0, BIT(0)); // disable autoEQ controller
306 }
307 }
308 }
309
310 break;
311 #endif
312
313 #if(MHL_FUNCTION_SUPPORT_PORTC)
314 case MHL_CBUS_SELECT_PORTC:
315 if(GET_MHL_PATH_SUPPORT_PORTC())
316 {
317 if(!bAutoEQFlag)
318 {
319 if((R2BYTE(REG_DVI_DTOP3_2F_L) &BIT(0)) == BIT(0))
320 {
321 bAutoEQFlag = TRUE;
322 }
323 }
324
325 if(bAutoEQFlag)
326 {
327 if(bFlag)
328 {
329 W2BYTEMSK(REG_DVI_DTOP3_00_L, BIT(4), BIT(4)); // enable EQ new mode
330 W2BYTEMSK(REG_DVI_DTOP3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
331 }
332 else
333 {
334 W2BYTEMSK(REG_DVI_DTOP3_00_L, 0, BIT(4)); // disable EQ new mode
335 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BIT(0)); // disable autoEQ controller
336 }
337 }
338 }
339
340 break;
341 #endif
342
343 #if(MHL_FUNCTION_SUPPORT_PORTD)
344 case MHL_CBUS_SELECT_PORTD:
345 if(GET_MHL_PATH_SUPPORT_PORTD())
346 {
347 if(!bAutoEQFlag)
348 {
349 if((R2BYTE(REG_DVI_DTOP2_2F_L) &BIT(0)) == BIT(0))
350 {
351 bAutoEQFlag = TRUE;
352 }
353 }
354
355 if(bAutoEQFlag)
356 {
357 if(bFlag)
358 {
359 W2BYTEMSK(REG_DVI_DTOP2_00_L, BIT(4), BIT(4)); // enable EQ new mode
360 W2BYTEMSK(REG_DVI_DTOP2_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
361 }
362 else
363 {
364 W2BYTEMSK(REG_DVI_DTOP2_00_L, 0, BIT(4)); // disable EQ new mode
365 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BIT(0)); // disable autoEQ controller
366 }
367 }
368 }
369
370 break;
371 #endif
372
373 default:
374
375 break;
376 };
377 }
378
379 //**************************************************************************
380 // [Function Name]:
381 // _mhal_mhl_HdmiBypassModeSetting()
382 // [Description]
383 // MHL HDMI bypass setting
384 // [Arguments]:
385 //
386 // [Return]:
387 //
388 //**************************************************************************
_mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect)389 void _mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect)
390 {
391 switch(ucCbusSelect)
392 {
393 #if(MHL_FUNCTION_SUPPORT_PORTA)
394 case MHL_CBUS_SELECT_PORTA:
395 if(GET_MHL_PATH_SUPPORT_PORTA())
396 {
397 W2BYTEMSK(REG_DVI_DTOP_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL
398 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
399 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
400 W2BYTEMSK(REG_DVI_DTOP_3B_L, 0, BIT(4)); // overwirte enable
401 W2BYTEMSK(REG_DVI_DTOP_3D_L, 0, BIT(4)); // overwirte enable
402 W2BYTEMSK(REG_DVI_DTOP_3F_L, 0, BIT(4)); // overwirte enable
403 W2BYTE(REG_DVI_DTOP_30_L, 0);
404 W2BYTEMSK(REG_DVI_DTOP_2F_L, 0, BMASK(15:4)| BMASK(3:2));
405 W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
406 W2BYTEMSK(REG_DVI_ATOP_38_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
407 W2BYTEMSK(REG_DVI_ATOP_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
408 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator
409 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble
410
411 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
412 {
413 W2BYTEMSK(REG_DVI_DTOP_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0));
414 }
415 }
416
417 break;
418 #endif
419
420 #if(MHL_FUNCTION_SUPPORT_PORTB)
421 case MHL_CBUS_SELECT_PORTB:
422 if(GET_MHL_PATH_SUPPORT_PORTB())
423 {
424 W2BYTEMSK(REG_DVI_DTOP1_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL
425 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
426 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
427 W2BYTEMSK(REG_DVI_DTOP1_3B_L, 0, BIT(4)); // overwirte enable
428 W2BYTEMSK(REG_DVI_DTOP1_3D_L, 0, BIT(4)); // overwirte enable
429 W2BYTEMSK(REG_DVI_DTOP1_3F_L, 0, BIT(4)); // overwirte enable
430 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
431 W2BYTEMSK(REG_DVI_ATOP1_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
432 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BIT(7)); // power on DVI PLL
433 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator
434 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(2:1)); // [2:0]: power down RD
435 W2BYTEMSK(REG_DVI_ATOP1_74_L, 0, BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ
436 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
437
438 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
439 {
440 W2BYTEMSK(REG_DVI_DTOP1_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0));
441 }
442 }
443
444 break;
445 #endif
446
447 #if(MHL_FUNCTION_SUPPORT_PORTC)
448 case MHL_CBUS_SELECT_PORTC:
449 if(GET_MHL_PATH_SUPPORT_PORTC())
450 {
451 W2BYTEMSK(REG_DVI_DTOP3_27_L, 0, BMASK(2:1)); // [2:1]: MHL_SEL
452 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
453 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
454 W2BYTEMSK(REG_DVI_DTOP3_3B_L, 0, BIT(4)); // overwirte enable
455 W2BYTEMSK(REG_DVI_DTOP3_3D_L, 0, BIT(4)); // overwirte enable
456 W2BYTEMSK(REG_DVI_DTOP3_3F_L, 0, BIT(4)); // overwirte enable
457 W2BYTE(REG_DVI_DTOP3_30_L, 0);
458 W2BYTEMSK(REG_DVI_DTOP3_2F_L, 0, BMASK(15:4)| BMASK(3:2));
459 W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
460 W2BYTEMSK(REG_DVI_ATOP3_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
461 W2BYTEMSK(REG_DVI_ATOP3_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
462 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator
463 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
464
465 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
466 {
467 W2BYTEMSK(REG_DVI_DTOP3_0C_L, MHL_IMPEDANCE_VALUE, BIT(9)| BMASK(3:0));
468 }
469 }
470
471 break;
472 #endif
473
474 #if(MHL_FUNCTION_SUPPORT_PORTD)
475 case MHL_CBUS_SELECT_PORTD:
476 if(GET_MHL_PATH_SUPPORT_PORTD())
477 {
478 W2BYTEMSK(REG_DVI_DTOP2_27_L, 0x2C6C, BMASK(14:0)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, [0]: MHL enable
479 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
480 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // auto clear phase accumulator
481 W2BYTEMSK(REG_DVI_DTOP2_3B_L, 0, BIT(4)); // overwirte enable
482 W2BYTEMSK(REG_DVI_DTOP2_3D_L, 0, BIT(4)); // overwirte enable
483 W2BYTEMSK(REG_DVI_DTOP2_3F_L, 0, BIT(4)); // overwirte enable
484 W2BYTE(REG_DVI_DTOP2_30_L, 0);
485 W2BYTEMSK(REG_DVI_DTOP2_2F_L, 0, BMASK(15:4)| BMASK(3:2));
486 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
487 W2BYTEMSK(REG_DVI_ATOP2_35_L, 0, BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
488 W2BYTEMSK(REG_DVI_ATOP2_5E_L, 0, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
489 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator
490 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
491
492 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
493 {
494 W2BYTEMSK(REG_DVI_DTOP2_0C_L, MHL_IMPEDANCE_VALUE, BIT(9) |BMASK(3:0));
495 }
496 }
497
498 break;
499 #endif
500
501 default:
502
503 break;
504 };
505
506 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, TRUE);
507 }
508
509 //**************************************************************************
510 // [Function Name]:
511 // _mhal_mhl_Mhl24bitsModeSetting()
512 // [Description]
513 // MHL 24 bits mode setting
514 // [Arguments]:
515 //
516 // [Return]:
517 //
518 //**************************************************************************
_mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect)519 void _mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect)
520 {
521 switch(ucCbusSelect)
522 {
523 #if(MHL_FUNCTION_SUPPORT_PORTA)
524 case MHL_CBUS_SELECT_PORTA:
525 if(GET_MHL_PATH_SUPPORT_PORTA())
526 {
527 W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL
528 W2BYTEMSK(REG_DVI_DTOP_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
529 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4)); // auto clear phase accumulator
530 W2BYTEMSK(REG_DVI_DTOP_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
531 W2BYTEMSK(REG_DVI_DTOP_3B_L, BIT(4), BIT(4)); // overwirte enable
532 W2BYTEMSK(REG_DVI_DTOP_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
533 W2BYTEMSK(REG_DVI_DTOP_3D_L, BIT(4), BIT(4)); // overwirte enable
534 W2BYTEMSK(REG_DVI_DTOP_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
535 W2BYTEMSK(REG_DVI_DTOP_3F_L, BIT(4), BIT(4)); // overwirte enable
536 W2BYTE(REG_DVI_DTOP_30_L, (MHL_UNLOCK_RESOLUTION << 8) |MHL_LOCK_RESOLUTION);
537 W2BYTEMSK(REG_DVI_DTOP_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2));
538 W2BYTEMSK(REG_DVI_ATOP_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
539 W2BYTEMSK(REG_DVI_ATOP_38_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
540 W2BYTEMSK(REG_DVI_ATOP_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
541 W2BYTEMSK(REG_HDCP_09_L, 0, BIT(0)); // PP mode + HDCP eanble
542
543 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
544 {
545 W2BYTEMSK(REG_DVI_DTOP_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
546 }
547 }
548
549 break;
550 #endif
551
552 #if(MHL_FUNCTION_SUPPORT_PORTB)
553 case MHL_CBUS_SELECT_PORTB:
554 if(GET_MHL_PATH_SUPPORT_PORTB())
555 {
556 W2BYTEMSK(REG_DVI_DTOP1_27_L, BIT(2), BMASK(2:1)); // [2:1]: MHL_SEL
557 W2BYTEMSK(REG_DVI_DTOP1_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
558 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4)); // auto clear phase accumulator
559 W2BYTEMSK(REG_DVI_DTOP1_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
560 W2BYTEMSK(REG_DVI_DTOP1_3B_L, BIT(4), BIT(4)); // overwirte enable
561 W2BYTEMSK(REG_DVI_DTOP1_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
562 W2BYTEMSK(REG_DVI_DTOP1_3D_L, BIT(4), BIT(4)); // overwirte enable
563 W2BYTEMSK(REG_DVI_DTOP1_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
564 W2BYTEMSK(REG_DVI_DTOP1_3F_L, BIT(4), BIT(4)); // overwirte enable
565 W2BYTEMSK(REG_DVI_ATOP1_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
566 W2BYTEMSK(REG_DVI_ATOP1_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICTL value
567 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(2:1), BMASK(2:1)); // [2:0]: power down RD
568 W2BYTEMSK(REG_DVI_ATOP1_74_L, BMASK(5:0), BMASK(5:0)); // [2:0]: power down DPLPHI, [5:3]: power down DPLPHQ
569 W2BYTEMSK(REG_HDCP1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
570
571 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
572 {
573 W2BYTEMSK(REG_DVI_DTOP1_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
574 }
575 }
576
577 break;
578 #endif
579
580 #if(MHL_FUNCTION_SUPPORT_PORTC)
581 case MHL_CBUS_SELECT_PORTC:
582 if(GET_MHL_PATH_SUPPORT_PORTC())
583 {
584 W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, [0]: MHL enable
585 W2BYTEMSK(REG_DVI_DTOP3_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
586 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4)); // auto clear phase accumulator
587 W2BYTEMSK(REG_DVI_DTOP3_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
588 W2BYTEMSK(REG_DVI_DTOP3_3B_L, BIT(4), BIT(4)); // overwirte enable
589 W2BYTEMSK(REG_DVI_DTOP3_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
590 W2BYTEMSK(REG_DVI_DTOP3_3D_L, BIT(4), BIT(4)); // overwirte enable
591 W2BYTEMSK(REG_DVI_DTOP3_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
592 W2BYTEMSK(REG_DVI_DTOP3_3F_L, BIT(4), BIT(4)); // overwirte enable
593 W2BYTE(REG_DVI_DTOP3_30_L, (MHL_UNLOCK_RESOLUTION << 8) |MHL_LOCK_RESOLUTION);
594 W2BYTEMSK(REG_DVI_DTOP3_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2));
595 W2BYTEMSK(REG_DVI_ATOP3_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
596 W2BYTEMSK(REG_DVI_ATOP3_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
597 W2BYTEMSK(REG_DVI_ATOP3_5E_L, BIT(4)| ucIControlValue, BMASK(4:0)); //[4]: overwrtie DPL ICTL value, [3:0]: ictl overwrtie value
598 W2BYTEMSK(REG_HDCP3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
599
600 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
601 {
602 W2BYTEMSK(REG_DVI_DTOP3_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
603 }
604 }
605
606 break;
607 #endif
608
609 #if(MHL_FUNCTION_SUPPORT_PORTD)
610 case MHL_CBUS_SELECT_PORTD:
611 if(GET_MHL_PATH_SUPPORT_PORTD())
612 {
613 W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(2), BMASK(2:1)); // [7]: MHL HW mode, [1]: MHL pack-pixel mode, [0]: MHL enable
614 W2BYTEMSK(REG_DVI_DTOP2_20_L, MHL_EQ_SETTING_VALUE, BMASK(3:0)); // EQ strength
615 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4)); // auto clear phase accumulator
616 W2BYTEMSK(REG_DVI_DTOP2_3A_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
617 W2BYTEMSK(REG_DVI_DTOP2_3B_L, BIT(4), BIT(4)); // overwirte enable
618 W2BYTEMSK(REG_DVI_DTOP2_3C_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
619 W2BYTEMSK(REG_DVI_DTOP2_3D_L, BIT(4), BIT(4)); // overwirte enable
620 W2BYTEMSK(REG_DVI_DTOP2_3E_L, MHL_PHASE_CODE_VALUE, 0xFFFF); // phase code = 0x0A
621 W2BYTEMSK(REG_DVI_DTOP2_3F_L, BIT(4), BIT(4)); // overwirte enable
622 W2BYTE(REG_DVI_DTOP2_30_L, (MHL_UNLOCK_RESOLUTION << 8) |MHL_LOCK_RESOLUTION);
623 W2BYTEMSK(REG_DVI_DTOP2_2F_L, (MHL_DIGITAL_UNLOCK_RANGE << 4)| BMASK(3:2), BMASK(15:4)| BMASK(3:2));
624 W2BYTEMSK(REG_DVI_ATOP2_32_L, BIT(8) |BIT(4) |BIT(0), BMASK(9:8) |BMASK(6:4) |BMASK(2:0)); // HF, Enable ACDR, Bypass CLK
625 W2BYTEMSK(REG_DVI_ATOP2_35_L, BIT(10) |BIT(8), BIT(10) |BIT(8)); // [10]: auto acdr mode selection, [8]: enable auto acdr function
626 W2BYTEMSK(REG_DVI_ATOP2_5E_L, BIT(4) |ucIControlValue, BMASK(4:0)); // enable to overwrtie DPL ICTL value
627 W2BYTEMSK(REG_HDCP2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
628
629 if(ucImpedanceValue != MHL_IMPEDANCE_VALUE)
630 {
631 W2BYTEMSK(REG_DVI_DTOP2_0C_L, BIT(9)| ucImpedanceValue, BIT(9)| BMASK(3:0));
632 }
633 }
634
635 break;
636 #endif
637
638 default:
639
640 break;
641 };
642
643 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, FALSE);
644 }
645
646 //**************************************************************************
647 // [Function Name]:
648 // _mhal_mhl_MhlPackedPixelModeSetting()
649 // [Description]
650 // MHL packed pixel mode setting
651 // [Arguments]:
652 //
653 // [Return]:
654 //
655 //**************************************************************************
_mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)656 void _mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)
657 {
658 switch(ucCbusSelect)
659 {
660 #if(MHL_FUNCTION_SUPPORT_PORTA)
661 case MHL_CBUS_SELECT_PORTA:
662 if(GET_MHL_PATH_SUPPORT_PORTA())
663 {
664 W2BYTEMSK(REG_DVI_DTOP_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
665 W2BYTEMSK(REG_DVI_ATOP_32_L, BMASK(9:8), BMASK(9:8)); // HF
666 W2BYTEMSK(REG_HDCP_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
667 }
668
669 break;
670 #endif
671
672 #if(MHL_FUNCTION_SUPPORT_PORTB)
673 case MHL_CBUS_SELECT_PORTB:
674 if(GET_MHL_PATH_SUPPORT_PORTB())
675 {
676 W2BYTEMSK(REG_DVI_DTOP1_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
677 W2BYTEMSK(REG_DVI_ATOP1_32_L, BMASK(9:8), BMASK(9:8)); // HF
678 W2BYTEMSK(REG_HDCP1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
679 }
680
681 break;
682 #endif
683
684 #if(MHL_FUNCTION_SUPPORT_PORTC)
685 case MHL_CBUS_SELECT_PORTC:
686 if(GET_MHL_PATH_SUPPORT_PORTC())
687 {
688 W2BYTEMSK(REG_DVI_DTOP3_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
689 W2BYTEMSK(REG_DVI_ATOP3_32_L, BMASK(9:8), BMASK(9:8)); // HF
690 W2BYTEMSK(REG_HDCP3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
691 }
692
693 break;
694 #endif
695
696 #if(MHL_FUNCTION_SUPPORT_PORTD)
697 case MHL_CBUS_SELECT_PORTD:
698 if(GET_MHL_PATH_SUPPORT_PORTD())
699 {
700 W2BYTEMSK(REG_DVI_DTOP2_27_L, BMASK(2:1), BMASK(2:1)); // [2:1]: MHL_SEL
701 W2BYTEMSK(REG_DVI_ATOP2_32_L, BMASK(9:8), BMASK(9:8)); // HF
702 W2BYTEMSK(REG_HDCP2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
703 }
704
705 break;
706 #endif
707
708 default:
709
710 break;
711 };
712 }
713
714 //**************************************************************************
715 // [Function Name]:
716 // _mhal_mhl_RxRtermControl()
717 // [Description]
718 // MHL TMDS termination resistor control
719 // [Arguments]:
720 //
721 // [Return]:
722 //
723 //**************************************************************************
_mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect,RXRtermControl_T rctrl)724 void _mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect, RXRtermControl_T rctrl)
725 {
726 switch(ucCbusSelect)
727 {
728 #if(MHL_FUNCTION_SUPPORT_PORTA)
729 case MHL_CBUS_SELECT_PORTA:
730 if(GET_MHL_PATH_SUPPORT_PORTA())
731 {
732 if (rctrl == RX_HDMI_RTERM)
733 {
734 W2BYTEMSK(REG_DVI_ATOP_60_L, 0, BMASK(13:11));// data R-term
735 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term
736 }
737 else if (rctrl == RX_MHL_RTERM)
738 {
739 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:12), BMASK(13:11));// data R-term
740 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(8));// clock R-term
741 }
742 else if (rctrl == RX_RTERM_OFF)
743 {
744 W2BYTEMSK(REG_DVI_ATOP_60_L, BMASK(13:11), BMASK(13:11));// data R-term
745 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(8), BIT(8));// clock R-term
746 }
747 }
748
749 break;
750 #endif
751
752 #if(MHL_FUNCTION_SUPPORT_PORTB)
753 case MHL_CBUS_SELECT_PORTB:
754 if(GET_MHL_PATH_SUPPORT_PORTB())
755 {
756 if (rctrl == RX_HDMI_RTERM)
757 {
758 W2BYTEMSK(REG_DVI_ATOP1_60_L, 0, BMASK(13:11));// data R-term
759 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term
760 }
761 else if (rctrl == RX_MHL_RTERM)
762 {
763 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:12), BMASK(13:11));// data R-term
764 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(9));// clock R-term
765 }
766 else if (rctrl == RX_RTERM_OFF)
767 {
768 W2BYTEMSK(REG_DVI_ATOP1_60_L, BMASK(13:11), BMASK(13:11));// data R-term
769 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(9), BIT(9));// clock R-term
770 }
771 }
772
773 break;
774 #endif
775
776 #if(MHL_FUNCTION_SUPPORT_PORTC)
777 case MHL_CBUS_SELECT_PORTC:
778 if(GET_MHL_PATH_SUPPORT_PORTC())
779 {
780 if (rctrl == RX_HDMI_RTERM)
781 {
782 W2BYTEMSK(REG_DVI_ATOP3_60_L, 0, BMASK(13:11));// data R-term
783 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term
784 }
785 else if (rctrl == RX_MHL_RTERM)
786 {
787 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:12), BMASK(13:11));// data R-term
788 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(11));// clock R-term
789 }
790 else if (rctrl == RX_RTERM_OFF)
791 {
792 W2BYTEMSK(REG_DVI_ATOP3_60_L, BMASK(13:11), BMASK(13:11));// data R-term
793 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(11), BIT(11));// clock R-term
794 }
795 }
796
797 break;
798 #endif
799
800 #if(MHL_FUNCTION_SUPPORT_PORTD)
801 case MHL_CBUS_SELECT_PORTD:
802 if(GET_MHL_PATH_SUPPORT_PORTD())
803 {
804 if (rctrl == RX_HDMI_RTERM)
805 {
806 W2BYTEMSK(REG_DVI_ATOP2_60_L, 0, BMASK(13:11));// data R-term
807 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term
808 }
809 else if (rctrl == RX_MHL_RTERM)
810 {
811 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:12), BMASK(13:11));// data R-term
812 W2BYTEMSK(REG_PM_SLEEP_4B_L, 0, BIT(10));// clock R-term
813 }
814 else if (rctrl == RX_RTERM_OFF)
815 {
816 W2BYTEMSK(REG_DVI_ATOP2_60_L, BMASK(13:11), BMASK(13:11));// data R-term
817 W2BYTEMSK(REG_PM_SLEEP_4B_L, BIT(10), BIT(10));// clock R-term
818 }
819 }
820
821 break;
822 #endif
823
824 default:
825
826 break;
827 };
828 }
829
830 //**************************************************************************
831 // [Function Name]:
832 // _mhal_mhl_CbusForceToStandby()
833 // [Description]
834 //
835 // [Arguments]:
836 //
837 // [Return]:
838 //
839 //**************************************************************************
_mhal_mhl_CbusForceToStandby(void)840 void _mhal_mhl_CbusForceToStandby(void)
841 {
842 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
843 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode
844 }
845
846 //**************************************************************************
847 // [Function Name]:
848 // _mhal_mhl_MHLForceToAttach()
849 // [Description]:
850 //
851 // [Arguments]:
852 //
853 // [Return]:
854 //
855 //**************************************************************************
_mhal_mhl_MHLForceToAttach(void)856 void _mhal_mhl_MHLForceToAttach(void)
857 {
858 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14));
859 }
860
861 #if(DMHL_LG_PRADA_PATCH)
862 //**************************************************************************
863 // [Function Name]:
864 // _mhal_mhl_AdjustCommonModeResistor()
865 // [Description]:
866 //
867 // [Arguments]:
868 //
869 // [Return]:
870 //
871 //**************************************************************************
_mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect,MS_BOOL bflag)872 void _mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect, MS_BOOL bflag)
873 {
874 switch(ucCbusSelect)
875 {
876 #if(MHL_FUNCTION_SUPPORT_PORTA)
877 case MHL_CBUS_SELECT_PORTA:
878 if(GET_MHL_PATH_SUPPORT_PORTA())
879 {
880 W2BYTEMSK(REG_DVI_DTOP_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
881 }
882
883 break;
884 #endif
885
886 #if(MHL_FUNCTION_SUPPORT_PORTB)
887 case MHL_CBUS_SELECT_PORTB:
888 if(GET_MHL_PATH_SUPPORT_PORTB())
889 {
890 W2BYTEMSK(REG_DVI_DTOP1_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
891 }
892
893 break;
894 #endif
895
896 #if(MHL_FUNCTION_SUPPORT_PORTC)
897 case MHL_CBUS_SELECT_PORTC:
898 if(GET_MHL_PATH_SUPPORT_PORTC())
899 {
900 W2BYTEMSK(REG_DVI_DTOP3_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
901 }
902
903 break;
904 #endif
905
906 #if(MHL_FUNCTION_SUPPORT_PORTD)
907 case MHL_CBUS_SELECT_PORTD:
908 if(GET_MHL_PATH_SUPPORT_PORTD())
909 {
910 W2BYTEMSK(REG_DVI_DTOP2_27_L, bflag ?0 :BIT(0), BIT(0)); // [0]: MHL enable
911 }
912
913 break;
914 #endif
915
916 default:
917
918 break;
919 };
920 }
921
922 #endif
923
924 //**************************************************************************
925 // [Function Name]:
926 // _mhal_mhl_ClockBigChangeFlag()
927 // [Description]:
928 //
929 // [Arguments]:
930 //
931 // [Return]:
932 //
933 //**************************************************************************
_mhal_mhl_ClockBigChangeFlag(MS_U8 ucCbusSelect)934 MS_BOOL _mhal_mhl_ClockBigChangeFlag(MS_U8 ucCbusSelect)
935 {
936 MS_BOOL bindex = FALSE;
937
938 switch(ucCbusSelect)
939 {
940 #if(MHL_FUNCTION_SUPPORT_PORTA)
941 case MHL_CBUS_SELECT_PORTA:
942 if(GET_MHL_PATH_SUPPORT_PORTA())
943 {
944 bindex = ((R2BYTE(REG_DVI_ATOP_70_L) &BIT(0)) ?TRUE: FALSE);
945
946 if(bindex)
947 {
948 W2BYTEMSK(REG_DVI_ATOP_71_L, BIT(8), BIT(8));
949 W2BYTEMSK(REG_DVI_ATOP_71_L, 0, BIT(8));
950 }
951 }
952
953 break;
954 #endif
955
956 #if(MHL_FUNCTION_SUPPORT_PORTB)
957 case MHL_CBUS_SELECT_PORTB:
958 if(GET_MHL_PATH_SUPPORT_PORTB())
959 {
960 bindex = ((R2BYTE(REG_DVI_ATOP1_70_L) &BIT(0)) ?TRUE: FALSE);
961
962 if(bindex)
963 {
964 W2BYTEMSK(REG_DVI_ATOP1_71_L, BIT(8), BIT(8));
965 W2BYTEMSK(REG_DVI_ATOP1_71_L, 0, BIT(8));
966 }
967 }
968
969 break;
970 #endif
971
972 #if(MHL_FUNCTION_SUPPORT_PORTC)
973 case MHL_CBUS_SELECT_PORTC:
974 if(GET_MHL_PATH_SUPPORT_PORTC())
975 {
976 bindex = ((R2BYTE(REG_DVI_ATOP3_70_L) &BIT(0)) ?TRUE: FALSE);
977
978 if(bindex)
979 {
980 W2BYTEMSK(REG_DVI_ATOP3_71_L, BIT(8), BIT(8));
981 W2BYTEMSK(REG_DVI_ATOP3_71_L, 0, BIT(8));
982 }
983 }
984
985 break;
986 #endif
987
988 #if(MHL_FUNCTION_SUPPORT_PORTD)
989 case MHL_CBUS_SELECT_PORTD:
990 if(GET_MHL_PATH_SUPPORT_PORTD())
991 {
992 bindex = ((R2BYTE(REG_DVI_ATOP2_70_L) &BIT(0)) ?TRUE: FALSE);
993
994 if(bindex)
995 {
996 W2BYTEMSK(REG_DVI_ATOP2_71_L, BIT(8), BIT(8));
997 W2BYTEMSK(REG_DVI_ATOP2_71_L, 0, BIT(8));
998 }
999 }
1000
1001 break;
1002 #endif
1003
1004 default:
1005
1006 break;
1007 };
1008
1009 return bindex;
1010 }
1011
1012 //**************************************************************************
1013 // [Function Name]:
1014 // _mhal_mhl_CheckClockStatus()
1015 // [Description]:
1016 //
1017 // [Arguments]:
1018 //
1019 // [Return]:
1020 //
1021 //**************************************************************************
_mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)1022 MS_U8 _mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)
1023 {
1024 MS_BOOL bStable = FALSE;
1025 MS_U16 usClkCount = 0;
1026
1027 switch(ucCbusSelect)
1028 {
1029 #if(MHL_FUNCTION_SUPPORT_PORTA)
1030 case MHL_CBUS_SELECT_PORTA:
1031 if(GET_MHL_PATH_SUPPORT_PORTA())
1032 {
1033 usClkCount = R2BYTE(REG_DVI_DTOP_17_L) & 0x0FFF;
1034
1035 if((R2BYTE(REG_DVI_DTOP_16_L) &BIT(9)) == BIT(9))
1036 {
1037 bStable = TRUE;
1038
1039 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1040 {
1041 bStable = FALSE;
1042 }
1043 }
1044 }
1045
1046 break;
1047 #endif
1048
1049 #if(MHL_FUNCTION_SUPPORT_PORTB)
1050 case MHL_CBUS_SELECT_PORTB:
1051 if(GET_MHL_PATH_SUPPORT_PORTB())
1052 {
1053 usClkCount = R2BYTE(REG_DVI_DTOP1_17_L) & 0x0FFF;
1054
1055 if((R2BYTE(REG_DVI_DTOP1_16_L) &BIT(9)) == BIT(9))
1056 {
1057 bStable = TRUE;
1058
1059 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1060 {
1061 bStable = FALSE;
1062 }
1063 }
1064 }
1065
1066 break;
1067 #endif
1068
1069 #if(MHL_FUNCTION_SUPPORT_PORTC)
1070 case MHL_CBUS_SELECT_PORTC:
1071 if(GET_MHL_PATH_SUPPORT_PORTC())
1072 {
1073 usClkCount = R2BYTE(REG_DVI_DTOP3_17_L) & 0x0FFF;
1074
1075 if((R2BYTE(REG_DVI_DTOP3_16_L) &BIT(9)) == BIT(9))
1076 {
1077 bStable = TRUE;
1078
1079 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1080 {
1081 bStable = FALSE;
1082 }
1083 }
1084 }
1085
1086 break;
1087 #endif
1088
1089 #if(MHL_FUNCTION_SUPPORT_PORTD)
1090 case MHL_CBUS_SELECT_PORTD:
1091 if(GET_MHL_PATH_SUPPORT_PORTD())
1092 {
1093 usClkCount = R2BYTE(REG_DVI_DTOP2_17_L) & 0x0FFF;
1094
1095 if((R2BYTE(REG_DVI_DTOP2_16_L) &BIT(9)) == BIT(9))
1096 {
1097 bStable = TRUE;
1098
1099 if((usClkCount < CBUS_CLOCK_DETECT_LEVEL) || _mhal_mhl_ClockBigChangeFlag(ucCbusSelect))
1100 {
1101 bStable = FALSE;
1102 }
1103 }
1104 }
1105
1106 break;
1107 #endif
1108
1109 default:
1110
1111 break;
1112 };
1113
1114 return bStable;
1115 }
1116
1117 //**************************************************************************
1118 // [Function Name]:
1119 // _mhal_mhl_RtermHWControl()
1120 // [Description]
1121 //
1122 // [Arguments]:
1123 //
1124 // [Return]:
1125 //
1126 //**************************************************************************
_mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect,MS_BOOL bFlag)1127 void _mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect, MS_BOOL bFlag)
1128 {
1129 switch(ucCbusSelect)
1130 {
1131 #if(MHL_FUNCTION_SUPPORT_PORTA)
1132 case MHL_CBUS_SELECT_PORTA:
1133 if(GET_MHL_PATH_SUPPORT_PORTA())
1134 {
1135 W2BYTEMSK(REG_DVI_ATOP_7F_L, bFlag ?BIT(14) :0, BIT(14));
1136 }
1137
1138 break;
1139 #endif
1140
1141 #if(MHL_FUNCTION_SUPPORT_PORTB)
1142 case MHL_CBUS_SELECT_PORTB:
1143 if(GET_MHL_PATH_SUPPORT_PORTB())
1144 {
1145
1146 }
1147
1148 break;
1149 #endif
1150
1151 #if(MHL_FUNCTION_SUPPORT_PORTC)
1152 case MHL_CBUS_SELECT_PORTC:
1153 if(GET_MHL_PATH_SUPPORT_PORTC())
1154 {
1155 W2BYTEMSK(REG_DVI_ATOP3_01_L, bFlag ?BIT(0) :0, BIT(0));
1156 }
1157
1158 break;
1159 #endif
1160
1161 #if(MHL_FUNCTION_SUPPORT_PORTD)
1162 case MHL_CBUS_SELECT_PORTD:
1163 if(GET_MHL_PATH_SUPPORT_PORTD())
1164 {
1165 W2BYTEMSK(REG_DVI_ATOP2_00_L, bFlag ?BIT(0) :0, BIT(0));
1166 }
1167
1168 break;
1169 #endif
1170
1171 default:
1172
1173 break;
1174 };
1175 }
1176
1177 //**************************************************************************
1178 // [Function Name]:
1179 // _mhal_mhl_ChangeScalerMainMux()
1180 // [Description]
1181 //
1182 // [Arguments]:
1183 //
1184 // [Return]:
1185 //
1186 //**************************************************************************
_mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)1187 void _mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)
1188 {
1189 MS_U8 ucScalerMainMux = (R2BYTE(0x102E02) &BMASK(7:4)) >> 4;
1190
1191 if(bFlag)
1192 {
1193 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI)
1194 {
1195 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4));
1196 }
1197 }
1198 else
1199 {
1200 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_MHL)
1201 {
1202 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4));
1203 }
1204 }
1205 }
1206
1207 //**************************************************************************
1208 // [Function Name]:
1209 // _mhal_mhl_AudioPathSelect()
1210 // [Description]
1211 //
1212 // [Arguments]:
1213 //
1214 // [Return]:
1215 //
1216 //**************************************************************************
_mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)1217 void _mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)
1218 {
1219 W2BYTEMSK(REG_HDMI2_08_L, bMHLPath ?BIT(0) :0, BIT(0)); // [0]: audio source selection, 0: HDMI / 1: MHL
1220 }
1221
1222 //**************************************************************************
1223 // [Function Name]:
1224 // _mhal_mhl_CbusAndClockSelect()
1225 // [Description]
1226 //
1227 // [Arguments]:
1228 //
1229 // [Return]:
1230 //
1231 //**************************************************************************
_mhal_mhl_CbusAndClockSelect(void)1232 void _mhal_mhl_CbusAndClockSelect(void)
1233 {
1234 MS_U8 ucClockSelect = MHL_DVI_PORT_A;
1235
1236 if(GET_MHL_PATH_SUPPORT_PORTA())
1237 {
1238 ucClockSelect = MHL_DVI_PORT_A;
1239 }
1240 else if(GET_MHL_PATH_SUPPORT_PORTB())
1241 {
1242 ucClockSelect = MHL_DVI_PORT_B;
1243 }
1244 else if(GET_MHL_PATH_SUPPORT_PORTC())
1245 {
1246 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(6)| BIT(8)| BIT(0)); // [0]: reg_hplugc_mhl_en
1247 ucClockSelect = MHL_DVI_PORT_C;
1248 }
1249 else if(GET_MHL_PATH_SUPPORT_PORTD())
1250 {
1251 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(8), BIT(14)| BIT(8)| BIT(0)); // [8]: reg_hpluga_mhl_en
1252 ucClockSelect = MHL_DVI_PORT_D;
1253 }
1254
1255 W2BYTEMSK(REG_DVI_ATOP_6A_L, (ucClockSelect << 2), BMASK(3:2)); // [3:2]: HDCP clock select
1256 }
1257
1258 //**************************************************************************
1259 // [Function Name]:
1260 // _mhal_mhl_PhyInitialSetting()
1261 // [Description]
1262 //
1263 // [Arguments]:
1264 //
1265 // [Return]:
1266 //
1267 //**************************************************************************
_mhal_mhl_PhyInitialSetting(MS_U8 ucCbusSelect)1268 void _mhal_mhl_PhyInitialSetting(MS_U8 ucCbusSelect)
1269 {
1270 switch(ucCbusSelect)
1271 {
1272 #if(MHL_FUNCTION_SUPPORT_PORTA)
1273 case MHL_CBUS_SELECT_PORTA:
1274 if(GET_MHL_PATH_SUPPORT_PORTA())
1275 {
1276 W2BYTEMSK(REG_DVI_DTOP_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria
1277 W2BYTEMSK(REG_DVI_DTOP_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2
1278 }
1279
1280 break;
1281 #endif
1282
1283 #if(MHL_FUNCTION_SUPPORT_PORTB)
1284 case MHL_CBUS_SELECT_PORTB:
1285 if(GET_MHL_PATH_SUPPORT_PORTB())
1286 {
1287
1288 }
1289
1290 break;
1291 #endif
1292
1293 #if(MHL_FUNCTION_SUPPORT_PORTC)
1294 case MHL_CBUS_SELECT_PORTC:
1295 if(GET_MHL_PATH_SUPPORT_PORTC())
1296 {
1297 W2BYTEMSK(REG_DVI_DTOP3_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria
1298 W2BYTEMSK(REG_DVI_DTOP3_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2
1299 }
1300
1301 break;
1302 #endif
1303
1304 #if(MHL_FUNCTION_SUPPORT_PORTD)
1305 case MHL_CBUS_SELECT_PORTD:
1306 if(GET_MHL_PATH_SUPPORT_PORTD())
1307 {
1308 W2BYTEMSK(REG_DVI_DTOP2_27_L, BIT(15), BIT(15)); // [15]: Enable MHL packed-pixel mode criteria
1309 W2BYTEMSK(REG_DVI_DTOP2_28_L, BIT(0), BIT(0)); // [0]: MHL v1.2
1310 }
1311
1312 break;
1313 #endif
1314
1315 default:
1316
1317 break;
1318 };
1319 }
1320
1321 //-------------------------------------------------------------------------------------------------
1322 // Global Functions
1323 //-------------------------------------------------------------------------------------------------
1324
1325 //**************************************************************************
1326 // [Function Name]:
1327 // mhal_mhl_GetCbusSelect()
1328 // [Description]
1329 //
1330 // [Arguments]:
1331 //
1332 // [Return]:
1333 //
1334 //**************************************************************************
mhal_mhl_GetCbusSelect(MS_U8 ucPort)1335 MS_U8 mhal_mhl_GetCbusSelect(MS_U8 ucPort)
1336 {
1337 MS_U8 uctemp = MHL_CBUS_SELECT_MASK;
1338
1339 switch(ucPort)
1340 {
1341 case MHL_DVI_PORT_A:
1342 uctemp = MHL_CBUS_SELECT_PORTA;
1343 break;
1344
1345 case MHL_DVI_PORT_B:
1346 uctemp = MHL_CBUS_SELECT_PORTB;
1347 break;
1348
1349 case MHL_DVI_PORT_C:
1350 uctemp = MHL_CBUS_SELECT_PORTC;
1351 break;
1352
1353 case MHL_DVI_PORT_D:
1354 uctemp = MHL_CBUS_SELECT_PORTD;
1355 break;
1356
1357 default:
1358
1359 break;
1360 };
1361
1362 return uctemp;
1363 }
1364
1365 //**************************************************************************
1366 // [Function Name]:
1367 // mhal_mhl_GetInputPort()
1368 // [Description]
1369 // MHL get current input port
1370 // [Arguments]:
1371 //
1372 // [Return]:
1373 //
1374 //**************************************************************************
mhal_mhl_GetInputPort(void)1375 MS_U8 mhal_mhl_GetInputPort(void)
1376 {
1377 return (R2BYTE(REG_DVI_ATOP_6A_L) &BMASK(1:0));
1378 }
1379
1380 //**************************************************************************
1381 // [Function Name]:
1382 // mhal_mhl_CheckInputPort()
1383 // [Description]
1384 // MHL check current input port
1385 // [Arguments]:
1386 //
1387 // [Return]:
1388 //
1389 //**************************************************************************
mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)1390 MS_BOOL mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)
1391 {
1392 MS_BOOL bindex = FALSE;
1393
1394 if(mhal_mhl_GetCbusSelect(mhal_mhl_GetInputPort()) == ucCbusSelect)
1395 {
1396 bindex = TRUE;
1397 }
1398
1399 return bindex;
1400 }
1401
1402 //**************************************************************************
1403 // [Function Name]:
1404 // mhal_mhl_CheckPIPWindow()
1405 // [Description]
1406 //
1407 // [Arguments]:
1408 //
1409 // [Return]:
1410 //
1411 //**************************************************************************
mhal_mhl_CheckPIPWindow(void)1412 MS_BOOL mhal_mhl_CheckPIPWindow(void)
1413 {
1414 MS_BOOL bFlag = FALSE;
1415 MS_U8 ucScalerMainMux = R2BYTE(0x102E02) &BMASK(7:0);
1416 MS_U8 ucScalerSubMux = ucScalerMainMux &BMASK(3:0);
1417
1418 ucScalerMainMux = (ucScalerMainMux &BMASK(7:4)) >> 4;
1419
1420 if((ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI) || (ucScalerMainMux == MHL_SCALER_MUX_SELECT_MHL)) // Check scaler main window mux
1421 {
1422 bFlag = TRUE;
1423 }
1424 else if((ucScalerSubMux == MHL_SCALER_MUX_SELECT_DVI) || (ucScalerSubMux == MHL_SCALER_MUX_SELECT_MHL)) // Check scaler sub window mux
1425 {
1426 bFlag = TRUE;
1427 }
1428
1429 return bFlag;
1430 }
1431
1432 //**************************************************************************
1433 // [Function Name]:
1434 // mhal_mhl_MHLSupportPath()
1435 // [Description]
1436 // MHL support path
1437 // [Arguments]:
1438 //
1439 // [Return]:
1440 //
1441 //**************************************************************************
mhal_mhl_MHLSupportPath(MS_U8 ucSelect)1442 void mhal_mhl_MHLSupportPath(MS_U8 ucSelect)
1443 {
1444 ucMHLSupportPort = ucSelect;
1445
1446 if(GET_MHL_PATH_SUPPORT_PORTC() && GET_MHL_PATH_SUPPORT_PORTD())
1447 {
1448 msg_mhl(printf("** MHL Cbus illegal support path T^T\r\n"));
1449 }
1450 }
1451
1452 //**************************************************************************
1453 // [Function Name]:
1454 // mhal_mhl_CheckEfuseControlFlag()
1455 // [Description]
1456 //
1457 // [Arguments]:
1458 //
1459 // [Return]:
1460 //
1461 //**************************************************************************
mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)1462 MS_BOOL mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)
1463 {
1464 MS_BOOL bFlag = FALSE;
1465
1466 #if(MHL_EFUSE_FUNCTION_CONTROL)
1467 MS_U8 uctemp = 0;
1468
1469 if(!bEfuseFlag)
1470 {
1471 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
1472 {
1473 mhal_mhl_CbusIsolate(uctemp, TRUE);
1474 }
1475
1476 bFlag = TRUE;
1477 }
1478
1479 #endif
1480
1481 return bFlag;
1482 }
1483
1484 //**************************************************************************
1485 // [Function Name]:
1486 // mhal_mhl_InsertChipIDforCheck()
1487 // [Description]
1488 //
1489 // [Arguments]:
1490 //
1491 // [Return]:
1492 //
1493 //**************************************************************************
mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)1494 void mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)
1495 {
1496 ucChipIDValue = ucChipID;
1497
1498 msg_mhl(printf("** MHL Cbus index value %x\r\n", ucChipID));
1499 }
1500
1501 //**************************************************************************
1502 // [Function Name]:
1503 // mhal_mhl_CbusSelectSetMux()
1504 // [Description]
1505 //
1506 // [Arguments]:
1507 //
1508 // [Return]:
1509 //
1510 //**************************************************************************
mhal_mhl_CbusSelectSetMux(MS_U8 ucCbusSelect)1511 void mhal_mhl_CbusSelectSetMux(MS_U8 ucCbusSelect)
1512 {
1513 switch(ucCbusSelect)
1514 {
1515 #if(MHL_FUNCTION_SUPPORT_PORTA)
1516 case MHL_CBUS_SELECT_PORTA:
1517 if(GET_MHL_PATH_SUPPORT_PORTA())
1518 {
1519
1520 }
1521
1522 break;
1523 #endif
1524
1525 #if(MHL_FUNCTION_SUPPORT_PORTB)
1526 case MHL_CBUS_SELECT_PORTB:
1527 if(GET_MHL_PATH_SUPPORT_PORTB())
1528 {
1529
1530 }
1531
1532 break;
1533 #endif
1534
1535 #if(MHL_FUNCTION_SUPPORT_PORTC)
1536 case MHL_CBUS_SELECT_PORTC:
1537 if(GET_MHL_PATH_SUPPORT_PORTC())
1538 {
1539
1540 }
1541
1542 break;
1543 #endif
1544
1545 #if(MHL_FUNCTION_SUPPORT_PORTD)
1546 case MHL_CBUS_SELECT_PORTD:
1547 if(GET_MHL_PATH_SUPPORT_PORTD())
1548 {
1549
1550 }
1551
1552 break;
1553 #endif
1554
1555 default:
1556
1557 break;
1558 };
1559 }
1560
1561 //**************************************************************************
1562 // [Function Name]:
1563 // mhal_mhl_CableDetect()
1564 // [Description]
1565 // MHL cable detection
1566 // [Arguments]:
1567 //
1568 // [Return]:
1569 // TRUE: MHL cable plugged
1570 // FALSE: MHL cable unplugged
1571 //**************************************************************************
mhal_mhl_CableDetect(MS_U8 ucCbusSelect)1572 MS_BOOL mhal_mhl_CableDetect(MS_U8 ucCbusSelect)
1573 {
1574 MS_BOOL bFlag = FALSE;
1575
1576 switch(ucCbusSelect)
1577 {
1578 #if(MHL_FUNCTION_SUPPORT_PORTA)
1579 case MHL_CBUS_SELECT_PORTA:
1580 if(GET_MHL_PATH_SUPPORT_PORTA())
1581 {
1582 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
1583 }
1584
1585 break;
1586 #endif
1587
1588 #if(MHL_FUNCTION_SUPPORT_PORTB)
1589 case MHL_CBUS_SELECT_PORTB:
1590 if(GET_MHL_PATH_SUPPORT_PORTB())
1591 {
1592
1593 }
1594
1595 break;
1596 #endif
1597
1598 #if(MHL_FUNCTION_SUPPORT_PORTC)
1599 case MHL_CBUS_SELECT_PORTC:
1600 if(GET_MHL_PATH_SUPPORT_PORTC())
1601 {
1602 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
1603 }
1604
1605 break;
1606 #endif
1607
1608 #if(MHL_FUNCTION_SUPPORT_PORTD)
1609 case MHL_CBUS_SELECT_PORTD:
1610 if(GET_MHL_PATH_SUPPORT_PORTD())
1611 {
1612 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
1613 }
1614
1615 break;
1616 #endif
1617
1618 default:
1619
1620 break;
1621 };
1622
1623 return bFlag;
1624 }
1625
1626 //**************************************************************************
1627 // [Function Name]:
1628 // mhal_mhl_Accumulator_Clr()
1629 // [Description]
1630 // to clear accumulator when input is not MHL
1631 // [Arguments]:
1632 //
1633 // [Return]:
1634 //**************************************************************************
mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)1635 void mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)
1636 {
1637 switch(ucCbusSelect)
1638 {
1639 #if(MHL_FUNCTION_SUPPORT_PORTA)
1640 case MHL_CBUS_SELECT_PORTA:
1641 if(GET_MHL_PATH_SUPPORT_PORTA())
1642 {
1643 if(R2BYTE(REG_DVI_DTOP_16_L) & BIT(9)) // clk stable
1644 {
1645 if((R2BYTE(REG_DVI_DTOP_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP_01_L) == 0x7FF7) ||
1646 (R2BYTE(REG_DVI_DTOP_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP_02_L) == 0x7FF7) ||
1647 (R2BYTE(REG_DVI_DTOP_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP_03_L) == 0x7FF7))
1648 {
1649 W2BYTEMSK(REG_DVI_DTOP_0E_L, BIT(4), BIT(4)); // clear accumulator
1650 W2BYTEMSK(REG_DVI_DTOP_0E_L, 0, BIT(4));
1651 }
1652 }
1653 }
1654
1655 break;
1656 #endif
1657
1658 #if(MHL_FUNCTION_SUPPORT_PORTB)
1659 case MHL_CBUS_SELECT_PORTB:
1660 if(GET_MHL_PATH_SUPPORT_PORTB())
1661 {
1662 if(R2BYTE(REG_DVI_DTOP1_16_L) & BIT(9)) // clk stable
1663 {
1664 if((R2BYTE(REG_DVI_DTOP1_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP1_01_L) == 0x7FF7) ||
1665 (R2BYTE(REG_DVI_DTOP1_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP1_02_L) == 0x7FF7) ||
1666 (R2BYTE(REG_DVI_DTOP1_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP1_03_L) == 0x7FF7))
1667 {
1668 W2BYTEMSK(REG_DVI_DTOP1_0E_L, BIT(4), BIT(4)); // clear accumulator
1669 W2BYTEMSK(REG_DVI_DTOP1_0E_L, 0, BIT(4));
1670 }
1671 }
1672 }
1673
1674 break;
1675 #endif
1676
1677 #if(MHL_FUNCTION_SUPPORT_PORTC)
1678 case MHL_CBUS_SELECT_PORTC:
1679 if(GET_MHL_PATH_SUPPORT_PORTC())
1680 {
1681 if(R2BYTE(REG_DVI_DTOP3_16_L) & BIT(9)) // clk stable
1682 {
1683 if((R2BYTE(REG_DVI_DTOP3_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP3_01_L) == 0x7FF7) ||
1684 (R2BYTE(REG_DVI_DTOP3_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP3_02_L) == 0x7FF7) ||
1685 (R2BYTE(REG_DVI_DTOP3_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP3_03_L) == 0x7FF7))
1686 {
1687 W2BYTEMSK(REG_DVI_DTOP3_0E_L, BIT(4), BIT(4)); // clear accumulator
1688 W2BYTEMSK(REG_DVI_DTOP3_0E_L, 0, BIT(4));
1689 }
1690 }
1691 }
1692
1693 break;
1694 #endif
1695
1696 #if(MHL_FUNCTION_SUPPORT_PORTD)
1697 case MHL_CBUS_SELECT_PORTD:
1698 if(GET_MHL_PATH_SUPPORT_PORTD())
1699 {
1700 if(R2BYTE(REG_DVI_DTOP2_16_L) & BIT(9)) // clk stable
1701 {
1702 if((R2BYTE(REG_DVI_DTOP2_01_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP2_01_L) == 0x7FF7) ||
1703 (R2BYTE(REG_DVI_DTOP2_02_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP2_02_L) == 0x7FF7) ||
1704 (R2BYTE(REG_DVI_DTOP2_03_L) == 0x8008) || (R2BYTE(REG_DVI_DTOP2_03_L) == 0x7FF7))
1705 {
1706 W2BYTEMSK(REG_DVI_DTOP2_0E_L, BIT(4), BIT(4)); // clear accumulator
1707 W2BYTEMSK(REG_DVI_DTOP2_0E_L, 0, BIT(4));
1708 }
1709 }
1710 }
1711
1712 break;
1713 #endif
1714
1715 default:
1716
1717 break;
1718 };
1719 }
1720
1721 //**************************************************************************
1722 // [Function Name]:
1723 // mhal_mhl_CDRModeMonitor()
1724 // [Description]:
1725 // MHL CDR mode monitor
1726 // [Arguments]:
1727 // isCbusConnected: Cbus is at connected state or not
1728 // [Return]:
1729 //
1730 //**************************************************************************
mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect,MS_BOOL bPathEnable)1731 MS_BOOL mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect, MS_BOOL bPathEnable)
1732 {
1733 MS_BOOL bindex = FALSE;
1734 static MS_U8 ucStableCount = 0;
1735 static MS_BOOL bPLLPower[MHL_CBUS_SELECT_MASK] = {TRUE, TRUE, TRUE, TRUE};
1736
1737 switch(ucCbusSelect)
1738 {
1739 #if(MHL_FUNCTION_SUPPORT_PORTA)
1740 case MHL_CBUS_SELECT_PORTA:
1741 if(GET_MHL_PATH_SUPPORT_PORTA())
1742 {
1743 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
1744 {
1745 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
1746 {
1747 ucStableCount++;
1748 }
1749
1750 if((R2BYTE(REG_DVI_DTOP_31_L) &BIT(6)) == BIT(6)) // DE stable
1751 {
1752 if(!bPLLPower[ucCbusSelect])
1753 {
1754 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12));
1755 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12));
1756
1757 bPLLPower[ucCbusSelect] = TRUE;
1758 }
1759 }
1760 else // DE unstable
1761 {
1762 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
1763 {
1764 ucStableCount = 0;
1765 bPLLPower[ucCbusSelect] = FALSE;
1766 }
1767 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -MHL_CDR_STABLE_OFFSET))
1768 {
1769 bPLLPower[ucCbusSelect] = TRUE;
1770 }
1771 }
1772 }
1773 else
1774 {
1775 if(bPLLPower[ucCbusSelect])
1776 {
1777 bPLLPower[ucCbusSelect] = FALSE;
1778 ucStableCount = 0;
1779 }
1780 }
1781 }
1782
1783 break;
1784 #endif
1785
1786 #if(MHL_FUNCTION_SUPPORT_PORTB)
1787 case MHL_CBUS_SELECT_PORTB:
1788 if(GET_MHL_PATH_SUPPORT_PORTB())
1789 {
1790
1791 }
1792
1793 break;
1794 #endif
1795
1796 #if(MHL_FUNCTION_SUPPORT_PORTC)
1797 case MHL_CBUS_SELECT_PORTC:
1798 if(GET_MHL_PATH_SUPPORT_PORTC())
1799 {
1800 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
1801 {
1802 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
1803 {
1804 ucStableCount++;
1805 }
1806
1807 if((R2BYTE(REG_DVI_DTOP3_31_L) &BIT(6)) == BIT(6)) // DE stable
1808 {
1809 if(!bPLLPower[ucCbusSelect])
1810 {
1811 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12));
1812 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12));
1813
1814 bPLLPower[ucCbusSelect] = TRUE;
1815 }
1816 }
1817 else // DE unstable
1818 {
1819 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
1820 {
1821 ucStableCount = 0;
1822 bPLLPower[ucCbusSelect] = FALSE;
1823 }
1824 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -MHL_CDR_STABLE_OFFSET))
1825 {
1826 bPLLPower[ucCbusSelect] = TRUE;
1827 }
1828 }
1829 }
1830 else
1831 {
1832 if(bPLLPower[ucCbusSelect])
1833 {
1834 bPLLPower[ucCbusSelect] = FALSE;
1835 ucStableCount = 0;
1836 }
1837 }
1838 }
1839
1840 break;
1841 #endif
1842
1843 #if(MHL_FUNCTION_SUPPORT_PORTD)
1844 case MHL_CBUS_SELECT_PORTD:
1845 if(GET_MHL_PATH_SUPPORT_PORTD())
1846 {
1847 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
1848 {
1849 if(ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
1850 {
1851 ucStableCount++;
1852 }
1853
1854 if((R2BYTE(REG_DVI_DTOP2_31_L) &BIT(6)) == BIT(6)) // DE stable
1855 {
1856 if(!bPLLPower[ucCbusSelect])
1857 {
1858 W2BYTEMSK(REG_HDMI2_06_L, BIT(12), BIT(12));
1859 W2BYTEMSK(REG_HDMI2_06_L, 0, BIT(12));
1860
1861 bPLLPower[ucCbusSelect] = TRUE;
1862 }
1863 }
1864 else // DE unstable
1865 {
1866 if(ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
1867 {
1868 ucStableCount = 0;
1869 bPLLPower[ucCbusSelect] = FALSE;
1870 }
1871 else if(ucStableCount == (MHL_CDR_STABLE_THRESHOLD -MHL_CDR_STABLE_OFFSET))
1872 {
1873 bPLLPower[ucCbusSelect] = TRUE;
1874 }
1875 }
1876 }
1877 else
1878 {
1879 if(bPLLPower[ucCbusSelect])
1880 {
1881 bPLLPower[ucCbusSelect] = FALSE;
1882 ucStableCount = 0;
1883 }
1884 }
1885 }
1886
1887 break;
1888 #endif
1889
1890 default:
1891
1892 break;
1893 };
1894
1895 if(ucStableCount >= MHL_CDR_FORCE_THRESHOLD)
1896 {
1897 bMHLSignalStable = TRUE;
1898 }
1899 else if(bMHLSignalStable)
1900 {
1901 bMHLSignalStable = FALSE;
1902 }
1903
1904 return bindex;
1905 }
1906
1907 //**************************************************************************
1908 // [Function Name]:
1909 // mhal_mhl_CbusIsolate()
1910 // [Description]
1911 // MHL cable isolate
1912 // [Arguments]:
1913 //
1914 // [Return]:
1915 //
1916 //**************************************************************************
mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect,MS_BOOL bFlag)1917 void mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect, MS_BOOL bFlag)
1918 {
1919 switch(ucCbusSelect)
1920 {
1921 #if(MHL_FUNCTION_SUPPORT_PORTA)
1922 case MHL_CBUS_SELECT_PORTA:
1923 if(GET_MHL_PATH_SUPPORT_PORTA())
1924 {
1925 if(bFlag)
1926 {
1927 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
1928 }
1929 else
1930 {
1931 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
1932 }
1933 }
1934
1935 break;
1936 #endif
1937
1938 #if(MHL_FUNCTION_SUPPORT_PORTB)
1939 case MHL_CBUS_SELECT_PORTB:
1940 if(GET_MHL_PATH_SUPPORT_PORTB())
1941 {
1942
1943 }
1944
1945 break;
1946 #endif
1947
1948 #if(MHL_FUNCTION_SUPPORT_PORTC)
1949 case MHL_CBUS_SELECT_PORTC:
1950 if(GET_MHL_PATH_SUPPORT_PORTC())
1951 {
1952 if(bFlag)
1953 {
1954 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
1955 }
1956 else
1957 {
1958 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
1959 }
1960 }
1961
1962 break;
1963 #endif
1964
1965 #if(MHL_FUNCTION_SUPPORT_PORTD)
1966 case MHL_CBUS_SELECT_PORTD:
1967 if(GET_MHL_PATH_SUPPORT_PORTD())
1968 {
1969 if(bFlag)
1970 {
1971 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
1972 }
1973 else
1974 {
1975 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
1976 }
1977 }
1978
1979 break;
1980 #endif
1981
1982 default:
1983
1984 break;
1985 };
1986 }
1987
1988 //**************************************************************************
1989 // [Function Name]:
1990 // mhal_mhl_VbusCharge()
1991 // [Description]
1992 // MHL Vbus charge
1993 // [Arguments]:
1994 //
1995 // [Return]:
1996 //
1997 //**************************************************************************
mhal_mhl_VbusCharge(MS_U8 ucCbusSelect,MS_U8 bState)1998 void mhal_mhl_VbusCharge(MS_U8 ucCbusSelect, MS_U8 bState)
1999 {
2000 switch(ucCbusSelect)
2001 {
2002 #if(MHL_FUNCTION_SUPPORT_PORTA)
2003 case MHL_CBUS_SELECT_PORTA:
2004 if(GET_MHL_PATH_SUPPORT_PORTA())
2005 {
2006 if(bState == VBUS_SW_CHARGE)
2007 {
2008 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2009 }
2010 else if(bState == VBUS_SW_UNCHARGE)
2011 {
2012 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2013 }
2014 else
2015 {
2016 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2017 }
2018 }
2019
2020 break;
2021 #endif
2022
2023 #if(MHL_FUNCTION_SUPPORT_PORTB)
2024 case MHL_CBUS_SELECT_PORTB:
2025 if(GET_MHL_PATH_SUPPORT_PORTB())
2026 {
2027
2028 }
2029
2030 break;
2031 #endif
2032
2033 #if(MHL_FUNCTION_SUPPORT_PORTC)
2034 case MHL_CBUS_SELECT_PORTC:
2035 if(GET_MHL_PATH_SUPPORT_PORTC())
2036 {
2037 if(bState == VBUS_SW_CHARGE)
2038 {
2039 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2040 }
2041 else if(bState == VBUS_SW_UNCHARGE)
2042 {
2043 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2044 }
2045 else
2046 {
2047 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2048 }
2049 }
2050
2051 break;
2052 #endif
2053
2054 #if(MHL_FUNCTION_SUPPORT_PORTD)
2055 case MHL_CBUS_SELECT_PORTD:
2056 if(GET_MHL_PATH_SUPPORT_PORTD())
2057 {
2058 if(bState == VBUS_SW_CHARGE)
2059 {
2060 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
2061 }
2062 else if(bState == VBUS_SW_UNCHARGE)
2063 {
2064 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
2065 }
2066 else
2067 {
2068 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
2069 }
2070 }
2071
2072 break;
2073 #endif
2074
2075 default:
2076
2077 break;
2078 };
2079 }
2080
2081 //**************************************************************************
2082 // [Function Name]:
2083 // mhal_mhl_CbusFloating()
2084 // [Description]
2085 // MHL cable floating
2086 // [Arguments]:
2087 //
2088 // [Return]:
2089 //
2090 //**************************************************************************
mhal_mhl_CbusFloating(MS_BOOL bFlag)2091 void mhal_mhl_CbusFloating(MS_BOOL bFlag)
2092 {
2093 if(bFlag)
2094 {
2095 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5));
2096 }
2097 else
2098 {
2099 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5));
2100 }
2101 }
2102
2103 //**************************************************************************
2104 // [Function Name]:
2105 // mhal_mhl_CbusStucktoLow()
2106 // [Description]
2107 //
2108 // [Arguments]:
2109 //
2110 // [Return]:
2111 //
2112 //**************************************************************************
mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)2113 void mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)
2114 {
2115 if(bFlag)
2116 {
2117 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask
2118 }
2119 else
2120 {
2121 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask
2122 }
2123
2124 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag
2125 }
2126
2127 //**************************************************************************
2128 // [Function Name]:
2129 // mhal_mhl_CbusWakeupInterrupt()
2130 // [Description]
2131 //
2132 // [Arguments]:
2133 //
2134 // [Return]:
2135 //
2136 //**************************************************************************
mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)2137 void mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)
2138 {
2139 if(bFlag)
2140 {
2141 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask
2142 }
2143 else
2144 {
2145 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask
2146 }
2147
2148 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag
2149 }
2150
2151 //**************************************************************************
2152 // [Function Name]:
2153 // mhal_mhl_SetVenderID()
2154 // [Description]
2155 //
2156 // [Arguments]:
2157 //
2158 // [Return]:
2159 //
2160 //**************************************************************************
mhal_mhl_SetVenderID(MS_U8 ucVenderID)2161 void mhal_mhl_SetVenderID(MS_U8 ucVenderID)
2162 {
2163 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8));
2164 }
2165
2166 //**************************************************************************
2167 // [Function Name]:
2168 // mhal_mhl_LoadEDID()
2169 // [Description]
2170 //
2171 // [Arguments]:
2172 //
2173 // [Return]:
2174 //
2175 //**************************************************************************
mhal_mhl_LoadEDID(MS_U8 * edid)2176 void mhal_mhl_LoadEDID(MS_U8 *edid)
2177 {
2178 MS_U16 ustemp = 0;
2179
2180 if(edid != NULL)
2181 {
2182 // Load EDID
2183 msg_mhl(printf("** Munich Load MHL EDID...\r\n"));
2184
2185 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable
2186
2187 for(ustemp = 0; ustemp <256; ustemp++)
2188 {
2189 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
2190 W2BYTEMSK(REG_MHL_CBUS_53, edid[ustemp], 0x00FF); // data
2191 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger
2192 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
2193 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5));
2194 }
2195
2196 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable
2197 }
2198 }
2199
2200 //**************************************************************************
2201 // [Function Name]:
2202 // mhal_mhl_ReadEDID()
2203 // [Description]
2204 //
2205 // [Arguments]:
2206 //
2207 // [Return]:
2208 //
2209 //**************************************************************************
mhal_mhl_ReadEDID(MS_U16 usSize,MS_U8 * edid)2210 void mhal_mhl_ReadEDID(MS_U16 usSize, MS_U8 *edid)
2211 {
2212 MS_U16 ustemp = 0;
2213
2214 if(edid != NULL)
2215 {
2216 // Read EDID
2217 msg_mhl(printf("** Munich Read MHL EDID...\r\n"));
2218
2219 for(ustemp = 0; ustemp < usSize; ustemp++)
2220 {
2221 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
2222 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger
2223 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
2224 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4));
2225
2226 edid[ustemp] = (MS_U8)((R2BYTE(REG_MHL_CBUS_53) & 0xFF00) >> 8); // data
2227 }
2228 }
2229 }
2230
2231 //**************************************************************************
2232 // [Function Name]:
2233 // mhal_mhl_LoadDeviceCapability()
2234 // [Description]
2235 //
2236 // [Arguments]:
2237 //
2238 // [Return]:
2239 //
2240 //**************************************************************************
mhal_mhl_LoadDeviceCapability(MS_U8 * devcap)2241 void mhal_mhl_LoadDeviceCapability(MS_U8 *devcap)
2242 {
2243 MS_U8 ucIndex = 0;
2244 MS_U8 uctemp = 0;
2245
2246 if(devcap != NULL)
2247 {
2248 msg_mhl(printf("** Munich Load DevCap...\r\n"));
2249
2250 // Load MHL device capability
2251 for(uctemp = 0; uctemp <8; uctemp++)
2252 {
2253 if(uctemp == 2)
2254 {
2255 ucIndex = 1;
2256 }
2257
2258 W2BYTE(REG_MHL_CBUS_01 +(uctemp *2), (devcap[(uctemp *2) +1 -ucIndex] <<8) | devcap[uctemp *2 -ucIndex]);
2259 }
2260
2261 W2BYTE(REG_MHL_CBUS_03, (devcap[3] <<8) | devcap[4]);
2262 W2BYTE(REG_MHL_CBUS_07, (devcap[11] <<8) | devcap[12]);
2263
2264 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0));
2265 }
2266 }
2267
2268 //**************************************************************************
2269 // [Function Name]:
2270 // mhal_mhl_initial()
2271 // [Description]
2272 // MHL init
2273 // [Arguments]:
2274 // *edid: MHL EDID data
2275 // *devcap: MHL device capability
2276 // [Return]:
2277 //
2278 //**************************************************************************
mhal_mhl_initial(MS_U8 * edid,MS_U8 * devcap,MS_U8 ucVenderID)2279 MS_U8 mhal_mhl_initial(MS_U8 *edid, MS_U8 *devcap, MS_U8 ucVenderID)
2280 {
2281 MS_U16 uctemp = 0;
2282
2283 // Initial setting
2284 for(uctemp = 0; uctemp <(sizeof(tMHL_INITIAL_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
2285 {
2286 W2BYTEMSK(tMHL_INITIAL_TABLE[uctemp].addr, tMHL_INITIAL_TABLE[uctemp].databuf, tMHL_INITIAL_TABLE[uctemp].mask);
2287 }
2288
2289 W2BYTEMSK(REG_PM_SLEEP_72_L, BMASK(7:6), BMASK(8:6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en_sel , [6]: reg_mhl_cable_detect_sel
2290
2291 _mhal_mhl_CbusAndClockSelect();
2292
2293 #if(MHL_INTERRUPT_USE_PM_IRQ)
2294 // Open PM irq mask
2295 W2BYTEMSK(0x2B28, 0, BIT(11));
2296 #endif
2297
2298 // Load EDID
2299 mhal_mhl_LoadEDID(edid);
2300
2301 // Load vendor ID
2302 mhal_mhl_SetVenderID(ucVenderID);
2303
2304 // Load DevCap
2305 mhal_mhl_LoadDeviceCapability(devcap);
2306
2307 // Clear Cbus received interrupt status
2308 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask
2309
2310 mhal_mhl_CbusStucktoLow(FALSE);
2311 mhal_mhl_CbusWakeupInterrupt(FALSE);
2312
2313 _mhal_mhl_MHLForceToAttach();
2314
2315 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
2316 {
2317 _mhal_mhl_RtermHWControl(uctemp, FALSE);
2318 _mhal_mhl_PhyInitialSetting(uctemp);
2319 }
2320
2321 #if(DMHL_TEST_SIGNAL_SUPPORT)
2322 W2BYTEMSK(0x001102, BIT(7), BIT(7));
2323 W2BYTEMSK(0x001128, BIT(0), BIT(0));
2324
2325 #endif
2326
2327 mhal_mhl_CbusFloating(TRUE);
2328
2329 return MHL_CHIP_FUNCTION_CAPABILITY;
2330 }
2331
2332 //**************************************************************************
2333 // [Function Name]:
2334 // mhal_mhl_InvertCableDetect()
2335 // [Description]
2336 //
2337 // [Arguments]:
2338 //
2339 // [Return]:
2340 //
2341 //**************************************************************************
mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect,MS_BOOL bCableDetectInvert)2342 void mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect, MS_BOOL bCableDetectInvert)
2343 {
2344 switch(ucCbusSelect)
2345 {
2346 #if(MHL_FUNCTION_SUPPORT_PORTA)
2347 case MHL_CBUS_SELECT_PORTA:
2348 if(GET_MHL_PATH_SUPPORT_PORTA())
2349 {
2350 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
2351 }
2352
2353 break;
2354 #endif
2355
2356 #if(MHL_FUNCTION_SUPPORT_PORTB)
2357 case MHL_CBUS_SELECT_PORTB:
2358 if(GET_MHL_PATH_SUPPORT_PORTB())
2359 {
2360
2361 }
2362
2363 break;
2364 #endif
2365
2366 #if(MHL_FUNCTION_SUPPORT_PORTC)
2367 case MHL_CBUS_SELECT_PORTC:
2368 if(GET_MHL_PATH_SUPPORT_PORTC())
2369 {
2370 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
2371 }
2372
2373 break;
2374 #endif
2375
2376 #if(MHL_FUNCTION_SUPPORT_PORTD)
2377 case MHL_CBUS_SELECT_PORTD:
2378 if(GET_MHL_PATH_SUPPORT_PORTD())
2379 {
2380 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
2381 }
2382
2383 break;
2384 #endif
2385
2386 default:
2387
2388 break;
2389 };
2390 }
2391
2392 //**************************************************************************
2393 // [Function Name]:
2394 // mhal_mhl_VbusConfigSetting()
2395 // [Description]
2396 //
2397 // [Arguments]:
2398 //
2399 // [Return]:
2400 //
2401 //**************************************************************************
mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect,MS_U8 ucState)2402 void mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect, MS_U8 ucState)
2403 {
2404 MS_U8 ucOutputState = ucState &(MHL_VBUS_LOW_ENABLE_MODE | MHL_VBUS_HIGH_ENABLE_MODE);
2405
2406 ucState = ucState &(MHL_VBUS_OUTPUT_MODE | MHL_VBUS_INVERSE_MODE);
2407
2408 switch(ucCbusSelect)
2409 {
2410 #if(MHL_FUNCTION_SUPPORT_PORTA)
2411 case MHL_CBUS_SELECT_PORTA:
2412 if(GET_MHL_PATH_SUPPORT_PORTA())
2413 {
2414 if(ucState == MHL_VBUS_OUTPUT_MODE)
2415 {
2416 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2417 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
2418 }
2419 else if(ucState > 0)
2420 {
2421 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2422 }
2423
2424 if(ucOutputState > 0)
2425 {
2426 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
2427 {
2428 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
2429 }
2430 else
2431 {
2432 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
2433 }
2434 }
2435 }
2436
2437 break;
2438 #endif
2439
2440 #if(MHL_FUNCTION_SUPPORT_PORTB)
2441 case MHL_CBUS_SELECT_PORTB:
2442 if(GET_MHL_PATH_SUPPORT_PORTB())
2443 {
2444
2445 }
2446
2447 break;
2448 #endif
2449
2450 #if(MHL_FUNCTION_SUPPORT_PORTC)
2451 case MHL_CBUS_SELECT_PORTC:
2452 if(GET_MHL_PATH_SUPPORT_PORTC())
2453 {
2454 if(ucState == MHL_VBUS_OUTPUT_MODE)
2455 {
2456 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2457 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
2458 }
2459 else if(ucState > 0)
2460 {
2461 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2462 }
2463
2464 if(ucOutputState > 0)
2465 {
2466 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
2467 {
2468 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
2469 }
2470 else
2471 {
2472 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
2473 }
2474 }
2475 }
2476
2477 break;
2478 #endif
2479
2480 #if(MHL_FUNCTION_SUPPORT_PORTD)
2481 case MHL_CBUS_SELECT_PORTD:
2482 if(GET_MHL_PATH_SUPPORT_PORTD())
2483 {
2484 if(ucState == MHL_VBUS_OUTPUT_MODE)
2485 {
2486 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2487 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
2488 }
2489 else if(ucState > 0)
2490 {
2491 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
2492 }
2493
2494 if(ucOutputState > 0)
2495 {
2496 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
2497 {
2498 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
2499 }
2500 else
2501 {
2502 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
2503 }
2504 }
2505 }
2506
2507 break;
2508 #endif
2509
2510 default:
2511
2512 break;
2513 };
2514 }
2515
2516 //**************************************************************************
2517 // [Function Name]:
2518 // mhal_mhl_CableDetectPadSetting()
2519 // [Description]
2520 //
2521 // [Arguments]:
2522 //
2523 // [Return]:
2524 //
2525 //**************************************************************************
mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)2526 void mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)
2527 {
2528 if((ucSelect &MHL_CABLE_DETECT_SELECT_PORTC) && (ucSelect &MHL_CABLE_DETECT_SELECT_PORTD))
2529 {
2530 msg_mhl(printf("** MHL cable detect only select one port T^T\r\n"));
2531 }
2532 else
2533 {
2534 // Do nothing
2535 }
2536 }
2537
2538 //**************************************************************************
2539 // [Function Name]:
2540 // mhal_mhl_CbusPadConfigSwitch()
2541 // [Description]
2542 //
2543 // [Arguments]:
2544 //
2545 // [Return]:
2546 //
2547 //**************************************************************************
mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)2548 void mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
2549 {
2550 switch(ucCbusSelect)
2551 {
2552 #if(MHL_FUNCTION_SUPPORT_PORTA)
2553 case MHL_CBUS_SELECT_PORTA:
2554 if(GET_MHL_PATH_SUPPORT_PORTA())
2555 {
2556 if(bFlag)
2557 {
2558 _mhal_mhl_MHLForceToAttach();
2559 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
2560 }
2561 else
2562 {
2563 _mhal_mhl_CbusForceToStandby();
2564 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
2565 }
2566 }
2567
2568 break;
2569 #endif
2570
2571 #if(MHL_FUNCTION_SUPPORT_PORTB)
2572 case MHL_CBUS_SELECT_PORTB:
2573 if(GET_MHL_PATH_SUPPORT_PORTB())
2574 {
2575
2576 }
2577
2578 break;
2579 #endif
2580
2581 #if(MHL_FUNCTION_SUPPORT_PORTC)
2582 case MHL_CBUS_SELECT_PORTC:
2583 if(GET_MHL_PATH_SUPPORT_PORTC())
2584 {
2585 if(bFlag)
2586 {
2587 _mhal_mhl_MHLForceToAttach();
2588 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
2589 }
2590 else
2591 {
2592 _mhal_mhl_CbusForceToStandby();
2593 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
2594 }
2595 }
2596
2597 break;
2598 #endif
2599
2600 #if(MHL_FUNCTION_SUPPORT_PORTD)
2601 case MHL_CBUS_SELECT_PORTD:
2602 if(GET_MHL_PATH_SUPPORT_PORTD())
2603 {
2604 if(bFlag)
2605 {
2606 _mhal_mhl_MHLForceToAttach();
2607 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
2608 }
2609 else
2610 {
2611 _mhal_mhl_CbusForceToStandby();
2612 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
2613 }
2614 }
2615
2616 break;
2617 #endif
2618
2619 default:
2620
2621 break;
2622 };
2623 }
2624
2625 //**************************************************************************
2626 // [Function Name]:
2627 // _mhal_mhl_CbusStatus()
2628 // [Description]:
2629 // MHL Cbus status
2630 // [Arguments]:
2631 //
2632 // [Return]:
2633 // Cbus status value
2634 //**************************************************************************
mhal_mhl_CbusStatus(void)2635 MS_U16 mhal_mhl_CbusStatus(void)
2636 {
2637 return (R2BYTE(REG_PM_MHL_CBUS_17));
2638 }
2639
2640 //**************************************************************************
2641 // [Function Name]:
2642 // mhal_mhl_CbusIsMscMsgReceived()
2643 // [Description]
2644 // MHL Cbus check whether msc message is received or not
2645 // [Arguments]:
2646 //
2647 // [Return]:
2648 // TRUE: recieved
2649 // FALSE: not yet
2650 //**************************************************************************
mhal_mhl_CbusIsMscMsgReceived(void)2651 MS_BOOL mhal_mhl_CbusIsMscMsgReceived(void)
2652 {
2653 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE);
2654
2655 if(bindex)
2656 {
2657 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0));
2658 }
2659
2660 return bindex;
2661 }
2662
2663 //**************************************************************************
2664 // [Function Name]:
2665 // mhal_mhl_CbusStucktoLowFlag()
2666 // [Description]
2667 //
2668 // [Arguments]:
2669 //
2670 // [Return]:
2671 //
2672 //**************************************************************************
mhal_mhl_CbusStucktoLowFlag(void)2673 MS_BOOL mhal_mhl_CbusStucktoLowFlag(void)
2674 {
2675 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE);
2676
2677 if(bindex)
2678 {
2679 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0));
2680 }
2681
2682 return bindex;
2683 }
2684
2685 //**************************************************************************
2686 // [Function Name]:
2687 // mhal_mhl_CbusWakeupIntFlag()
2688 // [Description]
2689 //
2690 // [Arguments]:
2691 //
2692 // [Return]:
2693 //
2694 //**************************************************************************
mhal_mhl_CbusWakeupIntFlag(void)2695 MS_BOOL mhal_mhl_CbusWakeupIntFlag(void)
2696 {
2697 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE);
2698
2699 if(bindex)
2700 {
2701 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4));
2702 }
2703
2704 return bindex;
2705 }
2706
2707 //**************************************************************************
2708 // [Function Name]:
2709 // mhal_mhl_CBusWrite()
2710 // [Description]
2711 // MHL Cbus write trigger
2712 // [Arguments]:
2713 // *pdatabuf: Cbus tx data
2714 // [Return]:
2715 //
2716 //**************************************************************************
mhal_mhl_CBusWrite(mhalCbusFifo_S * pdatabuf)2717 MS_BOOL mhal_mhl_CBusWrite(mhalCbusFifo_S *pdatabuf)
2718 {
2719 MS_U8 uctemp = 0;
2720
2721 if(_mhal_mhl_IsCbusBusy())
2722 {
2723 return FALSE;
2724 }
2725
2726 for(uctemp = 0; uctemp < pdatabuf->lens; uctemp++)
2727 {
2728 W2BYTE(REG_MHL_CBUS_26 +uctemp *2, pdatabuf->databuf[uctemp]);
2729 }
2730
2731 // clear the unsed parts
2732 W2BYTE(REG_MHL_CBUS_26 +((pdatabuf->lens) *2), 0);
2733
2734 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send
2735
2736 return TRUE;
2737 }
2738
2739 //**************************************************************************
2740 // [Function Name]:
2741 // _mhal_mhl_Cbus_SetPathEn()
2742 // [Description]:
2743 // MHL Cbus set path enable
2744 // [Arguments]:
2745 // TRUE: Enable
2746 // FALSE: Disable
2747 // [Return]:
2748 //
2749 //**************************************************************************
mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)2750 void mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)
2751 {
2752 if(bflag) // set state to PATH_EN
2753 {
2754 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12));
2755 }
2756 else // clear state to not PATH_EN
2757 {
2758 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13));
2759 }
2760 }
2761
2762 //**************************************************************************
2763 // [Function Name]:
2764 // mhal_mhl_CbusIntCB()
2765 // [Description]
2766 // MHL Cbus Interrupt Call Back function
2767 // [Arguments]:
2768 // *rcstate: recevied state, 0:normal / 1:timeout
2769 // *rccmd: recevied command
2770 // *rcdata: recevied data
2771 // *rclen: received length
2772 // *bIsCmdInData: Is command in data field
2773 // [Return]:
2774 //
2775 //**************************************************************************
mhal_mhl_CbusIntCB(MS_U8 * rcstate,MS_U8 * rccmd,MS_U8 * rcdata,MS_U8 * rclen,MS_U8 * bIsCmdInData)2776 MS_BOOL mhal_mhl_CbusIntCB(MS_U8 *rcstate, MS_U8 *rccmd, MS_U8 *rcdata, MS_U8 *rclen, MS_U8 *bIsCmdInData)
2777 {
2778 MS_BOOL bindex = FALSE;
2779 MS_U8 uctemp = 0;
2780 MS_U16 reg_val;
2781
2782 *rcstate = R2BYTE(REG_MHL_CBUS_3B) & 0x000F; // received state, 0: normal, 1: timeout
2783
2784 //W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); // clear INT
2785
2786 reg_val = R2BYTE(REG_MHL_CBUS_3C);
2787
2788 if(!(reg_val &BIT(8))) // Received data
2789 {
2790 bindex = TRUE;
2791 }
2792
2793 *rccmd = reg_val & 0x00FF;
2794 *bIsCmdInData = FALSE;
2795
2796 for(uctemp = 0; uctemp <=(MHL_CBUS_DATA_SIZE +1); uctemp++) // offset+16bytes+EOF
2797 {
2798 reg_val = R2BYTE(REG_MHL_CBUS_3D +(uctemp *2));
2799
2800 if(reg_val & BIT(15))
2801 {
2802 rcdata[uctemp] = reg_val & 0x00FF;
2803
2804 if(((uctemp <= 2) ||(uctemp == (MHL_CBUS_DATA_SIZE +1))) && !(*bIsCmdInData))
2805 {
2806 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE;
2807 }
2808 }
2809 else
2810 {
2811 *rclen = uctemp;
2812 break;
2813 }
2814 }
2815
2816 // CTS 6.3.11.19
2817 if(uctemp >(MHL_CBUS_DATA_SIZE +1))
2818 {
2819 *rclen = MHL_CBUS_DATA_SIZE +2;
2820 }
2821
2822 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
2823
2824 return bindex;
2825 }
2826
2827 //**************************************************************************
2828 // [Function Name]:
2829 // mdrv_mhl_CBusCheckBCHError()
2830 // [Description]:
2831 // MHL Cbus check BCH error
2832 // [Arguments]:
2833 //
2834 // [Return]:
2835 //
2836 //**************************************************************************
mhal_mhl_CBusCheckBCHError(void)2837 MS_BOOL mhal_mhl_CBusCheckBCHError(void)
2838 {
2839 MS_BOOL bindex = FALSE;
2840
2841 if(R2BYTE(REG_HDMI_04_L) &BIT(1))
2842 {
2843 //bindex = TRUE;
2844
2845 W2BYTEMSK(REG_HDMI_04_L, BIT(1), BIT(1));
2846 }
2847
2848 return bindex;
2849 }
2850
2851 //**************************************************************************
2852 // [Function Name]:
2853 // mhal_mhl_CablePlugProc()
2854 // [Description]
2855 //
2856 // [Arguments]:
2857 //
2858 // [Return]:
2859 //
2860 //**************************************************************************
mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect)2861 void mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect)
2862 {
2863 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect);
2864
2865 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
2866
2867 #if(DMHL_LG_PRADA_PATCH)
2868 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
2869 #endif
2870
2871 if(mhal_mhl_CheckInputPort(ucCbusSelect))
2872 {
2873 //_mhal_mhl_ChangeScalerMainMux(TRUE);
2874 //_mhal_mhl_AudioPathSelect(TRUE);
2875 }
2876 }
2877
2878 //**************************************************************************
2879 // [Function Name]:
2880 // mhal_mhl_CableRemoveProc()
2881 // [Description]
2882 //
2883 // [Arguments]:
2884 //
2885 // [Return]:
2886 //
2887 //**************************************************************************
mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect)2888 void mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect)
2889 {
2890 _mhal_mhl_HdmiBypassModeSetting(ucCbusSelect);
2891 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_HDMI_RTERM);
2892
2893 if(mhal_mhl_CheckInputPort(ucCbusSelect))
2894 {
2895 //_mhal_mhl_ChangeScalerMainMux(FALSE);
2896 //_mhal_mhl_AudioPathSelect(FALSE);
2897 }
2898 }
2899
2900 //**************************************************************************
2901 // [Function Name]:
2902 // mhal_mhl_CbusConnectProc()
2903 // [Description]
2904 //
2905 // [Arguments]:
2906 //
2907 // [Return]:
2908 //
2909 //**************************************************************************
mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)2910 void mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)
2911 {
2912 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
2913
2914 #if(DMHL_LG_PRADA_PATCH)
2915 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, FALSE);
2916 #endif
2917
2918 mhal_mhl_CbusStucktoLow(TRUE);
2919 }
2920
2921 //**************************************************************************
2922 // [Function Name]:
2923 // mhal_mhl_CbusStucktoLowProc()
2924 // [Description]
2925 //
2926 // [Arguments]:
2927 //
2928 // [Return]:
2929 //
2930 //**************************************************************************
mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)2931 void mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)
2932 {
2933 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
2934
2935 #if(DMHL_LG_PRADA_PATCH)
2936 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
2937 #endif
2938
2939 mhal_mhl_CDRModeMonitor(ucCbusSelect, FALSE);
2940 }
2941
2942 //**************************************************************************
2943 // [Function Name]:
2944 // mhal_mhl_SourceChangeProc()
2945 // [Description]
2946 //
2947 // [Arguments]:
2948 //
2949 // [Return]:
2950 //
2951 //**************************************************************************
mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect)2952 void mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect)
2953 {
2954 if(mhal_mhl_CheckInputPort(ucCbusSelect))
2955 {
2956 //_mhal_mhl_ChangeScalerMainMux(TRUE);
2957 //_mhal_mhl_AudioPathSelect(TRUE);
2958 }
2959 else
2960 {
2961 //_mhal_mhl_ChangeScalerMainMux(FALSE);
2962 //_mhal_mhl_AudioPathSelect(FALSE);
2963 }
2964 }
2965
2966 //**************************************************************************
2967 // [Function Name]:
2968 // mhal_mhl_ClockModeSwitchProc()
2969 // [Description]
2970 //
2971 // [Arguments]:
2972 //
2973 // [Return]:
2974 //
2975 //**************************************************************************
mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect,MS_BOOL bPPmode)2976 void mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect, MS_BOOL bPPmode)
2977 {
2978 if(bPPmode)
2979 {
2980 _mhal_mhl_MhlPackedPixelModeSetting(ucCbusSelect);
2981 }
2982 else
2983 {
2984 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect);
2985 }
2986 }
2987
2988 //**************************************************************************
2989 // [Function Name]:
2990 // mhal_mhl_CbusWakeupIntSetting()
2991 // [Description]
2992 //
2993 // [Arguments]:
2994 //
2995 // [Return]:
2996 //
2997 //**************************************************************************
mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect,MS_BOOL bFlag)2998 void mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect, MS_BOOL bFlag)
2999 {
3000 if(bFlag)
3001 {
3002 _mhal_mhl_CbusForceToStandby();
3003 mhal_mhl_CbusWakeupInterrupt(TRUE);
3004 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_CHARGE);
3005 }
3006 else
3007 {
3008 _mhal_mhl_MHLForceToAttach();
3009 mhal_mhl_CbusWakeupInterrupt(FALSE);
3010 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3011 }
3012 }
3013
3014 //**************************************************************************
3015 // [Function Name]:
3016 // mhal_mhl_RtermControlHWMode()
3017 // [Description]
3018 //
3019 // [Arguments]:
3020 //
3021 // [Return]:
3022 //
3023 //**************************************************************************
mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect,MS_BOOL bFlag)3024 void mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3025 {
3026 MS_U16 ustemp = mhal_mhl_CbusStatus();
3027
3028 if(!bFlag) // HW to SW control rterm
3029 {
3030 if((ustemp & BMASK(1:0)) == 0x03)
3031 {
3032 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
3033 }
3034 else
3035 {
3036 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
3037 }
3038 }
3039
3040 _mhal_mhl_RtermHWControl(ucCbusSelect, bFlag);
3041 }
3042
3043 //**************************************************************************
3044 // [Function Name]:
3045 // mhal_mhl_AdjustSettingIControl()
3046 // [Description]
3047 //
3048 // [Arguments]:
3049 //
3050 // [Return]:
3051 //
3052 //**************************************************************************
mhal_mhl_AdjustSettingIControl(MS_U8 ucIControl)3053 void mhal_mhl_AdjustSettingIControl(MS_U8 ucIControl)
3054 {
3055 ucIControlValue = ucIControl;
3056 }
3057
3058 //**************************************************************************
3059 // [Function Name]:
3060 // mhal_mhl_AdjustImpedanceSetting()
3061 // [Description]
3062 //
3063 // [Arguments]:
3064 //
3065 // [Return]:
3066 //
3067 //**************************************************************************
mhal_mhl_AdjustImpedanceSetting(MS_U8 ucImpedance)3068 void mhal_mhl_AdjustImpedanceSetting(MS_U8 ucImpedance)
3069 {
3070 ucImpedanceValue = ucImpedance;
3071 }
3072
3073 //**************************************************************************
3074 // [Function Name]:
3075 // mhal_mhl_GetSignalStableFlag()
3076 // [Description]
3077 //
3078 // [Arguments]:
3079 //
3080 // [Return]:
3081 //
3082 //**************************************************************************
mhal_mhl_GetSignalStableFlag(void)3083 MS_BOOL mhal_mhl_GetSignalStableFlag(void)
3084 {
3085 return bMHLSignalStable;
3086 }
3087
3088 //**************************************************************************
3089 // [Function Name]:
3090 // mhal_mhl_PowerControl()
3091 // [Description]
3092 // MHL power control
3093 // [Arguments]:
3094 //
3095 // [Return]:
3096 //
3097 //**************************************************************************
mhal_mhl_LoadPowerOnTbl(void)3098 void mhal_mhl_LoadPowerOnTbl(void)
3099 {
3100 MS_U8 uctemp = 0;
3101
3102 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_ON_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3103 {
3104 W2BYTEMSK(tMHL_POWER_ON_TABLE[uctemp].addr, tMHL_POWER_ON_TABLE[uctemp].databuf, tMHL_POWER_ON_TABLE[uctemp].mask);
3105 }
3106
3107 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3108 {
3109 _mhal_mhl_RxRtermControl(uctemp, RX_HDMI_RTERM);
3110 }
3111 }
3112
mhal_mhl_LoadPowerStandbyTbl(void)3113 void mhal_mhl_LoadPowerStandbyTbl(void)
3114 {
3115 MS_U8 uctemp = 0;
3116
3117 //_mhal_mhl_CbusForceToStandby();
3118
3119 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_SAVING_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3120 {
3121 W2BYTEMSK(tMHL_POWER_SAVING_TABLE[uctemp].addr, tMHL_POWER_SAVING_TABLE[uctemp].databuf, tMHL_POWER_SAVING_TABLE[uctemp].mask);
3122 }
3123
3124 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3125 {
3126 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
3127 mhal_mhl_VbusCharge(uctemp, VBUS_SW_CHARGE);
3128 }
3129 }
3130
mhal_mhl_LoadPowerDownTbl(void)3131 void mhal_mhl_LoadPowerDownTbl(void)
3132 {
3133 MS_U8 uctemp = 0;
3134
3135 //_mhal_mhl_CbusForceToStandby();
3136
3137 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_DOWN_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3138 {
3139 W2BYTEMSK(tMHL_POWER_DOWN_TABLE[uctemp].addr, tMHL_POWER_DOWN_TABLE[uctemp].databuf, tMHL_POWER_DOWN_TABLE[uctemp].mask);
3140 }
3141
3142 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3143 {
3144 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
3145 }
3146 }
3147
3148 //**************************************************************************
3149 // [Function Name]:
3150 // mhal_mhl_SetHPD()
3151 // [Description]
3152 // config HPD in combo(MHL/HDMI) port A
3153 // [Arguments]:
3154 //
3155 // [Return]:
3156 //
3157 //**************************************************************************
mhal_mhl_SetHPD(MS_BOOL bflag)3158 void mhal_mhl_SetHPD(MS_BOOL bflag)
3159 {
3160 W2BYTEMSK(REG_PM_SLEEP_73_L, BIT(0), BIT(0)); // [0]: reg_hplugc_mhl_en
3161
3162 if(bflag) // HPD is high
3163 {
3164 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen
3165 //msg_mhl(printf("**MHL_HPD is High"));
3166 }
3167 else // hpd is low
3168 {
3169 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen
3170 //msg_mhl(printf("**MHL_HPD is Low"));
3171 }
3172 }
3173
3174 //**************************************************************************
3175 // [Function Name]:
3176 // mhal_mhl_GetDDCErrorCode()
3177 // [Description]
3178 // Get DDC error code
3179 // [Arguments]:
3180 //
3181 // [Return]:
3182 //
3183 //**************************************************************************
mhal_mhl_GetDDCErrorCode(void)3184 MS_U8 mhal_mhl_GetDDCErrorCode(void)
3185 {
3186 return (R2BYTE(REG_MHL_CBUS_21)>>8);
3187 }
3188
3189 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
3190 //**************************************************************************
3191 // [Function Name]:
3192 // mhal_mhl_CheckSRAMReceiveBuffer()
3193 // [Description]
3194 //
3195 // [Arguments]:
3196 //
3197 // [Return]:
3198 //
3199 //**************************************************************************
mhal_mhl_CheckSRAMReceiveBuffer(void)3200 MS_BOOL mhal_mhl_CheckSRAMReceiveBuffer(void)
3201 {
3202 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE);
3203 }
3204
3205 //**************************************************************************
3206 // [Function Name]:
3207 // mhal_mhl_GetSRAMReceiveData()
3208 // [Description]
3209 //
3210 // [Arguments]:
3211 //
3212 // [Return]:
3213 //
3214 //**************************************************************************
mhal_mhl_GetSRAMReceiveData(void)3215 MS_U16 mhal_mhl_GetSRAMReceiveData(void)
3216 {
3217 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15));
3218
3219 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14));
3220
3221 return R2BYTE(REG_MHL_CBUS_0F);
3222 }
3223
3224 #endif
3225
3226 #if(DMHL_TEST_SIGNAL_SUPPORT)
3227 //**************************************************************************
3228 // [Function Name]:
3229 // mhal_mhl_AdjustCommonModeResistor()
3230 // [Description]:
3231 //
3232 // [Arguments]:
3233 //
3234 // [Return]:
3235 //
3236 //**************************************************************************
mhal_mhl_TestSignal(MS_BOOL bflag)3237 void mhal_mhl_TestSignal(MS_BOOL bflag)
3238 {
3239 if(bflag)
3240 {
3241 W2BYTEMSK(0x001106, BIT(10), BIT(10));
3242 }
3243 else
3244 {
3245 W2BYTEMSK(0x001106, 0, BIT(10));
3246 }
3247 }
3248
3249 #endif
3250
3251 #endif // _MHAL_MHL_C_
3252
3253