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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 ///////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regHDMITx.h 98 /// @author MStar Semiconductor,Inc. 99 /// @brief HDMITx Register Definition 100 ///////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_HDMITX_H_ 103 #define _REG_HDMITX_H_ 104 105 //#include "MsCommon.h" 106 107 //------------------------------------------------------------------------------------------------- 108 // Hardware Capability 109 //------------------------------------------------------------------------------------------------- 110 111 112 //------------------------------------------------------------------------------------------------- 113 // Macro and Define 114 //------------------------------------------------------------------------------------------------- 115 116 #define HDMITX_MISC_REG_BASE (0x172A00U) 117 #define HDMITX_HDCP_REG_BASE (0x172B00U) 118 #define HDMITX_REG_BASE (0x172C00U) 119 #define HDMITX_VIDEO_REG_BASE (0x172D00U) 120 #define HDMITX_AUDIO_REG_BASE (0x172E00U) 121 #define HDMITX_PHY_REG_BASE (0x173000U) 122 123 #define HDMITX_SECUTZPC_BASE (0x172700U) 124 #define HDMITX_HDCP2TX_BASE (0x172F00U) 125 126 #define HDMITX_2_REG_BASE (0x173800U) 127 128 #define HDMIRX_COMBOPHY0_REG_BASE (0x172800U) 129 #define HDMIRX_COMBOPHY1_REG_BASE (0x172900U) 130 131 #define PMBK_PMSLEEP_REG_BASE (0x000E00U) 132 #define CLKGEN1_REG_BASE (0x103300U) 133 #define CHIPTOP_REG_BASE (0x101E00U) 134 #define HDCP_REG_BASE (0x172500U) 135 136 //***** Bank 1728 - COMBO PHY 0 *****// 137 #define REG_COMBOPHY1_CONFIG_3C 0x3CU 138 139 //***** Bank 1729 - COMBO PHY 1 *****// 140 #define REG_COMBOPHY0_CONFIG_4C 0x4CU 141 #define REG_COMBOPHY0_CONFIG_4B 0x4BU 142 #define REG_COMBOPHY0_CONFIG_4A 0x4AU 143 #define REG_COMBOPHY0_CONFIG_49 0x49U 144 #define REG_COMBOPHY0_CONFIG_09 0x09U 145 #define REG_COMBOPHY0_CONFIG_22 0x22U 146 147 //***** Bank 1026 - PADTOP *****// 148 #define REG_SYNC_GPIO0 0x1EU 149 150 //***** Bank 1033(0x28) - CHIPTOP *****// 151 #define REG_CKG_HDMITx_CLK_28 0x28U 152 #define REG_I2S_GPIO4 0x1BU 153 154 //***** Bank 172C - HDMITX *****// 155 #define REG_HDMI_CONFIG1_00 0x00U 156 #define REG_ACT_HDMI_PKTS_CMD_01 0x01U 157 #define REG_PKT_NUL_CFG_02 0x02U 158 #define REG_PKT_GC_CFG_03 0x03U 159 #define REG_PKT_GC12_04 0x04U 160 #define REG_PKT_ACR_1_05 0x05U 161 #define REG_PKT_ACR_2_06 0x06U 162 #define REG_PKT_ACR_3_07 0x07U 163 #define REG_PKT_ACR_CFG_08 0x08U 164 #define REG_PKT_AVI_1_09 0x09U 165 #define REG_PKT_AVI_2_0A 0x0AU 166 #define REG_PKT_AVI_3_0B 0x0BU 167 #define REG_PKT_AVI_4_0C 0x0CU 168 #define REG_PKT_AVI_5_0D 0x0DU 169 #define REG_PKT_AVI_6_0E 0x0EU 170 #define REG_PKT_AVI_7_0F 0x0FU 171 #define REG_PKT_AVI_CFG_10 0x10U 172 #define REG_PKT_AUD_1_11 0x11U 173 #define REG_PKT_AUD_2_12 0x12U 174 #define REG_PKT_AUD_3_13 0x13U 175 #define REG_PKT_AUD_CFG_14 0x14U 176 #define REG_PKT_SPD_1_15 0x15U 177 #define REG_PKT_SPD_2_16 0x16U 178 #define REG_PKT_SPD_3_17 0x17U 179 #define REG_PKT_SPD_4_18 0x18U 180 #define REG_PKT_SPD_5_19 0x19U 181 #define REG_PKT_SPD_6_1A 0x1AU 182 #define REG_PKT_SPD_7_1B 0x1BU 183 #define REG_PKT_SPD_8_1C 0x1CU 184 #define REG_PKT_SPD_9_1D 0x1DU 185 #define REG_PKT_SPD_10_1E 0x1EU 186 #define REG_PKT_SPD_11_1F 0x1FU 187 #define REG_PKT_SPD_12_20 0x20U 188 #define REG_PKT_SPD_13_21 0x21U 189 #define REG_PKT_SPD_CFG_22 0x22U 190 #define REG_PKT_MPG_1_23 0x23U 191 #define REG_PKT_MPG_2_24 0x24U 192 #define REG_PKT_MPG_3_25 0x25U 193 #define REG_PKT_MPG_CFG_26 0x26U 194 #define REG_PKT_VS_1_27 0x27U 195 #define REG_PKT_VS_2_28 0x28U 196 #define REG_PKT_VS_3_29 0x29U 197 #define REG_PKT_VS_4_2A 0x2AU 198 #define REG_PKT_VS_5_2B 0x2BU 199 #define REG_PKT_VS_6_2C 0x2CU 200 #define REG_PKT_VS_7_2D 0x2DU 201 #define REG_PKT_VS_8_2E 0x2EU 202 #define REG_PKT_VS_9_2F 0x2FU 203 #define REG_PKT_VS_10_30 0x30U 204 #define REG_PKT_VS_11_31 0x31U 205 #define REG_PKT_VS_12_32 0x32U 206 #define REG_PKT_VS_13_33 0x33U 207 #define REG_PKT_VS_14_34 0x34U 208 #define REG_PKT_VS_CFG_35 0x35U 209 #define REG_USER_TYPE_36 0x36U 210 #define REG_USER_HB_37 0x37U 211 #define REG_PKT_ACP_0_38 0x38U 212 #define REG_PKT_ACP_1_39 0x39U 213 #define REG_PKT_ACP_2_3A 0x3AU 214 #define REG_PKT_ACP_3_3B 0x3BU 215 #define REG_PKT_ACP_4_3C 0x3CU 216 #define REG_PKT_ACP_5_3D 0x3DU 217 #define REG_PKT_ACP_6_3E 0x3EU 218 #define REG_PKT_ACP_7_3F 0x3FU 219 #define REG_PKT_ACP_CFG_40 0x40U 220 #define REG_PKT_ISRC_0_41 0x41U 221 #define REG_PKT_ISRC_1_42 0x42U 222 #define REG_PKT_ISRC_2_43 0x43U 223 #define REG_PKT_ISRC_3_44 0x44U 224 #define REG_PKT_ISRC_4_45 0x45U 225 #define REG_PKT_ISRC_5_46 0x46U 226 #define REG_PKT_ISRC_6_47 0x47U 227 #define REG_PKT_ISRC_7_48 0x48U 228 #define REG_PKT_ISRC_8_49 0x49U 229 #define REG_PKT_ISRC_9_4A 0x4AU 230 #define REG_PKT_ISRC_10_4B 0x4BU 231 #define REG_PKT_ISRC_11_4C 0x4CU 232 #define REG_PKT_ISRC_12_4D 0x4DU 233 #define REG_PKT_ISRC_13_4E 0x4EU 234 #define REG_PKT_ISRC_14_4F 0x4FU 235 #define REG_PKT_ISRC_15_50 0x50U 236 #define REG_PKT_ISRC_CFG_51 0x51U 237 #define REG_TMDS_DE_CNT_52 0x52U 238 #define REG_HPLL_LOCK_CNT_53 0x53U 239 #define REG_PKT_GM_CFG_54 0x54U 240 #define REG_PKT_GM_HB2_55 0x55U 241 #define REG_PKT_GM_1_56 0x56U 242 #define REG_PKT_GM_3_57 0x57U 243 #define REG_PKT_GM_5_58 0x58U 244 #define REG_PKT_GM_7_59 0x59U 245 #define REG_PKT_GM_9_5A 0x5AU 246 #define REG_PKT_GM_11_5B 0x5BU 247 #define REG_PKT_GM_13_5C 0x5CU 248 #define REG_PKT_GM_15_5D 0x5DU 249 #define REG_PKT_GM_17_5E 0x5EU 250 #define REG_PKT_GM_19_5F 0x5FU 251 #define REG_PKT_N_PKT_60 0x60U 252 #define REG_PKT_N_PKT_61 0x61U 253 254 //***** Bank 172D - HDMITX_Video *****// 255 #define REG_VE_CONFIG_00 0x00U 256 #define REG_VE_CONFIG_01 0x01U 257 #define REG_VE_CONFIG_02 0x02U 258 #define REG_VE_CONFIG_03 0x03U 259 #define REG_VE_CONFIG_04 0x04U 260 #define REG_VE_CONFIG_05 0x05U 261 #define REG_VE_CONFIG_06 0x06U 262 #define REG_VE_CONFIG_07 0x07U 263 #define REG_VE_CONFIG_08 0x08U 264 #define REG_VE_CONFIG_09 0x09U 265 #define REG_VE_CONFIG_0A 0x0AU 266 #define REG_VE_CONFIG_0B 0x0BU 267 #define REG_VE_CONFIG_0C 0x0CU 268 #define REG_VE_CONFIG_0D 0x0DU 269 #define REG_VE_CONFIG_0E 0x0EU 270 #define REG_VE_CONFIG_0F 0x0FU 271 #define REG_VE_CONFIG_10 0x10U 272 #define REG_VE_CONFIG_11 0x11U 273 #define REG_VE_CONFIG_12 0x12U 274 #define REG_VE_CONFIG_13 0x13U 275 #define REG_VE_CONFIG_14 0x14U 276 #define REG_VE_STATUS_15 0x15U 277 #define REG_VE_STATUS_16 0x16U 278 #define REG_VE_CONFIG_17 0x17U 279 #define REG_VE_CONFIG_18 0x18U 280 #define REG_VE_CONFIG_20 0x20U 281 #define REG_VE_CONFIG_21 0x21U 282 #define REG_VE_CONFIG_22 0x22U 283 #define REG_VE_CONFIG_23 0x23U 284 #define REG_VE_CONFIG_24 0x24U 285 #define REG_VE_CONFIG_25 0x25U 286 #define REG_VE_CONFIG_26 0x26U 287 #define REG_VE_CONFIG_27 0x27U 288 #define REG_VE_CONFIG_28 0x28U 289 #define REG_VE_CONFIG_29 0x29U 290 #define REG_VE_CONFIG_2A 0x2AU 291 #define REG_VE_CONFIG_30 0x30U 292 #define REG_VE_CONFIG_31 0x31U 293 #define REG_VE_CONFIG_32 0x32U 294 #define REG_VE_CONFIG_33 0x33U 295 #define REG_VE_CONFIG_34 0x34U 296 #define REG_VE_CONFIG_35 0x35U 297 #define REG_VE_CONFIG_36 0x36U 298 #define REG_VE_CONFIG_37 0x37U 299 #define REG_VE_CONFIG_38 0x38U 300 #define REG_VE_CONFIG_39 0x39U 301 #define REG_VE_CONFIG_3A 0x3AU 302 #define REG_VE_CONFIG_3B 0x3BU 303 #define REG_VE_CONFIG_3C 0x3CU 304 #define REG_VE_CONFIG_3D 0x3DU 305 306 //***** Bank 172E - HDMITX_Audio *****// 307 #define REG_AE_CH_STATUS0_00 0x00U 308 #define REG_AE_CH_STATUS1_01 0x01U 309 #define REG_AE_CH_STATUS2_02 0x02U 310 #define REG_AE_CH_STATUS3_03 0x03U 311 #define REG_AE_CH_STATUS4_04 0x04U 312 #define REG_AE_CONFIG_05 0x05U 313 #define REG_AE_STATUS_06 0x06U 314 #define REG_AE_STATUS_07 0x07U 315 #define REG_AE_CH_STATUS0_0A 0x0AU 316 #define REG_AE_CH_STATUS1_0B 0x0BU 317 #define REG_AE_CH_STATUS2_0C 0x0CU 318 #define REG_AE_CH_STATUS3_0D 0x0DU 319 #define REG_AE_CH_STATUS4_0E 0x0EU 320 321 322 //***** Bank 172A - MISC *****// 323 #define REG_MISC_CONFIG_00 0x00U 324 #define REG_MISC_CONFIG_01 0x01U 325 #define REG_MISC_CONFIG_02 0x02U 326 #define REG_MISC_CONFIG_03 0x03U 327 #define REG_MISC_CONFIG_04 0x04U 328 #define REG_MISC_CONFIG_05 0x05U 329 #define REG_MISC_CONFIG_06 0x06U 330 #define REG_MISC_CONFIG_07 0x07U 331 #define REG_MISC_CONFIG_08 0x08U 332 #define REG_MISC_CONFIG_09 0x09U 333 #define REG_MISC_STATUS_0A 0x0AU 334 #define REG_MISC_STATUS_0B 0x0BU 335 #define REG_MISC_CONFIG_0C 0x0CU 336 #define REG_MISC_STATUS_0D 0x0DU 337 #define REG_MISC_STATUS_0E 0x0EU 338 #define REG_MISC_STATUS_0F 0x0FU 339 #define REG_MISC_CONFIG_17 0x17U 340 #define REG_MISC_CONFIG_1B 0x1BU 341 #define REG_MISC_CONFIG_1C 0x1CU 342 #define REG_MISC_CONFIG_1D 0x1DU 343 #define REG_MISC_CONFIG_1E 0x1EU 344 #define REG_MISC_CONFIG_1F 0x1FU 345 #define REG_MISC_CONFIG_20 0x20U 346 #define REG_MISC_CONFIG_21 0x21U 347 #define REG_MISC_CONFIG_22 0x22U 348 #define REG_MISC_CONFIG_23 0x23U 349 #define REG_MISC_CONFIG_24 0x24U 350 #define REG_MISC_CONFIG_25 0x25U 351 #define REG_MISC_CONFIG_26 0x26U 352 #define REG_MISC_CONFIG_27 0x27U 353 #define REG_MISC_CONFIG_2A 0x2AU 354 #define REG_MISC_CONFIG_2B 0x2BU 355 #define REG_MISC_CONFIG_2C 0x2CU 356 #define REG_MISC_CONFIG_2D 0x2DU 357 #define REG_MISC_CONFIG_2E 0x2EU 358 #define REG_MISC_CONFIG_2F 0x2FU 359 #define REG_MISC_CONFIG_33 0x33U 360 #define REG_MISC_CONFIG_34 0x34U 361 #define REG_MISC_CONFIG_36 0x36U 362 #define REG_MISC_CONFIG_38 0x38U 363 #define REG_MISC_CONFIG_40 0x40U 364 #define REG_MISC_CONFIG_41 0x41U 365 #define REG_MISC_CONFIG_45 0x45U 366 #define REG_MISC_CONFIG_48 0x48U 367 #define REG_MISC_CONFIG_4D 0x4DU 368 #define REG_MISC_CONFIG_52 0x52U 369 #define REG_MISC_CONFIG_58 0x58U 370 #define REG_MISC_CONFIG_59 0x59U 371 #define REG_MISC_CONFIG_5D 0x5DU 372 373 374 //***** Bank 172B - HDCP *****// 375 #define REG_HDCP_TX_RI_00 0x00U 376 #define REG_HDCP_TX_MODE_01 0x01U // Pj[7:0] : 61h[7:0]; Tx_mode[7:0] : 61h[15:8] 377 #define REG_HDCP_TX_COMMAND_02 0x02U 378 #define REG_HDCP_TX_RI127_03 0x03U // RI[15:0] 127th frame : 63[15:0] 379 #define REG_HDCP_TX_LN_04 0x04U // Ln[55:0] : 64h[7:0] ~ 67h[7:0] 380 #define REG_HDCP_TX_LN_SEED_07 0x07U // Ln seed[7:0] : 67h[15:8] 381 #define REG_HDCP_TX_AN_08 0x08U // An[63:0] : 68[7:0] ~ 6B[15:8] 382 #define REG_HDCP_TX_MI_0C 0x0CU // Mi[63:0] : 6C[7:0] ~ 6F[15:8] 383 384 //***** Bank 1730 - HDMI PHY *****// 385 #define REG_HDMITxPHY_CONFIG_01 0x01U 386 #define REG_HDMITxPHY_CONFIG_02 0x02U 387 #define REG_HDMITxPHY_CONFIG_03 0x03U 388 #define REG_HDMITxPHY_CONFIG_05 0x05U 389 #define REG_HDMITxPHY_CONFIG_06 0x06U 390 #define REG_HDMITxPHY_CONFIG_07 0x07U 391 #define REG_HDMITxPHY_CONFIG_0F 0x0FU 392 #define REG_HDMITxPHY_CONFIG_10 0x10U 393 #define REG_HDMITxPHY_CONFIG_11 0x11U 394 #define REG_HDMITxPHY_CONFIG_15 0x15U 395 #define REG_HDMITxPHY_CONFIG_16 0x16U 396 #define REG_HDMITxPHY_CONFIG_17 0x17U 397 #define REG_HDMITxPHY_CONFIG_18 0x18U 398 #define REG_HDMITxPHY_CONFIG_19 0x19U 399 #define REG_HDMITxPHY_CONFIG_26 0x26U 400 #define REG_HDMITxPHY_CONFIG_2E 0x2EU 401 #define REG_HDMITxPHY_CONFIG_30 0x30U 402 #define REG_HDMITxPHY_CONFIG_31 0x31U 403 #define REG_HDMITxPHY_CONFIG_32 0x32U 404 #define REG_HDMITxPHY_CONFIG_33 0x33U 405 #define REG_HDMITxPHY_CONFIG_34 0x34U 406 #define REG_HDMITxPHY_CONFIG_35 0x35U 407 #define REG_HDMITxPHY_CONFIG_36 0x36U 408 #define REG_HDMITxPHY_CONFIG_37 0x37U 409 #define REG_HDMITxPHY_CONFIG_38 0x38U 410 #define REG_HDMITxPHY_CONFIG_39 0x39U 411 #define REG_HDMITxPHY_CONFIG_3A 0x3AU 412 #define REG_HDMITxPHY_CONFIG_3C 0x3CU 413 #define REG_HDMITxPHY_CONFIG_3D 0x3DU 414 #define REG_HDMITxPHY_CONFIG_3F 0x3FU 415 #define REG_HDMITxPHY_CONFIG_41 0x41U 416 #define REG_HDMITxPHY_CONFIG_42 0x42U 417 #define REG_HDMITxPHY_CONFIG_46 0x46U 418 #define REG_HDMITxPHY_CONFIG_60 0x60U 419 #define REG_HDMITxPHY_CONFIG_79 0x79U 420 #define REG_HDMITxPHY_CONFIG_7A 0x7AU 421 #define REG_HDMITxPHY_CONFIG_7E 0x7EU 422 423 //***** Bank 1738 - HDMITX 2 *****// 424 #define REG_HDMI_2_CONFIG_00 0x00U 425 #define REG_HDMI_2_CONFIG_10 0x10U 426 #define REG_HDMI_2_CONFIG_1D 0x1DU 427 #define REG_HDMI_2_CONFIG_1E 0x1EU 428 #define REG_HDMI_2_CONFIG_1F 0x1FU 429 430 //***** Bank 0E - PM_SLEEP *****// 431 #define REG_PM_SLP_0F 0x0FU 432 #define REG_PM_SLP_10 0x10U 433 #define REG_PM_SLP_12 0x12U 434 #define REG_PM_SLP_20 0x20U 435 #define REG_PM_SLP_27 0x27U 436 #define REG_PM_SLP_4A 0x4AU 437 #define REG_PM_SLP_4B 0x4BU 438 #define REG_PM_SLP_4C 0x4CU 439 #define REG_PM_SLP_57 0x57U 440 #define REG_PM_SLP_62 0x62U 441 442 //***** Bank 14 - PM_SAR *****// 443 #define REG_PM_SAR_11 0x11U 444 #define REG_PM_SAR_12 0x12U 445 446 //***** Bank 21 - TX_PM *****// 447 #define REG_PM_HDMITX_03 0x03U 448 #define REG_PM_HDMITX_1C 0x1CU 449 #define REG_PM_HDMITX_2B 0x2BU 450 #define REG_PM_HDMITX_2C 0x2CU 451 #define REG_PM_HDMITX_2E 0x2EU 452 #define REG_PM_HDMITX_2F 0x2FU 453 #define REG_PM_HDMITX_33 0x33U 454 #define REG_PM_HDMITX_34 0x34U 455 #define REG_PM_HDMITX_38 0x38U 456 457 //***** Bank 22 - RX_PM *****// 458 #define REG_PM_HDMIRX_ATOP_06 0x06U 459 #define REG_PM_HDMIRX_ATOP_60 0x60U 460 #define REG_PM_HDMIRX_ATOP_7F 0x7FU 461 462 //------------------------------------------------------------------------------------------------- 463 // Type and Structure 464 //------------------------------------------------------------------------------------------------- 465 466 #endif // _REG_HDMITX_H_ 467 468