1 //<MStar Software>
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #define MHAL_HDMITX_C
96
97 //-------------------------------------------------------------------------------------------------
98 // Include Files
99 //-------------------------------------------------------------------------------------------------
100 // Common Definition
101 #ifdef MSOS_TYPE_LINUX_KERNEL
102 #include <linux/string.h>
103 #else
104 #include <string.h>
105 #endif
106
107 #include "MsCommon.h"
108
109 // Internal Definition
110 #include "regHDMITx.h"
111 #include "halHDMIUtilTx.h"
112 #include "halHDMITx.h"
113 #include "drvHDMITx.h"
114
115 // External Definition
116 #include "drvGPIO.h"
117 #include "drvSYS.h"
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126
127 #define GENERAL_PKT_NUM 0x0BU //wilson@kano
128 #define INFOFRM_PKT_NUM 0x08U //for HDR packet ID = 0x87; 0x06U //wilson@kano
129
130
131 #define HDMITX_VS_INFO_PKT_VER 0x01U
132 #define HDMITX_VS_INFO_PKT_LEN 0x1BU
133
134 #define HDMITX_AVI_INFO_PKT_VER 0x02U
135 #define HDMITX_AVI_INFO_PKT_LEN 0x0DU
136
137 #define HDMITX_SPD_INFO_PKT_VER 0x01U
138 #define HDMITX_SPD_INFO_PKT_LEN 0x19U
139
140 #define HDMITX_AUD_INFO_PKT_VER 0x01U
141 #define HDMITX_AUD_INFO_PKT_LEN 0x0AU
142
143 #define HDMITX_HDR_INFO_PKT_VER 0x01U
144 #define HDMITX_HDR_INFO_PKT_LEN 0x1BU //wilson@kano: temp solution
145
146
147
148 #define IS_STOP_PKT(_X_) ( (_X_ & E_HDMITX_STOP_PACKET) ? 1 : 0 )
149 #define IS_CYCLIC_PKT(_X_) ( (_X_ & E_HDMITX_CYCLIC_PACKET) ? 1 : 0 )
150
151 // HDMI packet cyclic frame count
152 #define HDMITX_PACKET_NULL_FCNT 0U ///< 0 ~ 31
153 #define HDMITX_PACKET_ACR_FCNT 0U ///< 0 ~ 15
154 #define HDMITX_PACKET_GC_FCNT 0U ///< 0 ~ 1
155 #define HDMITX_PACKET_ACP_FCNT 15U ///< 0 ~ 31
156 #define HDMITX_PACKET_ISRC_FCNT 15U ///< 0 ~ 31
157
158 #define HDMITX_PACKET_VS_FCNT 0U ///< 0 ~ 31
159 #define HDMITX_PACKET_AVI_FCNT 0U ///< 0 ~ 31
160 #define HDMITX_PACKET_SPD_FCNT 1U ///< 0 ~ 31
161 #define HDMITX_PACKET_AUD_FCNT 0U ///< 0 ~ 31
162 #define HDMITX_PACKET_HDR_FCNT 0U
163
164 #define HDMITX_PACKET_SPD_SDI 1U // Digital STB
165 #define HDMITX_CSC_SUPPORT_R2Y 1U
166
167 #define HDMITX_MAX_PIXEL_CLK 597000000 //Max cupported pixel clock
168
169 //-------------------------------------------------------------------------------------------------
170 // Local Structures
171 //-------------------------------------------------------------------------------------------------
172
173 //*********************//
174 // Video //
175 //*********************//
176
177 typedef enum
178 {
179 E_HDMITX_VIDEO_INTERLACE_MODE = 0,
180 E_HDMITX_VIDEO_PROGRESSIVE_MODE = 1,
181 } MDrv_HDMITx_VIDEO_MODE;
182
183 typedef enum
184 {
185 E_HDMITX_VIDEO_POLARITY_HIGH = 0,
186 E_HDMITX_VIDEO_POLARITY_LOW = 1,
187 } MDrv_HDMITx_VIDEO_POLARITY;
188
189 typedef struct
190 {
191 MDrv_HDMITx_VIDEO_MODE i_p_mode; // interlace / progressive mode
192 MDrv_HDMITx_VIDEO_POLARITY h_polarity; // Hsync polarity
193 MDrv_HDMITx_VIDEO_POLARITY v_polarity; // Vsync polarity
194 MS_U16 vs_width; // Vsync pulse width
195 MS_U16 vs_bporch; // Vsync back-porch
196 MS_U16 vde_width; // Vde active width
197 MS_U16 vs_delayline; // Vsync line delay
198 MS_U16 vs_delaypixel; // Vsync pixel delay
199 MS_U16 hs_width; // Hsync pulse width
200 MS_U16 hs_bporch; // Hsync back-porch
201 MS_U16 hde_width; // Hde active width
202 MS_U16 hs_delay; // Hsync delay
203 MS_U16 vtotal; // Vsync total
204 MS_U16 htotal; // Hsync total
205 MS_U16 frame_rate; // Frame Rate
206 MS_U32 pixel_clk; //pixel clock
207 } MDrv_HDMITx_VIDEO_MODE_INFO_TYPE;
208
209 //*********************//
210 // Packet //
211 //*********************//
212
213 typedef enum
214 {
215 E_HDMITX_ACT_GCP_CMD = 0,
216 E_HDMITX_ACT_ACR_CMD = 1,
217 E_HDMITX_ACT_AVI_CMD = 2,
218 E_HDMITX_ACT_AUD_CMD = 3,
219 E_HDMITX_ACT_SPD_CMD = 4,
220 E_HDMITX_ACT_MPG_CMD = 5,
221 E_HDMITX_ACT_VSP_CMD = 6,
222 E_HDMITX_ACT_NUL_CMD = 7,
223 E_HDMITX_ACT_ACP_CMD = 8,
224 E_HDMITX_ACT_ISRC_CMD = 9,
225 E_HDMITX_ACT_GCP_DC_CMD = 10, // GCP with non-zero CD
226 E_HDMITX_ACT_GMP_CMD = 11, // Gamut Metadata packet
227 } MDrvHDMITX_PKTS_ACT_CMD;
228
229 typedef struct PKT
230 {
231 MS_BOOL User_Define;
232 MsHDMITX_PACKET_PROCESS Define_Process;
233 MS_U8 Define_FCnt;
234 }PKT_Behavior;
235 //*********************//
236 // Audio //
237 //*********************//
238 typedef struct
239 {
240 MS_U8 CH_Status3;
241 MS_U32 NcodeValue;
242 } MDrv_HDMITx_AUDIO_FREQ_TYPE;
243
244 //-------------------------------------------------------------------------------------------------
245 // Global Variables
246 //-------------------------------------------------------------------------------------------------
247 MS_U8 gDivider = 0x00;
248 MS_BOOL gDivFlag = FALSE;
249 static MS_U8 gu8ChipVerNum = 0x00;
250 MS_BOOL g_bSupportSCDC = FALSE;
251
252 stHDMITx_PKT_ATTRIBUTE gbGeneralPktList[GENERAL_PKT_NUM]; //wilson@kano
253 stHDMITx_PKT_ATTRIBUTE gbInfoFrmPktList[INFOFRM_PKT_NUM]; //wilson@kano
254
255 // User defined packet behavior
256 PKT_Behavior NULL_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
257 PKT_Behavior ACR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
258 PKT_Behavior AS_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
259 PKT_Behavior GC_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
260 PKT_Behavior ACP_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
261 PKT_Behavior ISRC1_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
262 PKT_Behavior ISRC2_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
263 PKT_Behavior DSD_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
264 PKT_Behavior HBR_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
265 PKT_Behavior GM_PACKET = {FALSE, E_HDMITX_STOP_PACKET, 0};
266
267 PKT_Behavior VS_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
268 PKT_Behavior AVI_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
269 PKT_Behavior SPD_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
270 PKT_Behavior AUDIO_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
271 PKT_Behavior MPEG_INFORAME = {FALSE, E_HDMITX_STOP_PACKET, 0};
272 //-------------------------------------------------------------------------------------------------
273 // Local Variables
274 //-------------------------------------------------------------------------------------------------
275
276 //*********************//
277 // Video //
278 //*********************//
279
280 // It should be mapped with MsHDMITX_VIDEO_TIMING structure in drvHDMITx.h
281 MDrv_HDMITx_VIDEO_MODE_INFO_TYPE HDMITxVideoModeTbl[E_HDMITX_RES_MAX]=
282 {
283 //IorPMode; PolarityH; PolarityV; VSW; VbckP; VDe; VSDel; VSDelP; HSW; HbckP; HDe; HSDel; VSTotal; HSTotal;
284 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0002, 0x0021, 0x01E0, 0x000A, 0, 0x0060, 0x0030, 0x0280, 0x0010, 0x020D, 0x0320, 60, 25175000}, // 0: 640x480p
285 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x000F, 0x01E0, 0x0004, 0, 0x007C, 0x0072, 0x05A0, 0x0026, 0x020D, 0x06B4, 60, 27000000}, // 1: 720x480i
286 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0003, 0x0013, 0x0240, 0x0002, 0, 0x007E, 0x008A, 0x05A0, 0x0018, 0x0271, 0x06C0, 50, 27000000}, // 2: 720x576i
287 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0006, 0x001E, 0x01E0, 0x0009, 0, 0x003E, 0x003C, 0x02D0, 0x0010, 0x020D, 0x035A, 60, 27000000}, // 3: 720x480p
288 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_LOW, E_HDMITX_VIDEO_POLARITY_LOW, 0x0005, 0x0027, 0x0240, 0x0005, 0, 0x0040, 0x0044, 0x02D0, 0x000C, 0x0271, 0x0360, 50, 27000000}, // 4: 720x576p
289 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x02EE, 0x07BC, 50, 74250000}, // 5: 1280x720p_50Hz
290 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x02D0, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x02EE, 0x0672, 60, 74250000}, // 6: 1280x720p_60Hz
291 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 74250000}, // 7: 1920x1080i_50Hz
292 {E_HDMITX_VIDEO_INTERLACE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x000F, 0x0438, 0x0002, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 74250000}, // 8: 1920x1080i_60Hz
293 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x0465, 0x0ABE, 24, 74250000}, // 9: 1920x1080p_24Hz
294 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 25, 74250000}, // 10: 1920x1080p_25Hz
295 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 30, 74250000}, // 11: 1920x1080p_30Hz
296 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0210, 0x0465, 0x0A50, 50, 148500000}, // 12: 1920x1080p_50Hz
297 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x0438, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x0058, 0x0465, 0x0898, 60, 148500000}, // 13: 1920x1080p_60Hz
298 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0024, 0x089D, 0x0004, 0, 0x002C, 0x0094, 0x0780, 0x027E, 0x08CA, 0x0ABE, 24, 148500000}, // 14: 1920x2205p_24Hz //3D: 1920x1080p_24Hz x2
299 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x01B8, 0x05DC, 0x07BC, 50, 148500000}, // 15: 1280x1470p_50Hz //3D: 1280x720_50Hz x2
300 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0005, 0x0014, 0x05BE, 0x0005, 0, 0x0028, 0x00DC, 0x0500, 0x006E, 0x05DC, 0x0672, 60, 148500000}, // 16: 1280x1470p_60Hz //3D: 1280x720_60Hz x2
301
302 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x04FC, 0x08CA, 0x157C, 24, 297000000}, // 17:93: 3840x2160p_24Hz
303 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 25, 297000000}, // 18:94: 3840x2160p_25Hz
304 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 30, 297000000}, // 19:95: 3840x2160p_30Hz
305 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x0420, 0x08CA, 0x14A0, 50, 594000000}, // 20:96: 3840x2160p_50Hz
306 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x0F00, 0x00B0, 0x08CA, 0x1130, 60, 594000000}, // 21:97: 3840x2160p_60Hz
307
308 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0128, 0x1000, 0x03FC, 0x08CA, 0x157C, 24, 297000000}, // 22:98: 4096x2160p_24Hz
309 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 25, 297000000}, // 23:99: 4096x2160p_25Hz
310 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 30, 297000000}, // 24:100: 4096x2160p_30Hz
311 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x03C8, 0x08CA, 0x14A0, 50, 594000000}, // 25:101: 4096x2160p_50Hz
312 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x000A, 0x0048, 0x0870, 0x0008, 0, 0x0058, 0x0080, 0x1000, 0x0058, 0x08CA, 0x1130, 60, 594000000}, // 26:102: 4096x2160p_60Hz
313
314 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x002E, 0x04B0, 0x0001, 0, 0x00C0, 0x0130, 0x0640, 0x0040, 0x04E2, 0x0870, 60, 162000000}, // 27: 1600x1200p_60Hz
315 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x0019, 0x0384, 0x0003, 0, 0x0098, 0x00E8, 0x05A0, 0x0050, 0x03A6, 0x0770, 60, 106500000}, // 28: 1440x900p_60Hz
316 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0003, 0x0026, 0x0400, 0x0001, 0, 0x0070, 0x00F8, 0x0500, 0x0030, 0x042A, 0x0698, 60, 108000000}, // 29: 1280x1024p_60Hz
317 {E_HDMITX_VIDEO_PROGRESSIVE_MODE, E_HDMITX_VIDEO_POLARITY_HIGH, E_HDMITX_VIDEO_POLARITY_HIGH, 0x0006, 0x001D, 0x0300, 0x0003, 0, 0x0088, 0x00A0, 0x0400, 0x0024, 0x0326, 0x0540, 60, 65000000}, // 30: 1024x768p_60Hz
318 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
319 };
320
321 //atop setting
322 stHDMITx_ATOP_SETTING HDMITxVideoAtopSetting[HDMITX_COLOR_DEPTH_TYPE_NUM][E_HDMITX_RES_MAX] =
323 {
324 //color depth = 8bit
325 {
326 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
327 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
328 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
329 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
330 {0x03, 0x03, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
331 // 74Mhz
332 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
333 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
334 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
335 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
336 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
337 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
338 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
339 // 148Mhz
340 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 12: 1920x1080p_50Hz
341 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 13: 1920x1080p_60Hz
342 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 14: 1920x2205p_24Hz
343 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 15: 1280x1470p_50Hz
344 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 16: 1280x1470p_60Hz
345 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
346 // 300Mhz
347 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
348 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
349 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
350 // 600Mhz
351 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
352 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
353 // 300Mhz
354 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
355 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
356 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
357 // 600Mhz
358 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
359 {0x00, 0x00, 0x00, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
360
361 // 150MHz
362 {0x01, 0x01, 0x00, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 27: 1600x1200p_60Hz
363 // 106.5MHz
364 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x40EB71}, // 28: 1440x900p_60Hz
365 // 108MHz
366 {0x01, 0x01, 0x00, 0x03, 0x14, 0x0F, 0x400000}, // 29: 1280x1024p_60Hz
367 // 65MHz
368 {0x02, 0x02, 0x00, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
369 },
370
371 //color depth = 10 bit
372 {
373 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 0: 640x480p
374 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 1: 720x480i
375 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 2: 720x576i
376 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 3: 720x480p
377 {0x03, 0x03, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 4: 720x576p
378 // 74Mhz
379 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 5: 1280x720p_50Hz
380 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 6: 1280x720p_60Hz
381 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 7: 1920x1080i_50Hz
382 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x25460A}, // 8: 1920x1080i_60Hz
383 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 9: 1920x1080p_24Hz
384 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 10: 1920x1080p_25Hz
385 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 11: 1920x1080p_30Hz
386 // 148Mhz
387 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 12: 1920x1080p_50Hz
388 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 13: 1920x1080p_60Hz
389 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 14: 1920x2205p_24Hz
390 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 15: 1280x1470p_50Hz
391 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x253C82}, // 16: 1280x1470p_60Hz
392 // the following is 4k2k timing list, if not support, default is 3840x2160p@3
393
394 // 300Mhz
395 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 17:93: 3840x2160p_24Hz
396 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 18:94: 3840x2160p_25Hz
397 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 19:95: 3840x2160p_30Hz
398 // 600Mhz ==> not support !!!
399 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 20:96: 3840x2160p_50Hz
400 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 21:97: 3840x2160p_60Hz
401 // 300Mhz
402 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 22:98: 4096x2160p_24Hz
403 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 23:99: 4096x2160p_25Hz
404 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 24:100: 4096x2160p_30Hz
405 // 600Mhz ==> not support !!!
406 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 25:101: 4096x2160p_50Hz
407 {0x00, 0x00, 0x01, 0x0C, 0x38, 0x08, 0x253C82}, // 26:102: 4096x2160p_60Hz
408
409 // 150MHz
410 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x222222}, // 27: 1600x1200p_60Hz
411 // 106.5MHz
412 //{0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x33EBCE}, // 28: 1440x900p_60Hz
413 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x33EF8D},
414 // 108MHz
415 {0x01, 0x01, 0x01, 0x03, 0x14, 0x0F, 0x333333}, // 29: 1280x1024p_60Hz
416 // 65MHz
417 {0x02, 0x02, 0x01, 0x03, 0x14, 0x0F, 0x2A890E}, // 30: 1024x768p_60Hz
418 },
419
420 //color depth = 12 bit
421 {
422 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 0: 640x480p
423 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 1: 720x480i
424 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 2: 720x576i
425 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 3: 720x480p
426 {0x03, 0x03, 0x02, 0x03, 0x14, 0x0F, 0x2AAAAA}, // 4: 720x576p
427 // 74Mhz
428 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 5: 1280x720p_50Hz
429 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 6: 1280x720p_60Hz
430 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 7: 1920x1080i_50Hz
431 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F0FB3}, // 8: 1920x1080i_60Hz
432 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 9: 1920x1080p_24Hz
433 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 10: 1920x1080p_25Hz
434 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x1F07C1}, // 11: 1920x1080p_30Hz
435 // 148Mhz
436 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 12: 1920x1080p_50Hz
437 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 13: 1920x1080p_60Hz
438 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 14: 1920x2205p_24Hz
439 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 15: 1280x1470p_50Hz
440 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 16: 1280x1470p_60Hz
441 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
442
443 // 300Mhz
444 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 17:93: 3840x2160p_24Hz
445 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 18:94: 3840x2160p_25Hz
446 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 19:95: 3840x2160p_30Hz
447 // 600Mhz ==> not support !!!
448 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 20:96: 3840x2160p_50Hz
449 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 21:97: 3840x2160p_60Hz
450 // 300Mhz
451 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 22:98: 4096x2160p_24Hz
452 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 23:99: 4096x2160p_25Hz
453 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 24:100: 4096x2160p_30Hz
454 // 600Mhz ==> not support !!!
455 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 25:101: 4096x2160p_50Hz
456 {0x00, 0x00, 0x02, 0x0C, 0x38, 0x08, 0x1F07C1}, // 26:102: 4096x2160p_60Hz
457
458 // 150MHz
459 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x04, 0x1C71C7}, // 27: 1600x1200p_60Hz
460 // 106.5MHz
461 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2B47A0}, // 28: 1440x900p_60Hz
462 // 108MHz
463 {0x01, 0x01, 0x02, 0x0C, 0x38, 0x08, 0x2AAAAA}, // 29: 1280x1024p_60Hz
464 // 65MHz
465 {0x02, 0x02, 0x02, 0x03, 0x14, 0x0F, 0x237237}, // 30: 1024x768p_60Hz
466 },
467
468 //color depth = 16 bit
469 {
470 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 0: 640x480p
471 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 1: 720x480i
472 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 2: 720x576i
473 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 3: 720x480p
474 {0x02, 0x02, 0x03, 0x03, 0x14, 0x0F, 0x400000}, // 4: 720x576p
475 // 74Mhz
476 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 5: 1280x720p_50Hz
477 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 6: 1280x720p_60Hz
478 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 7: 1920x1080i_50Hz
479 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E978D}, // 8: 1920x1080i_60Hz
480 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 9: 1920x1080p_24Hz
481 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 10: 1920x1080p_25Hz
482 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x2E8BA2}, // 11: 1920x1080p_30Hz
483 // 148Mhz
484 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 12: 1920x1080p_50Hz
485 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 13: 1920x1080p_60Hz
486 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 14: 1920x2205p_24Hz
487 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 15: 1280x1470p_50Hz
488 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x2E8BA2}, // 16: 1280x1470p_60Hz
489 // the following is 4k2k timing list, if not support, default is 3840x2160p@30
490
491 // 300Mhz
492 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 17:93: 3840x2160p_24Hz
493 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 18:94: 3840x2160p_25Hz
494 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 19:95: 3840x2160p_30Hz
495 // 600Mhz ==> Not support !!!
496 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 20:96: 3840x2160p_50Hz
497 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 21:97: 3840x2160p_60Hz
498 // 300Mhz
499 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 22:98: 4096x2160p_24Hz
500 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 23:99: 4096x2160p_25Hz
501 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 24:100: 4096x2160p_30Hz
502 // 600Mhz ==> Not support !!!
503 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 25:101: 4096x2160p_50Hz
504 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x1745D1}, // 26:102: 4096x2160p_60Hz
505
506 // 150MHz
507 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x04, 0x2AAAAA}, // 27: 1600x1200p_60Hz
508 // 106.5MHz
509 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x40EB71}, // 28: 1440x900p_60Hz
510 // 108MHz
511 {0x00, 0x00, 0x03, 0x0C, 0x38, 0x08, 0x400000}, // 29: 1280x1024p_60Hz
512 // 65MHz
513 {0x01, 0x01, 0x03, 0x03, 0x14, 0x0F, 0x352B52}, // 30: 1024x768p_60Hz
514 },
515 };
516
517 //*********************//
518 // Audio //
519 //*********************//
520
521 MSTHDMITX_REG_TYPE HDMITxAudioOnTbl[] =
522 {
523 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1086}, //[12]: CH status swap[7:0], [7]: enable audio FIFO, [2]:enable CTS Gen, [1]: automatically block start, [0]: audio FIFO not flush
524 };
525
526 MSTHDMITX_REG_TYPE HDMITxAudioOffTbl[] =
527 {
528 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
529 };
530
531 MSTHDMITX_REG_TYPE HDMITxAudioInitTbl[] =
532 {
533 {HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x1087, 0x1003}, //[12]: CH status swap[7:0], [7]: disable audio FIFO, [2]:disable CTS Gen, [1]: automatically block start, [0]: audio FIFO flush
534 };
535
536 MDrv_HDMITx_AUDIO_FREQ_TYPE TxAudioFreqTbl[E_HDMITX_AUDIO_FREQ_MAX_NUM] =
537 {
538 {0x02, 0x001800}, // No signal, set to 48 KHz
539 {0x03, 0x001000}, // 0 ~(32)~ 38 KHz, 4096
540 {0x00, 0x001880}, // 38 ~(44.1)~ 46 KHz, 6272
541 {0x02, 0x001800}, // 46 ~(48)~ 60 KHz, 6144
542 {0x08, 0x003100}, // 60 ~(88.2)~ 92 KHz, 12544
543 {0x0a, 0x003000}, // 92 ~(96)~ 140 KHz, 12288
544 {0x0c, 0x006200}, // 140 ~(176.4)~ 180 KHz, 25088
545 {0x0e, 0x006000}, // 180 ~(192)~ ~~ KHz, 24576
546 };
547
548 //*********************//
549 // Packet //
550 //*********************//
551
552 MS_U8 HDMITX_AviCmrTbl[E_HDMITX_RES_MAX] =
553 {
554 0x48, 0x48, 0x48, 0x48, 0x48, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, // SDTV C=01(601),M=00(no data) ,R=1000(same)
555 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0x48,
556 0xA8, 0x48, 0x48,
557 };
558
559 MS_U8 HDMITX_AviVicTbl[E_HDMITX_RES_MAX] =
560 {
561 1, 6, 21, 2, 17, 19, 4, 20, 5, 32, 33, 34, 31, 16, // SDTV 480i60,576i50,480p60,576p50,720p50,720p60,1080i50,1080i60,1080p24,1080p25,1080p30, 1080p50, 1080p60
562 32, 19, 4, 0, 0, 0, 96, 97, 0, 99, 100, 101, 102, 0,
563 0, 0, 0,
564 };
565
566 MS_U8 HDMITX_VendorName[8] =
567 {
568 "MStar "
569 };
570
571 MS_U8 HDMITX_ProductName[16] =
572 {
573 "HDMI Tx Demo",
574 };
575
576 MS_U8 _gHPDGpioPin = 0;
577
578 //-------------------------------------------------------------------------------------------------
579 // Debug Functions
580 //-------------------------------------------------------------------------------------------------
581
582 #ifdef MS_DEBUG
583 #define DBG_HDMITX(_f) (_f)
584 #else
585 #define DBG_HDMITX(_f)
586 #endif
587
588 //-------------------------------------------------------------------------------------------------
589 // Local Functions
590 //-------------------------------------------------------------------------------------------------
591
592
593 //-------------------------------------------------------------------------------------------------
594 // Global Functions
595 //-------------------------------------------------------------------------------------------------
596 /*********************************************************************/
597 /* */
598 /* HDCP22 Relative */
599 /* */
600 /*********************************************************************/
MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)601 void MHal_HDMITx_HDCP2TxInit(MS_BOOL bEnable)
602 {
603 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x11, bEnable ? 0x11 : 0x00); // bit 0: enable hdcp22; bit 4: enable EESS
604 if (bEnable)
605 {
606 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x02); //reset hdcp22 FSM
607 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x02, 0x00);
608 }
609 }
610
MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)611 void MHal_HDMITx_HDCP2TxEnableEncryptEnable(MS_BOOL bEnable)
612 {
613 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x04, bEnable ? 0x04 : 0x00); //bit 2: authentication pass
614 MHal_HDMITx_Mask_Write(HDMITX_HDCP2TX_BASE, 0x0000, 0x08, bEnable ? 0x08 : 0x00); //bit 3: enable hdcp22 to issue encryption enable signal
615 }
616
MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 * pu8Riv,MS_U8 * pu8KsXORLC128)617 void MHal_HDMITx_HDCP2TxFillCipherKey(MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128)
618 {
619 #define DEF_HDCP2CIPHER_DBG 0
620 #define SIZE_OF_KSXORLC128 16
621 #define SIZE_OF_RIV 8
622
623 MS_U8 cnt = 0;
624
625 #if (DEF_HDCP2CIPHER_DBG == 1)
626 printf("Ks^LC128:\r\n");
627 for ( cnt = 0; cnt < SIZE_OF_KSXORLC128; cnt++ )
628 {
629 printf("0x%02X ", *(pu8KsXORLC128 + cnt));
630 }
631 printf("\r\n");
632
633 printf("Riv:\r\n");
634 for ( cnt = 0; cnt < SIZE_OF_RIV; cnt++ )
635 {
636 printf("0x%02X ", *(pu8Riv + cnt));
637 }
638 printf("\r\n");
639 #endif
640
641 #undef DEF_HDCP2CIPHER_DBG
642 //MHal_HDMITx_Mask_Write(0x172F00, 0x01, 0x0020, 0x0020); //reverse order of cihper key
643 //MHal_HDMITx_Mask_Write(0x172B00, 0x01, 0x8000, 0x0000); //disable hdcp 1.4 module
644
645 for ( cnt = 0; cnt < (SIZE_OF_KSXORLC128>>1); cnt++)
646 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x60 + (SIZE_OF_KSXORLC128 >> 1) - 1 - cnt, *(pu8KsXORLC128 + cnt*2 + 1)|(*(pu8KsXORLC128 + cnt*2)<<8));
647
648 for ( cnt = 0; cnt < (SIZE_OF_RIV>>1); cnt++)
649 MHal_HDMITx_Write(HDMITX_SECUTZPC_BASE, 0x68 + (SIZE_OF_RIV >> 1) - 1 - cnt, *(pu8Riv + cnt*2 + 1)|(*(pu8Riv + cnt*2)<<8));
650 }
651
Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)652 void Mhal_HDMITx_SetSCDCCapability(MS_BOOL bFlag)
653 {
654 g_bSupportSCDC = bFlag;
655 }
656
MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)657 void MHal_HDMITx_SetChipVersion(MS_U8 u8ChipVer)
658 {
659 gu8ChipVerNum = u8ChipVer;
660 }
661
662 // HPD: GPIO_PM[11] -> external interrupt[11], register 0x000E00[14]
663 // DVI disconnet: must power down clock termination resistor: TM_REG[0] = 1, TM_REG[16:15] = 00, TM_REG[35:34] = 00.
664 // Interrupt helper functoins
665 //------------------------------------------------------------------------------
666 /// @brief Disable interrupt
667 /// @param[in] u32Int interrupter value
668 /// @return None
669 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Disable(MS_U32 u32Int)670 void MHal_HDMITx_Int_Disable(MS_U32 u32Int)
671 {
672 //MS_U16 u16reg_val = 0;
673
674 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, (MS_U16)u32Int, (MS_U16)u32Int);
675 // [9]: mask FIQ, [8]: mask IRQ
676 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, (MS_U16)(u32Int>>16), (MS_U16)(u32Int>>16) );
677
678 #if 0 // K1 HPD pin doesn't have interrupt function
679 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
680 {
681 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
682 if(u32Int & E_HDMITX_IRQ_12) // HPD IRQ is move to PM_Sleep bank
683 {
684 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, u16reg_val); // GPIO_PM mask
685 }
686 }
687 #endif
688 }
689
690 //------------------------------------------------------------------------------
691 /// @brief Enable interrupt
692 /// @param[in] u32Int interrupter value
693 /// @return None
694 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Enable(MS_U32 u32Int)695 void MHal_HDMITx_Int_Enable(MS_U32 u32Int)
696 {
697 //MS_U16 u16reg_val = 0;
698
699 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_0C, 0xFFFF, ~u32Int);
700 // [9]: mask FIQ, [8]: unmask IRQ
701 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0D, 0xFFFF, (~u32Int)>>16 );
702
703 #if 0 // K1 HPD pin doesn't have interrupt function
704 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
705 {
706 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
707 if(u32Int & E_HDMITX_IRQ_12)
708 {
709 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x0F, 1<<_gHPDGpioPin, 1<<_gHPDGpioPin); // GPIO_PM output disable
710 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x00, u16reg_val, 0); // GPIO_PM non-mask
711 }
712 }
713 #endif
714 }
715
716 //------------------------------------------------------------------------------
717 /// @brief MHal_HDMITx_Int_Clear
718 /// @param[in] u32Int interrupter value
719 /// @return None
720 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Clear(MS_U32 u32Int)721 void MHal_HDMITx_Int_Clear(MS_U32 u32Int)
722 {
723 //MS_U16 u16reg_val = 0;
724
725 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E, u32Int);
726 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F, (u32Int>>16));
727
728 #if 0 // K1 HPD pin doesn't have interrupt function
729 if(_gHPDGpioPin != 0xC4) // HPD != I2S_GPIO4
730 {
731 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
732 if(u32Int & E_HDMITX_IRQ_12)
733 {
734 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, u16reg_val);
735 MHal_HDMITxPM_Mask_Write(PMBK_PMSLEEP_REG_BASE, 0x04, u16reg_val, 0);
736 }
737 }
738 #endif
739 }
740
741 //------------------------------------------------------------------------------
742 /// @brief MHal_HDMITx_Int_Status
743 /// @param[in] u32Int interrupter value
744 /// @return None
745 //------------------------------------------------------------------------------
MHal_HDMITx_Int_Status(void)746 MS_U32 MHal_HDMITx_Int_Status(void)
747 {
748 //MS_U16 u16reg_val = 0;
749 MS_U32 reg_value=0;
750
751 reg_value |= MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0E);
752 reg_value |= (MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_STATUS_0F)<<16);
753
754 #if 0 // K1 HPD pin doesn't have interrupt function
755 if(_gHPDGpioPin != 0xC4) // HPD = I2S_GPIO4
756 {
757 u16reg_val = (_gHPDGpioPin > 10) ? (1<<(_gHPDGpioPin+4)) : (1<<_gHPDGpioPin);
758 reg_value = ((MHal_HDMITxPM_Read(PMBK_PMSLEEP_REG_BASE, 0x0A) & u16reg_val) ? (reg_value|E_HDMITX_IRQ_12):(reg_value&(~E_HDMITX_IRQ_12)));
759 }
760 #endif
761 return reg_value;
762 }
763
764
765 //------------------------------------------------------------------------------
766 /// @brief This routine is to get HDMI receiver DVI clock and HPD status.
767 /// @return MsHDMITX_RX_STATUS
768 //------------------------------------------------------------------------------
MHal_HDMITx_GetRXStatus(void)769 MsHDMITX_RX_STATUS MHal_HDMITx_GetRXStatus(void)
770 {
771 MS_BOOL dviclock_s, hpd_s = FALSE;
772 MsHDMITX_RX_STATUS state;
773
774 dviclock_s = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F) & BIT0 ? FALSE : TRUE;
775
776 hpd_s = mdrv_gpio_get_level(_gHPDGpioPin);
777
778 if((dviclock_s == FALSE) && (hpd_s == FALSE))
779 state = E_HDMITX_DVIClock_L_HPD_L;
780 else if((dviclock_s == FALSE) && (hpd_s == TRUE))
781 state = E_HDMITX_DVIClock_L_HPD_H;
782 else if((dviclock_s == TRUE) && (hpd_s == FALSE))
783 state = E_HDMITX_DVIClock_H_HPD_L;
784 else
785 state = E_HDMITX_DVIClock_H_HPD_H;
786
787 return state;
788 }
789
790
791 //------------------------------------------------------------------------------
792 /// @brief MHal_HDMITX_SetHDCPConfig
793 /// @param[in] u32Int HDCP mode
794 /// @return None
795 //------------------------------------------------------------------------------
MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)796 void MHal_HDMITX_SetHDCPConfig(MS_U8 HDCP_mode)
797 {
798 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0E00, HDCP_mode << 8);
799 }
800
801
802 //------------------------------------------------------------------------------
803 /// @brief MHal_HDMITX_GetM02Bytes
804 /// @param[in] u16Int index
805 /// @return M0 2 bytes
806 //------------------------------------------------------------------------------
MHal_HDMITX_GetM02Bytes(MS_U16 idx)807 MS_U16 MHal_HDMITX_GetM02Bytes(MS_U16 idx)
808 {
809 return (MHal_HDMITx_Read(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MI_0C + idx));
810 }
811
812
813 //------------------------------------------------------------------------------
814 /// @brief MHal_HDMITx_InitSeq
815 /// @param[in] None
816 /// @return None
817 //------------------------------------------------------------------------------
MHal_HDMITx_InitSeq(void)818 void MHal_HDMITx_InitSeq(void)
819 {
820 MHal_HDMITx_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, 0); // enable clk_hdmi_tx_p
821
822 //wilson@temp solution
823 MHal_HDMITx_Mask_Write(0x101E00, 0x0B, BIT12, BIT12); //enable hdmitx DDC
824
825 //MAC setting
826 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1C, 0x0000);
827 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1D, 0x0000);
828 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1E, 0xFFFF);
829 MHal_HDMITx_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1F, 0x0000);
830
831 //sw reset modules
832 if(MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E) & 0xE800)
833 {
834 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
835 }
836 else
837 {
838 //disable power down
839 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
840 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
841 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0x0200);
842 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0017);
843 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_00, 0x0017, 0x0000);
844 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x001F);
845 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x001F, 0x0000);
846 }
847
848 //MHal_HDMITx_Write(HDMITX_REG_BASE, REG_HPLL_LOCK_CNT_53, 0x0300); // HPLL lock counter
849
850 //enable PHY setting
851 //[0]:enable synth clock; [4]:enable synth clock to a top; [8]:enable tmds clock; [12]: enable atop 40 bit clock
852 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101, 0x1101);
853 //[9]:pixel clock [11]:tmds clock [15..13]:enable data out
854 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00);
855
856 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3F, 0x0010, 0x0010); //reg_atop_nodie_en_disc
857
858 //disable power down
859 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
860 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, 0x0000);
861
862 //rterm set by Mboot according to data of EFUSE, rterm 50 Ohm
863 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x01F0, 0x0000);
864
865 //txpll input div 1
866 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x03F3, 0x0051);
867
868 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3D, 0x030F, 0x0003); //REG_TXPLL_SEL_CLKIN, REG_TXPLL_ICP_ICTRL
869 //MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0003); //REG_ICTRL_PREDRV_MAIN_CLK
870 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x003F, 0x0000); //REG_ICTRL_PREDRV_MAIN_CLK
871 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x003F, 0x0014); //REG_ICTRL_DRV_MAIN_CLK
872
873 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_32, 0x3F3F, 0x0000);
874 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_36, 0x3F3F, 0x0000);
875 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_37, 0x3F3F, 0x0000);
876
877 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
878
879 //lane fifo setting
880 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x0007, 0x0004);
881 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x0007, 0x0005);
882 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x0007, 0x0006);
883 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x0007, 0x0007);
884
885 //timing field regen enable (due to scaler can't guarantee field signal and even/odd frame is asynchronize)
886 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x0010, 0x0010);
887
888 //for U02: QD980 CTS compatibility issue
889 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x8000, (gu8ChipVerNum > 0x00) ? 0x8000 : 0x0000);
890
891 }
892
893 //------------------------------------------------------------------------------
894 /// @brief This routine is the initialization for Video module.
895 /// @return None
896 //------------------------------------------------------------------------------
MHal_HDMITx_VideoInit(void)897 void MHal_HDMITx_VideoInit(void)
898 {
899 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, BIT4, BIT4); //enable video engine fifo r/w pointer
900 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_12, 0x000F, BIT3); // [3]: manual mode of pixel-repetition enable
901 }
902
903 //------------------------------------------------------------------------------
904 /// @brief This routine is the initialization for Audio module.
905 /// @return None
906 //------------------------------------------------------------------------------
MHal_HDMITx_AudioInit(void)907 void MHal_HDMITx_AudioInit(void)
908 {
909 int num;
910
911 num = sizeof(HDMITxAudioInitTbl) / sizeof(MSTHDMITX_REG_TYPE);
912 MHal_HDMITx_RegsTbl_Write(HDMITxAudioInitTbl, num);
913 }
914
915
916 //------------------------------------------------------------------------------
917 /// @brief This routine turn on/off HDMI PLL
918 /// @return None
919 //------------------------------------------------------------------------------
MHal_HDMITx_PLLOnOff(MS_BOOL bflag)920 void MHal_HDMITx_PLLOnOff(MS_BOOL bflag)
921 {
922 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x0070, bflag ? 0x0000 : 0x0010);
923 }
924
925
MHal_HDMITx_PKT_User_Define_Clear(void)926 void MHal_HDMITx_PKT_User_Define_Clear(void)
927 {
928 MS_U8 i = 0;
929
930 for ( i = 0; i < GENERAL_PKT_NUM; i++ )
931 {
932 gbGeneralPktList[i].EnableUserDef = FALSE;
933 gbGeneralPktList[i].FrmCntNum = 0x00;
934 gbGeneralPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
935 memset(&gbGeneralPktList[i].PktPara, 0x00, sizeof(gbGeneralPktList[i].PktPara));
936 }
937
938 for ( i = 0; i < INFOFRM_PKT_NUM; i++ )
939 {
940 gbInfoFrmPktList[i].EnableUserDef = FALSE;
941 gbInfoFrmPktList[i].FrmCntNum = 0x00;
942 gbInfoFrmPktList[i].enPktCtrl = E_HDMITX_STOP_PACKET;
943 memset(&gbInfoFrmPktList[i].PktPara, 0x00, sizeof(gbInfoFrmPktList[i].PktPara));
944 }
945 }
946
MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type,MS_BOOL def_flag,MsHDMITX_PACKET_PROCESS def_process,MS_U8 def_fcnt)947 void MHal_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag,
948 MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt)
949 {
950 if (packet_type & 0x80) //infoframe packet type
951 {
952 gbInfoFrmPktList[packet_type & (~0x80)].EnableUserDef = def_flag;
953 gbInfoFrmPktList[packet_type & (~0x80)].FrmCntNum = def_fcnt;
954 gbInfoFrmPktList[packet_type & (~0x80)].enPktCtrl = def_process;
955 }
956 else
957 {
958 gbGeneralPktList[packet_type].EnableUserDef = def_flag;
959 gbGeneralPktList[packet_type].FrmCntNum = def_fcnt;
960 gbGeneralPktList[packet_type].enPktCtrl = def_process;
961 }
962 }
963
MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type,MS_U8 * data,MS_U8 length)964 MS_BOOL MHal_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length)
965 {
966 MS_BOOL bRet = TRUE;
967 MS_U8 i, j, *ptr;
968 ptr = data;
969
970 switch(packet_type)
971 {
972 case E_HDMITX_VS_INFOFRAME:
973 for (i=0; i < length; i++)
974 {
975 j = i>>1;
976
977 if ((REG_PKT_VS_1_27+j > REG_PKT_VS_14_34) || ((REG_PKT_VS_1_27+j == REG_PKT_VS_14_34) && (i % 2 == 1)))
978 {
979 //Packet over size, last VS packet PB register is REG_PKT_VS_14_34[7:0]
980 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
981 break;
982 }
983
984 if((i%2)==0)
985 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0x00FF, *(ptr+i));
986 else
987 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27+j, 0xFF00, (*(ptr+i))<<8);
988 }
989 break;
990 case E_HDMITX_SPD_INFOFRAME:
991 for(i=0;i<length;i++)
992 {
993 j = i>>1;
994
995 if((REG_PKT_SPD_1_15+j > REG_PKT_SPD_13_21) || ((REG_PKT_SPD_1_15+j == REG_PKT_SPD_13_21) && (i % 2 == 1)))
996 {
997 //Packet over size, last SPD packet PB register is REG_PKT_SPD_13_21[7:0]
998 DBG_HDMITX(printf("VS packet over size, length = %d \n", length));
999 break;
1000 }
1001
1002 if((i%2)==0)
1003 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0x00FF, *(ptr+i));
1004 else
1005 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+j, 0xFF00, (*(ptr+i))<<8);
1006 }
1007 break;
1008
1009 case E_HDMITX_AVI_INFOFRAME:
1010 for ( i = 0; i < length; i++ )
1011 {
1012 j = i >> 1;
1013
1014 if (((REG_PKT_AVI_1_09 + j) > REG_PKT_AVI_7_0F) || (((REG_PKT_AVI_1_09 + j) == REG_PKT_AVI_7_0F) && (i % 2 == 1)))
1015 {
1016 DBG_HDMITX(printf("AVI packet over size, length = %d \n", length));
1017 break;
1018 }
1019
1020 if ((i % 2) == 0)
1021 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0x00FF, *(ptr+i));
1022 else
1023 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + j, 0xFF00, *(ptr+i) << 8);
1024 }
1025 break;
1026
1027 //wilson@kano HDR packet
1028 case E_HDMITX_HDR_INFOFRAME:
1029 //first 3 bytes will follow spec, (1) type code (2) version (3) length, and reamins will be content
1030 length = (length > (HDMITX_HDR_INFO_PKT_LEN + 3)) ? (HDMITX_HDR_INFO_PKT_LEN + 3) : length;
1031 //fill length and version
1032 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F,(*(ptr+2) << 8) | *(ptr+1));
1033
1034 if (length >= 3)
1035 {
1036 for ( i = 0; i < (length-3); i++ )
1037 {
1038 j = i >> 1;
1039
1040 if ( ((REG_HDMI_2_CONFIG_10 + j) > REG_HDMI_2_CONFIG_1D) || (((REG_HDMI_2_CONFIG_10 + j) == REG_HDMI_2_CONFIG_1D) && (i % 2 == 1)) )
1041 {
1042 DBG_HDMITX(printf("HDR packet over size, length = %d \n", length));
1043 break;
1044 }
1045
1046 if ((i % 2) == 0)
1047 {
1048 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0x00FF, *(ptr+i+3));
1049 }
1050 else
1051 {
1052 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, (REG_HDMI_2_CONFIG_10 + j), 0xFF00, (*(ptr+i+3))<<8);
1053 }
1054 }
1055 }
1056 break;
1057
1058 case E_HDMITX_AUDIO_INFOFRAME:
1059 {
1060 //total length should be 192 bits *2 = 384 bits = 48 bytes;
1061
1062 length = (length < ((192>>3)<<1) ) ? length : ((192>>3)<<1);
1063
1064 for ( i = 0; i < length; i++ )
1065 {
1066 j = i >> 1;
1067
1068 if ((i % 2) == 0)
1069 {
1070 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0x00FF, *(ptr+i));
1071 }
1072 else
1073 {
1074 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A + j, 0xFF00, (*(ptr+i) << 8));
1075 }
1076 }
1077 }
1078 break;
1079
1080 default:
1081 i = 0;
1082 j = 0;
1083 bRet = FALSE;
1084 DBG_HDMITX(printf("Not implemented, packet type = %u\n", packet_type));
1085 break;
1086 }
1087
1088 return bRet;
1089 }
1090
1091 //------------------------------------------------------------------------------
1092 /// @brief This routine turn on/off HDMI Tx TMDS signal
1093 /// @param[in] bRB_Swap: R/B swap; bTMDS: TMDS flag
1094 /// @return None
1095 //------------------------------------------------------------------------------
MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap,MS_BOOL bTMDS)1096 void MHal_HDMITx_SetTMDSOnOff(MS_BOOL bRB_Swap, MS_BOOL bTMDS)
1097 {
1098 if(bRB_Swap) // R/B channel swap
1099 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, BIT13);
1100 else
1101 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, BIT13, 0);
1102
1103 //reg_atop_en_data_out[13..15]: Enable data channel data output
1104 if (bTMDS == TRUE)
1105 {
1106 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xF000);
1107 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0xE800);
1108 //TBD: turn off tmds clock
1109
1110 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0001); //flush audio fifo
1111 MsOS_DelayTask(10);
1112 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, 0x0000);
1113 }
1114 else
1115 {
1116 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0xFFFF);
1117 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xE800, 0x0000);
1118 //TBD: turn off tmds clock
1119 }
1120 }
1121
1122 //------------------------------------------------------------------------------
1123 /// @brief This routine return on/off status of HDMI Tx TMDS signal
1124 /// @return On/Off
1125 //------------------------------------------------------------------------------
MHal_HDMITx_GetTMDSStatus(void)1126 MS_U32 MHal_HDMITx_GetTMDSStatus(void)
1127 {
1128 MS_U16 usTMDSOutput = 0;
1129 MS_U16 usTMDSPD = 0;
1130 MS_U32 uiTMDSOn = 0;
1131
1132 usTMDSOutput = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E);
1133 usTMDSPD = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39);
1134
1135 if( ((usTMDSOutput&0xE800) == 0xE800) && ((usTMDSPD &0x0FFF) == 0x0000) )
1136 {
1137 uiTMDSOn = TRUE;
1138 }
1139 else
1140 {
1141 uiTMDSOn = FALSE;
1142 }
1143
1144 return uiTMDSOn;
1145 }
1146
1147 //------------------------------------------------------------------------------
1148 /// @brief This routine turn on/off HDMI Tx video output
1149 /// @param[in] bVideo: Video flag; bCSC: CSC flag, b709format = BT.709-5
1150 /// @return None
1151 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo,MS_BOOL bCSC,MS_BOOL b709format)1152 void MHal_HDMITx_SetVideoOnOff(MS_BOOL bVideo, MS_BOOL bCSC, MS_BOOL b709format)
1153 {
1154 if (bVideo == TRUE)
1155 {
1156 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0, 0x0000); // disable test pattern
1157 }
1158 else
1159 {
1160 MS_U8 i = 0x00;
1161
1162 DBG_HDMITX(printf("MDrv_HDMITx_SetVideoOnOff: csc flag= %d \n", bCSC));
1163
1164 // enable test pattern
1165 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3A, 0x0000);
1166 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3B, 0x0000);
1167 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3C, 0x03FF); // whole-blue
1168 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, BIT0|BIT1, BIT0|BIT1);
1169
1170 for ( i = 0; i < 6; i++ )
1171 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_3D + i, 0x0000);
1172 }
1173 }
1174
1175 //------------------------------------------------------------------------------
1176 /// @brief This routine sets video color formatt
1177 /// @param[in] bCSC: CSC flag, YUV422 12 bit, b709format = BT.709-5
1178 /// @return None
1179 //------------------------------------------------------------------------------
MHal_HDMITx_SetColorFormat(MS_BOOL bCSC,MS_BOOL bHdmi422b12,MS_BOOL b709format)1180 void MHal_HDMITx_SetColorFormat(MS_BOOL bCSC, MS_BOOL bHdmi422b12, MS_BOOL b709format)
1181 {
1182 if (bCSC) // YUV -> RGB
1183 {
1184 DBG_HDMITX(printf("YUV -> RGB \n"));
1185 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, BIT0); //bypass
1186 }
1187 else // bypass
1188 {
1189 DBG_HDMITX(printf("bypass YUV -> RGB \n"));
1190 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, BIT0, 0x00); //bypass
1191 }
1192
1193 // YUV422 12 bits output
1194 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, bHdmi422b12 ? BIT15 : 0x00);
1195 }
1196
1197 //------------------------------------------------------------------------------
1198 /// @brief This routine get CSC capability
1199 /// @param[in]
1200 /// @return False : not support R2Y. Ture : ok.
1201 //------------------------------------------------------------------------------
MHal_HDMITx_CSC_Support_R2Y(void * pDatatIn)1202 MS_BOOL MHal_HDMITx_CSC_Support_R2Y(void* pDatatIn)
1203 {
1204 pDatatIn = pDatatIn;
1205 return HDMITX_CSC_SUPPORT_R2Y;
1206 }
1207
1208 //------------------------------------------------------------------------------
1209 /// @brief This routine sets color domain and color range transform
1210 /// @param[in]
1211 /// @return False : not support this command. Ture : ok.
1212 //------------------------------------------------------------------------------
MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor,MsHDMITX_VIDEO_COLOR_FORMAT outcolor,MsHDMITX_YCC_QUANT_RANGE inrange,MsHDMITX_YCC_QUANT_RANGE outrange)1213 MS_BOOL MHal_HDMITx_ColorandRange_Transform(MsHDMITX_VIDEO_COLOR_FORMAT incolor, MsHDMITX_VIDEO_COLOR_FORMAT outcolor, MsHDMITX_YCC_QUANT_RANGE inrange, MsHDMITX_YCC_QUANT_RANGE outrange)
1214 {
1215 MS_BOOL bReturn = FALSE;
1216
1217 if( (incolor == outcolor) && (inrange == outrange) )
1218 {
1219 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1220 bReturn = TRUE;
1221 DBG_HDMITX(printf("Input equals output \n"));
1222 }
1223 else if(incolor == E_HDMITX_VIDEO_COLOR_RGB444)
1224 {
1225 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LR
1226 {
1227 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1228 { //LR -> LY
1229 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1230 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1231 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1232 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1233 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1234 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1235 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1236 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1237 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1238 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1239 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1240 bReturn = TRUE;
1241 DBG_HDMITX(printf("LR->LY! \n"));
1242 }
1243 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1244 { //LR -> FY
1245 #if 1
1246 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1247 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x020C);
1248 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E24);
1249 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD0);
1250 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1251 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1252 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1253 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F88);
1254 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E6C);
1255 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x020C);
1256 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1257
1258 DBG_HDMITX(printf("Not Support This! Replace by LR -> LY\n"));
1259 DBG_HDMITX(printf("LR->FY! \n"));
1260 bReturn = FALSE;
1261 #else
1262 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0CB0);
1263 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0256);
1264 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1DE1);
1265 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FC9);
1266 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00FE);
1267 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0357);
1268 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0056);
1269 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F77);
1270 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E33);
1271 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0256);
1272 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1273 bReturn = TRUE;
1274 DBG_HDMITX(printf("LR->FY! \n"));
1275 #endif
1276 }
1277 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_FULL))
1278 { //LR -> FR
1279 #if 1
1280 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1281 DBG_HDMITX(printf("Not Support This! \n"));
1282 DBG_HDMITX(printf("LR->FR! \n"));
1283 bReturn = FALSE;
1284 #else
1285 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x0C10);
1286 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1287 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1288 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1289 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1290 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1291 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1292 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1293 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1294 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1295 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1296 bReturn = TRUE;
1297 DBG_HDMITX(printf("LR->FR! \n"));
1298 #endif
1299 }
1300 else
1301 {
1302 DBG_HDMITX(printf("LR->LR! \n"));
1303 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1304 DBG_HDMITX(printf("In/Out Same Color! \n"));
1305 bReturn = TRUE;
1306 }
1307
1308 }
1309 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FR
1310 {
1311 if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1312 { //FR -> LY
1313 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00E0);
1314 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x01C0);
1315 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E69);
1316 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD7);
1317 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00BA);
1318 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0273);
1319 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x003F);
1320 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F99);
1321 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1EA6);
1322 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x01C0);
1323 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1324 bReturn = TRUE;
1325 DBG_HDMITX(printf("FR->LY! \n"));
1326 }
1327 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1328 { //FR -> FY
1329 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00A0);
1330 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0200);
1331 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x1E2F);
1332 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x1FD1);
1333 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x00DA);
1334 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x02DC);
1335 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x004A);
1336 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x1F8B);
1337 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x1E75);
1338 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0200);
1339 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1340 bReturn = TRUE;
1341 DBG_HDMITX(printf("FR->FY! \n"));
1342 }
1343 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444)&& (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1344 { //FR -> LR
1345 #if 1
1346 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1347 DBG_HDMITX(printf("Not Support This! \n"));
1348 DBG_HDMITX(printf("FR->LR! \n"));
1349 bReturn = FALSE;
1350 #else
1351 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x5040);
1352 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0381);
1353 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1354 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1355 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1356 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1357 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1358 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1359 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1360 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0381);
1361 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1362 bReturn = TRUE;
1363 DBG_HDMITX(printf("FR->LR! \n"));
1364 #endif
1365 }
1366 else
1367 {
1368 DBG_HDMITX(printf("FR->FR! \n"));
1369 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1370 DBG_HDMITX(printf("In/Out Same Color! \n"));
1371 bReturn = TRUE;
1372 }
1373 }
1374 else
1375 {
1376 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1377 DBG_HDMITX(printf("Not Support This! \n"));
1378 }
1379 }
1380 else if((incolor == E_HDMITX_VIDEO_COLOR_YUV444) || (incolor == E_HDMITX_VIDEO_COLOR_YUV422))
1381 {
1382 if(inrange == E_HDMITX_YCC_QUANT_LIMIT)//LY
1383 {
1384 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1385 {//LY->FR
1386 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x001A);
1387 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0731);
1388 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x04AC);
1389 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1390 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1DDD);
1391 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1392 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F25);
1393 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1394 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x04AC);
1395 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0879);
1396 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1397 bReturn = TRUE;
1398 DBG_HDMITX(printf("LY->FR! \n"));
1399 }
1400 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1401 {//LY->LR
1402 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1403 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0629);
1404 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1405 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1406 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E2B);
1407 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1408 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F44);
1409 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1410 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1411 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0742);
1412 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1413 bReturn = TRUE;
1414 DBG_HDMITX(printf("May over range! \n"));
1415 DBG_HDMITX(printf("LY->LR! \n"));
1416 }
1417 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1418 {//LY->FY
1419 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00BA);
1420 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0491);
1421 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1422 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1423 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1424 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1425 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1426 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1427 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1428 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x0491);
1429 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1430 bReturn = TRUE;
1431 DBG_HDMITX(printf("LY->FY! \n"));
1432 }
1433 else
1434 {
1435 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1436 DBG_HDMITX(printf("In/Out Same Color! \n"));
1437 DBG_HDMITX(printf("LY->LY! \n"));
1438 bReturn = TRUE;
1439 }
1440
1441 }
1442 else if(inrange == E_HDMITX_YCC_QUANT_FULL)//FY
1443 {
1444 if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_FULL))
1445 {//FY->FR
1446 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1447 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1448 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1449 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1450 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1451 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1452 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1453 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1454 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1455 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1456 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1457 bReturn = TRUE;
1458 DBG_HDMITX(printf("FY->FR! \n"));
1459 }
1460 else if((outcolor == E_HDMITX_VIDEO_COLOR_RGB444) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1461 {//FY->LR
1462 #if 1
1463 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x000A);
1464 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x064D);
1465 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0400);
1466 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1467 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E21);
1468 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x0400);
1469 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F40);
1470 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1471 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0400);
1472 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x076C);
1473 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1474
1475 DBG_HDMITX(printf("Not Support This! Replace by FY -> FR\n"));
1476 DBG_HDMITX(printf("FY->LR! \n"));
1477 bReturn = FALSE;
1478 #else
1479 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x504A);
1480 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x0565);
1481 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x036D);
1482 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1483 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x1E66);
1484 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x036D);
1485 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x1F5C);
1486 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1487 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x036D);
1488 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x065B);
1489 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1490 bReturn = TRUE;
1491 DBG_HDMITX(printf("FY->LR! \n"));
1492 #endif
1493 }
1494 else if(((outcolor == E_HDMITX_VIDEO_COLOR_YUV444)||(outcolor == E_HDMITX_VIDEO_COLOR_YUV422)) && (outrange == E_HDMITX_YCC_QUANT_LIMIT))
1495 {//FY->LY
1496 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x7FFF, 0x00EA);
1497 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_21, 0x1FFF, 0x04AC);
1498 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_22, 0x1FFF, 0x0000);
1499 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_23, 0x1FFF, 0x0000);
1500 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_24, 0x1FFF, 0x0000);
1501 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_25, 0x1FFF, 0x04AC);
1502 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_26, 0x1FFF, 0x0000);
1503 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_27, 0x1FFF, 0x0000);
1504 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_28, 0x1FFF, 0x0000);
1505 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_29, 0x1FFF, 0x04AC);
1506 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0001);
1507 bReturn = TRUE;
1508 DBG_HDMITX(printf("FY->LY! \n"));
1509 }
1510 else
1511 {
1512 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1513 DBG_HDMITX(printf("In/Out Same Color! \n"));
1514 DBG_HDMITX(printf("FY->FY! \n"));
1515 bReturn = TRUE;
1516 }
1517 }
1518 else
1519 {
1520 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1521 DBG_HDMITX(printf("Not Support This! \n"));
1522 }
1523 }
1524 else
1525 {
1526 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_20, 0x0001, 0x0000);
1527 DBG_HDMITX(printf("Not Support This! \n"));
1528 }
1529
1530 //if((bReturn == TRUE) && (outcolor == E_HDMITX_VIDEO_COLOR_YUV422))
1531 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT15, (outcolor == E_HDMITX_VIDEO_COLOR_YUV422) ? BIT15 : 0);
1532
1533 return bReturn;
1534 }
1535
1536 //------------------------------------------------------------------------------
1537 /// @brief This routine will set or stop all HDMI packet generation
1538 /// @param[in] bflag True: Enable packet gen, False : Disable packet gen
1539 /// @return None
1540 //------------------------------------------------------------------------------
MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)1541 void MHal_HDMITx_EnablePacketGen(MS_BOOL bflag)
1542 {
1543 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT2, bflag ? BIT2:0);
1544 }
1545
1546 //------------------------------------------------------------------------------
1547 /// @brief This routine sets HDMI/DVI mode
1548 /// @param[in] bflag
1549 /// @return None
1550 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDMImode(MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)1551 void MHal_HDMITx_SetHDMImode(MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val)
1552 {
1553 MS_U8 ucRegVal = 0x00;
1554
1555 DBG_HDMITX(printf("[%s][%d]HDMI mode = %d, Color Depth = %d \n", __FUNCTION__, __LINE__, bflag, bflag));
1556
1557 if (bflag) // HDMI mode
1558 {
1559 switch(cd_val)
1560 {
1561 case E_HDMITX_VIDEO_CD_NoID:
1562 case E_HDMITX_VIDEO_CD_24Bits:
1563 default:
1564 ucRegVal = 0x00;
1565 break;
1566
1567 case E_HDMITX_VIDEO_CD_30Bits:
1568 ucRegVal = 0x40;
1569 break;
1570
1571 case E_HDMITX_VIDEO_CD_36Bits:
1572 ucRegVal = 0x80;
1573 break;
1574
1575 case E_HDMITX_VIDEO_CD_48Bits:
1576 ucRegVal = 0xC0;
1577 break;
1578 }
1579
1580 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, ucRegVal|BIT2); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1581 }
1582 else // DVI
1583 {
1584 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00FF, BIT0); // [7:6]: DC_mode, [2]: packet enable, [0]: HDMI/DVI
1585 }
1586 }
1587
1588
1589 //------------------------------------------------------------------------------
1590 /// @brief This routine sets audio on/off
1591 /// @param[in] bflag
1592 /// @return None
1593 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)1594 void MHal_HDMITx_SetAudioOnOff(MS_BOOL bflag)
1595 {
1596 MS_U8 num;
1597
1598 if(bflag) // audio on
1599 {
1600 num = sizeof(HDMITxAudioOnTbl)/sizeof(MSTHDMITX_REG_TYPE);
1601 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOnTbl, num);
1602 }
1603 else // audio off
1604 {
1605 num = sizeof(HDMITxAudioOffTbl)/sizeof(MSTHDMITX_REG_TYPE);
1606 MHal_HDMITx_RegsTbl_Write(HDMITxAudioOffTbl, num);
1607 }
1608 }
1609
1610 //------------------------------------------------------------------------------
1611 /// @brief This routine sets audio sampling freq.
1612 /// @return None
1613 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,MsHDMITX_AUDIO_CHANNEL_COUNT achidx,MsHDMITX_AUDIO_CODING_TYPE actidx)1614 void MHal_HDMITx_SetAudioFrequency(MsHDMITX_AUDIO_FREQUENCY afidx,
1615 MsHDMITX_AUDIO_CHANNEL_COUNT achidx, MsHDMITX_AUDIO_CODING_TYPE actidx
1616 )
1617 {
1618 // HDMI audio channel setting
1619 if(achidx == E_HDMITX_AUDIO_CH_2) // 2 channels
1620 {
1621 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4|BIT5|BIT6, BIT5|BIT6); //[6:5]: audio FIFO depth ch1234, [4]=1'b0: 2 channels
1622 }
1623 else // 8 channels
1624 {
1625 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT4, BIT4); //[4]=1'b1: 8 channels
1626 }
1627
1628 // Audio channel status
1629 #if 1 //NOTE:: kano: move channel status from address 0x00 to address 0x0A
1630 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1631 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[afidx].CH_Status3 << 8) | (achidx << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
1632 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
1633 #else
1634 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_00, ((actidx == E_HDMITX_AUDIO_PCM) ? 0 : BIT1) ); // [1]: PCM / non-PCM
1635 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_01, 0);
1636 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_02, (achidx<<4)); // [7:4]: audio channel count
1637 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS3_03, TxAudioFreqTbl[afidx].CH_Status3); // [3:0]: audio sampling frequncy
1638 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS4_04, 0);
1639 #endif
1640 // ACR N code
1641 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_2_06, 0x0F00, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000));
1642 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_3_07, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1643
1644 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_61, 0x000F, (TxAudioFreqTbl[afidx].NcodeValue & 0x0F0000) >> 8);
1645 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_N_PKT_60, 0xFFFF, (TxAudioFreqTbl[afidx].NcodeValue & 0x00FFFF));
1646 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x0100, 0x0100); //enable cts * 2
1647 }
1648
1649 //------------------------------------------------------------------------------
1650 /// @brief This routine sets audio source format.
1651 /// @return None
1652 //------------------------------------------------------------------------------
MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)1653 void MHal_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt)
1654 {
1655 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT9|BIT8, fmt << 8);
1656 }
1657
1658 //------------------------------------------------------------------------------
1659 /// @brief This routine Get Audio CTS value
1660 /// @return CTS
1661 //------------------------------------------------------------------------------
MHal_HDMITx_GetAudioCTS(void)1662 MS_U32 MHal_HDMITx_GetAudioCTS(void)
1663 {
1664 MS_U32 ret;
1665
1666 ret = ((MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_2_06) & 0x000F) << 16) | MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ACR_1_05);
1667 return ret;
1668 }
1669
1670 //------------------------------------------------------------------------------
1671 /// @brief This routine Mute Audio FIFO
1672 /// @param[in] bflag: True: mute audio, False: unmute audio
1673 /// @return None
1674 //------------------------------------------------------------------------------
MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)1675 void MHal_HDMITx_MuteAudioFIFO(MS_BOOL bflag)
1676 {
1677 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, 0x0001, (MS_U16)bflag);
1678 }
1679
1680 //------------------------------------------------------------------------------
1681 /// @brief This routine sets HDMI Tx HDCP encryption On/Off
1682 /// @return None
1683 //------------------------------------------------------------------------------
MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag,MS_BOOL hdmi_flag)1684 void MHal_HDMITx_SetHDCPOnOff(MS_BOOL hdcp_flag, MS_BOOL hdmi_flag)
1685 {
1686 if(hdcp_flag) // HDCP on
1687 {
1688 if (hdmi_flag) // HDMI EESS
1689 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0400);
1690 else // DVI OESS
1691 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_MODE_01, 0x0C00, 0x0000);
1692 // HDCP encryption
1693 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0008);
1694 }
1695 else // HDCP off
1696 MHal_HDMITx_Mask_Write(HDMITX_HDCP_REG_BASE, REG_HDCP_TX_COMMAND_02, 0x0008, 0x0000);
1697 }
1698
1699 //------------------------------------------------------------------------------
1700 /// @brief This routine calculate check sum of infoframes.
1701 /// @param[in] packet_type packet type
1702 /// @return checksum
1703 //------------------------------------------------------------------------------
MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)1704 MS_U8 MHal_HDMITx_InfoFrameCheckSum(MsHDMITX_PACKET_TYPE packet_type)
1705 {
1706 MS_U8 ucSumVal = 0;
1707 MS_U8 i = 0;
1708 MS_U8 j = 0;
1709 MS_U16 wRegVal = 0;
1710
1711 switch (packet_type)
1712 {
1713 case E_HDMITX_VS_INFOFRAME:
1714 ucSumVal += (E_HDMITX_VS_INFOFRAME + HDMITX_VS_INFO_PKT_VER + HDMITX_VS_INFO_PKT_LEN);
1715
1716 for ( i = 0; i < (HDMITX_VS_INFO_PKT_LEN + 1) >> 1; i++ )
1717 {
1718 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_VS_1_27 + i);
1719
1720 for ( j = 0; j < 2; j++ )
1721 {
1722 if ((i == 13) && (j==1))
1723 {
1724 ucSumVal += 0x00;
1725 }
1726 else
1727 {
1728 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1729 }
1730 }
1731 }
1732 break;
1733
1734 case E_HDMITX_AVI_INFOFRAME:
1735 ucSumVal += (E_HDMITX_AVI_INFOFRAME + HDMITX_AVI_INFO_PKT_VER + HDMITX_AVI_INFO_PKT_LEN);
1736
1737 for ( i = 0; i < ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1); i++ )
1738 {
1739 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AVI_1_09 + i);
1740
1741 for ( j = 0; j < 2; j++ )
1742 {
1743 if ((i == 1) && (j == 0)) // SC[1:0]
1744 {
1745 ucSumVal += (HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)(wRegVal & 0x00FF) & 0x03);
1746 }
1747 else if ((i == 1) && (j == 1)) // VIC[6:0]
1748 {
1749 ucSumVal += ((HDMITX_AVI_INFO_PKT_VER >= 0x02U) ? ((MS_U8)((wRegVal & 0xFF00) >> 8) & 0x7F) : 0x00);
1750 }
1751 else if ((i == 2) && (j == 0)) // PR[3:0]
1752 {
1753 ucSumVal += (MS_U8)(wRegVal & 0x00FF); //bit 4:7 used for HDR; //ucSumVal += ((MS_U8)(wRegVal & 0x00FF) & 0x0F);
1754 }
1755 #if 0 //not resevered byte anymore; should be counted
1756 else if ((i == 2) && (j == 1)) // reserved
1757 {
1758 ucSumVal += 0x00;
1759 }
1760 #endif
1761 else if (( i == ((HDMITX_AVI_INFO_PKT_LEN + 1) >> 1) - 1)&&(j == 1))
1762 {
1763 ucSumVal += 0x00;
1764 }
1765 else
1766 {
1767 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1768 }
1769 }
1770 }
1771 break;
1772
1773 case E_HDMITX_SPD_INFOFRAME:
1774 ucSumVal += (E_HDMITX_SPD_INFOFRAME + HDMITX_SPD_INFO_PKT_VER + HDMITX_SPD_INFO_PKT_LEN);
1775
1776 for ( i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN+ 1) >> 1); i++ )
1777 {
1778 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_SPD_1_15 + i);
1779
1780 for ( j = 0; j < 2; j++ )
1781 {
1782 if ((i == 12) && (j == 0))
1783 {
1784 ucSumVal += (MS_U8)(wRegVal & 0x00FF);
1785 }
1786 else if ((i == 12) && (j == 1)) //reserved
1787 {
1788 ucSumVal += 0x00;
1789 }
1790 else
1791 {
1792 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1793 }
1794 }
1795 }
1796 break;
1797
1798 case E_HDMITX_AUDIO_INFOFRAME:
1799 ucSumVal += (E_HDMITX_AUDIO_INFOFRAME + HDMITX_AUD_INFO_PKT_VER + HDMITX_AUD_INFO_PKT_LEN);
1800
1801 for ( i = 0; i < (((HDMITX_AUD_INFO_PKT_LEN >> 1) + 1) >> 1); i++ )
1802 {
1803 wRegVal = MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_AUD_1_11 + i);
1804
1805 if (i == 1)
1806 {
1807 for ( j = 0; j < 2; j++ )
1808 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1809 }
1810
1811 if (i == 0)
1812 {
1813 for ( j = 0; j < 2; j++ )
1814 ucSumVal += ( (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xF7) : (((MS_U8)(wRegVal & 0xFF00) >> 8) & 0x1F));
1815 }
1816
1817 if (i == 2)
1818 {
1819 for ( j = 0; j < 2; j++ )
1820 ucSumVal += ((j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF) & 0xFB) : 0x00);
1821 }
1822 }
1823 break;
1824
1825 case E_HDMITX_MPEG_INFOFRAME:
1826 //TBD
1827 break;
1828
1829 case E_HDMITX_HDR_INFOFRAME:
1830 {
1831 MS_U8 u8PktLen = 0x00;
1832
1833 u8PktLen = (MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0xFF00) >> 8;
1834 ucSumVal += (E_HDMITX_HDR_INFOFRAME + (MS_U8)(MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1F) & 0x00FF) + u8PktLen);
1835
1836 for ( i = 0; i < ((u8PktLen + 1) >> 1); i++ )
1837 {
1838 wRegVal = MHal_HDMITx_Read(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_10 + i);
1839
1840 for ( j = 0; j < 2; j++ )
1841 {
1842 if ((i == 0x0D) && (j % 2 == 0x00))
1843 ucSumVal += (j % 2 == 0) ? (MS_U8)(wRegVal & 0x00FF) : 0x00;
1844 else
1845 ucSumVal += (j % 2 == 0) ? ((MS_U8)(wRegVal & 0x00FF)) : ((MS_U8)((wRegVal & 0xFF00) >> 8));
1846 }
1847 }
1848 }
1849 break;
1850
1851 default:
1852 break;
1853 }
1854
1855 return (MS_U8)((~ucSumVal) + 0x01);
1856
1857 }
1858
1859 //------------------------------------------------------------------------------
1860 /// @brief This routine sets video output mode (color/repetition/regen)
1861 /// @param[in] idx: gHDMITxInfo.output_video_timing
1862 /// @return None
1863 //------------------------------------------------------------------------------
MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx,MS_BOOL bflag,MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val,MsHDMITX_ANALOG_TUNING * pInfo,MS_U8 ubSSCEn)1864 void MHal_HDMITx_SetVideoOutputMode(MsHDMITX_VIDEO_TIMING idx, MS_BOOL bflag, MsHDMITX_VIDEO_COLORDEPTH_VAL cd_val, MsHDMITX_ANALOG_TUNING *pInfo, MS_U8 ubSSCEn)
1865 {
1866 //MS_U16 reg_value=0;
1867 MS_U8 ucCDIdx = 0;
1868 MS_U16 wHfront = 0;
1869 MS_U16 wVfront = 0;
1870 MS_BOOL bIsHDMI20 = FALSE;
1871 MS_BOOL bIs420Fmt = FALSE;
1872 MS_BOOL bIsRPMode = FALSE;
1873 MS_U32 uiTMDSCLK = 0;
1874
1875 //wilson@kano:TBD
1876 printf("video idx = 0x%X, color depth = 0x%X\r\n", idx, cd_val);
1877 // Deep color FIFO reset
1878 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, BIT10);
1879 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, BIT10, 0);
1880 MsOS_DelayTask(10);
1881
1882 // Interlace mode
1883 if (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE)
1884 {
1885 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x005F);
1886 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x4000); //reg_interlace_mode_sel
1887 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2
1888 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0004); // PG interlace enable
1889 }
1890 else
1891 {
1892 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_00, 0x017F, 0x004E);
1893 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, 0x4000, 0x0000); //reg_interlace_mode_sel
1894 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0000); //video clock div 2
1895 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0004, 0x0000); // PG interlace disable
1896 }
1897
1898 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt != E_HDMITX_VIDEO_COLOR_YUV420) &&
1899 (
1900 (idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || \
1901 (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz) || \
1902 (
1903 (
1904 (idx == E_HDMITX_RES_1280x1470p_60Hz) || \
1905 (idx == E_HDMITX_RES_3840x2160p_24Hz) || \
1906 (idx == E_HDMITX_RES_3840x2160p_25Hz) || \
1907 (idx == E_HDMITX_RES_3840x2160p_30Hz) || \
1908 (idx == E_HDMITX_RES_4096x2160p_24Hz) || \
1909 (idx == E_HDMITX_RES_4096x2160p_25Hz) || \
1910 (idx == E_HDMITX_RES_4096x2160p_30Hz)
1911
1912 ) &&
1913 (
1914 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID)
1915 )
1916 )
1917 ))
1918 bIsHDMI20 = TRUE;
1919
1920 if ((gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420) &&
1921 ((idx == E_HDMITX_RES_3840x2160p_60Hz) || (idx == E_HDMITX_RES_3840x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_50Hz) || (idx == E_HDMITX_RES_4096x2160p_60Hz)) &&
1922 (cd_val != E_HDMITX_VIDEO_CD_24Bits) && (cd_val != E_HDMITX_VIDEO_CD_NoID))
1923 bIsHDMI20 = TRUE;
1924
1925 if (g_bSupportSCDC == TRUE)
1926 {
1927 //for 2.0
1928 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, bIsHDMI20 ? 0x0100 : 0x00);
1929 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, bIsHDMI20 ? BIT0 : 0x00);
1930
1931 //scdc
1932 if (bIsHDMI20 == TRUE)
1933 Mhal_HDMITx_SCDCSetTmdsConfig(TRUE, TRUE);
1934 else
1935 Mhal_HDMITx_SCDCSetTmdsConfig(FALSE, FALSE);
1936 }
1937 else
1938 {
1939 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0100, 0x00);
1940 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_52, BIT0, 0x00);
1941 }
1942
1943 uiTMDSCLK = MHal_HDMITx_GetPixelClk_ByTiming(idx, gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt, cd_val);
1944 uiTMDSCLK /= 1000;
1945
1946 if (gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME &(~0x80)].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_YUV420)
1947 {
1948 switch (idx)
1949 {
1950 case E_HDMITX_RES_3840x2160p_50Hz:
1951 idx = E_HDMITX_RES_3840x2160p_25Hz;
1952 break;
1953
1954 case E_HDMITX_RES_3840x2160p_60Hz:
1955 idx = E_HDMITX_RES_3840x2160p_30Hz;
1956 break;
1957
1958 case E_HDMITX_RES_4096x2160p_50Hz:
1959 idx = E_HDMITX_RES_4096x2160p_25Hz;
1960 break;
1961
1962 case E_HDMITX_RES_4096x2160p_60Hz:
1963 idx = E_HDMITX_RES_4096x2160p_30Hz;
1964 break;
1965
1966 default:
1967 printf("[HDMITX] Invalid Combination of Color Format & Video Timing, Keep Origional Timing Setting!!\r\n");
1968 break;
1969 }
1970
1971 bIs420Fmt = TRUE;
1972 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_1B, 0x0040, 0x0040); //video clock div 2 for 420
1973 }
1974
1975 if((idx == E_HDMITX_RES_720x480i) || (idx == E_HDMITX_RES_720x576i))
1976 {
1977 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x008B);
1978
1979 bIsRPMode = TRUE;
1980 }
1981 else
1982 {
1983 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_39, 0x00FF, 0x00AC);
1984
1985 bIsRPMode = FALSE;
1986 }
1987
1988 //enable H, VSync regen
1989 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x8001, 0x8001);
1990 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0002, HDMITxVideoModeTbl[idx].h_polarity ? 0x0002 : 0x0000);
1991 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_01, 0x0004, HDMITxVideoModeTbl[idx].v_polarity ? 0x0004 : 0x0000);
1992
1993 ucCDIdx = (cd_val == 0)? 0x00 : (cd_val - 4);
1994
1995 //deep color setting
1996 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_HDMI_CONFIG1_00, 0x00C0, ucCDIdx << 6);
1997
1998 //HDMITx phy clock
1999 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0xCC0C, 0x0000);
2000
2001 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_15, 0x7000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 12);
2002
2003 //sythesizer setting
2004 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, (MS_U16)(HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x0000FFFF));
2005 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x00FF, (MS_U16)((HDMITxVideoAtopSetting[ucCDIdx][idx].SynthSSCSet & 0x00FF0000) >> 16));
2006
2007 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1003, 0x0000);
2008 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_26, 0x0100, 0x0000);
2009
2010 //atop
2011 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_38, 0x0003, HDMITxVideoAtopSetting[ucCDIdx][idx].MUX_DIVSEL_POST);
2012 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0xC000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_POST << 14);
2013 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3C, 0x3000, HDMITxVideoAtopSetting[ucCDIdx][idx].TXPLL_DIVSEL_PIXEL << 12);
2014
2015 #if 0
2016 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
2017 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012 << 8);
2018 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_PREDRV_MAIN_L012);
2019 #else //RD suggestion
2020 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_34, 0x3F00, 0x0000);
2021 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x3F00, 0x0000);
2022 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_35, 0x003F, 0x0000);
2023 #endif
2024
2025 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_30, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
2026 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x3F00, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012 << 8);
2027 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_31, 0x003F, HDMITxVideoAtopSetting[ucCDIdx][idx].ICTRL_DRV_MAIN_L012);
2028
2029 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x000F, HDMITxVideoAtopSetting[ucCDIdx][idx].PD_RT);
2030
2031
2032 // Timing regeneration
2033 MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_17, BIT10|BIT13, 0x0000/*BIT10|BIT13*/); // 0: delay from DE end; 1: delay from end of h, v sync
2034
2035 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_02, HDMITxVideoModeTbl[idx].vs_width);
2036 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_05, HDMITxVideoModeTbl[idx].vs_delayline);
2037 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_06, HDMITxVideoModeTbl[idx].vs_delaypixel);
2038 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_07, HDMITxVideoModeTbl[idx].hs_width >> (bIs420Fmt ? 0x01 : 0x00));
2039 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_0A, HDMITxVideoModeTbl[idx].hs_delay >> (bIs420Fmt ? 0x01 : 0x00));
2040
2041 //for PG
2042 wHfront = HDMITxVideoModeTbl[idx].hs_delay;
2043 wVfront = HDMITxVideoModeTbl[idx].vs_delayline;
2044
2045 //MHal_HDMITx_Mask_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_30, 0x0003, 0x0003);
2046 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_31, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hde_width/4 - 1) : (HDMITxVideoModeTbl[idx].hde_width/2 - 1));
2047 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_32, (bIs420Fmt||bIsRPMode) ?
2048 ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/4 - 1) : ((HDMITxVideoModeTbl[idx].htotal - HDMITxVideoModeTbl[idx].hde_width)/2 - 1));
2049 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_33, (bIs420Fmt||bIsRPMode) ? (wHfront/4 - 1) : (wHfront/2 - 1));
2050 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_34, (bIs420Fmt||bIsRPMode) ? (HDMITxVideoModeTbl[idx].hs_width/4 - 1) : (HDMITxVideoModeTbl[idx].hs_width/2 - 1));
2051
2052 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_35, HDMITxVideoModeTbl[idx].vde_width - 1);
2053 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_36, (HDMITxVideoModeTbl[idx].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) ?
2054 ((HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width)/2 - 1) : (HDMITxVideoModeTbl[idx].vtotal - HDMITxVideoModeTbl[idx].vde_width - 1));
2055 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_37, wVfront - 1);
2056 MHal_HDMITx_Write(HDMITX_VIDEO_REG_BASE, REG_VE_CONFIG_38, HDMITxVideoModeTbl[idx].vs_width - 1);
2057
2058 MHal_HDMITx_EnableSSC(ubSSCEn, uiTMDSCLK);
2059
2060 // fifo reset
2061 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0x0008);
2062 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_0F, 0x0008, 0);
2063 }
2064
2065 //------------------------------------------------------------------------------
2066 /// @brief This routine will power on or off HDMITx clock (power saving)
2067 /// @param[in] bEnable: TRUE/FALSE
2068 /// @return None
2069 //------------------------------------------------------------------------------
MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)2070 void MHal_HDMITx_Power_OnOff(MS_BOOL bEnable)
2071 {
2072 if (bEnable)
2073 {
2074 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, 0);
2075 }
2076 else
2077 {
2078 MHal_HDMITx_Mask_Write(CLKGEN1_REG_BASE, REG_CKG_HDMITx_CLK_28, BIT0, BIT0);
2079 }
2080 }
2081
2082
MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq,MS_BOOL bflag)2083 MS_BOOL MHal_HDMITx_RxBypass_Mode(MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag)
2084 {
2085 //wilson@kano:TBD
2086 #if 0
2087 return FALSE;
2088 #else
2089 printf("[HDMITx] Bypass Mode = 0x%d\r\n", bflag);
2090 if (bflag == TRUE)
2091 {
2092 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, BIT0); //reg_atop_en_clko_vcodiv8_syn
2093
2094 //Note: change frequency tolerance if need
2095 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4C, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2096 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4B, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2097 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_4A, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2098 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2099 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_09, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2100 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_22, 0xE000, 0xA000); //[13..15] reg_hdmi_clk_thr1 tolerance
2101 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY0_CONFIG_49, 0x1FFF, 0x0C6A); //change 250Mhz -> 297Mhz
2102
2103 //Enable Fifo and select input source
2104 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1919); //selct clock from Rx;
2105
2106 #if 0
2107 if (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7A) & 0x00C0) //for HDMI 2.0 timing bypass mode
2108 {
2109 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, BIT0); //tmds clock div 2;
2110 }
2111 #endif
2112
2113 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_16, 0x000E, 0x0004); //[1:0]: Lane 0 to fifo; [2]: enable
2114 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_17, 0x000E, 0x0005); //[1:0]: Lane 1 to fifo; [2]: enable
2115 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_18, 0x000E, 0x0006); //[1:0]: Lane 2 to fifo; [2]: enable
2116 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_19, 0x000E, 0x0007); //[1:0]: Lane 3 to fifo; [2]: enable
2117
2118 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x1000, 0x1000); //bit repetition HW mode;
2119
2120 //synthesizer setting //TBD
2121 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x0001, 0x0001);
2122 //ssc_set = 0x140000
2123 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02, 0x0000); //ssc_set [15..0]
2124 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03, 0x00FF, 0x0014);//ssc_set [7..0]
2125
2126 #if 0 //with SSC clock
2127 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, ssc_step);
2128 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3000, ssc_span);
2129 #else //without SSC clock
2130 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_05, 0xFFF0, 0x0000);
2131 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_06, 0x3FFF, 0x0000);
2132 #endif
2133
2134 //ATOP setting
2135 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_2E, 0xEA00, 0xEA00); //[9]:en_clk_pixel;[11]:en_clk_tmds;[13..15]:en_data_out
2136 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_39, 0xFFFF, 0x0000); //[11..0]: disable power down;[15:12]:pre-emphasis
2137 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_3A, 0x007F, 0x000F); //[3:0]:rterm turn off;[6:4]:disable power down
2138 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x2001); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2139 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0200); //[9] hdmi20 hw config mode;
2140 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_7E, 0x0200, 0x0200); //[9]: freq range tolerance up direction;
2141 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_60, 0x0001, 0x0001); //[0]: freq range reset follow rx big change;
2142 }
2143 else
2144 {
2145 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY1_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2146 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2147 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2148 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2149 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2150 }
2151
2152 return TRUE;
2153
2154 #endif
2155 }
2156
2157
2158 /// @brief This routine will disable TMDS clock, data, and DDC... bypass mode
2159 /// @return None
2160 //------------------------------------------------------------------------------
MHal_HDMITx_Disable_RxBypass(void)2161 MS_BOOL MHal_HDMITx_Disable_RxBypass(void)
2162 {
2163 #if 0
2164 return FALSE;
2165 #else
2166 MHal_HDMITx_Mask_Write(HDMIRX_COMBOPHY0_REG_BASE, REG_COMBOPHY1_CONFIG_3C, BIT0, 0x0000);
2167 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_10, 0x1101); //selct clock from Rx;
2168 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_11, BIT0, 0x0000); //tmds clock div 2;
2169 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_79, 0x2001, 0x0000); //[0]:turn on HW mode; [13]: Rx to tmds bypass
2170 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_46, 0x0200, 0x0000); //[9] hdmi20 hw config mode;
2171
2172 return TRUE;
2173 #endif
2174 }
2175
2176
2177 //------------------------------------------------------------------------------
2178 /// @brief This routine will set GPIO pin for HPD
2179 /// @param[in] u8pin: GPIO0 ~ 12
2180 /// @return None
2181 //------------------------------------------------------------------------------
MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)2182 void MHal_HDMITx_SetHPDGpioPin(MS_U8 u8pin)
2183 {
2184 printf("_gHPDGpioPin = 0x%X\r\n", u8pin);
2185 _gHPDGpioPin = u8pin;
2186 }
2187
2188 //------------------------------------------------------------------------------
2189 /// @brief This routine return CHIP capability of DVI mode
2190 /// @return TRUE, FALSE
2191 //------------------------------------------------------------------------------
MHal_HDMITx_IsSupportDVIMode(void)2192 MS_BOOL MHal_HDMITx_IsSupportDVIMode(void)
2193 {
2194 return TRUE;
2195 }
2196
2197 // ************* For customer NDS **************//
2198
MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process,MsHDMITX_AVI_CONTENT_TYPE content_type,MS_U16 * data)2199 void MHal_HDMITx_Set_AVI_InfoFrame(MsHDMITX_PACKET_PROCESS packet_process, MsHDMITX_AVI_CONTENT_TYPE content_type, MS_U16 *data)
2200 {
2201 MS_U16 tmp_value=0;
2202
2203 if (IS_STOP_PKT(packet_process)) // Stop sending packet
2204 {
2205 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000); // Stop AVI packet
2206 }
2207 else
2208 {
2209 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x0300, 0x0200); // EIA version 2
2210 switch(content_type)
2211 {
2212 case E_HDMITX_AVI_PIXEL_FROMAT:
2213 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x00E0, *data);
2214 break;
2215 case E_HDMITX_AVI_ASPECT_RATIO:
2216 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x3F1F, *data);
2217 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0003, *(data+1));
2218 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_4_0C, 0xFFFF, *(data+2));
2219 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_5_0D, 0xFFFF, *(data+3));
2220 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_6_0E, 0xFFFF, *(data+4));
2221 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0x00FF, *(data+5));
2222 break;
2223 case E_HDMITX_AVI_COLORIMETRY:
2224 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xC000, *data);
2225 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0030, *(data+1));
2226 break;
2227 default:
2228 break;
2229 }
2230
2231 tmp_value = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME); // Checksum
2232 // cyclic packet
2233 if (IS_CYCLIC_PKT(packet_process))
2234 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ( (tmp_value<<8) | (HDMITX_PACKET_AVI_FCNT<<3) | 0x0005)); // send AVI packet
2235 // single packet
2236 else
2237 {
2238 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (tmp_value<<8) | 0x0001);
2239 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1<<E_HDMITX_ACT_AVI_CMD);
2240 }
2241 }
2242 }
2243
2244 //wilson@kano
2245 //**************************************************************************
2246 // [Function Name]:
2247 // MHal_HDMITx_SetGCPParameter()
2248 // [Description]:
2249 // setting General Control packet attribute
2250 // [Arguments]:
2251 // [stGC_PktPara] stPktPara
2252 // [Return]:
2253 // void
2254 //
2255 //**************************************************************************
MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)2256 void MHal_HDMITx_SetGCPParameter(stGC_PktPara stPktPara)
2257 {
2258 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enAVMute = stPktPara.enAVMute;
2259 gbGeneralPktList[E_HDMITX_GC_PACKET].PktPara.GCPktPara.enColorDepInfo = stPktPara.enColorDepInfo;
2260 }
2261
2262 //**************************************************************************
2263 // [Function Name]:
2264 // MHal_HDMITx_SetPktAttribute()
2265 // [Description]:
2266 // configure settings to corresponding packet
2267 // [Arguments]:
2268 // [MsHDMITX_PACKET_TYPE] enPktType
2269 // [MS_BOOL] bEnUserDef
2270 // [MS_U8] u8FrmCntNum
2271 // [MsHDMITX_PACKET_PROCESS] enPktCtrl
2272 // [Return]:
2273 // void
2274 //
2275 //**************************************************************************
MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType,MS_BOOL bEnUserDef,MS_U8 u8FrmCntNum,MsHDMITX_PACKET_PROCESS enPktCtrl)2276 void MHal_HDMITx_SetPktAttribute(MsHDMITX_PACKET_TYPE enPktType, MS_BOOL bEnUserDef, MS_U8 u8FrmCntNum, MsHDMITX_PACKET_PROCESS enPktCtrl)
2277 {
2278 if (enPktType & 0x80) //infoframe packet type
2279 {
2280 gbInfoFrmPktList[enPktType & (~0x80)].EnableUserDef = bEnUserDef;
2281 gbInfoFrmPktList[enPktType & (~0x80)].FrmCntNum = u8FrmCntNum;
2282 gbInfoFrmPktList[enPktType & (~0x80)].enPktCtrl = enPktCtrl;
2283 }
2284 else
2285 {
2286 gbGeneralPktList[enPktType].EnableUserDef = bEnUserDef;
2287 gbGeneralPktList[enPktType].FrmCntNum = u8FrmCntNum;
2288 gbGeneralPktList[enPktType].enPktCtrl = enPktCtrl;
2289 }
2290 }
2291
2292 //**************************************************************************
2293 // [Function Name]:
2294 // MHal_HDMITx_SetAVIInfoParameter()
2295 // [Description]:
2296 // Assign content to AVI Infoframe packet
2297 // [Arguments]:
2298 // [stAVIInfo_PktPara] stPktPara
2299 // [Return]:
2300 // void
2301 //
2302 //**************************************************************************
MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)2303 void MHal_HDMITx_SetAVIInfoParameter(stAVIInfo_PktPara stPktPara)
2304 {
2305 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.A0Value = stPktPara.A0Value;
2306 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enableAFDoverWrite = stPktPara.enableAFDoverWrite;
2307 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorFmt = stPktPara.enColorFmt;
2308 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enColorimetry = stPktPara.enColorimetry;
2309 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enExtColorimetry = stPktPara.enExtColorimetry;
2310 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enYCCQuantRange = stPktPara.enYCCQuantRange;
2311 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enVidTiming = stPktPara.enVidTiming;
2312 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAFDRatio = stPktPara.enAFDRatio;
2313 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enScanInfo = stPktPara.enScanInfo;
2314 gbInfoFrmPktList[E_HDMITX_AVI_INFOFRAME & (~0x80)].PktPara.AVIInfoPktPara.enAspectRatio = stPktPara.enAspectRatio;
2315 }
2316
2317 //**************************************************************************
2318 // [Function Name]:
2319 // MHal_HDMITx_SetVSInfoParameter()
2320 // [Description]:
2321 // Assign content to VendorSpecific Infoframe packet
2322 // [Arguments]:
2323 // [stVSInfo_PktPara] stPketPara
2324 // [Return]:
2325 // void
2326 //
2327 //**************************************************************************
MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)2328 void MHal_HDMITx_SetVSInfoParameter(stVSInfo_PktPara stPktPara)
2329 {
2330 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en3DStruct = stPktPara.en3DStruct;
2331 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.en4k2kVIC = stPktPara.en4k2kVIC;
2332 gbInfoFrmPktList[E_HDMITX_VS_INFOFRAME & (~0x80)].PktPara.VSInfoPktPara.enVSFmt = stPktPara.enVSFmt;
2333 }
2334
2335 //**************************************************************************
2336 // [Function Name]:
2337 // MHal_HDMITx_SetVSInfoParameter()
2338 // [Description]:
2339 // Assign content to VendorSpecific Infoframe packet
2340 // [Arguments]:
2341 // [stVSInfo_PktPara] stPketPara
2342 // [Return]:
2343 // void
2344 //
2345 //**************************************************************************
MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)2346 void MHal_HDMITx_SetAudioInfoParameter(stAUDInfo_PktPara stPktPara)
2347 {
2348 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudChCnt = stPktPara.enAudChCnt;
2349 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudType = stPktPara.enAudType;
2350 gbInfoFrmPktList[E_HDMITX_AUDIO_INFOFRAME & (~0x80)].PktPara.AUDInfoPktPara.enAudFreq = stPktPara.enAudFreq;
2351 }
2352
2353 //**************************************************************************
2354 // [Function Name]:
2355 // MHal_HDMITx_SendPacket()
2356 // [Description]:
2357 // configure packet content and process according to user define or defalut setting
2358 // [Arguments]:
2359 // [MsHDMITX_PACKET_TYPE] enPktType
2360 // [Return]:
2361 // void
2362 //
2363 //**************************************************************************
MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType,MsHDMITX_PACKET_PROCESS packet_process)2364 void MHal_HDMITx_SendPacket(MsHDMITX_PACKET_TYPE enPktType, MsHDMITX_PACKET_PROCESS packet_process)
2365 {
2366 if (enPktType & 0x80) //info frame packet
2367 {
2368 MS_U8 ucInfoPktType = enPktType & (~0x80);
2369 MS_U8 ucChkSum = 0;
2370
2371 gbInfoFrmPktList[ucInfoPktType].enPktCtrl = packet_process;
2372
2373 switch (enPktType)
2374 {
2375 case E_HDMITX_VS_INFOFRAME:
2376 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2377 {
2378 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, 0x0005, 0x0000);
2379 }
2380 else
2381 {
2382 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2383 {
2384 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2385
2386 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2387 {
2388 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2389 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2390 }
2391 else
2392 {
2393 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2394 }
2395 }
2396 else
2397 {
2398 //fill IEEE HDMI tag
2399 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_1_27, 0xFFFF, 0x0C03);
2400
2401 //check content
2402 if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_3D)
2403 {
2404 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_3D << 13); // video format
2405 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en3DStruct) << 4); // 3D structure
2406 }
2407 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.enVSFmt == E_HDMITX_VIDEO_VS_4k_2k)
2408 {
2409 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, E_HDMITX_VIDEO_VS_4k_2k << 13); // video format
2410 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, (gbInfoFrmPktList[ucInfoPktType].PktPara.VSInfoPktPara.en4k2kVIC)); // 4k2k vic
2411 }
2412 else
2413 {
2414 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_2_28, 0xE000, 0); // video format
2415 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_VS_3_29, 0x00FF, 0);
2416 }
2417
2418 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_VS_INFOFRAME);
2419
2420 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2421 {
2422 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, (ucChkSum << 8) | 0x0001);
2423 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_VSP_CMD);
2424 }
2425 else
2426 {
2427 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_VS_CFG_35, ((ucChkSum << 8) | (HDMITX_PACKET_VS_FCNT << 3) | 0x0005));
2428 }
2429 }
2430 }
2431 break;
2432
2433 case E_HDMITX_AVI_INFOFRAME:
2434 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2435 {
2436 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, 0x0005, 0x0000);
2437 }
2438 else
2439 {
2440 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2441 {
2442 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2443
2444 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2445 {
2446 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2447 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2448 }
2449 else
2450 {
2451 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2452 }
2453 }
2454 else
2455 {
2456 MS_U8 ucPktVal = 0;
2457
2458 //Y2, Y1, Y0: RGB, YCbCr 422, 444, 420
2459 ucPktVal = (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt << 5);// | 0x10;
2460 //A0 field
2461 ucPktVal |= ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.A0Value == 0x01) ? 0x10 : 0x00);
2462 //S1, S0 field
2463 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enScanInfo);
2464
2465 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0x00FF, (MS_U16)ucPktVal); //MDrv_WriteByte(REG_HDMITX_09_L, ucPktVal);
2466
2467 //C1, C0, M1, M0
2468 if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2469 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p))
2470 {
2471 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2472 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio << 4);
2473 }
2474 else
2475 {
2476 //HD timing is always 16:9
2477 ucPktVal = HDMITX_AviCmrTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2478 }
2479
2480 //R3, R2, R1, R0: active porting aspect ration
2481 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enableAFDoverWrite == TRUE)
2482 {
2483 ucPktVal |= (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAFDRatio & 0x0F);
2484 }
2485
2486 //ucPktVal |= ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry == 0) ? 0 : 0xC0; //set [C1, C0] = [1, 1]
2487
2488 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry != E_HDMITX_COLORIMETRY_MAX)
2489 {
2490 ucPktVal = (ucPktVal & 0x3F) | ( ((MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorimetry & 0x03) << 6);
2491 }
2492
2493 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_1_09, 0xFF00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_09_H, ucPktVal);
2494
2495 //EC0, EC1, EC2
2496 ucPktVal = (MS_U8)gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enExtColorimetry;
2497 ucPktVal = (ucPktVal > 6) ? 6 : ucPktVal; //BT2020 RGB & BT2020 YCbCr share same value 6; 7 is reserved;
2498 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x0070, ucPktVal << 4); //MDrv_WriteByteMask(REG_HDMITX_0A_L, ucPktVal << 4, 0x70);
2499
2500 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enColorFmt == E_HDMITX_VIDEO_COLOR_RGB444)
2501 {
2502 //Q1, Q0
2503 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2504 {
2505 ucPktVal = 1;
2506 }
2507 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2508 {
2509 ucPktVal = 2;
2510 }
2511 else
2512 {
2513 ucPktVal = 0;
2514 }
2515
2516 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, ucPktVal << 2);
2517 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, 0x00);
2518 }
2519 else
2520 {
2521 //YQ1, YQ0
2522 if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_LIMIT)
2523 {
2524 ucPktVal = 0;
2525 }
2526 else if(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange == E_HDMITX_YCC_QUANT_FULL)
2527 {
2528 ucPktVal = 1;
2529 }
2530 else
2531 {
2532 ucPktVal = 3;
2533 }
2534
2535 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x000C, 0x00);
2536 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, ucPktVal << 6);
2537 }
2538
2539 //VIC code: VIC code shoud +1 if aspect ration is 16:9
2540 ucPktVal = HDMITX_AviVicTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming];
2541
2542 if (((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_720x480i) &&
2543 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576p)) &&
2544 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_16_9))
2545 {
2546 ucPktVal += 1;
2547 }
2548 else if (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enAspectRatio == E_HDMITX_VIDEO_AR_21_9)
2549 {
2550 MS_U8 AR21_9MappingTbl[14][2] = {
2551 {60, 65},
2552 {61, 66},
2553 {62, 67},
2554 {19, 68},
2555 { 4, 69},
2556 {41, 70},
2557 {47, 71},
2558 {32, 72},
2559 {33, 73},
2560 {34, 74},
2561 {31, 75},
2562 {16, 76},
2563 {64, 77},
2564 {63, 78}
2565 };
2566
2567 if ((ucPktVal >= 93) && (ucPktVal <= 97))//3840*2160p@24 ~ 3840*2160@60
2568 {
2569 ucPktVal += 10;
2570 }
2571 else if ((gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming >= E_HDMITX_RES_3840x2160p_24Hz) &&\
2572 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_3840x2160p_30Hz))
2573 {
2574 ucPktVal += (103 + (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming - E_HDMITX_RES_3840x2160p_24Hz));
2575 }
2576 else if ((ucPktVal > 78) && (ucPktVal <= 92))
2577 {
2578 //do nothing;
2579 }
2580 else
2581 {
2582 MS_U8 i = 0;
2583 MS_BOOL bValidVIC = FALSE;
2584
2585 for ( i = 0; i < 14; i++ )
2586 {
2587 if (AR21_9MappingTbl[i][0] == ucPktVal)
2588 {
2589 ucPktVal = AR21_9MappingTbl[i][1];
2590 bValidVIC = TRUE;
2591 break;
2592 }
2593 }
2594
2595 if (!bValidVIC)
2596 {
2597 printf("%s :: Invalid VIC Code for 21:9 Aspect Ratio!!!\r\n", __FUNCTION__);
2598 }
2599 }
2600 }
2601
2602 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_2_0A, 0x7F00, ucPktVal << 8); //MDrv_WriteByte(REG_HDMITX_0A_H, (ucPktVal & 0x7F));
2603
2604 //check repetition
2605 if ((HDMITxVideoModeTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming].i_p_mode == E_HDMITX_VIDEO_INTERLACE_MODE) &&
2606 (gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enVidTiming <= E_HDMITX_RES_720x576i))
2607 {
2608 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0001); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x01, 0x0F);
2609 }
2610 else
2611 {
2612 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x000F, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_0B_L, 0x00, 0x0F);
2613 }
2614
2615 //YQ1, YQ0
2616 //MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_3_0B, 0x00C0, (MS_U8)(gbInfoFrmPktList[ucInfoPktType].PktPara.AVIInfoPktPara.enYCCQuantRange << 6));
2617
2618 //AVI version
2619 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AVI_7_0F, 0x0300, (MS_U16)(HDMITX_AVI_INFO_PKT_VER << 8));
2620 //MDrv_WriteByteMask(REG_HDMITX_0F_H, HDMITX_AVI_INFO_PKT_VER, 0x03);
2621
2622 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AVI_INFOFRAME);
2623
2624 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2625 {
2626 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, (ucChkSum << 8) | 0x0001);
2627 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AVI_CMD);
2628 }
2629 else
2630 {
2631 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AVI_CFG_10, ((ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3) | 0x0005));
2632 //MDrv_Write2Byte(REG_HDMITX_10_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_AVI_FCNT << 3));
2633 }
2634 }
2635 }
2636 break;
2637
2638 case E_HDMITX_SPD_INFOFRAME:
2639 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2640 {
2641 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, 0x0005, 0x0000); //MDrv_WriteByteMask(REG_HDMITX_22_L, 0x00, 0x05);
2642 }
2643 else
2644 {
2645 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2646 {
2647 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2648
2649 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2650 {
2651 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2652 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2653 }
2654 else
2655 {
2656 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2657 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3));
2658 }
2659 }
2660 else
2661 {
2662 MS_U8 i = 0;
2663 MS_U8 ucPktVal = 0;
2664
2665 for (i = 0; i < ((HDMITX_SPD_INFO_PKT_LEN + 1) >> 1); i++)
2666 {
2667 if (i < 4) // vendor name
2668 {
2669 ucPktVal = (HDMITX_VendorName[2*i+1]<<8) | HDMITX_VendorName[2*i];
2670 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_1_15+i, 0x7F7F, ucPktVal);
2671 }
2672 else if ((i >= 4) && (i < 12)) // product description
2673 {
2674 ucPktVal = (HDMITX_ProductName[2*(i-4)+1]<<8) | HDMITX_ProductName[2*(i-4)];
2675 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_5_19+(i-4), 0x7F7F, ucPktVal);
2676 }
2677 else // source device information
2678 {
2679 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_SPD_13_21, 0x00FF, HDMITX_PACKET_SPD_SDI);
2680 }
2681 }
2682
2683 #if 0
2684 for ( i = 0; i < (HDMITX_SPD_INFO_PKT_LEN - 1); i++ )
2685 {
2686 if ( i < 8 )
2687 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_VendorName[i]);
2688 else
2689 MDrv_WriteByte((REG_HDMITX_15_L + i), gbHDMITX_ProductName[i-8]);
2690 }
2691
2692 MDrv_WriteByte(REG_HDMITX_21_L, 0x01); //SPD infoframe, byte25: source information: 0x01 = Digital STB
2693 #endif
2694
2695 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_SPD_INFOFRAME);
2696
2697 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2698 {
2699 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, (ucChkSum << 8) | 0x0001);
2700 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_SPD_CMD);
2701 }
2702 else
2703 {
2704 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_SPD_CFG_22, ((ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3) | 0x0005));
2705 //MDrv_Write2Byte(REG_HDMITX_22_L, 0x05 | (ucChkSum << 8) | (HDMITX_PACKET_SPD_FCNT << 3));
2706 }
2707 }
2708 }
2709
2710 break;
2711
2712 case E_HDMITX_AUDIO_INFOFRAME:
2713 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2714 {
2715 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, 0x0005, 0x0000);
2716 }
2717 else
2718 {
2719 // Modified for HDMI CTS test -
2720 // - Audio Coding Type (CT3~CT0) is 0x0 then continue else then FAIL
2721 // - Sampling Frequency (SF2~ SF0) is zero then continue else then FAIL.
2722 // - Sample Size (SS1~ SS0) is zero then continue else then FAIL.
2723 //tmp_value = (gHDMITxInfo.output_audio_frequncy << 10) | 0x11; // audio sampling frequency, PCM and 2 channel.
2724 //MHal_HDMITx_Mask_Write(REG_HDMITX_BANK1, REG_PKT_AUD_1_11, 0x1FFF, tmp_value);
2725
2726 if (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt == E_HDMITX_AUDIO_CH_2) // 2-channel
2727 {
2728 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_2 - 1) & 0x07); // 2 channels
2729 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0); // Channel allocation
2730 }
2731 else //8- channel
2732 {
2733 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_1_11, (E_HDMITX_AUDIO_CH_8 - 1)&0x07); // 8 channels
2734 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_2_12, 0xFF00, 0x1F00); // Channel allocation
2735 }
2736 //clear LFEP value
2737 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_AUD_3_13, 0x0001, 0x0000); //Fix LFEP defalut value in Kappa.
2738
2739 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_AUDIO_INFOFRAME);
2740
2741 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2742 {
2743 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, (ucChkSum << 8) | 0x0001);
2744 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_AUD_CMD);
2745 }
2746 else
2747 {
2748 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2749 {
2750 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (gbInfoFrmPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2751 }
2752 else
2753 {
2754 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_AUD_CFG_14, ( (ucChkSum << 8) | (HDMITX_PACKET_AUD_FCNT << 3) | 0x0005));
2755 }
2756 }
2757 }
2758
2759 //NOTE:: Kano move channel status from 0x00 to 0x0A
2760 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == FALSE)
2761 {
2762 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS0_0A, ((gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudType == E_HDMITX_AUDIO_PCM) ? 0 : BIT1)); // [1]: PCM / non-PCM
2763 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS1_0B, (TxAudioFreqTbl[gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudFreq].CH_Status3 << 8) | (gbInfoFrmPktList[ucInfoPktType].PktPara.AUDInfoPktPara.enAudChCnt << 4)); //[11:8]: audio sampling frequncy; [7:4]: audio channel count
2764 MHal_HDMITx_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CH_STATUS2_0C, 0x0000);
2765 }
2766 // Audio sampling frequency
2767 // 1 1 0 0 32 kHz
2768 // 0 0 0 0 44.1 kHz
2769 // 0 0 0 1 88.2 kHz
2770 // 0 0 1 1 176.4 kHz
2771 // 0 1 0 0 48 kHz
2772 // 0 1 0 1 96 kHz
2773 // 0 1 1 1 192 kHz
2774 // 1 0 0 1 768 kHz
2775 break;
2776
2777 case E_HDMITX_MPEG_INFOFRAME:
2778 //TBD
2779 break;
2780
2781 case E_HDMITX_HDR_INFOFRAME:
2782 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2783 {
2784 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, 0x0001, 0x0000);
2785 }
2786 else
2787 {
2788 if (gbInfoFrmPktList[ucInfoPktType].EnableUserDef == TRUE)
2789 {
2790 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2791
2792 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2793 {
2794 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2795 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2796 }
2797 else
2798 {
2799 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (gbGeneralPktList[ucInfoPktType].FrmCntNum << 3) | 0x0005));
2800 }
2801 }
2802 else
2803 {
2804 //TBD
2805 ucChkSum = MHal_HDMITx_InfoFrameCheckSum(E_HDMITX_HDR_INFOFRAME);
2806
2807 if (gbInfoFrmPktList[ucInfoPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2808 {
2809 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, (ucChkSum << 8) | 0x0001); //[15..8]: chk_sum; [0]:hdr_send_cmd
2810 MHal_HDMITx_Mask_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_00, 0xFFFF, 0x0001); //[0]:reg_act_hdr_cmd
2811 }
2812 else
2813 {
2814 MHal_HDMITx_Write(HDMITX_2_REG_BASE, REG_HDMI_2_CONFIG_1E, ((ucChkSum<<8) | (HDMITX_PACKET_HDR_FCNT << 3) | 0x0005));
2815 }
2816
2817 }
2818 }
2819 break;
2820
2821 default:
2822 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
2823 break;
2824 }
2825 }
2826 else //general packet
2827 {
2828 gbGeneralPktList[enPktType].enPktCtrl = packet_process;
2829
2830 switch (enPktType)
2831 {
2832 case E_HDMITX_NULL_PACKET:
2833 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2834 {
2835 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x0005, 0x0000);
2836 }
2837 else
2838 {
2839 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2840 {
2841 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, 0x0001);
2842 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_NUL_CMD);
2843 }
2844 else
2845 {
2846 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2847 {
2848 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 3) |0x0005) );
2849 }
2850 else
2851 {
2852 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_NUL_CFG_02, 0x00FF, ((HDMITX_PACKET_NULL_FCNT << 3) |0x0005) );
2853 }
2854 }
2855 }
2856 break;
2857
2858 case E_HDMITX_ACR_PACKET:
2859 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2860 {
2861 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x000F, 0x0008);
2862 }
2863 else
2864 {
2865 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2866 {
2867 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, 0x0009);
2868 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACR_CMD);
2869 }
2870 else //cyclic
2871 {
2872 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2873 {
2874 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((gbGeneralPktList[enPktType].FrmCntNum << 4) |0x05));
2875 }
2876 else
2877 {
2878 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACR_CFG_08, 0x00FF, ((HDMITX_PACKET_ACR_FCNT << 4) |0x05));
2879 }
2880 }
2881 }
2882 break;
2883
2884 case E_HDMITX_AS_PACKET:
2885 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET)
2886 {
2887 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT0); // [7]: disable audio FIFO, [0]:audio FIFO flush
2888 }
2889 else
2890 {
2891 MHal_HDMITx_Mask_Write(HDMITX_AUDIO_REG_BASE, REG_AE_CONFIG_05, BIT7|BIT0, BIT7); // [7]: enable audio FIFO, [0]:audio FIFO not flush
2892 }
2893 break;
2894
2895 case E_HDMITX_GC_PACKET:
2896 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2897 {
2898 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x000F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | 0x0000);
2899 }
2900 else
2901 {
2902 //fill color depth information
2903 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC12_04, 0x010F, gbGeneralPktList[enPktType].PktPara.GCPktPara.enColorDepInfo); // [8]: default phase = 0, [3:0]: Color depth
2904
2905 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2906 {
2907 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, (gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1)| 0x21); // [6]: 0, DC and non-DC info send together
2908 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_GCP_CMD);
2909 //MDrv_WriteByteMask(REG_HDMITX_03_L, 0x21, 0x7F);
2910 }
2911 else //cyclic
2912 {
2913 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2914 {
2915 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (gbGeneralPktList[enPktType].FrmCntNum << 4) | 0x29));
2916 }
2917 else
2918 {
2919 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_GC_CFG_03, 0x007F, ((gbGeneralPktList[enPktType].PktPara.GCPktPara.enAVMute << 1) | (HDMITX_PACKET_GC_FCNT << 4) | 0x29));
2920 }
2921 }
2922 }
2923 break;
2924
2925 case E_HDMITX_ACP_PACKET:
2926 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2927 {
2928 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0005, 0x0000);
2929 }
2930 else
2931 {
2932 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ACP_0_38, 0xFFFF, 0x0000); //acp type is 0x00
2933
2934 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2935 {
2936 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, 0x0001);
2937 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ACP_CMD);
2938 }
2939 else //cyclic
2940 {
2941 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2942 {
2943 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
2944 }
2945 else
2946 {
2947 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ACP_CFG_40, (HDMITX_PACKET_ACP_FCNT | 0x0005));
2948 }
2949 }
2950 }
2951 break;
2952
2953 case E_HDMITX_ISRC1_PACKET:
2954 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2955 {
2956 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2957 }
2958 else
2959 {
2960 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2961 {
2962 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0001);
2963 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2964 }
2965 else //cyclic
2966 {
2967 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2968 {
2969 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005)); }
2970 else
2971 {
2972 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
2973 }
2974 }
2975 }
2976 break;
2977
2978 case E_HDMITX_ISRC2_PACKET:
2979 //check ISRC cnt value
2980 if (MHal_HDMITx_Read(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51) & 0x8000)
2981 {
2982 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_STOP_PACKET) //stop packet
2983 {
2984 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, 0x0005, 0x0000);
2985 }
2986 else
2987 {
2988 MS_U8 u8ISRCCntVal = 0x80;
2989
2990 if (gbGeneralPktList[enPktType].enPktCtrl == E_HDMITX_SEND_PACKET) //single
2991 {
2992 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, (u8ISRCCntVal << 8) | 0x0001 ); // 0x80: ISRC_CONT = 1, ISRC1 & ISRC2
2993 MHal_HDMITx_Mask_Write(HDMITX_REG_BASE, REG_ACT_HDMI_PKTS_CMD_01, 0x03FF, 1 << E_HDMITX_ACT_ISRC_CMD);
2994 }
2995 else //cyclic
2996 {
2997 if (gbGeneralPktList[enPktType].EnableUserDef == TRUE)
2998 {
2999 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (gbGeneralPktList[enPktType].FrmCntNum << 3) | 0x0005));
3000 }
3001 else
3002 {
3003 MHal_HDMITx_Write(HDMITX_REG_BASE, REG_PKT_ISRC_CFG_51, ((u8ISRCCntVal << 8) | (HDMITX_PACKET_ISRC_FCNT << 3) | 0x0005));
3004 }
3005 }
3006 }
3007 }
3008 break;
3009
3010 case E_HDMITX_DSD_PACKET:
3011 //TBD
3012 break;
3013
3014 case E_HDMITX_HBR_PACKET:
3015 //TBD
3016 break;
3017
3018 case E_HDMITX_GM_PACKET:
3019 //TBD
3020 break;
3021
3022 default:
3023 printf("hal_HDMITx_SendPacket():: Invalid Packet Type!!\r\n");
3024 break;
3025 }
3026 }
3027 }
3028
MHal_HDMITx_EnableSSC(MS_BOOL bEnable,MS_U32 uiTMDSCLK)3029 void MHal_HDMITx_EnableSSC(MS_BOOL bEnable, MS_U32 uiTMDSCLK)
3030 {
3031 //Kano does not implement SSC yet.
3032 #if 0
3033 #define HDMITX_MPLL_CLK 432 //432MHz
3034 #define HDMITX_SSC_CLK 30 //30KHz
3035 #define HDMITX_SSC_DEVIATION 1 // 0.1%
3036 #define HDMITX_SSC_DEVIATION_DIVIDER 1000
3037 #define HDMITX_SSC_THREAD_LEVEL1 150 ///1080p 8bits
3038 #define HDMITX_SSC_THREAD_LEVEL2 300 ///4K30 8bits
3039 #define HDMITX_SSC_SPAN_REG REG_HDMITxPHY_CONFIG_06
3040 #define HDMITX_SSC_STEP_REG REG_HDMITxPHY_CONFIG_07
3041 #define HDMITX_SSC_SUB_DIVIDER_REG REG_HDMITxPHY_CONFIG_01
3042
3043 MS_U32 ub2x19times = 524288;// 2^ 19
3044 MS_U32 dSYNCLK = 1;
3045 MS_U32 ub432MHz = HDMITX_MPLL_CLK;
3046 MS_U32 ubSSCClk = HDMITX_SSC_CLK;
3047 MS_U32 dSSc_Deviation= HDMITX_SSC_DEVIATION;
3048 MS_U32 ubSYNSet = 0;
3049 MS_U32 dSSC_Span = 0;
3050 MS_U32 dSSC_Step = 0;
3051 MS_U32 dPixel_Clk = 0;
3052
3053 if(!bEnable)
3054 {
3055 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, 0 );//Span
3056 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, 0);//Step
3057 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0 );//Sub-Divider
3058 return;
3059 }
3060
3061 ubSYNSet = MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_02);
3062 ubSYNSet |= ( (MHal_HDMITx_Read(HDMITX_PHY_REG_BASE, REG_HDMITxPHY_CONFIG_03) & 0xFF) << 16);
3063
3064 if(ubSYNSet != 0)
3065 dSYNCLK = ((ub432MHz*ub2x19times)/ubSYNSet);
3066
3067 if(ubSSCClk != 0)
3068 dSSC_Span = (dSYNCLK * 250) / (ubSSCClk); //Span = SYN_CLK_KHz / (SSC_CLK_KHz * 4)
3069
3070 if( (dSSC_Span != 0) && (HDMITX_SSC_DEVIATION_DIVIDER != 0) )
3071 dSSC_Step = (((ubSYNSet/ dSSC_Span)/HDMITX_SSC_DEVIATION_DIVIDER) * dSSc_Deviation) ; //Step = SYN_SET * deviation / Span
3072
3073 printf("ubSYNSet=%x, dSYNCLK=%d, dSSC_Span=%d, dSSC_Step=%d\r\n", ubSYNSet, dSYNCLK, dSSC_Span, dSSC_Step);
3074
3075 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SPAN_REG, 0x3FFF, ( ((int)dSSC_Span) & 0x3FFF) );//Span
3076 MHal_HDMITx_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_STEP_REG, ( ((int)dSSC_Step) & 0xFFFF) );//Step
3077
3078 //Read tmds clock
3079 #if 0
3080 MHal_HDMITx_Mask_Write(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_20, 0x3F, 0x3F);
3081 dPixel_Clk = ((MHal_HDMITx_Read(HDMITX_MISC_REG_BASE, REG_MISC_CONFIG_21) << 1) * 12 / 128);
3082 #else
3083 dPixel_Clk = uiTMDSCLK;
3084 #endif
3085 printf("dPixel_Clk=%d\r\n", dPixel_Clk);
3086
3087 if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL1)
3088 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x0000 );//Sub-Divider
3089 else if(dPixel_Clk < HDMITX_SSC_THREAD_LEVEL2)
3090 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x1000 );//Sub-Divider
3091 else
3092 MHal_HDMITx_Mask_Write(HDMITX_PHY_REG_BASE, HDMITX_SSC_SUB_DIVIDER_REG, 0x7000, 0x3000 );//Sub-Divider
3093
3094 #endif
3095 }
3096
MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx,MsHDMITX_VIDEO_COLOR_FORMAT color_fmt,MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)3097 MS_U32 MHal_HDMITx_GetPixelClk_ByTiming(MsHDMITX_VIDEO_TIMING idx, MsHDMITX_VIDEO_COLOR_FORMAT color_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth)
3098 {
3099 MS_U32 dwTMDSDataRate = 0;
3100 MS_U8 ubBitNum = 8;
3101
3102 switch(color_depth)
3103 {
3104 case E_HDMITX_VIDEO_CD_NoID:
3105 case E_HDMITX_VIDEO_CD_24Bits:
3106 {
3107 ubBitNum = 8;
3108 }
3109 break;
3110
3111 case E_HDMITX_VIDEO_CD_30Bits:
3112 {
3113 ubBitNum = 10;
3114 }
3115 break;
3116
3117 case E_HDMITX_VIDEO_CD_36Bits:
3118 {
3119 ubBitNum = 12;
3120 }
3121 break;
3122
3123 case E_HDMITX_VIDEO_CD_48Bits:
3124 {
3125 ubBitNum = 16;
3126 }
3127 break;
3128
3129 default:
3130 {
3131 ubBitNum = 8;
3132 }
3133 break;
3134 }
3135
3136 dwTMDSDataRate = (HDMITxVideoModeTbl[idx].pixel_clk/1000) * ubBitNum / 8;
3137
3138 if(color_fmt == E_HDMITX_VIDEO_COLOR_YUV420)
3139 dwTMDSDataRate = dwTMDSDataRate/2;
3140
3141 //printf("Time_ID = %d, C_FMT = %d, C_DEP = %d, PXL_CLK = %d\r\n", idx, color_fmt, color_depth, dwTMDSDataRate);
3142 return dwTMDSDataRate;
3143 }
3144
MHal_HDMITx_GetMaxPixelClk(void)3145 MS_U32 MHal_HDMITx_GetMaxPixelClk(void)
3146 {
3147 return HDMITX_MAX_PIXEL_CLK/1000;
3148 }
3149