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76 //******************************************************************************
77 //<MStar Software>
78 ///////////////////////////////////////////////////////////////////////////////////////////////////
79 ///
80 /// file mhal_mhl.c
81 /// @author MStar Semiconductor Inc.
82 /// @brief MHL driver Function
83 ///////////////////////////////////////////////////////////////////////////////////////////////////
84
85 #ifndef _MHAL_MHL_C_
86 #define _MHAL_MHL_C_
87
88 //-------------------------------------------------------------------------------------------------
89 // Include Files
90 //-------------------------------------------------------------------------------------------------
91 // Common Definition
92 #include "MsCommon.h"
93 #include "MsVersion.h"
94 #ifdef MSOS_TYPE_LINUX_KERNEL
95 #include <linux/string.h>
96 #else
97 #include <string.h>
98 #endif
99 #include "MsIRQ.h"
100 #include "MsOS.h"
101 #include "mhal_xc_chip_config.h"
102 #include "mhl_hwreg_utility2.h"
103 #include "hwreg_pm_sleep.h"
104 #include "hwreg_hdmi.h"
105 #include "hwreg_hdcp.h"
106 #include "hwregMHL.h"
107 #include "mdrv_mhl_st.h"
108 #include "halMHL.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Local Defines
112 //-------------------------------------------------------------------------------------------------
113 #if(defined(CONFIG_MLOG))
114 #include "ULog.h"
115
116 #define MHAL_MHL_MSG_INFO(format, args...) ULOGI("MHL", format, ##args)
117 #define MHAL_MHL_MSG_WARNING(format, args...) ULOGW("MHL", format, ##args)
118 #define MHAL_MHL_MSG_DEBUG(format, args...) ULOGD("MHL", format, ##args)
119 #define MHAL_MHL_MSG_ERROR(format, args...) ULOGE("MHL", format, ##args)
120 #define MHAL_MHL_MSG_FATAL(format, args...) ULOGF("MHL", format, ##args)
121
122 #else
123 #define MHAL_MHL_MSG_INFO(format, args...) printf(format, ##args)
124 #define MHAL_MHL_MSG_WARNING(format, args...) printf(format, ##args)
125 #define MHAL_MHL_MSG_DEBUG(format, args...) printf(format, ##args)
126 #define MHAL_MHL_MSG_ERROR(format, args...) printf(format, ##args)
127 #define MHAL_MHL_MSG_FATAL(format, args...) printf(format, ##args)
128
129 #endif
130
131 #define MHL_DEBUG_SEND_MSC 0
132 #define MHL_DEBUG_RECEIVE_EMSC 0
133
134 #define DMHLInit 0
135
136 //-------------------------------------------------------------------------------------------------
137 // Local Structures
138 //-------------------------------------------------------------------------------------------------
139 typedef struct
140 {
141 MS_U32 addr;
142 MS_U16 mask;
143 MS_U16 databuf;
144 } msLoadTbl_S;
145
146 //-------------------------------------------------------------------------------------------------
147 // Global Variables
148 //-------------------------------------------------------------------------------------------------
149 MS_U8 ucChipIDValue = MHL_CHIP_ID_MAXIM;
150 MS_VIRT MHL_XC_RIU_BASE;
151 MS_VIRT MHL_PM_RIU_BASE;
152
153 //-------------------------------------------------------------------------------------------------
154 // MHL initial table
155 //-------------------------------------------------------------------------------------------------
156 static msLoadTbl_S tMHL_INITIAL_TABLE[] =
157 {
158 // Set accepted discover pulse high pulse width to ignore USB pulse
159 {REG_PM_MHL_CBUS_0C, BMASK(15:0), 0x0046}, // reject cbus discovery pulse below this limit
160 {REG_PM_MHL_CBUS_0D, BMASK(15:0), 0x0082}, // reject cbus discovery pulse above this limit
161 // CTS 4.3.7.1
162 {REG_MHL_CBUS_55, BMASK(7:4), BIT(4)}, // [7:4]: cbus requester transmit opportunity after arbitration
163 {REG_MHL_CBUS_70, BIT(14), BIT(14)}, // [14]: let edid current read initial address add 1
164
165 {REG_PM_MHL_CBUS_21, BIT(1), BIT(1)}, // [1]: output mhl_zxsense_tmds inv
166
167 // For CTS 6.3.10.7
168 {REG_MHL_CBUS_59, BMASK(15:0), 0xFBD0}, // timeout for a device receiving a packet within a command
169 {REG_MHL_CBUS_5A, BMASK(15:0), 0x0001}, // modify to 130ms
170
171 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
172
173 #if(MHL_CBUS_OPERATION_MODE >= MHL_CBUS_HW_ISR_MODE)
174 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), BIT(10) |BIT(4)}, // [10]: enable HW auto response read_devcap request
175 {REG_MHL_CBUS_6D, BMASK(11:0), BMASK(11:0)}, // Enable MHL HW mode
176 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), BMASK(15:14)| BMASK(11:10)},
177 {REG_MHL_CBUS_50, BIT(13), BIT(13)}, // [13]: MSC send command keep mode
178 #else
179 {REG_MHL_CBUS_23, BMASK(10:8) |BIT(4), 0}, // [10]: enable HW auto response read_devcap request
180 {REG_MHL_CBUS_6D, BMASK(11:0), 0}, // Enable MHL HW mode
181 {REG_MHL_CBUS_71, BMASK(15:14)| BMASK(11:10), 0},
182 {REG_MHL_CBUS_50, BIT(13), 0}, // [13]: MSC send command keep mode
183 #endif
184
185 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
186 {REG_MHL_CBUS_0B, BIT(14), BIT(14)}, // [14]: MSC send command keep mode
187 #endif
188
189 #if DMHL_INT_ENABLE
190 // Mask unused interrupt events
191 {REG_PM_MHL_CBUS_16, BIT(13)|BIT(9), BIT(13)|BIT(9)}, // [13]: lnk_lay_en_chg_int mask, [9]: conn_state_chg_int mask
192 {REG_PM_MHL_CBUS_18, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: cbus_discover_pul_confirm_int mask, [5]: wakeup_pul_confirm_int mask, [1]: cbus_stuck_to_low_int mask.
193 {REG_PM_MHL_CBUS_30, BIT(1), BIT(1)}, // [1]: cbus conflict_int mask
194 {REG_PM_MHL_CBUS_38, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
195 {REG_MHL_CBUS_14, BIT(13), BIT(13)}, // [13]: int mask for monitor_sram_full
196 {REG_MHL_CBUS_18, BIT(13), BIT(13)}, // [13]: send rcv_pkt_ddc_sw_overwrite_err_in mask
197 {REG_MHL_CBUS_19, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: send ddc send complete interrupt mask, [1]: send ddc error interrupt mask
198 {REG_MHL_CBUS_1B, BIT(1), BIT(1)}, // [1]: receive ddc packet valid mask
199 {REG_MHL_CBUS_1F, BIT(5)|BIT(1), BIT(5)|BIT(1)}, // [5]: ddc access edid timeout int mask, [1]: client_wrt_ddc_ram interrupt mask
200 {REG_MHL_CBUS_21, BIT(5), BIT(5)}, // [5]: ddc error interrupt mask
201 {REG_MHL_CBUS_22, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: ddc access hdcp timeout int mask, [5]: receive nack pkt int_mask, [1]: receive abort pkt int mask
202 {REG_MHL_CBUS_23, BIT(13), BIT(13)}, // [13]: send rcv_pkt_msc_sw_overwrite_err_in mask
203 {REG_MHL_CBUS_24, BIT(1), BIT(1)}, // [1]: send error interrupt mask
204 {REG_MHL_CBUS_25, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: response_pkt_msc_hw_int mask, [5]: snd_pkt_msc_hw_int mask, [1]: msc sw send complete interrupt mask
205 {REG_MHL_CBUS_63, BIT(9), BIT(9)}, // [9]: dytycycle_bad_int mask
206 {REG_MHL_CBUS_65, BIT(9)|BIT(5)|BIT(1), BIT(9)|BIT(5)|BIT(1)}, // [9]: rcv_parity_err_int mask, [5]: rcv_data_err_int mask, [1]: rcv_sync_err_int mask
207 {REG_MHL_CBUS_78, BIT(13)|BIT(9)|BIT(5)|BIT(1), BIT(13)|BIT(9)|BIT(5)|BIT(1)}, // [13]: unused mask, [9]: unused mask, [5]: unused mask, [1]: unused mask.
208 #endif
209 };
210
211 //-------------------------------------------------------------------------------------------------
212 // MHL power on table
213 //-------------------------------------------------------------------------------------------------
214 static msLoadTbl_S tMHL_POWER_ON_TABLE[] =
215 {
216 {REG_PM_MHL_CBUS_01, BMASK(5:2), 0}, // Not overwrite pull down resistor
217 };
218
219 //-------------------------------------------------------------------------------------------------
220 // MHL power down table
221 //-------------------------------------------------------------------------------------------------
222 static msLoadTbl_S tMHL_POWER_DOWN_TABLE[] =
223 {
224 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
225 };
226
227 //-------------------------------------------------------------------------------------------------
228 // MHL power saving table
229 //-------------------------------------------------------------------------------------------------
230 static msLoadTbl_S tMHL_POWER_SAVING_TABLE[] =
231 {
232 {REG_PM_MHL_CBUS_01, BMASK(5:2), BIT(5)|BMASK(3:2)},
233 };
234
235 //-------------------------------------------------------------------------------------------------
236 // Local Functions
237 //-------------------------------------------------------------------------------------------------
238
239 //**************************************************************************
240 // [Function Name]:
241 // _mhal_mhl_IsCbusBusy()
242 // [Description]
243 //
244 // [Arguments]:
245 //
246 // [Return]:
247 //
248 //**************************************************************************
_mhal_mhl_IsCbusBusy(MS_BOOL bECbusEnableFlag)249 MS_BOOL _mhal_mhl_IsCbusBusy(MS_BOOL bECbusEnableFlag)
250 {
251 MS_BOOL bBusyFlag = FALSE;
252
253 if(!bECbusEnableFlag)
254 {
255 bBusyFlag = ((R2BYTE(REG_MHL_CBUS_5D) & 0x00F0) != 0 ? TRUE : FALSE);
256 }
257 return bBusyFlag;
258 }
259
260 //**************************************************************************
261 // [Function Name]:
262 // _mhal_mhl_DviAutoEQSwitch()
263 // [Description]
264 //
265 // [Arguments]:
266 //
267 // [Return]:
268 //
269 //**************************************************************************
_mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)270 void _mhal_mhl_DviAutoEQSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
271 {
272 static MS_BOOL bAutoEQFlag = FALSE;
273
274 switch(ucCbusSelect)
275 {
276 #if(MHL_FUNCTION_SUPPORT_PORTA)
277 case MHL_CBUS_SELECT_PORTA:
278 if(!bAutoEQFlag)
279 {
280 //if((R2BYTE(REG_DVI_DTOP_DUAL_P0_2F_L) &BIT(0)) == BIT(0))
281 {
282 bAutoEQFlag = TRUE;
283 }
284 }
285
286 if(bAutoEQFlag)
287 {
288 if(bFlag)
289 {
290 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_00_L, BIT(4), BIT(4)); // enable EQ new mode
291 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
292 }
293 else
294 {
295 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_00_L, 0, BIT(4)); // disable EQ new mode
296 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_2F_L, 0, BIT(0)); // disable autoEQ controller
297 }
298 }
299
300 break;
301 #endif
302
303 #if(MHL_FUNCTION_SUPPORT_PORTB)
304 case MHL_CBUS_SELECT_PORTB:
305 if(!bAutoEQFlag)
306 {
307 //if((R2BYTE(REG_DVI_DTOP_DUAL_P1_2F_L) &BIT(0)) == BIT(0))
308 {
309 bAutoEQFlag = TRUE;
310 }
311 }
312
313 if(bAutoEQFlag)
314 {
315 if(bFlag)
316 {
317 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_00_L, BIT(4), BIT(4)); // enable EQ new mode
318 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
319 }
320 else
321 {
322 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_00_L, 0, BIT(4)); // disable EQ new mode
323 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_2F_L, 0, BIT(0)); // disable autoEQ controller
324 }
325 }
326
327 break;
328 #endif
329
330 #if(MHL_FUNCTION_SUPPORT_PORTC)
331 case MHL_CBUS_SELECT_PORTC:
332 if(!bAutoEQFlag)
333 {
334 //if((R2BYTE(REG_DVI_DTOP_DUAL_P2_2F_L) &BIT(0)) == BIT(0))
335 {
336 bAutoEQFlag = TRUE;
337 }
338 }
339
340 if(bAutoEQFlag)
341 {
342 if(bFlag)
343 {
344 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_00_L, BIT(4), BIT(4)); // enable EQ new mode
345 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
346 }
347 else
348 {
349 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_00_L, 0, BIT(4)); // disable EQ new mode
350 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_2F_L, 0, BIT(0)); // disable autoEQ controller
351 }
352 }
353
354 break;
355 #endif
356
357 #if(MHL_FUNCTION_SUPPORT_PORTD)
358 case MHL_CBUS_SELECT_PORTD:
359 if(!bAutoEQFlag)
360 {
361 //if((R2BYTE(REG_DVI_DTOP_DUAL_P3_2F_L) &BIT(0)) == BIT(0))
362 {
363 bAutoEQFlag = TRUE;
364 }
365 }
366
367 if(bAutoEQFlag)
368 {
369 if(bFlag)
370 {
371 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_00_L, BIT(4), BIT(4)); // enable EQ new mode
372 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_2F_L, BIT(0), BIT(0)); // enable autoEQ controller
373 }
374 else
375 {
376 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_00_L, 0, BIT(4)); // disable EQ new mode
377 //W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_2F_L, 0, BIT(0)); // disable autoEQ controller
378 }
379 }
380
381 break;
382 #endif
383
384 default:
385 if(bAutoEQFlag)
386 {
387
388 }
389
390 break;
391 };
392 }
393
394 //**************************************************************************
395 // [Function Name]:
396 // _mhal_mhl_HdmiBypassModeSetting()
397 // [Description]
398 // MHL HDMI bypass setting
399 // [Arguments]:
400 //
401 // [Return]:
402 //
403 //**************************************************************************
_mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect,stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus)404 void _mhal_mhl_HdmiBypassModeSetting(MS_U8 ucCbusSelect, stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus)
405 {
406 switch(ucCbusSelect)
407 {
408 #if(MHL_FUNCTION_SUPPORT_PORTA)
409 case MHL_CBUS_SELECT_PORTA:
410 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
411 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
412 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
413 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble
414 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, 0, BIT(10)); // I-control PD overwrite write
415 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
416 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, 0, BMASK(12:0));
417 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8));
418
419 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
420 {
421 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P0_6B_L) >> 12;
422 }
423
424 if(pMHLSignalStatus->ucImpedanceOffset > 0)
425 {
426 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12));
427 }
428
429 break;
430 #endif
431
432 #if(MHL_FUNCTION_SUPPORT_PORTB)
433 case MHL_CBUS_SELECT_PORTB:
434 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
435 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
436 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
437 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
438 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, 0, BIT(10)); // I-control PD overwrite write
439 W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
440 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, 0, BMASK(12:0));
441 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BIT(8), BIT(8));
442
443 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
444 {
445 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P1_6B_L) >> 12;
446 }
447
448 if(pMHLSignalStatus->ucImpedanceOffset > 0)
449 {
450 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12));
451 }
452
453 break;
454 #endif
455
456 #if(MHL_FUNCTION_SUPPORT_PORTC)
457 case MHL_CBUS_SELECT_PORTC:
458 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
459 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
460 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
461 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
462 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, 0, BIT(10)); // I-control PD overwrite write
463 W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
464 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, 0, BMASK(12:0));
465 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BIT(8), BIT(8));
466
467 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
468 {
469 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12;
470 }
471
472 if(pMHLSignalStatus->ucImpedanceOffset > 0)
473 {
474 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12));
475 }
476
477 break;
478 #endif
479
480 #if(MHL_FUNCTION_SUPPORT_PORTD)
481 case MHL_CBUS_SELECT_PORTD:
482 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, 0, BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
483 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_HDMI_EQ_SETTING_VALUE, BMASK(4:0)); // B channel EQ
484 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, BIT(13)| BMASK(3:0), BIT(13)| BMASK(3:0));
485 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
486 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, 0, BIT(10)); // I-control PD overwrite write
487 W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_HDMI_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
488 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, 0, BMASK(12:0));
489 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8));
490
491 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
492 {
493 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P3_6B_L) >> 12;
494 }
495
496 if(pMHLSignalStatus->ucImpedanceOffset > 0)
497 {
498 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, (pMHLSignalStatus->ucImpedanceValue << 12), BMASK(15:12));
499 }
500
501 break;
502 #endif
503
504 default:
505
506 break;
507 };
508
509 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, TRUE);
510 }
511
512 //**************************************************************************
513 // [Function Name]:
514 // _mhal_mhl_Mhl24bitsModeSetting()
515 // [Description]
516 // MHL 24 bits mode setting
517 // [Arguments]:
518 //
519 // [Return]:
520 //
521 //**************************************************************************
_mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect,stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus)522 void _mhal_mhl_Mhl24bitsModeSetting(MS_U8 ucCbusSelect, stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus)
523 {
524 MS_U16 usImpedanceSetting = 0;
525
526 switch(ucCbusSelect)
527 {
528 #if(MHL_FUNCTION_SUPPORT_PORTA)
529 case MHL_CBUS_SELECT_PORTA:
530 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
531 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
532 W2BYTEMSK(REG_COMBO_PHY0_P0_5B_L, 0, BIT(13)| BMASK(3:0));
533 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, 0, BIT(0)); // PP mode + HDCP eanble
534 W2BYTEMSK(REG_COMBO_PHY0_P0_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
535 W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD
536 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
537 W2BYTEMSK(REG_COMBO_PHY0_P0_11_L, BIT(12) |0x30, BMASK(12:0));
538 W2BYTEMSK(REG_COMBO_PHY1_P0_10_L, 0, BMASK(1:0));
539 W2BYTE(REG_COMBO_PHY0_P0_60_L, 0);
540 W2BYTE(REG_COMBO_PHY0_P0_61_L, 0);
541 W2BYTE(REG_COMBO_PHY0_P0_62_L, 0);
542
543 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
544 {
545 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P0_6B_L) >> 12;
546 }
547
548 if(pMHLSignalStatus->ucImpedanceOffset > 0)
549 {
550 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7))
551 {
552 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue +pMHLSignalStatus->ucImpedanceOffset) << 12;
553 }
554 else
555 {
556 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue -pMHLSignalStatus->ucImpedanceOffset) << 12;
557 }
558
559 W2BYTEMSK(REG_COMBO_PHY0_P0_6B_L, usImpedanceSetting, BMASK(15:12));
560 }
561
562 break;
563 #endif
564
565 #if(MHL_FUNCTION_SUPPORT_PORTB)
566 case MHL_CBUS_SELECT_PORTB:
567 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
568 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
569 W2BYTEMSK(REG_COMBO_PHY0_P1_5B_L, 0, BIT(13)| BMASK(3:0));
570 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, 0, BIT(0)); // PP mode + HDCP eanble
571 W2BYTEMSK(REG_COMBO_PHY0_P1_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
572 W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD
573 W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
574 W2BYTEMSK(REG_COMBO_PHY0_P1_11_L, BIT(12) |0x30, BMASK(12:0));
575 W2BYTEMSK(REG_COMBO_PHY1_P1_10_L, 0, BMASK(1:0));
576 W2BYTE(REG_COMBO_PHY0_P1_60_L, 0);
577 W2BYTE(REG_COMBO_PHY0_P1_61_L, 0);
578 W2BYTE(REG_COMBO_PHY0_P1_62_L, 0);
579
580 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
581 {
582 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P1_6B_L) >> 12;
583 }
584
585 if(pMHLSignalStatus->ucImpedanceOffset > 0)
586 {
587 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7))
588 {
589 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue +pMHLSignalStatus->ucImpedanceOffset) << 12;
590 }
591 else
592 {
593 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue -pMHLSignalStatus->ucImpedanceOffset) << 12;
594 }
595
596 W2BYTEMSK(REG_COMBO_PHY0_P1_6B_L, usImpedanceSetting, BMASK(15:12));
597 }
598
599 break;
600 #endif
601
602 #if(MHL_FUNCTION_SUPPORT_PORTC)
603 case MHL_CBUS_SELECT_PORTC:
604 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
605 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
606 W2BYTEMSK(REG_COMBO_PHY0_P2_5B_L, 0, BIT(13)| BMASK(3:0));
607 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, 0, BIT(0)); // PP mode + HDCP eanble
608 W2BYTEMSK(REG_COMBO_PHY0_P2_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
609 W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD
610 W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
611 W2BYTEMSK(REG_COMBO_PHY0_P2_11_L, BIT(12) |0x30, BMASK(12:0));
612 W2BYTEMSK(REG_COMBO_PHY1_P2_10_L, 0, BMASK(1:0));
613 W2BYTE(REG_COMBO_PHY0_P2_60_L, 0);
614 W2BYTE(REG_COMBO_PHY0_P2_61_L, 0);
615 W2BYTE(REG_COMBO_PHY0_P2_62_L, 0);
616
617 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
618 {
619 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P2_6B_L) >> 12;
620 }
621
622 if(pMHLSignalStatus->ucImpedanceOffset > 0)
623 {
624 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7))
625 {
626 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue +pMHLSignalStatus->ucImpedanceOffset) << 12;
627 }
628 else
629 {
630 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue -pMHLSignalStatus->ucImpedanceOffset) << 12;
631 }
632
633 W2BYTEMSK(REG_COMBO_PHY0_P2_6B_L, usImpedanceSetting, BMASK(15:12));
634 }
635
636 break;
637 #endif
638
639 #if(MHL_FUNCTION_SUPPORT_PORTD)
640 case MHL_CBUS_SELECT_PORTD:
641 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(6), BIT(6)| BIT(1)); // [6]: align, [1]: MHL pack-pixel mode
642 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
643 W2BYTEMSK(REG_COMBO_PHY0_P3_5B_L, 0, BIT(13)| BMASK(3:0));
644 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, 0, BIT(0)); // PP mode + HDCP eanble
645 W2BYTEMSK(REG_COMBO_PHY0_P3_6F_L, BIT(10), BIT(10)); // I-control PD overwrite write
646 W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, (MHL_ICONTROL_PD_20_VALUE << 9), BMASK(13:9)); // I-control PD
647 W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, (MHL_LOCK_TIME_VALUE << 8), BMASK(14:8)); // Digital lock time value
648 W2BYTEMSK(REG_COMBO_PHY0_P3_11_L, BIT(12) |0x30, BMASK(12:0));
649 W2BYTEMSK(REG_COMBO_PHY1_P3_10_L, 0, BMASK(1:0));
650 W2BYTE(REG_COMBO_PHY0_P3_60_L, 0);
651 W2BYTE(REG_COMBO_PHY0_P3_61_L, 0);
652 W2BYTE(REG_COMBO_PHY0_P3_62_L, 0);
653
654 if(pMHLSignalStatus->ucImpedanceValue == MHL_IMPEDANCE_VALUE)
655 {
656 pMHLSignalStatus->ucImpedanceValue = R2BYTE(REG_COMBO_PHY0_P3_6B_L) >> 12;
657 }
658
659 if(pMHLSignalStatus->ucImpedanceOffset > 0)
660 {
661 if(pMHLSignalStatus->ucImpedanceOffset &BIT(7))
662 {
663 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue +pMHLSignalStatus->ucImpedanceOffset) << 12;
664 }
665 else
666 {
667 usImpedanceSetting = (pMHLSignalStatus->ucImpedanceValue -pMHLSignalStatus->ucImpedanceOffset) << 12;
668 }
669
670 W2BYTEMSK(REG_COMBO_PHY0_P3_6B_L, usImpedanceSetting, BMASK(15:12));
671 }
672
673 break;
674 #endif
675
676 default:
677 usImpedanceSetting = 0;
678 break;
679 };
680
681 _mhal_mhl_DviAutoEQSwitch(ucCbusSelect, FALSE);
682 }
683
684 //**************************************************************************
685 // [Function Name]:
686 // _mhal_mhl_MhlPackedPixelModeSetting()
687 // [Description]
688 // MHL packed pixel mode setting
689 // [Arguments]:
690 //
691 // [Return]:
692 //
693 //**************************************************************************
_mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)694 void _mhal_mhl_MhlPackedPixelModeSetting(MS_U8 ucCbusSelect)
695 {
696 switch(ucCbusSelect)
697 {
698 #if(MHL_FUNCTION_SUPPORT_PORTA)
699 case MHL_CBUS_SELECT_PORTA:
700 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
701 W2BYTEMSK(REG_HDCP_DUAL_P0_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
702
703 break;
704 #endif
705
706 #if(MHL_FUNCTION_SUPPORT_PORTB)
707 case MHL_CBUS_SELECT_PORTB:
708 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
709 W2BYTEMSK(REG_HDCP_DUAL_P1_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
710
711 break;
712 #endif
713
714 #if(MHL_FUNCTION_SUPPORT_PORTC)
715 case MHL_CBUS_SELECT_PORTC:
716 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
717 W2BYTEMSK(REG_HDCP_DUAL_P2_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
718
719 break;
720 #endif
721
722 #if(MHL_FUNCTION_SUPPORT_PORTD)
723 case MHL_CBUS_SELECT_PORTD:
724 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, BIT(1), BIT(1)); // [1]: MHL pack-pixel mode
725 W2BYTEMSK(REG_HDCP_DUAL_P3_09_L, BIT(0), BIT(0)); // PP mode + HDCP eanble
726
727 break;
728 #endif
729
730 default:
731
732 break;
733 };
734 }
735
736 //**************************************************************************
737 // [Function Name]:
738 // _mhal_mhl_RxRtermControl()
739 // [Description]
740 // MHL TMDS termination resistor control
741 // [Arguments]:
742 //
743 // [Return]:
744 //
745 //**************************************************************************
_mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect,RXRtermControl_T rctrl)746 void _mhal_mhl_RxRtermControl(MS_U8 ucCbusSelect, RXRtermControl_T rctrl)
747 {
748 switch(ucCbusSelect)
749 {
750 #if(MHL_FUNCTION_SUPPORT_PORTA)
751 case MHL_CBUS_SELECT_PORTA:
752 if (rctrl == RX_HDMI_RTERM)
753 {
754 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(3:1));// data R-term
755 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term
756 }
757 else if (rctrl == RX_MHL_RTERM)
758 {
759 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(2), BMASK(3:1));// data R-term
760 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(0));// clock R-term
761 }
762 else if (rctrl == RX_RTERM_OFF)
763 {
764 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(3:1), BMASK(3:1));// data R-term
765 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(0), BIT(0));// clock R-term
766 }
767
768 break;
769 #endif
770
771 #if(MHL_FUNCTION_SUPPORT_PORTB)
772 case MHL_CBUS_SELECT_PORTB:
773 if (rctrl == RX_HDMI_RTERM)
774 {
775 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(7:5));// data R-term
776 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term
777 }
778 else if (rctrl == RX_MHL_RTERM)
779 {
780 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(6), BMASK(7:5));// data R-term
781 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(4));// clock R-term
782 }
783 else if (rctrl == RX_RTERM_OFF)
784 {
785 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(7:5), BMASK(7:5));// data R-term
786 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(4), BIT(4));// clock R-term
787 }
788
789 break;
790 #endif
791
792 #if(MHL_FUNCTION_SUPPORT_PORTC)
793 case MHL_CBUS_SELECT_PORTC:
794 if (rctrl == RX_HDMI_RTERM)
795 {
796 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(11:9));// data R-term
797 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term
798 }
799 else if (rctrl == RX_MHL_RTERM)
800 {
801 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(10), BMASK(11:9));// data R-term
802 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(8));// clock R-term
803 }
804 else if (rctrl == RX_RTERM_OFF)
805 {
806 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(11:9), BMASK(11:9));// data R-term
807 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(8), BIT(8));// clock R-term
808 }
809
810 break;
811 #endif
812
813 #if(MHL_FUNCTION_SUPPORT_PORTD)
814 case MHL_CBUS_SELECT_PORTD:
815 if (rctrl == RX_HDMI_RTERM)
816 {
817 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BMASK(15:13));// data R-term
818 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term
819 }
820 else if (rctrl == RX_MHL_RTERM)
821 {
822 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(14), BMASK(15:13));// data R-term
823 W2BYTEMSK(REG_PM_SLEEP_4C_L, 0, BIT(12));// clock R-term
824 }
825 else if (rctrl == RX_RTERM_OFF)
826 {
827 W2BYTEMSK(REG_PM_SLEEP_4C_L, BMASK(15:13), BMASK(15:13));// data R-term
828 W2BYTEMSK(REG_PM_SLEEP_4C_L, BIT(12), BIT(12));// clock R-term
829 }
830
831 break;
832 #endif
833
834 default:
835
836 break;
837 };
838 }
839
840 //**************************************************************************
841 // [Function Name]:
842 // _mhal_mhl_CbusForceToStandby()
843 // [Description]
844 //
845 // [Arguments]:
846 //
847 // [Return]:
848 //
849 //**************************************************************************
_mhal_mhl_CbusForceToStandby(void)850 void _mhal_mhl_CbusForceToStandby(void)
851 {
852 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
853 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(15), BIT(15)); // force enter PM mode
854 }
855
856 //**************************************************************************
857 // [Function Name]:
858 // _mhal_mhl_MHLForceToAttach()
859 // [Description]:
860 //
861 // [Arguments]:
862 //
863 // [Return]:
864 //
865 //**************************************************************************
_mhal_mhl_MHLForceToAttach(void)866 void _mhal_mhl_MHLForceToAttach(void)
867 {
868 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(14), BIT(14));
869 }
870
871 #if(DMHL_LG_PRADA_PATCH)
872 //**************************************************************************
873 // [Function Name]:
874 // _mhal_mhl_AdjustCommonModeResistor()
875 // [Description]:
876 //
877 // [Arguments]:
878 //
879 // [Return]:
880 //
881 //**************************************************************************
_mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect,MS_BOOL bflag)882 void _mhal_mhl_AdjustCommonModeResistor(MS_U8 ucCbusSelect, MS_BOOL bflag)
883 {
884 switch(ucCbusSelect)
885 {
886 #if(MHL_FUNCTION_SUPPORT_PORTA)
887 case MHL_CBUS_SELECT_PORTA:
888 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
889 break;
890 #endif
891
892 #if(MHL_FUNCTION_SUPPORT_PORTB)
893 case MHL_CBUS_SELECT_PORTB:
894 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
895 break;
896 #endif
897
898 #if(MHL_FUNCTION_SUPPORT_PORTC)
899 case MHL_CBUS_SELECT_PORTC:
900 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
901 break;
902 #endif
903
904 #if(MHL_FUNCTION_SUPPORT_PORTD)
905 case MHL_CBUS_SELECT_PORTD:
906 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_27_L, bflag ? 0 : BIT(0), BIT(0)); // [0]: MHL mac enable
907 break;
908 #endif
909
910 default:
911
912 break;
913 };
914 }
915
916 #endif
917
918 //**************************************************************************
919 // [Function Name]:
920 // _mhal_mhl_CheckClockStatus()
921 // [Description]:
922 //
923 // [Arguments]:
924 //
925 // [Return]:
926 //
927 //**************************************************************************
_mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)928 MS_U8 _mhal_mhl_CheckClockStatus(MS_U8 ucCbusSelect)
929 {
930 MS_BOOL bStable = FALSE;
931 MS_U16 usClkCount = 0;
932
933 switch(ucCbusSelect)
934 {
935 #if(MHL_FUNCTION_SUPPORT_PORTA)
936 case MHL_CBUS_SELECT_PORTA:
937 usClkCount = R2BYTE(REG_COMBO_PHY0_P0_3C_L) & 0x0FFF;
938
939 if((R2BYTE(REG_COMBO_PHY0_P0_41_L) &BIT(9)) == BIT(9))
940 {
941 bStable = TRUE;
942
943 if(usClkCount < CBUS_CLOCK_DETECT_LEVEL)
944 {
945 bStable = FALSE;
946 }
947 }
948
949 break;
950 #endif
951
952 #if(MHL_FUNCTION_SUPPORT_PORTB)
953 case MHL_CBUS_SELECT_PORTB:
954 usClkCount = R2BYTE(REG_COMBO_PHY0_P1_3C_L) & 0x0FFF;
955
956 if((R2BYTE(REG_COMBO_PHY0_P1_41_L) &BIT(9)) == BIT(9))
957 {
958 bStable = TRUE;
959
960 if(usClkCount < CBUS_CLOCK_DETECT_LEVEL)
961 {
962 bStable = FALSE;
963 }
964 }
965
966 break;
967 #endif
968
969 #if(MHL_FUNCTION_SUPPORT_PORTC)
970 case MHL_CBUS_SELECT_PORTC:
971 usClkCount = R2BYTE(REG_COMBO_PHY0_P2_3C_L) & 0x0FFF;
972
973 if((R2BYTE(REG_COMBO_PHY0_P2_41_L) &BIT(9)) == BIT(9))
974 {
975 bStable = TRUE;
976
977 if(usClkCount < CBUS_CLOCK_DETECT_LEVEL)
978 {
979 bStable = FALSE;
980 }
981 }
982
983 break;
984 #endif
985
986 #if(MHL_FUNCTION_SUPPORT_PORTD)
987 case MHL_CBUS_SELECT_PORTD:
988 usClkCount = R2BYTE(REG_COMBO_PHY0_P3_3C_L) & 0x0FFF;
989
990 if((R2BYTE(REG_COMBO_PHY0_P3_41_L) &BIT(9)) == BIT(9))
991 {
992 bStable = TRUE;
993
994 if(usClkCount < CBUS_CLOCK_DETECT_LEVEL)
995 {
996 bStable = FALSE;
997 }
998 }
999
1000 break;
1001 #endif
1002
1003 default:
1004 usClkCount = 0;
1005 break;
1006 };
1007
1008 return bStable;
1009 }
1010
1011 //**************************************************************************
1012 // [Function Name]:
1013 // _mhal_mhl_RtermHWControl()
1014 // [Description]
1015 //
1016 // [Arguments]:
1017 //
1018 // [Return]:
1019 //
1020 //**************************************************************************
_mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect,MS_BOOL bFlag)1021 void _mhal_mhl_RtermHWControl(MS_U8 ucCbusSelect, MS_BOOL bFlag)
1022 {
1023 switch(ucCbusSelect)
1024 {
1025 #if(MHL_FUNCTION_SUPPORT_PORTA)
1026 case MHL_CBUS_SELECT_PORTA:
1027 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(8): 0, BIT(8));
1028 break;
1029 #endif
1030
1031 #if(MHL_FUNCTION_SUPPORT_PORTB)
1032 case MHL_CBUS_SELECT_PORTB:
1033 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(9): 0, BIT(9));
1034 break;
1035 #endif
1036
1037 #if(MHL_FUNCTION_SUPPORT_PORTC)
1038 case MHL_CBUS_SELECT_PORTC:
1039 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(10): 0, BIT(10));
1040 break;
1041 #endif
1042
1043 #if(MHL_FUNCTION_SUPPORT_PORTD)
1044 case MHL_CBUS_SELECT_PORTD:
1045 W2BYTEMSK(REG_PM_SLEEP_4A_L, bFlag? BIT(11): 0, BIT(11));
1046 break;
1047 #endif
1048
1049 default:
1050
1051 break;
1052 };
1053 }
1054
1055 //**************************************************************************
1056 // [Function Name]:
1057 // _mhal_mhl_ChangeScalerMainMux()
1058 // [Description]
1059 //
1060 // [Arguments]:
1061 //
1062 // [Return]:
1063 //
1064 //**************************************************************************
_mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)1065 void _mhal_mhl_ChangeScalerMainMux(MS_BOOL bFlag)
1066 {
1067 MS_U8 ucScalerMainMux = (R2BYTE(0x102E02) &BMASK(7:4)) >> 4;
1068
1069 if(bFlag)
1070 {
1071 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI)
1072 {
1073 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_MHL << 4), BMASK(7:4));
1074 }
1075 }
1076 else
1077 {
1078 if(ucScalerMainMux == MHL_SCALER_MUX_SELECT_MHL)
1079 {
1080 W2BYTEMSK(0x102E02, (MHL_SCALER_MUX_SELECT_DVI << 4), BMASK(7:4));
1081 }
1082 }
1083 }
1084
1085 //**************************************************************************
1086 // [Function Name]:
1087 // _mhal_mhl_AudioPathSelect()
1088 // [Description]
1089 //
1090 // [Arguments]:
1091 //
1092 // [Return]:
1093 //
1094 //**************************************************************************
_mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)1095 void _mhal_mhl_AudioPathSelect(MS_BOOL bMHLPath)
1096 {
1097 //W2BYTEMSK(REG_HDMI2_08_L, bMHLPath ?BIT(0) :0, BIT(0)); // [0]: audio source selection, 0: HDMI / 1: MHL
1098 }
1099
1100 //**************************************************************************
1101 // [Function Name]:
1102 // _mhal_mhl_CbusAndClockSelect()
1103 // [Description]
1104 //
1105 // [Arguments]:
1106 //
1107 // [Return]:
1108 //
1109 //**************************************************************************
_mhal_mhl_CbusAndClockSelect(MS_U8 ucCbusSelect)1110 void _mhal_mhl_CbusAndClockSelect(MS_U8 ucCbusSelect)
1111 {
1112 MS_U8 bSupportFlag = FALSE;
1113 MS_U8 ucClockSelect = MHL_DVI_PORT_A;
1114
1115 switch(ucCbusSelect)
1116 {
1117 #if(MHL_FUNCTION_SUPPORT_PORTA)
1118 case MHL_CBUS_SELECT_PORTA:
1119 ucClockSelect = MHL_DVI_PORT_A;
1120 bSupportFlag = TRUE;
1121
1122 W2BYTEMSK(REG_COMBO_PHY0_P0_45_L, 0x6, BMASK(3:0));
1123 W2BYTEMSK(REG_COMBO_PHY0_P0_47_L, 0x33, BMASK(9:0));
1124 W2BYTEMSK(REG_COMBO_PHY1_P0_18_L, 0x361, BMASK(9:0));
1125
1126 break;
1127 #endif
1128
1129 #if(MHL_FUNCTION_SUPPORT_PORTB)
1130 case MHL_CBUS_SELECT_PORTB:
1131 ucClockSelect = MHL_DVI_PORT_B;
1132 bSupportFlag = TRUE;
1133
1134 W2BYTEMSK(REG_COMBO_PHY0_P1_45_L, 0x6, BMASK(3:0));
1135 W2BYTEMSK(REG_COMBO_PHY0_P1_47_L, 0x33, BMASK(9:0));
1136 W2BYTEMSK(REG_COMBO_PHY1_P1_18_L, 0x361, BMASK(9:0));
1137
1138 break;
1139 #endif
1140
1141 #if(MHL_FUNCTION_SUPPORT_PORTC)
1142 case MHL_CBUS_SELECT_PORTC:
1143 ucClockSelect = MHL_DVI_PORT_C;
1144 bSupportFlag = TRUE;
1145
1146 W2BYTEMSK(REG_COMBO_PHY0_P2_45_L, 0x6, BMASK(3:0));
1147 W2BYTEMSK(REG_COMBO_PHY0_P2_47_L, 0x33, BMASK(9:0));
1148 W2BYTEMSK(REG_COMBO_PHY1_P2_18_L, 0x361, BMASK(9:0));
1149
1150 break;
1151 #endif
1152
1153 #if(MHL_FUNCTION_SUPPORT_PORTD)
1154 case MHL_CBUS_SELECT_PORTD:
1155 ucClockSelect = MHL_DVI_PORT_D;
1156 bSupportFlag = TRUE;
1157
1158 W2BYTEMSK(REG_COMBO_PHY0_P3_45_L, 0x6, BMASK(3:0));
1159 W2BYTEMSK(REG_COMBO_PHY0_P3_47_L, 0x33, BMASK(9:0));
1160 W2BYTEMSK(REG_COMBO_PHY1_P3_18_L, 0x361, BMASK(9:0));
1161
1162 break;
1163 #endif
1164
1165 default:
1166
1167 break;
1168 };
1169
1170 if(bSupportFlag)
1171 {
1172 W2BYTEMSK(REG_COMBO_GP_TOP_33_L, ucClockSelect, BMASK(2:0)); // [2:0]: mhl port select
1173 }
1174 }
1175
1176 //**************************************************************************
1177 // [Function Name]:
1178 // _mhal_mhl_ForcePullDown100K()
1179 // [Description]
1180 //
1181 // [Arguments]:
1182 //
1183 // [Return]:
1184 //
1185 //**************************************************************************
_mhal_mhl_ForcePullDown100K(MS_BOOL bEnable)1186 void _mhal_mhl_ForcePullDown100K(MS_BOOL bEnable)
1187 {
1188 W2BYTEMSK(REG_PM_MHL_CBUS_20, bEnable? BIT(7): 0, BIT(7));
1189 }
1190
1191 //**************************************************************************
1192 // [Function Name]:
1193 // _mhal_mhl_GetEMSCOneByteCRC()
1194 // [Description]
1195 //
1196 // [Arguments]:
1197 //
1198 // [Return]:
1199 //
1200 //**************************************************************************
_mhal_mhl_GetEMSCOneByteCRC(MS_U8 ucOpCode)1201 MS_U8 _mhal_mhl_GetEMSCOneByteCRC(MS_U8 ucOpCode)
1202 {
1203 MS_U8 ucAValue = 0;
1204 MS_U8 ucBValue = 0;
1205 MS_U8 ucCommand = BIT(7) |BIT(6) |((ucOpCode &BMASK(2:0)) << 2);
1206
1207 ucAValue = GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BIT(3)) +2;
1208 ucBValue = GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(4)) +GET_BIT(ucCommand &BIT(2)) +2;
1209
1210 if(ucAValue &BIT(0))
1211 {
1212 ucCommand |= BIT(1);
1213 }
1214
1215 if(ucBValue &BIT(0))
1216 {
1217 ucCommand |= BIT(0);
1218 }
1219
1220 return ucCommand;
1221 }
1222
1223 //**************************************************************************
1224 // [Function Name]:
1225 // _mhal_mhl_GetEMSCTwoByteCRC()
1226 // [Description]
1227 //
1228 // [Arguments]:
1229 //
1230 // [Return]:
1231 //
1232 //**************************************************************************
_mhal_mhl_GetEMSCTwoByteCRC(MS_U8 ucOpCode,MS_U8 ucValue)1233 MS_U8 _mhal_mhl_GetEMSCTwoByteCRC(MS_U8 ucOpCode, MS_U8 ucValue)
1234 {
1235 MS_U8 ucAValue = 0;
1236 MS_U8 ucBValue = 0;
1237 MS_U8 ucCValue = 0;
1238 MS_U16 ucCommand = BIT(13) |(((MS_U16)ucOpCode &BMASK(1:0)) << 11) |(((MS_U16)ucValue &BMASK(7:0)) << 3);
1239
1240 ucAValue = GET_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCommand &BIT(11)) +GET_BIT(ucCommand &BIT(8));
1241 ucAValue = ucAValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +GET_BIT(ucCommand &BIT(4)) +3;
1242 ucBValue = GET_BIT(ucCommand &BIT(15)) +GET_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(10)) +GET_BIT(ucCommand &BIT(8));
1243 ucBValue = ucBValue +GET_BIT(ucCommand &BIT(7)) +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(3)) +2;
1244 ucCValue = GET_BIT(ucCommand &BIT(14)) +GET_BIT(ucCommand &BIT(13)) +GET_BIT(ucCommand &BIT(12)) +GET_BIT(ucCommand &BIT(9)) +GET_BIT(ucCommand &BIT(7));
1245 ucCValue = ucCValue +GET_BIT(ucCommand &BIT(6)) +GET_BIT(ucCommand &BIT(5)) +2;
1246
1247 if(ucAValue &BIT(0))
1248 {
1249 ucCommand |= BIT(2);
1250 }
1251
1252 if(ucBValue &BIT(0))
1253 {
1254 ucCommand |= BIT(1);
1255 }
1256
1257 if(ucCValue &BIT(0))
1258 {
1259 ucCommand |= BIT(0);
1260 }
1261
1262 return (ucCommand &BMASK(7:0));
1263 }
1264
1265 //**************************************************************************
1266 // [Function Name]:
1267 // _mhal_mhl_GetEMSCPayloadCRC()
1268 // [Description]
1269 //
1270 // [Arguments]:
1271 //
1272 // [Return]:
1273 //
1274 //**************************************************************************
_mhal_mhl_GetEMSCPayloadCRC(MS_U8 ucOpCode,MS_U16 usCRCValus)1275 MS_U16 _mhal_mhl_GetEMSCPayloadCRC(MS_U8 ucOpCode, MS_U16 usCRCValus)
1276 {
1277 MS_U8 ucAValue = 0;
1278 MS_U8 ucBValue = 0;
1279 MS_U8 ucCValue = GET_BIT(ucOpCode &BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(usCRCValus &BIT(6)) +GET_BIT(usCRCValus &BIT(7));
1280 MS_U8 ucDValue = GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(usCRCValus &BIT(5)) +GET_BIT(usCRCValus &BIT(6));
1281 MS_U8 ucEValue = GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(usCRCValus &BIT(4)) +GET_BIT(usCRCValus &BIT(5));
1282 MS_U8 ucFValue = GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(usCRCValus &BIT(3)) +GET_BIT(usCRCValus &BIT(4));
1283 MS_U8 ucGValue = GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3));
1284 MS_U8 ucHValue = GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2));
1285 MS_U8 ucIValue = GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(15));
1286 MS_U8 ucJValue = GET_BIT(ucOpCode &BIT(0)) +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(14));
1287 MS_U8 ucKValue = GET_BIT(usCRCValus &BIT(13));
1288 MS_U8 ucLValue = GET_BIT(usCRCValus &BIT(12));
1289 MS_U8 ucMValue = GET_BIT(usCRCValus &BIT(11));
1290 MS_U8 ucNValue = GET_BIT(usCRCValus &BIT(10));
1291 MS_U8 ucOValue = GET_BIT(usCRCValus &BIT(9));
1292 MS_U8 ucPValue = 0;
1293 MS_U16 usCommand = 0;
1294
1295 ucAValue = GET_BIT(ucOpCode &BIT(7)) +GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0));
1296 ucAValue = ucAValue +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GET_BIT(usCRCValus &BIT(4)) +GET_BIT(usCRCValus &BIT(5)) +GET_BIT(usCRCValus &BIT(6)) +GET_BIT(usCRCValus &BIT(7));
1297 ucBValue = GET_BIT(ucOpCode &BIT(6)) +GET_BIT(ucOpCode &BIT(5)) +GET_BIT(ucOpCode &BIT(4)) +GET_BIT(ucOpCode &BIT(3)) +GET_BIT(ucOpCode &BIT(2)) +GET_BIT(ucOpCode &BIT(1)) +GET_BIT(ucOpCode &BIT(0));
1298 ucBValue = ucBValue +GET_BIT(usCRCValus &BIT(0)) +GET_BIT(usCRCValus &BIT(1)) +GET_BIT(usCRCValus &BIT(2)) +GET_BIT(usCRCValus &BIT(3)) +GET_BIT(usCRCValus &BIT(4)) +GET_BIT(usCRCValus &BIT(5)) +GET_BIT(usCRCValus &BIT(6));
1299 ucPValue = ucAValue +GET_BIT(usCRCValus &BIT(8));
1300
1301 if(ucAValue &BIT(0))
1302 {
1303 usCommand |= BIT(15);
1304 }
1305
1306 if(ucBValue &BIT(0))
1307 {
1308 usCommand |= BIT(14);
1309 }
1310
1311 if(ucCValue &BIT(0))
1312 {
1313 usCommand |= BIT(13);
1314 }
1315
1316 if(ucDValue &BIT(0))
1317 {
1318 usCommand |= BIT(12);
1319 }
1320
1321 if(ucEValue &BIT(0))
1322 {
1323 usCommand |= BIT(11);
1324 }
1325
1326 if(ucFValue &BIT(0))
1327 {
1328 usCommand |= BIT(10);
1329 }
1330
1331 if(ucGValue &BIT(0))
1332 {
1333 usCommand |= BIT(9);
1334 }
1335
1336 if(ucHValue &BIT(0))
1337 {
1338 usCommand |= BIT(8);
1339 }
1340
1341 if(ucIValue &BIT(0))
1342 {
1343 usCommand |= BIT(7);
1344 }
1345
1346 if(ucJValue &BIT(0))
1347 {
1348 usCommand |= BIT(6);
1349 }
1350
1351 if(ucKValue &BIT(0))
1352 {
1353 usCommand |= BIT(5);
1354 }
1355
1356 if(ucLValue &BIT(0))
1357 {
1358 usCommand |= BIT(4);
1359 }
1360
1361 if(ucMValue &BIT(0))
1362 {
1363 usCommand |= BIT(3);
1364 }
1365
1366 if(ucNValue &BIT(0))
1367 {
1368 usCommand |= BIT(2);
1369 }
1370
1371 if(ucOValue &BIT(0))
1372 {
1373 usCommand |= BIT(1);
1374 }
1375
1376 if(ucPValue &BIT(0))
1377 {
1378 usCommand |= BIT(0);
1379 }
1380
1381 return usCommand;
1382 }
1383
1384 //**************************************************************************
1385 // [Function Name]:
1386 // _mhal_mhl_ECbusInitialSetting()
1387 // [Description]
1388 //
1389 // [Arguments]:
1390 //
1391 // [Return]:
1392 //
1393 //**************************************************************************
_mhal_mhl_ECbusInitialSetting(void)1394 void _mhal_mhl_ECbusInitialSetting(void)
1395 {
1396 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x35, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0]: deglitch after reorder
1397
1398 W2BYTEMSK(REG_MHL_ECBUS_PHY_4C, 0x8880, BMASK(15:4));
1399 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, 0x8B14, BMASK(15:1));
1400 W2BYTEMSK(REG_MHL_ECBUS_PHY_4E, 0x001C, BMASK(15:0));
1401 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, 0x0100, BMASK(15:0));
1402 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0));
1403 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13)); // [14:13]
1404 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13));
1405 W2BYTEMSK(REG_MHL_ECBUS_PHY_55, 0, BMASK(15:4)); //[7:0]
1406 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, 0x00F0, BMASK(15:0)); // [7:4]:reg_ecbss_afe_tx_dri_step
1407 W2BYTEMSK(REG_MHL_ECBUS_PHY_78, BIT(0), BIT(0));
1408
1409 W2BYTEMSK(REG_MHL_ECBUS_0E, 8, BMASK(4:0));
1410 W2BYTEMSK(REG_MHL_ECBUS_2D, BIT(3), BIT(3));
1411
1412 //auto reset turn on
1413 W2BYTEMSK(REG_MHL_ECBUS_PHY_7F, BIT(2), BIT(2)); // [2]:reg_rst_aft_clklck_en
1414 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(4:3), BMASK(4:3)); // [4]:reg_rst_aft_fail_en, [3]:reg_rst_aft_clklck_en
1415
1416 // ECbus initial
1417 W2BYTEMSK(REG_MHL_ECBUS_02, BIT(7), BMASK(13:8)| BIT(7)); // [7]
1418 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(5), BMASK(6:5));
1419 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, 0x700, BMASK(11:8)); // [11:8]:
1420 W2BYTEMSK(REG_MHL_ECBUS_PHY_68, 0x30, BMASK(6:4)); // [6:4]: pre-deglitch
1421 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, 0x50, BMASK(6:4)| BMASK(2:0)); // [6:4]: rasing pattern type, [2:0]: deglitch after reorder
1422 W2BYTEMSK(REG_MHL_ECBUS_PHY_65, 0x08, BMASK(5:0)); // [5:0]: reg_dat_lsb_mask; after analog rwa data deglicth,re-order,the lsb data 1 will be mask
1423
1424 //U02 ECO item setting
1425 W2BYTEMSK(REG_MHL_ECBUS_77, (_mhal_mhl_GetEMSCOneByteCRC(5) << 8)| _mhal_mhl_GetEMSCOneByteCRC(4), BMASK(15:0)); // [15:8]:EMSC neck, [7:0]:EMSC ack
1426 W2BYTEMSK(REG_MHL_ECBUS_78, (_mhal_mhl_GetEMSCOneByteCRC(7) << 8)| _mhal_mhl_GetEMSCOneByteCRC(6), BMASK(15:0)); // [15:8]:Dstart, [7:0]:grant
1427 W2BYTEMSK(REG_MHL_ECBUS_79, BIT(11)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 1) << 3)| (_mhal_mhl_GetEMSCTwoByteCRC(1, 2) << 6), BIT(11)| BMASK(8:6)| BMASK(5:3)); // [8:6]:EMSC errsum cmd CRC, [5:3]:EMSC errCRC cmd CRC
1428 W2BYTEMSK(REG_MHL_ECBUS_PHY_13, BIT(4), BIT(4)); //
1429 W2BYTEMSK(REG_MHL_ECBUS_PHY_51, BIT(11), BIT(11)); //
1430
1431 //eCBUS fsm timing
1432 W2BYTEMSK(REG_MHL_ECBUS_04, 0xE0E, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_sink_cal, [6:0]: reg_t_snk_cal 1; sink sends eCBUS clock after detecting eCBUS clock form source.
1433 W2BYTEMSK(REG_MHL_ECBUS_06, 0x1C00, BMASK(14:8)); // [14:8]: reg_t_snk_tdm;
1434 W2BYTEMSK(REG_MHL_ECBUS_03, BMASK(15:14), BMASK(15:14)); // [15]:reg_wait_tdm_timer_dis [14]:reg_wait_comma2_timer_dis
1435 W2BYTEMSK(REG_MHL_ECBUS_07, 0x104, BMASK(14:8)| BMASK(6:0)); // [14:8]: reg_t_snk_tdm;
1436 W2BYTEMSK(REG_MHL_ECBUS_3F, 0, BMASK(1:0)); //
1437 W2BYTEMSK(REG_MHL_ECBUS_48, 0, BMASK(2:0)); //
1438
1439 //clock detect setting
1440 W2BYTEMSK(REG_MHL_ECBUS_PHY_70, 0x032B, BMASK(15:0)); // [15:0]:reg_crlock_mid; the CR lock reference value
1441 W2BYTEMSK(REG_MHL_ECBUS_PHY_71, 0x0C04, BMASK(15:0)); // [15:8]:reg_crlock_thr, the CR lock reference failure threshold range; [7:0]:reg_crlock_thr, the CR lock reference correct threshold range;
1442 W2BYTEMSK(REG_MHL_ECBUS_PHY_72, 0x0007, BMASK(15:0)); // [12:8]:reg_cr_unlock_num, clock unlock threshold; [4:0]:reg_cr_lock_num; CR lock success threshold time.
1443
1444 #if(MHL_ECBUS_AUTO_TRAINING)
1445 //auto training testing
1446 W2BYTEMSK(REG_MHL_ECBUS_PHY_5C, 0x010A, BMASK(15:0)); // [10:8]:reg_txloc_golden_lowr_tol, [5:0]:reg_txloc_golden_lower,
1447 W2BYTEMSK(REG_MHL_ECBUS_PHY_66, 0x2117, BMASK(15:0)); // [14:12]:reg_txloc_golden2_tol, [10:8]:reg_txloc_rev_golden_tol, [5:0]:reg_txloc_rev_golden
1448 W2BYTEMSK(REG_MHL_ECBUS_PHY_67, 0x0403, BMASK(15:0)); // [14:12]:reg_val_aft_adj_ok, [10:8]:reg_txloc_txdelay_add, [6:4]:reg_flow_retry_r, [2:0]:reg_flow_retry
1449 W2BYTEMSK(REG_MHL_ECBUS_PHY_69, BIT(10), BMASK(11:10)); // [11:10]:reg_txloc_set_time
1450 W2BYTEMSK(REG_MHL_ECBUS_PHY_6A, 0xf117, BMASK(15:0)); // [15:12]:reg_txloc_lck_thr, [10:8]:reg_txloc_golden_tol, [5:0]:ret_txloc_golden
1451 #else
1452 // Skip atop training
1453 // REG_PM_MHL_CBUS2_4A [14]tx_rep_pd_ove = 1 [13]tx_rep_pd_ov [8]:tx_width_ove = 1 [7:4]:tx_width_ov
1454 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(8)| 0x22, BIT(8)| BMASK(7:4));
1455
1456 // REG_PM_MHL_CBUS2_4B ,[14]tx_pd_ove = 1 [13]tx_pd_ov [8]:tx_delay_ove = 1 [7:4]:tx_delay_ov
1457 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(8)| 0x00, BIT(8)| BMASK(7:4));
1458
1459 //W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x8000, BMASK(15:8));
1460 W2BYTEMSK(REG_MHL_ECBUS_PHY_6D, BIT(8), BIT(8));
1461
1462 W2BYTEMSK(REG_MHL_ECBUS_PHY_6C, 0x0000, BMASK(15:0));
1463 //W2BYTEMSK(REG_MHL_ECBUS_04, (30 << 8), BMASK(14:8));
1464 #endif
1465 }
1466
1467 //**************************************************************************
1468 // [Function Name]:
1469 // _mhal_mhl_SetECbusStateChangeInterrupt()
1470 // [Description]
1471 //
1472 // [Arguments]:
1473 //
1474 // [Return]:
1475 //
1476 //**************************************************************************
_mhal_mhl_SetECbusStateChangeInterrupt(MS_BOOL bEnableFlag)1477 void _mhal_mhl_SetECbusStateChangeInterrupt(MS_BOOL bEnableFlag)
1478 {
1479 if(bEnableFlag)
1480 {
1481 W2BYTEMSK(REG_MHL_ECBUS_36, 0, BIT(0)); // Ecbus state change int mask
1482 }
1483 else
1484 {
1485 W2BYTEMSK(REG_MHL_ECBUS_36, BIT(0), BIT(0)); // Ecbus state change int mask
1486 }
1487
1488 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0)); // Ecbus state change int clear
1489 }
1490
1491 //**************************************************************************
1492 // [Function Name]:
1493 // _mhal_mhl_SetEMSCReceiveInterrupt()
1494 // [Description]
1495 //
1496 // [Arguments]:
1497 //
1498 // [Return]:
1499 //
1500 //**************************************************************************
_mhal_mhl_SetEMSCReceiveInterrupt(MS_BOOL bEnableFlag)1501 void _mhal_mhl_SetEMSCReceiveInterrupt(MS_BOOL bEnableFlag)
1502 {
1503 W2BYTEMSK(REG_MHL_ECBUS_36, bEnableFlag? 0: BIT(12), BIT(12)); // eMSC receive int mask
1504 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12)); // eMSC receive int clear
1505 }
1506
1507 //**************************************************************************
1508 // [Function Name]:
1509 // _mhal_mhl_CbusConnectCheckEnable()
1510 // [Description]
1511 //
1512 // [Arguments]:
1513 //
1514 // [Return]:
1515 //
1516 //**************************************************************************
_mhal_mhl_CbusConnectCheckEnable(MS_BOOL bEnableFlag)1517 void _mhal_mhl_CbusConnectCheckEnable(MS_BOOL bEnableFlag)
1518 {
1519 W2BYTEMSK(REG_PM_MHL_CBUS_0B, bEnableFlag? MHL_CBUS_CONNECT_CHECK_VALUE: 0, BMASK(15:0)); // [15:0]: Disable connection check
1520 }
1521
1522 //**************************************************************************
1523 // [Function Name]:
1524 // _mhal_mhl_ECbusEnableSetting()
1525 // [Description]
1526 //
1527 // [Arguments]:
1528 //
1529 // [Return]:
1530 //
1531 //**************************************************************************
_mhal_mhl_ECbusEnableSetting(MS_BOOL bEnableFlag)1532 void _mhal_mhl_ECbusEnableSetting(MS_BOOL bEnableFlag)
1533 {
1534 W2BYTEMSK(REG_MHL_ECBUS_PHY_4D, bEnableFlag? 0: BIT(0), BIT(0)); // ECbus PLL pd
1535 //W2BYTEMSK(REG_MHL_ECBUS_PHY_55, bEnableFlag? 0: BIT(14), BIT(14)); // Rx power down
1536 W2BYTEMSK(REG_MHL_ECBUS_PHY_57, bEnableFlag? BIT(3): BIT(2), BMASK(3:2)); //
1537 W2BYTEMSK(REG_MHL_ECBUS_PHY_6F, bEnableFlag? BIT(8): 0, BIT(8)); // ECbus clock detect
1538 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, bEnableFlag? 0: BIT(13), BIT(13));
1539 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, bEnableFlag? 0: BIT(13), BIT(13));
1540
1541 if(bEnableFlag)
1542 {
1543 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(13), BIT(13)); // [13]: ECbus on
1544 }
1545 else
1546 {
1547 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off
1548 }
1549 }
1550
1551 //**************************************************************************
1552 // [Function Name]:
1553 // _mhal_mhl_ECbusBISTSetting()
1554 // [Description]
1555 //
1556 // [Arguments]:
1557 //
1558 // [Return]:
1559 //
1560 //**************************************************************************
_mhal_mhl_ECbusBISTSetting(MS_BOOL bEnableFlag,stMHL_BIST_MODE_INFO * pBISTParameterInfo)1561 void _mhal_mhl_ECbusBISTSetting(MS_BOOL bEnableFlag, stMHL_BIST_MODE_INFO *pBISTParameterInfo)
1562 {
1563 if(bEnableFlag)
1564 {
1565 if(pBISTParameterInfo->bBISTeCbusRxFlag || pBISTParameterInfo->bBISTeCbusTxFlag)
1566 {
1567 #if(MHL_ECBUS_AUTO_TRAINING)
1568 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13));
1569 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BIT(13));
1570 #else
1571 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(14), BMASK(14:13));
1572 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(14), BMASK(14:13));
1573 #endif
1574 }
1575 else
1576 {
1577 switch(pBISTParameterInfo->ucBISTImpedanceMode)
1578 {
1579 case MHL_BIST_IMPEDANCE_AV_LINK_TX_LOW:
1580 case MHL_BIST_IMPEDANCE_ECBUS_S_RX:
1581 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13));
1582 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13));
1583 break;
1584
1585 case MHL_BIST_IMPEDANCE_AV_LINK_TX_HIGH:
1586 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, BIT(8), BIT(8));
1587 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13));
1588 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, 0, BMASK(14:13));
1589 break;
1590
1591 default:
1592 break;
1593 };
1594 }
1595 }
1596 else
1597 {
1598 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(14), BIT(14)); // [14]: ECbus off
1599
1600 #if(MHL_ECBUS_AUTO_TRAINING)
1601 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));
1602 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BIT(13), BIT(13));
1603 #else
1604 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BMASK(14:13), BMASK(14:13));
1605 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:13), BMASK(14:13));
1606 #endif
1607 W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0, BIT(8));
1608 }
1609 }
1610
1611 //**************************************************************************
1612 // [Function Name]:
1613 // _mhal_mhl_ECbusDmuxEnable()
1614 // [Description]
1615 //
1616 // [Arguments]:
1617 //
1618 // [Return]:
1619 //
1620 //**************************************************************************
_mhal_mhl_ECbusDmuxEnable(MS_BOOL bEnableFlag)1621 void _mhal_mhl_ECbusDmuxEnable(MS_BOOL bEnableFlag)
1622 {
1623 W2BYTEMSK(REG_MHL_ECBUS_PHY_4F, bEnableFlag? BIT(3): 0, BIT(3)); // [3]: Enable ECbus dmux
1624 }
1625
1626 //**************************************************************************
1627 // [Function Name]:
1628 // _mhal_mhl_CbusEngineReset()
1629 // [Description]
1630 //
1631 // [Arguments]:
1632 //
1633 // [Return]:
1634 //
1635 //**************************************************************************
_mhal_mhl_CbusEngineReset(void)1636 void _mhal_mhl_CbusEngineReset(void)
1637 {
1638 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(0), BIT(0));
1639 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(0));
1640 }
1641
1642 //**************************************************************************
1643 // [Function Name]:
1644 // _mhal_mhl_ECbusStateReset()
1645 // [Description]
1646 //
1647 // [Arguments]:
1648 //
1649 // [Return]:
1650 //
1651 //**************************************************************************
_mhal_mhl_ECbusStateReset(void)1652 void _mhal_mhl_ECbusStateReset(void)
1653 {
1654 W2BYTEMSK(REG_MHL_ECBUS_00, BMASK(1:0), BMASK(1:0)); // ECbus state reset
1655 W2BYTEMSK(REG_MHL_ECBUS_00, 0, BMASK(1:0)); // ECbus state reset
1656 }
1657
1658 //**************************************************************************
1659 // [Function Name]:
1660 // _mhal_mhl_SetShortReadAddress()
1661 // [Description]
1662 //
1663 // [Arguments]:
1664 //
1665 // [Return]:
1666 //
1667 //**************************************************************************
_mhal_mhl_SetShortReadAddress(MS_BOOL bECbusEnable)1668 void _mhal_mhl_SetShortReadAddress(MS_BOOL bECbusEnable)
1669 {
1670 W2BYTEMSK(REG_MHL_CBUS_17, bECbusEnable? 0x7000: 0x0800, BMASK(15:8)); // [15:8]: reg_ddc_hdcp_short_read_address
1671 }
1672
1673 //**************************************************************************
1674 // [Function Name]:
1675 // _mhal_mhl_ECbusStateOverwrite()
1676 // [Description]
1677 //
1678 // [Arguments]:
1679 //
1680 // [Return]:
1681 //
1682 //**************************************************************************
_mhal_mhl_ECbusStateOverwrite(MS_BOOL bEnableFlag)1683 void _mhal_mhl_ECbusStateOverwrite(MS_BOOL bEnableFlag)
1684 {
1685 //W2BYTEMSK(REG_MHL_ECBUS_03, bEnableFlag? (BIT(8)| 0x8): 0, BIT(8)| BMASK(3:0));
1686 W2BYTEMSK(REG_MHL_ECBUS_0F, bEnableFlag? (BIT(8)| 0x4): 0, BIT(8)| BMASK(3:0));
1687 }
1688
1689 //**************************************************************************
1690 // [Function Name]:
1691 // _mhal_mhl_Version3PhyEnable()
1692 // [Description]
1693 //
1694 // [Arguments]:
1695 //
1696 // [Return]:
1697 //
1698 //**************************************************************************
_mhal_mhl_Version3PhyEnable(MS_U8 ucCbusSelect,MS_BOOL bEnableFlag)1699 void _mhal_mhl_Version3PhyEnable(MS_U8 ucCbusSelect, MS_BOOL bEnableFlag)
1700 {
1701 switch(ucCbusSelect)
1702 {
1703 #if(MHL_FUNCTION_SUPPORT_PORTA)
1704 case MHL_CBUS_SELECT_PORTA:
1705 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1706 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1707 W2BYTEMSK(REG_COMBO_PHY0_P0_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-control PD
1708 W2BYTEMSK(REG_COMBO_PHY0_P0_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1709
1710 break;
1711 #endif
1712
1713 #if(MHL_FUNCTION_SUPPORT_PORTB)
1714 case MHL_CBUS_SELECT_PORTB:
1715 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1716 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1717 W2BYTEMSK(REG_COMBO_PHY0_P1_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-control PD
1718 W2BYTEMSK(REG_COMBO_PHY0_P1_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1719
1720 break;
1721 #endif
1722
1723 #if(MHL_FUNCTION_SUPPORT_PORTC)
1724 case MHL_CBUS_SELECT_PORTC:
1725 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1726 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1727 W2BYTEMSK(REG_COMBO_PHY0_P2_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-control PD
1728 W2BYTEMSK(REG_COMBO_PHY0_P2_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1729
1730 break;
1731 #endif
1732
1733 #if(MHL_FUNCTION_SUPPORT_PORTD)
1734 case MHL_CBUS_SELECT_PORTD:
1735 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_60_L, bEnableFlag? BMASK(10:8): 0, BMASK(10:8)); // [8]: MHL3 engine enable
1736 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, bEnableFlag? MHL_EQ_30_SETTING_VALUE: MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
1737 W2BYTEMSK(REG_COMBO_PHY0_P3_6C_L, ((bEnableFlag? MHL_ICONTROL_PD_30_VALUE: MHL_ICONTROL_PD_20_VALUE) << 9), BMASK(13:9)); // I-control PD
1738 W2BYTEMSK(REG_COMBO_PHY0_P3_60_L, bEnableFlag? 0: BIT(5), BIT(5));
1739
1740 break;
1741 #endif
1742
1743 default:
1744
1745 break;
1746 };
1747 }
1748
1749 //**************************************************************************
1750 // [Function Name]:
1751 // _mhal_mhl_SetECbusBISTTrigger()
1752 // [Description]
1753 //
1754 // [Arguments]:
1755 //
1756 // [Return]:
1757 //
1758 //**************************************************************************
_mhal_mhl_SetECbusBISTTrigger(MS_BOOL bEnableFlag,MS_BOOL bBISTeCbusTxFlag,MS_BOOL bBISTeCbusRxFlag)1759 void _mhal_mhl_SetECbusBISTTrigger(MS_BOOL bEnableFlag, MS_BOOL bBISTeCbusTxFlag, MS_BOOL bBISTeCbusRxFlag)
1760 {
1761 if(bBISTeCbusTxFlag)
1762 {
1763 if(bEnableFlag)
1764 {
1765 W2BYTEMSK(REG_MHL_ECBUS_3D, BIT(1), BIT(1));
1766 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(12), BMASK(13:12));
1767 }
1768 else
1769 {
1770 W2BYTEMSK(REG_MHL_ECBUS_2A, BIT(13), BMASK(13:12));
1771 W2BYTEMSK(REG_MHL_ECBUS_3D, 0, BIT(1));
1772 }
1773 }
1774
1775 if(bBISTeCbusRxFlag)
1776 {
1777 W2BYTEMSK(REG_MHL_ECBUS_2E, bEnableFlag? BIT(12): BIT(13), BMASK(13:12));
1778 }
1779 }
1780
1781 //**************************************************************************
1782 // [Function Name]:
1783 // _mhal_mhl_ECbusStateChangeProc()
1784 // [Description]
1785 //
1786 // [Arguments]:
1787 //
1788 // [Return]:
1789 //
1790 //**************************************************************************
_mhal_mhl_ECbusStateChangeProc(stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus,stMHL_BIST_MODE_INFO * pBISTParameterInfo)1791 void _mhal_mhl_ECbusStateChangeProc(stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus, stMHL_BIST_MODE_INFO *pBISTParameterInfo)
1792 {
1793 MS_U8 ucECbusTrainState = (R2BYTE(REG_MHL_ECBUS_03) &0xF0) >> 4; // [7:4]: ECbus state
1794
1795 if(ucECbusTrainState != pMHLSignalStatus->ucECbusTrainState)
1796 {
1797 if(ucECbusTrainState == MHL_ECBUS_STATE_ACTIVE)
1798 {
1799 if(pMHLSignalStatus->bBISTEnableFlag)
1800 {
1801 _mhal_mhl_SetECbusBISTTrigger(TRUE, pBISTParameterInfo->bBISTeCbusTxFlag, pBISTParameterInfo->bBISTeCbusRxFlag);
1802 }
1803 }
1804
1805 pMHLSignalStatus->ucECbusTrainState = ucECbusTrainState;
1806 }
1807 }
1808
1809 //**************************************************************************
1810 // [Function Name]:
1811 // _mhal_mhl_ECbusModeUpProc()
1812 // [Description]
1813 //
1814 // [Arguments]:
1815 //
1816 // [Return]:
1817 //
1818 //**************************************************************************
_mhal_mhl_ECbusModeUpProc(void)1819 void _mhal_mhl_ECbusModeUpProc(void)
1820 {
1821 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(4), BIT(4)); // [4]: clear PLL lock status
1822 W2BYTEMSK(REG_MHL_ECBUS_34, 0, BIT(4)); // [4]: clear PLL lock status
1823
1824 //W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0207, BMASK(15:0));
1825 #if(MHL_ECBUS_AUTO_TRAINING)
1826 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));
1827 W2BYTEMSK(REG_MHL_ECBUS_PHY_4B, BMASK(14:12), BMASK(14:12)); // delay
1828 #endif
1829 }
1830
1831 //**************************************************************************
1832 // [Function Name]:
1833 // _mhal_mhl_ECbusModeDownProc()
1834 // [Description]
1835 //
1836 // [Arguments]:
1837 //
1838 // [Return]:
1839 //
1840 //**************************************************************************
_mhal_mhl_ECbusModeDownProc(void)1841 void _mhal_mhl_ECbusModeDownProc(void)
1842 {
1843 //W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0207, BMASK(15:0));
1844 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, BIT(13), BIT(13));
1845 }
1846
1847 //**************************************************************************
1848 // [Function Name]:
1849 // _mhal_mhl_MHL3MuxSetting0()
1850 // [Description]
1851 //
1852 // [Arguments]:
1853 //
1854 // [Return]:
1855 //
1856 //**************************************************************************
_mhal_mhl_MHL3MuxSetting0(MS_BOOL bLinkRate6GFlag)1857 void _mhal_mhl_MHL3MuxSetting0(MS_BOOL bLinkRate6GFlag)
1858 {
1859 W2BYTEMSK(REG_HDMI2_DUAL_0_54_L, bLinkRate6GFlag? 0: BIT(1), BMASK(1:0)); // [1:0]: reg_avg_ctrl_case
1860 }
1861
1862 //**************************************************************************
1863 // [Function Name]:
1864 // _mhal_mhl_GetSRAMReceiveEMSCData()
1865 // [Description]
1866 //
1867 // [Arguments]:
1868 //
1869 // [Return]:
1870 //
1871 //**************************************************************************
_mhal_mhl_GetSRAMReceiveEMSCData(void)1872 MS_U8 _mhal_mhl_GetSRAMReceiveEMSCData(void)
1873 {
1874 W2BYTEMSK(REG_MHL_ECBUS_23, BIT(15), BIT(15));
1875
1876 while((R2BYTE(REG_MHL_ECBUS_23) & BIT(14)) == BIT(14));
1877
1878 return (R2BYTE(REG_MHL_ECBUS_22) &BMASK(7:0));
1879 }
1880
1881 //**************************************************************************
1882 // [Function Name]:
1883 // _mhal_mhl_GetSRAMReceiveEMSCData()
1884 // [Description]
1885 //
1886 // [Arguments]:
1887 //
1888 // [Return]:
1889 //
1890 //**************************************************************************
_mhal_mhl_InsertSRAMSendEMSCData(MS_U8 ucSendEMSC)1891 void _mhal_mhl_InsertSRAMSendEMSCData(MS_U8 ucSendEMSC)
1892 {
1893 W2BYTEMSK(REG_MHL_ECBUS_20, ucSendEMSC, BMASK(7:0));
1894
1895 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(15), BIT(15));
1896
1897 while((R2BYTE(REG_MHL_ECBUS_21) & BIT(14)) == BIT(14));
1898 }
1899
1900 #if(MHL_ECBUS_COMMAND_PARSING)
1901 //**************************************************************************
1902 // [Function Name]:
1903 // _mhal_mhl_ParsingECbusCommand()
1904 // [Description]
1905 //
1906 // [Arguments]:
1907 //
1908 // [Return]:
1909 //
1910 //**************************************************************************
_mhal_mhl_ParsingECbusCommand(MS_U16 * usECbusData)1911 void _mhal_mhl_ParsingECbusCommand(MS_U16 *usECbusData)
1912 {
1913 MS_U8 ucTimes = 0;
1914 MS_U16 ustemp = 0;
1915 MS_U16 usCounnter = 0;
1916 MS_U16 usValue = 0;
1917
1918 for(ustemp = 0; ustemp < MHL_BUFFER_ECBUS_DATA_LENGTH; ustemp++)
1919 {
1920 if((usECbusData[ustemp] &BMASK(7:0)) == 0x39) // Find CBUS1_START
1921 {
1922 ucTimes = 0;
1923
1924 if(usECbusData[ustemp] &BIT(15)) // Send case
1925 {
1926 for(usCounnter = ustemp +1; usCounnter < MHL_BUFFER_ECBUS_DATA_LENGTH; usCounnter++)
1927 {
1928 if(usECbusData[usCounnter] &BIT(15))
1929 {
1930 usValue = usValue << 8;
1931 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0));
1932
1933 ucTimes++;
1934 }
1935
1936 if(ucTimes == 2)
1937 {
1938 usValue = usValue >> 5;
1939 ucTimes = usValue >> 8;
1940
1941 if(ucTimes == 5)
1942 {
1943 MHAL_MHL_MSG_DEBUG(" MHL [SK][MSC][C] = %x\r\n", (usValue &BMASK(7:0)));
1944 }
1945 else if(ucTimes == 4)
1946 {
1947 MHAL_MHL_MSG_DEBUG(" MHL [SK][MSC][D] = %x\r\n", (usValue &BMASK(7:0)));
1948 }
1949 else if(ucTimes == 1)
1950 {
1951 MHAL_MHL_MSG_DEBUG(" MHL [SK][DDC][C] = %x\r\n", (usValue &BMASK(7:0)));
1952 }
1953 else if(ucTimes == 0)
1954 {
1955 MHAL_MHL_MSG_DEBUG(" MHL [SK][DDC][D] = %x\r\n", (usValue &BMASK(7:0)));
1956 }
1957 else
1958 {
1959 MHAL_MHL_MSG_DEBUG(" MHL [SK] unknow = %x\r\n", (usValue &BMASK(7:0)));
1960 }
1961
1962 break;
1963 }
1964 }
1965 }
1966 else // Receive case
1967 {
1968 for(usCounnter = ustemp +1; usCounnter < MHL_BUFFER_ECBUS_DATA_LENGTH; usCounnter++)
1969 {
1970 if((usECbusData[usCounnter] &BIT(15)) == 0)
1971 {
1972 usValue = usValue << 8;
1973 usValue = usValue |(usECbusData[usCounnter] &BMASK(7:0));
1974
1975 ucTimes++;
1976 }
1977
1978 if(ucTimes == 2)
1979 {
1980 usValue = usValue >> 5;
1981 ucTimes = usValue >> 8;
1982
1983 if(ucTimes == 5)
1984 {
1985 MHAL_MHL_MSG_DEBUG(" MHL [SO][MSC][C] = %x\r\n", (usValue &BMASK(7:0)));
1986 }
1987 else if(ucTimes == 4)
1988 {
1989 MHAL_MHL_MSG_DEBUG(" MHL [SO][MSC][D] = %x\r\n", (usValue &BMASK(7:0)));
1990 }
1991 else if(ucTimes == 1)
1992 {
1993 MHAL_MHL_MSG_DEBUG(" MHL [SO][DDC][C] = %x\r\n", (usValue &BMASK(7:0)));
1994 }
1995 else if(ucTimes == 0)
1996 {
1997 MHAL_MHL_MSG_DEBUG(" MHL [SO][DDC][D] = %x\r\n", (usValue &BMASK(7:0)));
1998 }
1999 else
2000 {
2001 MHAL_MHL_MSG_DEBUG(" MHL [SO] unknow = %x\r\n", (usValue &BMASK(7:0)));
2002 }
2003
2004 break;
2005 }
2006 }
2007 }
2008 }
2009 }
2010 }
2011
2012 //**************************************************************************
2013 // [Function Name]:
2014 // _mhal_mhl_GetECbusCommand()
2015 // [Description]
2016 //
2017 // [Arguments]:
2018 //
2019 // [Return]:
2020 //
2021 //**************************************************************************
_mhal_mhl_GetECbusCommand(void)2022 void _mhal_mhl_GetECbusCommand(void)
2023 {
2024 MS_BOOL bReDoFlag = TRUE;
2025 MS_U16 usReceiveData = 0;
2026 MS_U16 usPreReceiveData = 0;
2027 MS_U16 usECbusCData[MHL_BUFFER_ECBUS_DATA_LENGTH] = {0};
2028 MS_U32 ulTimerValue[MHL_BUFFER_ECBUS_DATA_LENGTH] = {0};
2029 MS_U16 ustemp = 0;
2030 MS_U16 usCounnter = 0;
2031 static MS_U32 ulTimeout = 0;
2032
2033 if(ulTimeout < 40000000)
2034 {
2035 do
2036 {
2037 usReceiveData = R2BYTE(REG_MHL_ECBUS_7C);
2038
2039 if(usReceiveData != usPreReceiveData)
2040 {
2041 usECbusCData[ustemp] = usReceiveData;
2042 ulTimerValue[ustemp] = ulTimeout;
2043 ustemp++;
2044
2045 usPreReceiveData = usReceiveData;
2046 bReDoFlag = TRUE;
2047 usCounnter = 0;
2048 }
2049
2050 if(ulTimeout < 40000000)
2051 {
2052 ulTimeout++;
2053 }
2054 else
2055 {
2056 for(usCounnter = 0; usCounnter < ustemp; usCounnter++)
2057 {
2058 MHAL_MHL_MSG_DEBUG(" MHL eCbus data = %x, %d\r\n", usECbusCData[usCounnter], ulTimerValue[usCounnter]);
2059 }
2060
2061 bReDoFlag = FALSE;
2062 ustemp = 0;
2063
2064 //_mhal_mhl_ParsingECbusCommand(usECbusCData);
2065 }
2066 }while(bReDoFlag);
2067 }
2068 }
2069
2070 #endif
2071
2072 //**************************************************************************
2073 // [Function Name]:
2074 // _mhal_mhl_BISTECbusEnable()
2075 // [Description]
2076 //
2077 // [Arguments]:
2078 //
2079 // [Return]:
2080 //
2081 //**************************************************************************
_mhal_mhl_BISTECbusEnable(MS_BOOL bEnableFlag)2082 void _mhal_mhl_BISTECbusEnable(MS_BOOL bEnableFlag)
2083 {
2084 W2BYTEMSK(REG_MHL_ECBUS_7A, bEnableFlag? BIT(5)| BIT(4)| BMASK(3:0): 0, BIT(5)| BIT(4)| BMASK(3:0));
2085 W2BYTEMSK(REG_MHL_ECBUS_06, bEnableFlag? 0x1800: 0x1C00, BMASK(14:8));
2086 W2BYTEMSK(REG_MHL_ECBUS_2D, bEnableFlag? BIT(4): BIT(5), BMASK(5:4));
2087 }
2088
2089 //**************************************************************************
2090 // [Function Name]:
2091 // _mhal_mhl_BISTAVLinkEnable()
2092 // [Description]
2093 //
2094 // [Arguments]:
2095 //
2096 // [Return]:
2097 //
2098 //**************************************************************************
_mhal_mhl_BISTAVLinkEnable(MS_U8 ucCbusSelect,MS_BOOL bEnableFlag)2099 void _mhal_mhl_BISTAVLinkEnable(MS_U8 ucCbusSelect, MS_BOOL bEnableFlag)
2100 {
2101 switch(ucCbusSelect)
2102 {
2103 #if(MHL_FUNCTION_SUPPORT_PORTA)
2104 case MHL_CBUS_SELECT_PORTA:
2105 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0));
2106
2107 if(bEnableFlag)
2108 {
2109 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, BIT(1), BIT(1));
2110 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_76_L, 0, BIT(1));
2111 }
2112
2113 break;
2114 #endif
2115
2116 #if(MHL_FUNCTION_SUPPORT_PORTB)
2117 case MHL_CBUS_SELECT_PORTB:
2118 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0));
2119
2120 if(bEnableFlag)
2121 {
2122 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, BIT(1), BIT(1));
2123 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_76_L, 0, BIT(1));
2124 }
2125
2126 break;
2127 #endif
2128
2129 #if(MHL_FUNCTION_SUPPORT_PORTC)
2130 case MHL_CBUS_SELECT_PORTC:
2131 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0));
2132
2133 if(bEnableFlag)
2134 {
2135 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, BIT(1), BIT(1));
2136 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_76_L, 0, BIT(1));
2137 }
2138
2139 break;
2140 #endif
2141
2142 #if(MHL_FUNCTION_SUPPORT_PORTD)
2143 case MHL_CBUS_SELECT_PORTD:
2144 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, bEnableFlag? BIT(0): BIT(2), BIT(2)| BIT(0));
2145
2146 if(bEnableFlag)
2147 {
2148 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, BIT(1), BIT(1));
2149 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_76_L, 0, BIT(1));
2150 }
2151
2152 break;
2153 #endif
2154
2155 default:
2156
2157 break;
2158 };
2159 }
2160
2161 //**************************************************************************
2162 // [Function Name]:
2163 // _mhal_mhl_GetBISTECbusErrorCount()
2164 // [Description]
2165 //
2166 // [Arguments]:
2167 //
2168 // [Return]:
2169 //
2170 //**************************************************************************
_mhal_mhl_GetBISTECbusErrorCount(void)2171 MS_U16 _mhal_mhl_GetBISTECbusErrorCount(void)
2172 {
2173 MS_U16 ucECbusErrorCount = 0;
2174
2175 if(R2BYTE(REG_MHL_ECBUS_30) &BIT(15))
2176 {
2177 ucECbusErrorCount = R2BYTE(REG_MHL_ECBUS_31);
2178 MHAL_MHL_MSG_DEBUG("** MHL eCbus error count vaild %x\r\n", ucECbusErrorCount);
2179 }
2180
2181 return ucECbusErrorCount;
2182 }
2183
2184 //**************************************************************************
2185 // [Function Name]:
2186 // _mhal_mhl_GetBISTAVLinkErrorCount()
2187 // [Description]
2188 //
2189 // [Arguments]:
2190 //
2191 // [Return]:
2192 //
2193 //**************************************************************************
_mhal_mhl_GetBISTAVLinkErrorCount(MS_U8 ucCbusSelect)2194 MS_U16 _mhal_mhl_GetBISTAVLinkErrorCount(MS_U8 ucCbusSelect)
2195 {
2196 MS_U16 ucAVLinkErrorCount = 0;
2197
2198 switch(ucCbusSelect)
2199 {
2200 #if(MHL_FUNCTION_SUPPORT_PORTA)
2201 case MHL_CBUS_SELECT_PORTA:
2202 ucAVLinkErrorCount = R2BYTE(REG_DVI_DTOP_DUAL_P0_73_L);
2203
2204 break;
2205 #endif
2206
2207 #if(MHL_FUNCTION_SUPPORT_PORTB)
2208 case MHL_CBUS_SELECT_PORTB:
2209 ucAVLinkErrorCount = R2BYTE(REG_DVI_DTOP_DUAL_P1_73_L);
2210
2211 break;
2212 #endif
2213
2214 #if(MHL_FUNCTION_SUPPORT_PORTC)
2215 case MHL_CBUS_SELECT_PORTC:
2216 ucAVLinkErrorCount = R2BYTE(REG_DVI_DTOP_DUAL_P2_73_L);
2217
2218 break;
2219 #endif
2220
2221 #if(MHL_FUNCTION_SUPPORT_PORTD)
2222 case MHL_CBUS_SELECT_PORTD:
2223 ucAVLinkErrorCount = R2BYTE(REG_DVI_DTOP_DUAL_P3_73_L);
2224
2225 break;
2226 #endif
2227
2228 default:
2229
2230 break;
2231 };
2232
2233 return ucAVLinkErrorCount;
2234 }
2235
2236 //**************************************************************************
2237 // [Function Name]:
2238 // _mhal_mhl_CheckDEChangeFlag()
2239 // [Description]
2240 //
2241 // [Arguments]:
2242 //
2243 // [Return]:
2244 //
2245 //**************************************************************************
_mhal_mhl_CheckDEChangeFlag(void)2246 MS_BOOL _mhal_mhl_CheckDEChangeFlag(void)
2247 {
2248 MS_BOOL bDEChangeFlag = ((R2BYTE(REG_HDMI_DUAL_0_02_L) & BIT(5)) ? TRUE : FALSE);
2249 static MS_U8 ucStableCount = 0;
2250
2251 if(bDEChangeFlag)
2252 {
2253 W2BYTE(REG_HDMI_DUAL_0_02_L, BIT(5));
2254
2255 ucStableCount = 0;
2256 }
2257 else if(ucStableCount <= 10)
2258 {
2259 ucStableCount++;
2260 }
2261
2262 if(ucStableCount == 10)
2263 {
2264 bDEChangeFlag = TRUE;
2265 }
2266 else
2267 {
2268 bDEChangeFlag = FALSE;
2269 }
2270
2271 return bDEChangeFlag;
2272 }
2273
2274 //**************************************************************************
2275 // [Function Name]:
2276 // _mhal_mhl_MHL30AutoEQSetting()
2277 // [Description]
2278 //
2279 // [Arguments]:
2280 //
2281 // [Return]:
2282 //
2283 //**************************************************************************
_mhal_mhl_MHL30AutoEQSetting(MS_U8 ucCbusSelect)2284 void _mhal_mhl_MHL30AutoEQSetting(MS_U8 ucCbusSelect)
2285 {
2286 switch(ucCbusSelect)
2287 {
2288 #if(MHL_FUNCTION_SUPPORT_PORTA)
2289 case MHL_CBUS_SELECT_PORTA:
2290 W2BYTEMSK(REG_COMBO_PHY1_P0_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0));
2291 W2BYTEMSK(REG_COMBO_PHY1_P0_49_L, BIT(5), BIT(5));
2292 W2BYTEMSK(REG_COMBO_PHY0_P0_29_L, BIT(8), BMASK(15:0));
2293 W2BYTEMSK(REG_COMBO_PHY1_P0_11_L, BIT(4), BIT(4));
2294 W2BYTEMSK(REG_COMBO_PHY1_P0_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0));
2295 W2BYTEMSK(REG_COMBO_PHY1_P0_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0));
2296 W2BYTEMSK(REG_COMBO_PHY1_P0_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0));
2297 W2BYTEMSK(REG_COMBO_PHY1_P0_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0));
2298 W2BYTEMSK(REG_COMBO_PHY0_P0_26_L, BIT(11)| BIT(9), BMASK(13:8));
2299
2300 break;
2301 #endif
2302
2303 #if(MHL_FUNCTION_SUPPORT_PORTB)
2304 case MHL_CBUS_SELECT_PORTB:
2305 W2BYTEMSK(REG_COMBO_PHY1_P1_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0));
2306 W2BYTEMSK(REG_COMBO_PHY1_P1_49_L, BIT(5), BIT(5));
2307 W2BYTEMSK(REG_COMBO_PHY0_P1_29_L, BIT(8), BMASK(15:0));
2308 W2BYTEMSK(REG_COMBO_PHY1_P1_11_L, BIT(4), BIT(4));
2309 W2BYTEMSK(REG_COMBO_PHY1_P1_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0));
2310 W2BYTEMSK(REG_COMBO_PHY1_P1_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0));
2311 W2BYTEMSK(REG_COMBO_PHY1_P1_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0));
2312 W2BYTEMSK(REG_COMBO_PHY1_P1_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0));
2313 W2BYTEMSK(REG_COMBO_PHY0_P1_26_L, BIT(11)| BIT(9), BMASK(13:8));
2314
2315 break;
2316 #endif
2317
2318 #if(MHL_FUNCTION_SUPPORT_PORTC)
2319 case MHL_CBUS_SELECT_PORTC:
2320 W2BYTEMSK(REG_COMBO_PHY1_P2_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0));
2321 W2BYTEMSK(REG_COMBO_PHY1_P2_49_L, BIT(5), BIT(5));
2322 W2BYTEMSK(REG_COMBO_PHY0_P2_29_L, BIT(8), BMASK(15:0));
2323 W2BYTEMSK(REG_COMBO_PHY1_P2_11_L, BIT(4), BIT(4));
2324 W2BYTEMSK(REG_COMBO_PHY1_P2_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0));
2325 W2BYTEMSK(REG_COMBO_PHY1_P2_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0));
2326 W2BYTEMSK(REG_COMBO_PHY1_P2_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0));
2327 W2BYTEMSK(REG_COMBO_PHY1_P2_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0));
2328 W2BYTEMSK(REG_COMBO_PHY0_P2_26_L, BIT(11)| BIT(9), BMASK(13:8));
2329
2330 break;
2331 #endif
2332
2333 #if(MHL_FUNCTION_SUPPORT_PORTD)
2334 case MHL_CBUS_SELECT_PORTD:
2335 W2BYTEMSK(REG_COMBO_PHY1_P3_45_L, MHL_COARSE_TUNE_30_MIN, BMASK(4:0));
2336 W2BYTEMSK(REG_COMBO_PHY1_P3_49_L, BIT(5), BIT(5));
2337 W2BYTEMSK(REG_COMBO_PHY0_P3_29_L, BIT(8), BMASK(15:0));
2338 W2BYTEMSK(REG_COMBO_PHY1_P3_11_L, BIT(4), BIT(4));
2339 W2BYTEMSK(REG_COMBO_PHY1_P3_42_L, MHL_COARSE_TUNE_30_DETECT_TIME, BMASK(15:0));
2340 W2BYTEMSK(REG_COMBO_PHY1_P3_4A_L, MHL_COARSE_TUNE_30_AABA_NUMBER, BMASK(15:0));
2341 W2BYTEMSK(REG_COMBO_PHY1_P3_4B_L, MHL_FINE_TUNE_AABA_30_NUMBER, BMASK(15:0));
2342 W2BYTEMSK(REG_COMBO_PHY1_P3_4C_L, MHL_FINE_TUNE_UNDER_30_THRESHOLD, BMASK(15:0));
2343 W2BYTEMSK(REG_COMBO_PHY0_P3_26_L, BIT(11)| BIT(9), BMASK(13:8));
2344
2345 break;
2346 #endif
2347
2348 default:
2349
2350 break;
2351 };
2352 }
2353
2354 //**************************************************************************
2355 // [Function Name]:
2356 // _mhal_mhl_MHL3AutoEQTrigger()
2357 // [Description]
2358 //
2359 // [Arguments]:
2360 //
2361 // [Return]:
2362 //
2363 //**************************************************************************
_mhal_mhl_MHL3AutoEQTrigger(MS_U8 ucCbusSelect)2364 void _mhal_mhl_MHL3AutoEQTrigger(MS_U8 ucCbusSelect)
2365 {
2366 MS_U16 ustemp = 1000;
2367
2368 switch(ucCbusSelect)
2369 {
2370 #if(MHL_FUNCTION_SUPPORT_PORTA)
2371 case MHL_CBUS_SELECT_PORTA:
2372 W2BYTEMSK(REG_COMBO_PHY0_P0_33_L, BIT(2), BIT(2));
2373
2374 while(ustemp--);
2375
2376 W2BYTEMSK(REG_COMBO_PHY0_P0_33_L, 0, BIT(2));
2377
2378 break;
2379 #endif
2380
2381 #if(MHL_FUNCTION_SUPPORT_PORTB)
2382 case MHL_CBUS_SELECT_PORTB:
2383 W2BYTEMSK(REG_COMBO_PHY0_P1_33_L, BIT(2), BIT(2));
2384
2385 while(ustemp--);
2386
2387 W2BYTEMSK(REG_COMBO_PHY0_P1_33_L, 0, BIT(2));
2388
2389 break;
2390 #endif
2391
2392 #if(MHL_FUNCTION_SUPPORT_PORTC)
2393 case MHL_CBUS_SELECT_PORTC:
2394 W2BYTEMSK(REG_COMBO_PHY0_P2_33_L, BIT(2), BIT(2));
2395
2396 while(ustemp--);
2397
2398 W2BYTEMSK(REG_COMBO_PHY0_P2_33_L, 0, BIT(2));
2399
2400 break;
2401 #endif
2402
2403 #if(MHL_FUNCTION_SUPPORT_PORTD)
2404 case MHL_CBUS_SELECT_PORTD:
2405 W2BYTEMSK(REG_COMBO_PHY0_P3_33_L, BIT(2), BIT(2));
2406
2407 while(ustemp--);
2408
2409 W2BYTEMSK(REG_COMBO_PHY0_P3_33_L, 0, BIT(2));
2410
2411 break;
2412 #endif
2413
2414 default:
2415 ustemp = 0;
2416 break;
2417 };
2418 }
2419
2420 //**************************************************************************
2421 // [Function Name]:
2422 // _mhal_mhl_GetAutoEQDoneFlag()
2423 // [Description]
2424 //
2425 // [Arguments]:
2426 //
2427 // [Return]:
2428 //
2429 //**************************************************************************
_mhal_mhl_GetAutoEQDoneFlag(MS_U8 ucCbusSelect)2430 MS_BOOL _mhal_mhl_GetAutoEQDoneFlag(MS_U8 ucCbusSelect)
2431 {
2432 MS_BOOL bAutoEQDone = FALSE;
2433
2434 switch(ucCbusSelect)
2435 {
2436 #if(MHL_FUNCTION_SUPPORT_PORTA)
2437 case MHL_CBUS_SELECT_PORTA:
2438 W2BYTEMSK(REG_COMBO_PHY0_P0_41_L, 0, BMASK(15:14));
2439
2440 if(R2BYTE(REG_COMBO_PHY0_P0_41_L) &BIT(8))
2441 {
2442 bAutoEQDone = TRUE;
2443 }
2444
2445 break;
2446 #endif
2447
2448 #if(MHL_FUNCTION_SUPPORT_PORTB)
2449 case MHL_CBUS_SELECT_PORTB:
2450 W2BYTEMSK(REG_COMBO_PHY0_P1_41_L, 0, BMASK(15:14));
2451
2452 if(R2BYTE(REG_COMBO_PHY0_P1_41_L) &BIT(8))
2453 {
2454 bAutoEQDone = TRUE;
2455 }
2456
2457 break;
2458 #endif
2459
2460 #if(MHL_FUNCTION_SUPPORT_PORTC)
2461 case MHL_CBUS_SELECT_PORTC:
2462 W2BYTEMSK(REG_COMBO_PHY0_P2_41_L, 0, BMASK(15:14));
2463
2464 if(R2BYTE(REG_COMBO_PHY0_P2_41_L) &BIT(8))
2465 {
2466 bAutoEQDone = TRUE;
2467 }
2468
2469 break;
2470 #endif
2471
2472 #if(MHL_FUNCTION_SUPPORT_PORTD)
2473 case MHL_CBUS_SELECT_PORTD:
2474 W2BYTEMSK(REG_COMBO_PHY0_P3_41_L, 0, BMASK(15:14));
2475
2476 if(R2BYTE(REG_COMBO_PHY0_P3_41_L) &BIT(8))
2477 {
2478 bAutoEQDone = TRUE;
2479 }
2480
2481 break;
2482 #endif
2483
2484 default:
2485
2486 break;
2487 };
2488
2489 return bAutoEQDone;
2490 }
2491
2492 //**************************************************************************
2493 // [Function Name]:
2494 // _mhal_mhl_MHL30AutoEQEnable()
2495 // [Description]
2496 //
2497 // [Arguments]:
2498 //
2499 // [Return]:
2500 //
2501 //**************************************************************************
_mhal_mhl_MHL30AutoEQEnable(MS_U8 ucCbusSelect,MS_BOOL bAutoEQEnable)2502 void _mhal_mhl_MHL30AutoEQEnable(MS_U8 ucCbusSelect, MS_BOOL bAutoEQEnable)
2503 {
2504 MS_BOOL bAutoEQTrigger = FALSE;
2505
2506 switch(ucCbusSelect)
2507 {
2508 #if(MHL_FUNCTION_SUPPORT_PORTA)
2509 case MHL_CBUS_SELECT_PORTA:
2510 if(bAutoEQEnable) // Disable overwrite EQ, then enable auto EQ and trigger auto EQ
2511 {
2512 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, 0, BMASK(7:4));
2513 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, BIT(2), BIT(2));
2514
2515 bAutoEQTrigger = TRUE;
2516 }
2517 else // Disable auto EQ, then overwrite EQ
2518 {
2519 W2BYTEMSK(REG_COMBO_PHY0_P0_25_L, 0, BIT(2));
2520 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BMASK(7:4), BMASK(7:4));
2521 W2BYTEMSK(REG_COMBO_PHY0_P0_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
2522 }
2523
2524 W2BYTEMSK(REG_COMBO_PHY0_P0_15_L, bAutoEQEnable? BIT(15): 0, BIT(15));
2525 W2BYTEMSK(REG_COMBO_PHY1_P0_44_L, bAutoEQEnable? 0: BIT(0), BIT(0));
2526 W2BYTEMSK(REG_COMBO_PHY1_P0_49_L, bAutoEQEnable? 0: BIT(5), BIT(5));
2527 W2BYTEMSK(REG_COMBO_PHY1_P0_11_L, bAutoEQEnable? 0: BIT(4), BIT(4));
2528
2529 break;
2530 #endif
2531
2532 #if(MHL_FUNCTION_SUPPORT_PORTB)
2533 case MHL_CBUS_SELECT_PORTB:
2534 if(bAutoEQEnable) // Disable overwrite EQ, then enable auto EQ and trigger auto EQ
2535 {
2536 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, 0, BMASK(7:4));
2537 W2BYTEMSK(REG_COMBO_PHY0_P1_25_L, BIT(2), BIT(2));
2538
2539 bAutoEQTrigger = TRUE;
2540 }
2541 else // Disable auto EQ, then overwrite EQ
2542 {
2543 W2BYTEMSK(REG_COMBO_PHY0_P1_25_L, 0, BIT(2));
2544 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BMASK(7:4), BMASK(7:4));
2545 W2BYTEMSK(REG_COMBO_PHY0_P1_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
2546 }
2547
2548 W2BYTEMSK(REG_COMBO_PHY0_P1_15_L, bAutoEQEnable? BIT(15): 0, BIT(15));
2549 W2BYTEMSK(REG_COMBO_PHY1_P1_44_L, bAutoEQEnable? 0: BIT(0), BIT(0));
2550 W2BYTEMSK(REG_COMBO_PHY1_P1_49_L, bAutoEQEnable? 0: BIT(5), BIT(5));
2551 W2BYTEMSK(REG_COMBO_PHY1_P1_11_L, bAutoEQEnable? 0: BIT(4), BIT(4));
2552
2553 break;
2554 #endif
2555
2556 #if(MHL_FUNCTION_SUPPORT_PORTC)
2557 case MHL_CBUS_SELECT_PORTC:
2558 if(bAutoEQEnable) // Disable overwrite EQ, then enable auto EQ and trigger auto EQ
2559 {
2560 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, 0, BMASK(7:4));
2561 W2BYTEMSK(REG_COMBO_PHY0_P2_25_L, BIT(2), BIT(2));
2562
2563 bAutoEQTrigger = TRUE;
2564 }
2565 else // Disable auto EQ, then overwrite EQ
2566 {
2567 W2BYTEMSK(REG_COMBO_PHY0_P2_25_L, 0, BIT(2));
2568 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BMASK(7:4), BMASK(7:4));
2569 W2BYTEMSK(REG_COMBO_PHY0_P2_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
2570 }
2571
2572 W2BYTEMSK(REG_COMBO_PHY0_P2_15_L, bAutoEQEnable? BIT(15): 0, BIT(15));
2573 W2BYTEMSK(REG_COMBO_PHY1_P2_44_L, bAutoEQEnable? 0: BIT(0), BIT(0));
2574 W2BYTEMSK(REG_COMBO_PHY1_P2_49_L, bAutoEQEnable? 0: BIT(5), BIT(5));
2575 W2BYTEMSK(REG_COMBO_PHY1_P2_11_L, bAutoEQEnable? 0: BIT(4), BIT(4));
2576
2577 break;
2578 #endif
2579
2580 #if(MHL_FUNCTION_SUPPORT_PORTD)
2581 case MHL_CBUS_SELECT_PORTD:
2582 if(bAutoEQEnable) // Disable overwrite EQ, then enable auto EQ and trigger auto EQ
2583 {
2584 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BMASK(7:4));
2585 W2BYTEMSK(REG_COMBO_PHY0_P3_25_L, BIT(2), BIT(2));
2586
2587 bAutoEQTrigger = TRUE;
2588 }
2589 else // Disable auto EQ, then overwrite EQ
2590 {
2591 W2BYTEMSK(REG_COMBO_PHY0_P3_25_L, 0, BIT(2));
2592 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BMASK(7:4), BMASK(7:4));
2593 W2BYTEMSK(REG_COMBO_PHY0_P3_73_L, MHL_EQ_20_SETTING_VALUE, BMASK(4:0)); // B channel EQ
2594 }
2595
2596 W2BYTEMSK(REG_COMBO_PHY0_P3_15_L, bAutoEQEnable? BIT(15): 0, BIT(15));
2597 W2BYTEMSK(REG_COMBO_PHY1_P3_44_L, bAutoEQEnable? 0: BIT(0), BIT(0));
2598 W2BYTEMSK(REG_COMBO_PHY1_P3_49_L, bAutoEQEnable? 0: BIT(5), BIT(5));
2599 W2BYTEMSK(REG_COMBO_PHY1_P3_11_L, bAutoEQEnable? 0: BIT(4), BIT(4));
2600
2601 break;
2602 #endif
2603
2604 default:
2605
2606 break;
2607 };
2608
2609 if(bAutoEQTrigger)
2610 {
2611 _mhal_mhl_GetAutoEQDoneFlag(ucCbusSelect);
2612 _mhal_mhl_MHL3AutoEQTrigger(ucCbusSelect);
2613 }
2614 }
2615
2616 //-------------------------------------------------------------------------------------------------
2617 // Global Functions
2618 //-------------------------------------------------------------------------------------------------
2619
2620 //**************************************************************************
2621 // [Function Name]:
2622 // mhal_mhl_SetRegisterBaseAddress()
2623 // [Description]
2624 //
2625 // [Arguments]:
2626 //
2627 // [Return]:
2628 //
2629 //**************************************************************************
mhal_mhl_SetRegisterBaseAddress(MS_VIRT ulRiuBassAddress,MS_VIRT ulPMRiuBassAddress)2630 void mhal_mhl_SetRegisterBaseAddress(MS_VIRT ulRiuBassAddress, MS_VIRT ulPMRiuBassAddress)
2631 {
2632 MHL_XC_RIU_BASE = ulPMRiuBassAddress;
2633 MHL_PM_RIU_BASE = ulPMRiuBassAddress;
2634
2635 ulRiuBassAddress = ulPMRiuBassAddress;
2636 }
2637
2638 //**************************************************************************
2639 // [Function Name]:
2640 // mhal_mhl_GetCbusSelect()
2641 // [Description]
2642 //
2643 // [Arguments]:
2644 //
2645 // [Return]:
2646 //
2647 //**************************************************************************
mhal_mhl_GetCbusSelect(MS_U8 ucPort)2648 MS_U8 mhal_mhl_GetCbusSelect(MS_U8 ucPort)
2649 {
2650 MS_U8 uctemp = MHL_CBUS_SELECT_MASK;
2651
2652 switch(ucPort)
2653 {
2654 case MHL_DVI_PORT_A:
2655 uctemp = MHL_CBUS_SELECT_PORTA;
2656 break;
2657
2658 case MHL_DVI_PORT_B:
2659 uctemp = MHL_CBUS_SELECT_PORTB;
2660 break;
2661
2662 case MHL_DVI_PORT_C:
2663 uctemp = MHL_CBUS_SELECT_PORTC;
2664 break;
2665
2666 case MHL_DVI_PORT_D:
2667 uctemp = MHL_CBUS_SELECT_PORTD;
2668 break;
2669
2670 default:
2671
2672 break;
2673 };
2674
2675 return uctemp;
2676 }
2677
2678 //**************************************************************************
2679 // [Function Name]:
2680 // mhal_mhl_GetInputPort()
2681 // [Description]
2682 // MHL get current input port
2683 // [Arguments]:
2684 //
2685 // [Return]:
2686 //
2687 //**************************************************************************
mhal_mhl_GetInputPort(void)2688 MS_U8 mhal_mhl_GetInputPort(void)
2689 {
2690 return (R2BYTE(REG_HDMI2_DUAL_0_50_L) &BMASK(1:0));
2691 }
2692
2693 //**************************************************************************
2694 // [Function Name]:
2695 // mhal_mhl_CheckInputPort()
2696 // [Description]
2697 // MHL check current input port
2698 // [Arguments]:
2699 //
2700 // [Return]:
2701 //
2702 //**************************************************************************
mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)2703 MS_BOOL mhal_mhl_CheckInputPort(MS_U8 ucCbusSelect)
2704 {
2705 MS_BOOL bindex = FALSE;
2706
2707 if(mhal_mhl_GetCbusSelect(mhal_mhl_GetInputPort()) == ucCbusSelect)
2708 {
2709 bindex = TRUE;
2710 }
2711
2712 return bindex;
2713 }
2714
2715 //**************************************************************************
2716 // [Function Name]:
2717 // mhal_mhl_CheckPIPWindow()
2718 // [Description]
2719 //
2720 // [Arguments]:
2721 //
2722 // [Return]:
2723 //
2724 //**************************************************************************
mhal_mhl_CheckPIPWindow(void)2725 MS_BOOL mhal_mhl_CheckPIPWindow(void)
2726 {
2727 MS_BOOL bFlag = FALSE;
2728 MS_U8 ucScalerMainMux = R2BYTE(0x102E02) &BMASK(7:0);
2729 MS_U8 ucScalerSubMux = ucScalerMainMux &BMASK(3:0);
2730
2731 ucScalerMainMux = (ucScalerMainMux &BMASK(7:4)) >> 4;
2732
2733 if((ucScalerMainMux == MHL_SCALER_MUX_SELECT_DVI) || (ucScalerSubMux == MHL_SCALER_MUX_SELECT_DVI))
2734 {
2735 bFlag = TRUE;
2736 }
2737
2738 return bFlag;
2739 }
2740
2741 //**************************************************************************
2742 // [Function Name]:
2743 // mhal_mhl_MHLSupportPath()
2744 // [Description]
2745 // MHL support path
2746 // [Arguments]:
2747 //
2748 // [Return]:
2749 //
2750 //**************************************************************************
mhal_mhl_MHLSupportPath(MS_U8 ucSelect)2751 void mhal_mhl_MHLSupportPath(MS_U8 ucSelect)
2752 {
2753 if(ucSelect > 0)
2754 {
2755 W2BYTEMSK(REG_PM_SLEEP_72_L, BMASK(7:6), BMASK(8:6)); // [8]: reg_cbus_debug_sel, [7]: reg_vbus_en_sel , [6]: reg_mhl_cable_detect_sel
2756 }
2757 }
2758
2759 //**************************************************************************
2760 // [Function Name]:
2761 // mhal_mhl_CheckEfuseControlFlag()
2762 // [Description]
2763 //
2764 // [Arguments]:
2765 //
2766 // [Return]:
2767 //
2768 //**************************************************************************
mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)2769 MS_BOOL mhal_mhl_CheckEfuseControlFlag(MS_BOOL bEfuseFlag)
2770 {
2771 MS_BOOL bFlag = FALSE;
2772
2773 #if(MHL_EFUSE_FUNCTION_CONTROL)
2774 MS_U8 uctemp = 0;
2775
2776 if(!bEfuseFlag)
2777 {
2778 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
2779 {
2780 mhal_mhl_CbusIsolate(uctemp, TRUE);
2781 }
2782
2783 bFlag = TRUE;
2784 }
2785
2786 #endif
2787
2788 return bFlag;
2789 }
2790
2791 //**************************************************************************
2792 // [Function Name]:
2793 // mhal_mhl_InsertChipIDforCheck()
2794 // [Description]
2795 //
2796 // [Arguments]:
2797 //
2798 // [Return]:
2799 //
2800 //**************************************************************************
mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)2801 void mhal_mhl_InsertChipIDforCheck(MS_U8 ucChipID)
2802 {
2803 ucChipIDValue = ucChipID;
2804
2805 MHAL_MHL_MSG_INFO("** MHL Cbus index value %x\r\n", ucChipID);
2806 }
2807
2808 //**************************************************************************
2809 // [Function Name]:
2810 // mhal_mhl_CableDetect()
2811 // [Description]
2812 // MHL cable detection
2813 // [Arguments]:
2814 //
2815 // [Return]:
2816 // TRUE: MHL cable plugged
2817 // FALSE: MHL cable unplugged
2818 //**************************************************************************
mhal_mhl_CableDetect(MS_U8 ucCbusSelect)2819 MS_BOOL mhal_mhl_CableDetect(MS_U8 ucCbusSelect)
2820 {
2821 MS_BOOL bFlag = FALSE;
2822
2823 switch(ucCbusSelect)
2824 {
2825 #if(MHL_FUNCTION_SUPPORT_PORTA)
2826 case MHL_CBUS_SELECT_PORTA:
2827 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
2828 break;
2829 #endif
2830
2831 #if(MHL_FUNCTION_SUPPORT_PORTB)
2832 case MHL_CBUS_SELECT_PORTB:
2833 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
2834 break;
2835 #endif
2836
2837 #if(MHL_FUNCTION_SUPPORT_PORTC)
2838 case MHL_CBUS_SELECT_PORTC:
2839 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
2840 break;
2841 #endif
2842
2843 #if(MHL_FUNCTION_SUPPORT_PORTD)
2844 case MHL_CBUS_SELECT_PORTD:
2845 bFlag = ((R2BYTE(REG_PM_MHL_CBUS_00) & BIT(10)) ? TRUE : FALSE);
2846 break;
2847 #endif
2848
2849 default:
2850
2851 break;
2852 };
2853
2854 return bFlag;
2855 }
2856
2857 //**************************************************************************
2858 // [Function Name]:
2859 // mhal_mhl_Accumulator_Clr()
2860 // [Description]
2861 // to clear accumulator when input is not MHL
2862 // [Arguments]:
2863 //
2864 // [Return]:
2865 //**************************************************************************
mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)2866 void mhal_mhl_Accumulator_Clr(MS_U8 ucCbusSelect)
2867 {
2868 switch(ucCbusSelect)
2869 {
2870 #if(MHL_FUNCTION_SUPPORT_PORTA)
2871 case MHL_CBUS_SELECT_PORTA:
2872
2873 break;
2874 #endif
2875
2876 #if(MHL_FUNCTION_SUPPORT_PORTB)
2877 case MHL_CBUS_SELECT_PORTB:
2878
2879 break;
2880 #endif
2881
2882 #if(MHL_FUNCTION_SUPPORT_PORTC)
2883 case MHL_CBUS_SELECT_PORTC:
2884
2885 break;
2886 #endif
2887
2888 #if(MHL_FUNCTION_SUPPORT_PORTD)
2889 case MHL_CBUS_SELECT_PORTD:
2890
2891 break;
2892 #endif
2893
2894 default:
2895
2896 break;
2897 };
2898 }
2899
2900 //**************************************************************************
2901 // [Function Name]:
2902 // mhal_mhl_CDRModeMonitor()
2903 // [Description]:
2904 // MHL CDR mode monitor
2905 // [Arguments]:
2906 // isCbusConnected: Cbus is at connected state or not
2907 // [Return]:
2908 //
2909 //**************************************************************************
mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect,MS_BOOL bPathEnable,stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus)2910 MS_BOOL mhal_mhl_CDRModeMonitor(MS_U8 ucCbusSelect, MS_BOOL bPathEnable, stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus)
2911 {
2912 MS_BOOL bindex = FALSE;
2913
2914 switch(ucCbusSelect)
2915 {
2916 #if(MHL_FUNCTION_SUPPORT_PORTA)
2917 case MHL_CBUS_SELECT_PORTA:
2918 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
2919 {
2920 if(pMHLSignalStatus->ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
2921 {
2922 pMHLSignalStatus->ucStableCount++;
2923 }
2924
2925 if(!pMHLSignalStatus->bClockStableFlag)
2926 {
2927 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, 0, BIT(8));
2928
2929 pMHLSignalStatus->bClockStableFlag = TRUE;
2930
2931 if(pMHLSignalStatus->bECbusEnableFlag)
2932 {
2933 pMHLSignalStatus->bAutoEnableFlag = TRUE;
2934 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_START;
2935 }
2936 }
2937
2938 if((R2BYTE(REG_DVI_DTOP_DUAL_P0_31_L) &BIT(6)) == BIT(6)) // DE stable
2939 {
2940 if(pMHLSignalStatus->ucStableCount < MHL_CDR_STABLE_THRESHOLD)
2941 {
2942 pMHLSignalStatus->ucStableCount = MHL_CDR_STABLE_THRESHOLD;
2943 }
2944 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
2945 {
2946 if(pMHLSignalStatus->bECbusEnableFlag)
2947 {
2948 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, BIT(13), BIT(13));
2949 //MsOS_DelayTaskUs(1);
2950 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_72_L, 0, BIT(13));
2951
2952 MHAL_MHL_MSG_INFO("** MHL toggle reset patch ~~~\r\n");
2953 }
2954
2955 pMHLSignalStatus->bSignalStableFlag = TRUE;
2956 }
2957
2958 if(pMHLSignalStatus->bBISTEnableFlag)
2959 {
2960 if(_mhal_mhl_CheckDEChangeFlag())
2961 {
2962 MHAL_MHL_MSG_INFO("** MHL trigger AV link BIST yo~~\r\n");
2963
2964 _mhal_mhl_BISTAVLinkEnable(ucCbusSelect, TRUE);
2965 }
2966 }
2967 }
2968 else // DE unstable
2969 {
2970 if(pMHLSignalStatus->ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
2971 {
2972 pMHLSignalStatus->ucStableCount = 0;
2973 pMHLSignalStatus->bSignalStableFlag = FALSE;
2974 }
2975 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
2976 {
2977 MHAL_MHL_MSG_INFO("** MHL time change toggle CDR mode\r\n");
2978
2979 pMHLSignalStatus->ucStableCount = 0;
2980 }
2981 }
2982 }
2983 else
2984 {
2985 if(pMHLSignalStatus->bClockStableFlag)
2986 {
2987 W2BYTEMSK(REG_COMBO_PHY0_P0_6E_L, BIT(8), BIT(8));
2988
2989 pMHLSignalStatus->bClockStableFlag = FALSE;
2990 pMHLSignalStatus->ucStableCount = 0;
2991 pMHLSignalStatus->bAutoEnableFlag = FALSE;
2992 pMHLSignalStatus->bSignalStableFlag = FALSE;
2993 }
2994 }
2995
2996 break;
2997 #endif
2998
2999 #if(MHL_FUNCTION_SUPPORT_PORTB)
3000 case MHL_CBUS_SELECT_PORTB:
3001 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
3002 {
3003 if(pMHLSignalStatus->ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
3004 {
3005 pMHLSignalStatus->ucStableCount++;
3006 }
3007
3008 if(!pMHLSignalStatus->bClockStableFlag)
3009 {
3010 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, 0, BIT(8));
3011
3012 pMHLSignalStatus->bClockStableFlag = TRUE;
3013
3014 if(pMHLSignalStatus->bECbusEnableFlag)
3015 {
3016 pMHLSignalStatus->bAutoEnableFlag = TRUE;
3017 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_START;
3018 }
3019 }
3020
3021 if((R2BYTE(REG_DVI_DTOP_DUAL_P1_31_L) &BIT(6)) == BIT(6)) // DE stable
3022 {
3023 if(pMHLSignalStatus->ucStableCount < MHL_CDR_STABLE_THRESHOLD)
3024 {
3025 pMHLSignalStatus->ucStableCount = MHL_CDR_STABLE_THRESHOLD;
3026 }
3027 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
3028 {
3029 if(pMHLSignalStatus->bECbusEnableFlag)
3030 {
3031 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, BIT(13), BIT(13));
3032 //MsOS_DelayTaskUs(1);
3033 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_72_L, 0, BIT(13));
3034
3035 MHAL_MHL_MSG_INFO("** MHL toggle reset patch ~~~\r\n");
3036 }
3037
3038 pMHLSignalStatus->bSignalStableFlag = TRUE;
3039 }
3040
3041 if(pMHLSignalStatus->bBISTEnableFlag)
3042 {
3043 if(_mhal_mhl_CheckDEChangeFlag())
3044 {
3045 MHAL_MHL_MSG_INFO("** MHL trigger AV link BIST yo~~\r\n");
3046
3047 _mhal_mhl_BISTAVLinkEnable(ucCbusSelect, TRUE);
3048 }
3049 }
3050 }
3051 else // DE unstable
3052 {
3053 if(pMHLSignalStatus->ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
3054 {
3055 pMHLSignalStatus->ucStableCount = 0;
3056 pMHLSignalStatus->bSignalStableFlag = FALSE;
3057 }
3058 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
3059 {
3060 MHAL_MHL_MSG_INFO("** MHL time change toggle CDR mode\r\n");
3061
3062 pMHLSignalStatus->ucStableCount = 0;
3063 }
3064 }
3065 }
3066 else
3067 {
3068 if(pMHLSignalStatus->bClockStableFlag)
3069 {
3070 W2BYTEMSK(REG_COMBO_PHY0_P1_6E_L, BIT(8), BIT(8));
3071
3072 pMHLSignalStatus->bClockStableFlag = FALSE;
3073 pMHLSignalStatus->ucStableCount = 0;
3074 pMHLSignalStatus->bAutoEnableFlag = FALSE;
3075 pMHLSignalStatus->bSignalStableFlag = FALSE;
3076 }
3077 }
3078
3079 break;
3080 #endif
3081
3082 #if(MHL_FUNCTION_SUPPORT_PORTC)
3083 case MHL_CBUS_SELECT_PORTC:
3084 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
3085 {
3086 if(pMHLSignalStatus->ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
3087 {
3088 pMHLSignalStatus->ucStableCount++;
3089 }
3090
3091 if(!pMHLSignalStatus->bClockStableFlag)
3092 {
3093 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, 0, BIT(8));
3094
3095 pMHLSignalStatus->bClockStableFlag = TRUE;
3096
3097 if(pMHLSignalStatus->bECbusEnableFlag)
3098 {
3099 pMHLSignalStatus->bAutoEnableFlag = TRUE;
3100 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_START;
3101 }
3102 }
3103
3104 if((R2BYTE(REG_DVI_DTOP_DUAL_P2_31_L) &BIT(6)) == BIT(6)) // DE stable
3105 {
3106 if(pMHLSignalStatus->ucStableCount < MHL_CDR_STABLE_THRESHOLD)
3107 {
3108 pMHLSignalStatus->ucStableCount = MHL_CDR_STABLE_THRESHOLD;
3109 }
3110 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
3111 {
3112 if(pMHLSignalStatus->bECbusEnableFlag)
3113 {
3114 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, BIT(13), BIT(13));
3115 //MsOS_DelayTaskUs(1);
3116 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_72_L, 0, BIT(13));
3117
3118 MHAL_MHL_MSG_INFO("** MHL toggle reset patch ~~~\r\n");
3119 }
3120
3121 pMHLSignalStatus->bSignalStableFlag = TRUE;
3122 }
3123
3124 if(pMHLSignalStatus->bBISTEnableFlag)
3125 {
3126 if(_mhal_mhl_CheckDEChangeFlag())
3127 {
3128 MHAL_MHL_MSG_INFO("** MHL trigger AV link BIST yo~~\r\n");
3129
3130 _mhal_mhl_BISTAVLinkEnable(ucCbusSelect, TRUE);
3131 }
3132 }
3133 }
3134 else // DE unstable
3135 {
3136 if(pMHLSignalStatus->ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
3137 {
3138 pMHLSignalStatus->ucStableCount = 0;
3139 pMHLSignalStatus->bSignalStableFlag = FALSE;
3140 }
3141 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
3142 {
3143 MHAL_MHL_MSG_INFO("** MHL time change toggle CDR mode\r\n");
3144
3145 pMHLSignalStatus->ucStableCount = 0;
3146 }
3147 }
3148 }
3149 else
3150 {
3151 if(pMHLSignalStatus->bClockStableFlag)
3152 {
3153 W2BYTEMSK(REG_COMBO_PHY0_P2_6E_L, BIT(8), BIT(8));
3154
3155 pMHLSignalStatus->bClockStableFlag = FALSE;
3156 pMHLSignalStatus->ucStableCount = 0;
3157 pMHLSignalStatus->bAutoEnableFlag = FALSE;
3158 pMHLSignalStatus->bSignalStableFlag = FALSE;
3159 }
3160 }
3161
3162 break;
3163 #endif
3164
3165 #if(MHL_FUNCTION_SUPPORT_PORTD)
3166 case MHL_CBUS_SELECT_PORTD:
3167 if(bPathEnable && (_mhal_mhl_CheckClockStatus(ucCbusSelect)))
3168 {
3169 if(pMHLSignalStatus->ucStableCount < (MHL_CDR_FORCE_THRESHOLD +1))
3170 {
3171 pMHLSignalStatus->ucStableCount++;
3172 }
3173
3174 if(!pMHLSignalStatus->bClockStableFlag)
3175 {
3176 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, 0, BIT(8));
3177
3178 pMHLSignalStatus->bClockStableFlag = TRUE;
3179
3180 if(pMHLSignalStatus->bECbusEnableFlag)
3181 {
3182 pMHLSignalStatus->bAutoEnableFlag = TRUE;
3183 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_START;
3184 }
3185 }
3186
3187 if((R2BYTE(REG_DVI_DTOP_DUAL_P3_31_L) &BIT(6)) == BIT(6)) // DE stable
3188 {
3189 if(pMHLSignalStatus->ucStableCount < MHL_CDR_STABLE_THRESHOLD)
3190 {
3191 pMHLSignalStatus->ucStableCount = MHL_CDR_STABLE_THRESHOLD;
3192 }
3193 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_FORCE_THRESHOLD -1))
3194 {
3195 if(pMHLSignalStatus->bECbusEnableFlag)
3196 {
3197 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, BIT(13), BIT(13));
3198 //MsOS_DelayTaskUs(1);
3199 W2BYTEMSK(REG_DVI_DTOP_DUAL_P3_72_L, 0, BIT(13));
3200
3201 MHAL_MHL_MSG_INFO("** MHL toggle reset patch ~~~\r\n");
3202 }
3203
3204 pMHLSignalStatus->bSignalStableFlag = TRUE;
3205 }
3206
3207 if(pMHLSignalStatus->bBISTEnableFlag)
3208 {
3209 if(_mhal_mhl_CheckDEChangeFlag())
3210 {
3211 MHAL_MHL_MSG_INFO("** MHL trigger AV link BIST yo~~\r\n");
3212
3213 _mhal_mhl_BISTAVLinkEnable(ucCbusSelect, TRUE);
3214 }
3215 }
3216 }
3217 else // DE unstable
3218 {
3219 if(pMHLSignalStatus->ucStableCount >= MHL_CDR_STABLE_THRESHOLD)
3220 {
3221 pMHLSignalStatus->ucStableCount = 0;
3222 pMHLSignalStatus->bSignalStableFlag = FALSE;
3223 }
3224 else if(pMHLSignalStatus->ucStableCount == (MHL_CDR_STABLE_THRESHOLD -1))
3225 {
3226 MHAL_MHL_MSG_INFO("** MHL time change toggle CDR mode\r\n");
3227
3228 pMHLSignalStatus->ucStableCount = 0;
3229 }
3230 }
3231 }
3232 else
3233 {
3234 if(pMHLSignalStatus->bClockStableFlag)
3235 {
3236 W2BYTEMSK(REG_COMBO_PHY0_P3_6E_L, BIT(8), BIT(8));
3237
3238 pMHLSignalStatus->bClockStableFlag = FALSE;
3239 pMHLSignalStatus->ucStableCount = 0;
3240 pMHLSignalStatus->bAutoEnableFlag = FALSE;
3241 pMHLSignalStatus->bSignalStableFlag = FALSE;
3242 }
3243 }
3244
3245 break;
3246 #endif
3247
3248 default:
3249
3250 break;
3251 };
3252
3253 return bindex;
3254 }
3255
3256 //**************************************************************************
3257 // [Function Name]:
3258 // mhal_mhl_CbusIsolate()
3259 // [Description]
3260 // MHL cable isolate
3261 // [Arguments]:
3262 //
3263 // [Return]:
3264 //
3265 //**************************************************************************
mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect,MS_BOOL bFlag)3266 void mhal_mhl_CbusIsolate(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3267 {
3268 switch(ucCbusSelect)
3269 {
3270 #if(MHL_FUNCTION_SUPPORT_PORTA)
3271 case MHL_CBUS_SELECT_PORTA:
3272 if(bFlag)
3273 {
3274 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
3275 }
3276 else
3277 {
3278 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
3279 }
3280
3281 break;
3282 #endif
3283
3284 #if(MHL_FUNCTION_SUPPORT_PORTB)
3285 case MHL_CBUS_SELECT_PORTB:
3286 if(bFlag)
3287 {
3288 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
3289 }
3290 else
3291 {
3292 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
3293 }
3294
3295 break;
3296 #endif
3297
3298 #if(MHL_FUNCTION_SUPPORT_PORTC)
3299 case MHL_CBUS_SELECT_PORTC:
3300 if(bFlag)
3301 {
3302 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
3303 }
3304 else
3305 {
3306 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
3307 }
3308
3309 break;
3310 #endif
3311
3312 #if(MHL_FUNCTION_SUPPORT_PORTD)
3313 case MHL_CBUS_SELECT_PORTD:
3314 if(bFlag)
3315 {
3316 W2BYTEMSK(REG_PM_MHL_CBUS_00, BIT(9), BIT(9) | BIT(8));
3317 }
3318 else
3319 {
3320 W2BYTEMSK(REG_PM_MHL_CBUS_00, 0, BIT(9) | BIT(8));
3321 }
3322
3323 break;
3324 #endif
3325
3326 default:
3327
3328 break;
3329 };
3330 }
3331
3332 //**************************************************************************
3333 // [Function Name]:
3334 // mhal_mhl_VbusCharge()
3335 // [Description]
3336 // MHL Vbus charge
3337 // [Arguments]:
3338 //
3339 // [Return]:
3340 //
3341 //**************************************************************************
mhal_mhl_VbusCharge(MS_U8 ucCbusSelect,MS_U8 bState)3342 void mhal_mhl_VbusCharge(MS_U8 ucCbusSelect, MS_U8 bState)
3343 {
3344 switch(ucCbusSelect)
3345 {
3346 #if(MHL_FUNCTION_SUPPORT_PORTA)
3347 case MHL_CBUS_SELECT_PORTA:
3348 if(bState == VBUS_SW_CHARGE)
3349 {
3350 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
3351 }
3352 else if(bState == VBUS_SW_UNCHARGE)
3353 {
3354 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
3355 }
3356 else
3357 {
3358 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
3359 }
3360
3361 break;
3362 #endif
3363
3364 #if(MHL_FUNCTION_SUPPORT_PORTB)
3365 case MHL_CBUS_SELECT_PORTB:
3366 if(bState == VBUS_SW_CHARGE)
3367 {
3368 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
3369 }
3370 else if(bState == VBUS_SW_UNCHARGE)
3371 {
3372 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
3373 }
3374 else
3375 {
3376 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
3377 }
3378
3379 break;
3380 #endif
3381
3382 #if(MHL_FUNCTION_SUPPORT_PORTC)
3383 case MHL_CBUS_SELECT_PORTC:
3384 if(bState == VBUS_SW_CHARGE)
3385 {
3386 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
3387 }
3388 else if(bState == VBUS_SW_UNCHARGE)
3389 {
3390 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
3391 }
3392 else
3393 {
3394 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
3395 }
3396
3397 break;
3398 #endif
3399
3400 #if(MHL_FUNCTION_SUPPORT_PORTD)
3401 case MHL_CBUS_SELECT_PORTD:
3402 if(bState == VBUS_SW_CHARGE)
3403 {
3404 W2BYTEMSK(REG_PM_MHL_CBUS_01, BMASK(1:0), BMASK(1:0));
3405 }
3406 else if(bState == VBUS_SW_UNCHARGE)
3407 {
3408 W2BYTEMSK(REG_PM_MHL_CBUS_01, BIT(1), BMASK(1:0));
3409 }
3410 else
3411 {
3412 W2BYTEMSK(REG_PM_MHL_CBUS_01, 0, BMASK(1:0));
3413 }
3414
3415 break;
3416 #endif
3417
3418 default:
3419
3420 break;
3421 };
3422 }
3423
3424 //**************************************************************************
3425 // [Function Name]:
3426 // mhal_mhl_CbusFloating()
3427 // [Description]
3428 // MHL cable floating
3429 // [Arguments]:
3430 //
3431 // [Return]:
3432 //
3433 //**************************************************************************
mhal_mhl_CbusFloating(MS_BOOL bFlag)3434 void mhal_mhl_CbusFloating(MS_BOOL bFlag)
3435 {
3436 if(bFlag)
3437 {
3438 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(5), BIT(5));
3439 }
3440 else
3441 {
3442 W2BYTEMSK(REG_PM_MHL_CBUS_17, 0, BIT(5));
3443 }
3444 }
3445
3446 //**************************************************************************
3447 // [Function Name]:
3448 // mhal_mhl_CbusStucktoLow()
3449 // [Description]
3450 //
3451 // [Arguments]:
3452 //
3453 // [Return]:
3454 //
3455 //**************************************************************************
mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)3456 void mhal_mhl_CbusStucktoLow(MS_BOOL bFlag)
3457 {
3458 if(bFlag)
3459 {
3460 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(1)); // cbus stuck to low int mask
3461 }
3462 else
3463 {
3464 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(1), BIT(1)); // cbus stuck to low int mask
3465 }
3466
3467 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0)); // Clear cbus stuck to low int flag
3468 }
3469
3470 //**************************************************************************
3471 // [Function Name]:
3472 // mhal_mhl_CbusWakeupInterrupt()
3473 // [Description]
3474 //
3475 // [Arguments]:
3476 //
3477 // [Return]:
3478 //
3479 //**************************************************************************
mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)3480 void mhal_mhl_CbusWakeupInterrupt(MS_BOOL bFlag)
3481 {
3482 if(bFlag)
3483 {
3484 W2BYTEMSK(REG_PM_MHL_CBUS_18, 0, BIT(5)); // wake up pulse int mask
3485 }
3486 else
3487 {
3488 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(5), BIT(5)); // wake up pulse int mask
3489 }
3490
3491 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4)); // Clear wake up pulse int flag
3492 }
3493
3494 //**************************************************************************
3495 // [Function Name]:
3496 // mhal_mhl_SetVenderID()
3497 // [Description]
3498 //
3499 // [Arguments]:
3500 //
3501 // [Return]:
3502 //
3503 //**************************************************************************
mhal_mhl_SetVenderID(MS_U8 ucVenderID)3504 void mhal_mhl_SetVenderID(MS_U8 ucVenderID)
3505 {
3506 W2BYTEMSK(REG_MHL_CBUS_00, (ucVenderID << 8), BMASK(15:8));
3507 }
3508
3509 //**************************************************************************
3510 // [Function Name]:
3511 // mhal_mhl_LoadEDID()
3512 // [Description]
3513 //
3514 // [Arguments]:
3515 //
3516 // [Return]:
3517 //
3518 //**************************************************************************
mhal_mhl_LoadEDID(MS_U8 * edid)3519 void mhal_mhl_LoadEDID(MS_U8 *edid)
3520 {
3521 MS_U16 ustemp = 0;
3522
3523 if(edid != NULL)
3524 {
3525 // Load EDID
3526 MHAL_MHL_MSG_INFO("** Maxim Load MHL EDID...\r\n");
3527
3528 W2BYTEMSK(REG_MHL_CBUS_52, BIT(1), BIT(1)); // CPU write enable
3529
3530 for(ustemp = 0; ustemp <256; ustemp++)
3531 {
3532 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
3533 W2BYTEMSK(REG_MHL_CBUS_53, edid[ustemp], 0x00FF); // data
3534 W2BYTEMSK(REG_MHL_CBUS_52, BIT(0), BIT(0)); // write trigger
3535 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
3536 while(R2BYTE(REG_MHL_CBUS_52) & BIT(5));
3537 }
3538
3539 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(1)); // CPU write disable
3540 }
3541 }
3542
3543 //**************************************************************************
3544 // [Function Name]:
3545 // mhal_mhl_ReadEDID()
3546 // [Description]
3547 //
3548 // [Arguments]:
3549 //
3550 // [Return]:
3551 //
3552 //**************************************************************************
mhal_mhl_ReadEDID(MS_U16 usSize,MS_U8 * edid)3553 void mhal_mhl_ReadEDID(MS_U16 usSize, MS_U8 *edid)
3554 {
3555 MS_U16 ustemp = 0;
3556
3557 if(edid != NULL)
3558 {
3559 // Read EDID
3560 MHAL_MHL_MSG_INFO("** Maxim Read MHL EDID...\r\n");
3561
3562 for(ustemp = 0; ustemp < usSize; ustemp++)
3563 {
3564 W2BYTEMSK(REG_MHL_CBUS_52, ustemp <<8, 0xFF00); // address
3565 W2BYTEMSK(REG_MHL_CBUS_52, BIT(3), BIT(3)); // read trigger
3566 W2BYTEMSK(REG_MHL_CBUS_52, 0, BIT(0));
3567 while(R2BYTE(REG_MHL_CBUS_52) & BIT(4));
3568
3569 edid[ustemp] = (MS_U8)((R2BYTE(REG_MHL_CBUS_53) & 0xFF00) >> 8); // data
3570 }
3571 }
3572 }
3573
3574 //**************************************************************************
3575 // [Function Name]:
3576 // mhal_mhl_LoadDeviceCapability()
3577 // [Description]
3578 //
3579 // [Arguments]:
3580 //
3581 // [Return]:
3582 //
3583 //**************************************************************************
mhal_mhl_LoadDeviceCapability(MS_U8 * devcap)3584 void mhal_mhl_LoadDeviceCapability(MS_U8 *devcap)
3585 {
3586 MS_U8 ucIndex = 0;
3587 MS_U8 uctemp = 0;
3588
3589 if(devcap != NULL)
3590 {
3591 MHAL_MHL_MSG_INFO("** Maxim Load DevCap...\r\n");
3592
3593 // Load MHL device capability
3594 for(uctemp = 0; uctemp <8; uctemp++)
3595 {
3596 if(uctemp == 2)
3597 {
3598 ucIndex = 1;
3599 }
3600
3601 W2BYTE(REG_MHL_CBUS_01 +(uctemp *2), (devcap[(uctemp *2) +1 -ucIndex] <<8) | devcap[uctemp *2 -ucIndex]);
3602 }
3603
3604 W2BYTE(REG_MHL_CBUS_03, (devcap[3] <<8) | devcap[4]);
3605 W2BYTE(REG_MHL_CBUS_07, (devcap[11] <<8) | devcap[12]);
3606
3607 W2BYTEMSK(REG_MHL_CBUS_09, devcap[15], BMASK(7:0));
3608
3609 for(uctemp = 0; uctemp <2; uctemp++)
3610 {
3611 W2BYTE(REG_MHL_CBUS_19 +(uctemp *2), (devcap[(uctemp *2) +17] <<8) | devcap[(uctemp *2) +16]); // [15:0], MHL_ECBUS_SPEEDS
3612 }
3613 }
3614 }
3615
3616 //**************************************************************************
3617 // [Function Name]:
3618 // mhal_mhl_initial()
3619 // [Description]
3620 // MHL init
3621 // [Arguments]:
3622 // *edid: MHL EDID data
3623 // *devcap: MHL device capability
3624 // [Return]:
3625 //
3626 //**************************************************************************
mhal_mhl_initial(MS_U8 ucCbusSelect,MS_U8 * edid,MS_U8 * devcap,MS_U8 ucVenderID)3627 MS_U8 mhal_mhl_initial(MS_U8 ucCbusSelect, MS_U8 *edid, MS_U8 *devcap, MS_U8 ucVenderID)
3628 {
3629 MS_U16 uctemp = 0;
3630
3631 // Initial setting
3632 for(uctemp = 0; uctemp <(sizeof(tMHL_INITIAL_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
3633 {
3634 W2BYTEMSK(tMHL_INITIAL_TABLE[uctemp].addr, tMHL_INITIAL_TABLE[uctemp].databuf, tMHL_INITIAL_TABLE[uctemp].mask);
3635 }
3636
3637 // ECbus initial setting
3638 _mhal_mhl_ECbusInitialSetting();
3639
3640 _mhal_mhl_CbusAndClockSelect(ucCbusSelect);
3641
3642 #if(MHL_INTERRUPT_USE_PM_IRQ)
3643 // Open PM irq mask
3644 W2BYTEMSK(0x2B28, 0, BIT(11));
3645 #endif
3646
3647 // Load EDID
3648 mhal_mhl_LoadEDID(edid);
3649
3650 // Load vendor ID
3651 mhal_mhl_SetVenderID(ucVenderID);
3652
3653 // Load DevCap
3654 mhal_mhl_LoadDeviceCapability(devcap);
3655
3656 // Clear Cbus received interrupt status
3657 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4)|BIT(0), BIT(4)|BIT(1)|BIT(0)); // [1]: receive packet valid mask
3658
3659 mhal_mhl_CbusStucktoLow(FALSE);
3660 mhal_mhl_CbusWakeupInterrupt(FALSE);
3661
3662 _mhal_mhl_MHLForceToAttach();
3663
3664 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
3665 {
3666 _mhal_mhl_RtermHWControl(uctemp, FALSE);
3667 }
3668
3669 _mhal_mhl_ForcePullDown100K(TRUE);
3670
3671 mhal_mhl_CbusFloating(TRUE);
3672
3673 return MHL_CHIP_FUNCTION_CAPABILITY;
3674 }
3675
3676 //**************************************************************************
3677 // [Function Name]:
3678 // mhal_mhl_InvertCableDetect()
3679 // [Description]
3680 //
3681 // [Arguments]:
3682 //
3683 // [Return]:
3684 //
3685 //**************************************************************************
mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect,MS_BOOL bCableDetectInvert)3686 void mhal_mhl_InvertCableDetect(MS_U8 ucCbusSelect, MS_BOOL bCableDetectInvert)
3687 {
3688 switch(ucCbusSelect)
3689 {
3690 #if(MHL_FUNCTION_SUPPORT_PORTA)
3691 case MHL_CBUS_SELECT_PORTA:
3692 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
3693 break;
3694 #endif
3695
3696 #if(MHL_FUNCTION_SUPPORT_PORTB)
3697 case MHL_CBUS_SELECT_PORTB:
3698 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
3699 break;
3700 #endif
3701
3702 #if(MHL_FUNCTION_SUPPORT_PORTC)
3703 case MHL_CBUS_SELECT_PORTC:
3704 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
3705 break;
3706 #endif
3707
3708 #if(MHL_FUNCTION_SUPPORT_PORTD)
3709 case MHL_CBUS_SELECT_PORTD:
3710 W2BYTEMSK(REG_PM_MHL_CBUS_00, bCableDetectInvert? BIT(11): 0, BIT(11));
3711 break;
3712 #endif
3713
3714 default:
3715
3716 break;
3717 };
3718 }
3719
3720 //**************************************************************************
3721 // [Function Name]:
3722 // mhal_mhl_VbusConfigSetting()
3723 // [Description]
3724 //
3725 // [Arguments]:
3726 //
3727 // [Return]:
3728 //
3729 //**************************************************************************
mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect,MS_U8 ucState)3730 void mhal_mhl_VbusConfigSetting(MS_U8 ucCbusSelect, MS_U8 ucState)
3731 {
3732 MS_U8 ucOutputState = ucState &(MHL_VBUS_LOW_ENABLE_MODE | MHL_VBUS_HIGH_ENABLE_MODE);
3733
3734 ucState = ucState &(MHL_VBUS_OUTPUT_MODE | MHL_VBUS_INVERSE_MODE);
3735
3736 switch(ucCbusSelect)
3737 {
3738 #if(MHL_FUNCTION_SUPPORT_PORTA)
3739 case MHL_CBUS_SELECT_PORTA:
3740 if(ucState == MHL_VBUS_OUTPUT_MODE)
3741 {
3742 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3743 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
3744 }
3745 else if(ucState > 0)
3746 {
3747 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3748 }
3749
3750 if(ucOutputState > 0)
3751 {
3752 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
3753 {
3754 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
3755 }
3756 else
3757 {
3758 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
3759 }
3760 }
3761
3762 break;
3763 #endif
3764
3765 #if(MHL_FUNCTION_SUPPORT_PORTB)
3766 case MHL_CBUS_SELECT_PORTB:
3767 if(ucState == MHL_VBUS_OUTPUT_MODE)
3768 {
3769 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3770 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
3771 }
3772 else if(ucState > 0)
3773 {
3774 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3775 }
3776
3777 if(ucOutputState > 0)
3778 {
3779 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
3780 {
3781 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
3782 }
3783 else
3784 {
3785 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
3786 }
3787 }
3788
3789 break;
3790 #endif
3791
3792 #if(MHL_FUNCTION_SUPPORT_PORTC)
3793 case MHL_CBUS_SELECT_PORTC:
3794 if(ucState == MHL_VBUS_OUTPUT_MODE)
3795 {
3796 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3797 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
3798 }
3799 else if(ucState > 0)
3800 {
3801 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3802 }
3803
3804 if(ucOutputState > 0)
3805 {
3806 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
3807 {
3808 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
3809 }
3810 else
3811 {
3812 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
3813 }
3814 }
3815
3816 break;
3817 #endif
3818
3819 #if(MHL_FUNCTION_SUPPORT_PORTD)
3820 case MHL_CBUS_SELECT_PORTD:
3821 if(ucState == MHL_VBUS_OUTPUT_MODE)
3822 {
3823 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3824 W2BYTEMSK(REG_PM_MHL_CBUS_21, BIT(7), BIT(7));
3825 }
3826 else if(ucState > 0)
3827 {
3828 W2BYTEMSK(REG_PM_MHL_CBUS_31, BIT(0), BIT(0));
3829 }
3830
3831 if(ucOutputState > 0)
3832 {
3833 if(ucOutputState == MHL_VBUS_HIGH_ENABLE_MODE)
3834 {
3835 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(9:8));
3836 }
3837 else
3838 {
3839 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(9), BMASK(9:8));
3840 }
3841 }
3842
3843 break;
3844 #endif
3845
3846 default:
3847 ucOutputState = 0;
3848 break;
3849 };
3850 }
3851
3852 //**************************************************************************
3853 // [Function Name]:
3854 // mhal_mhl_CableDetectPadSetting()
3855 // [Description]
3856 //
3857 // [Arguments]:
3858 //
3859 // [Return]:
3860 //
3861 //**************************************************************************
mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)3862 void mhal_mhl_CableDetectPadSetting(MS_U8 ucSelect)
3863 {
3864 // Nothing
3865 }
3866
3867 //**************************************************************************
3868 // [Function Name]:
3869 // mhal_mhl_CbusPadConfigSwitch()
3870 // [Description]
3871 //
3872 // [Arguments]:
3873 //
3874 // [Return]:
3875 //
3876 //**************************************************************************
mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect,MS_BOOL bFlag)3877 void mhal_mhl_CbusPadConfigSwitch(MS_U8 ucCbusSelect, MS_BOOL bFlag)
3878 {
3879 switch(ucCbusSelect)
3880 {
3881 #if(MHL_FUNCTION_SUPPORT_PORTA)
3882 case MHL_CBUS_SELECT_PORTA:
3883 if(bFlag)
3884 {
3885 _mhal_mhl_MHLForceToAttach();
3886 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3887 }
3888 else
3889 {
3890 _mhal_mhl_CbusForceToStandby();
3891 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
3892 }
3893
3894 break;
3895 #endif
3896
3897 #if(MHL_FUNCTION_SUPPORT_PORTB)
3898 case MHL_CBUS_SELECT_PORTB:
3899 if(bFlag)
3900 {
3901 _mhal_mhl_MHLForceToAttach();
3902 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3903 }
3904 else
3905 {
3906 _mhal_mhl_CbusForceToStandby();
3907 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
3908 }
3909
3910 break;
3911 #endif
3912
3913 #if(MHL_FUNCTION_SUPPORT_PORTC)
3914 case MHL_CBUS_SELECT_PORTC:
3915 if(bFlag)
3916 {
3917 _mhal_mhl_MHLForceToAttach();
3918 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3919 }
3920 else
3921 {
3922 _mhal_mhl_CbusForceToStandby();
3923 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
3924 }
3925
3926 break;
3927 #endif
3928
3929 #if(MHL_FUNCTION_SUPPORT_PORTD)
3930 case MHL_CBUS_SELECT_PORTD:
3931 if(bFlag)
3932 {
3933 _mhal_mhl_MHLForceToAttach();
3934 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
3935 }
3936 else
3937 {
3938 _mhal_mhl_CbusForceToStandby();
3939 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_UNCHARGE);
3940 }
3941
3942 break;
3943 #endif
3944
3945 default:
3946
3947 break;
3948 };
3949 }
3950
3951 //**************************************************************************
3952 // [Function Name]:
3953 // _mhal_mhl_CbusStatus()
3954 // [Description]:
3955 // MHL Cbus status
3956 // [Arguments]:
3957 //
3958 // [Return]:
3959 // Cbus status value
3960 //**************************************************************************
mhal_mhl_CbusStatus(void)3961 MS_U16 mhal_mhl_CbusStatus(void)
3962 {
3963 return (R2BYTE(REG_PM_MHL_CBUS_17));
3964 }
3965
3966 //**************************************************************************
3967 // [Function Name]:
3968 // mhal_mhl_CbusIsMscMsgReceived()
3969 // [Description]
3970 // MHL Cbus check whether msc message is received or not
3971 // [Arguments]:
3972 //
3973 // [Return]:
3974 // TRUE: recieved
3975 // FALSE: not yet
3976 //**************************************************************************
mhal_mhl_CbusIsMscMsgReceived(void)3977 MS_BOOL mhal_mhl_CbusIsMscMsgReceived(void)
3978 {
3979 MS_BOOL bindex = ((R2BYTE(REG_MHL_CBUS_3A) &BIT(3)) ?TRUE: FALSE);
3980
3981 if(bindex)
3982 {
3983 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0));
3984 }
3985
3986 return bindex;
3987 }
3988
3989 //**************************************************************************
3990 // [Function Name]:
3991 // mhal_mhl_CbusStucktoLowFlag()
3992 // [Description]
3993 //
3994 // [Arguments]:
3995 //
3996 // [Return]:
3997 //
3998 //**************************************************************************
mhal_mhl_CbusStucktoLowFlag(void)3999 MS_BOOL mhal_mhl_CbusStucktoLowFlag(void)
4000 {
4001 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(3)) ?TRUE: FALSE);
4002
4003 if(bindex)
4004 {
4005 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(0), BIT(0));
4006 }
4007
4008 return bindex;
4009 }
4010
4011 //**************************************************************************
4012 // [Function Name]:
4013 // mhal_mhl_CbusWakeupIntFlag()
4014 // [Description]
4015 //
4016 // [Arguments]:
4017 //
4018 // [Return]:
4019 //
4020 //**************************************************************************
mhal_mhl_CbusWakeupIntFlag(void)4021 MS_BOOL mhal_mhl_CbusWakeupIntFlag(void)
4022 {
4023 MS_BOOL bindex = ((R2BYTE(REG_PM_MHL_CBUS_18) &BIT(7)) ?TRUE: FALSE);
4024
4025 if(bindex)
4026 {
4027 W2BYTEMSK(REG_PM_MHL_CBUS_18, BIT(4), BIT(4));
4028 }
4029
4030 return bindex;
4031 }
4032
4033 //**************************************************************************
4034 // [Function Name]:
4035 // mhal_mhl_GetECbusStateChangeFlag()
4036 // [Description]
4037 //
4038 // [Arguments]:
4039 //
4040 // [Return]:
4041 //
4042 //**************************************************************************
mhal_mhl_GetECbusStateChangeFlag(stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus,stMHL_BIST_MODE_INFO * pBISTParameterInfo)4043 MS_BOOL mhal_mhl_GetECbusStateChangeFlag(stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus, stMHL_BIST_MODE_INFO *pBISTParameterInfo)
4044 {
4045 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(0)) ?TRUE: FALSE);
4046
4047 if(bindex)
4048 {
4049 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(0), BIT(0));
4050
4051 if((pMHLSignalStatus != NULL) && (pBISTParameterInfo != NULL))
4052 {
4053 _mhal_mhl_ECbusStateChangeProc(pMHLSignalStatus, pBISTParameterInfo);
4054 }
4055 }
4056
4057 return bindex;
4058 }
4059
4060 //**************************************************************************
4061 // [Function Name]:
4062 // mhal_mhl_GetEMSCReceiveFlag()
4063 // [Description]
4064 //
4065 // [Arguments]:
4066 //
4067 // [Return]:
4068 //
4069 //**************************************************************************
mhal_mhl_GetEMSCReceiveFlag(void)4070 MS_BOOL mhal_mhl_GetEMSCReceiveFlag(void)
4071 {
4072 MS_BOOL bindex = ((R2BYTE(REG_MHL_ECBUS_3A) &BIT(12)) ?TRUE: FALSE);
4073
4074 if(bindex)
4075 {
4076 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(12), BIT(12));
4077 }
4078
4079 return bindex;
4080 }
4081
4082 //**************************************************************************
4083 // [Function Name]:
4084 // mhal_mhl_GetEMSCSendStatus()
4085 // [Description]
4086 //
4087 // [Arguments]:
4088 //
4089 // [Return]:
4090 //
4091 //**************************************************************************
mhal_mhl_GetEMSCSendStatus(void)4092 MS_U8 mhal_mhl_GetEMSCSendStatus(void)
4093 {
4094 MS_U8 ucSendStatus = MHL_EMSC_SEND_NONE;
4095
4096 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(10)) // eMSC send pass interrupt.
4097 {
4098 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(10), BIT(10)); // eMSC send pass clear
4099
4100 ucSendStatus = MHL_EMSC_SEND_PASS;
4101 }
4102 else if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(9)) // eMSC send fail interrupt.
4103 {
4104 W2BYTEMSK(REG_MHL_ECBUS_34, BIT(9), BIT(9)); // eMSC send fail clear
4105
4106 ucSendStatus = MHL_EMSC_SEND_FAIL;
4107 }
4108
4109 return ucSendStatus;
4110 }
4111
4112 //**************************************************************************
4113 // [Function Name]:
4114 // mhal_mhl_CBusWrite()
4115 // [Description]
4116 // MHL Cbus write trigger
4117 // [Arguments]:
4118 // *pdatabuf: Cbus tx data
4119 // [Return]:
4120 //
4121 //**************************************************************************
mhal_mhl_CBusWrite(MS_BOOL bECbusEnableFlag,mhalCbusFifo_S * pdatabuf)4122 MS_BOOL mhal_mhl_CBusWrite(MS_BOOL bECbusEnableFlag, mhalCbusFifo_S *pdatabuf)
4123 {
4124 MS_BOOL bSendDondFlag = FALSE;
4125 MS_U8 uctemp = 0;
4126
4127 if(!_mhal_mhl_IsCbusBusy(bECbusEnableFlag))
4128 {
4129 for(uctemp = 0; uctemp < pdatabuf->lens; uctemp++)
4130 {
4131 W2BYTE(REG_MHL_CBUS_26 +uctemp *2, pdatabuf->databuf[uctemp]);
4132 }
4133
4134 // clear the unsed parts
4135 W2BYTE(REG_MHL_CBUS_26 +((pdatabuf->lens) *2), 0);
4136
4137 W2BYTEMSK(REG_MHL_CBUS_25, BIT(12), BIT(12)); // trigger to send
4138
4139 bSendDondFlag = TRUE;
4140
4141 #if(MHL_DEBUG_SEND_MSC)
4142 for(uctemp = 0; uctemp < pdatabuf->lens; uctemp++)
4143 {
4144 if((pdatabuf->databuf[uctemp]) &BIT(8))
4145 {
4146 MHAL_MHL_MSG_DEBUG(" MHL send MSG command = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0)));
4147 }
4148 else
4149 {
4150 MHAL_MHL_MSG_DEBUG(" MHL send MSG data = %x\r\n", (pdatabuf->databuf[uctemp] &BMASK(7:0)));
4151 }
4152 }
4153
4154 #endif
4155 }
4156
4157 return bSendDondFlag;
4158 }
4159
4160 //**************************************************************************
4161 // [Function Name]:
4162 // _mhal_mhl_Cbus_SetPathEn()
4163 // [Description]:
4164 // MHL Cbus set path enable
4165 // [Arguments]:
4166 // TRUE: Enable
4167 // FALSE: Disable
4168 // [Return]:
4169 //
4170 //**************************************************************************
mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)4171 void mhal_mhl_Cbus_SetPathEn(MS_BOOL bflag)
4172 {
4173 if(bflag) // set state to PATH_EN
4174 {
4175 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(12), BIT(12));
4176 }
4177 else // clear state to not PATH_EN
4178 {
4179 W2BYTEMSK(REG_PM_MHL_CBUS_17, BIT(13), BIT(13));
4180 }
4181 }
4182
4183 //**************************************************************************
4184 // [Function Name]:
4185 // mhal_mhl_CbusIntCB()
4186 // [Description]
4187 // MHL Cbus Interrupt Call Back function
4188 // [Arguments]:
4189 // *rcstate: recevied state, 0:normal / 1:timeout
4190 // *rccmd: recevied command
4191 // *rcdata: recevied data
4192 // *rclen: received length
4193 // *bIsCmdInData: Is command in data field
4194 // [Return]:
4195 //
4196 //**************************************************************************
mhal_mhl_CbusIntCB(MS_U8 * rcstate,MS_U8 * rccmd,MS_U8 * rcdata,MS_U8 * rclen,MS_U8 * bIsCmdInData)4197 MS_BOOL mhal_mhl_CbusIntCB(MS_U8 *rcstate, MS_U8 *rccmd, MS_U8 *rcdata, MS_U8 *rclen, MS_U8 *bIsCmdInData)
4198 {
4199 MS_BOOL bindex = FALSE;
4200 MS_U8 uctemp = 0;
4201 MS_U16 reg_val;
4202
4203 *rcstate = R2BYTE(REG_MHL_CBUS_3B) & 0x000F; // received state, 0: normal, 1: timeout
4204
4205 //W2BYTEMSK(REG_MHL_CBUS_3A, BIT(0), BIT(0)); // clear INT
4206
4207 reg_val = R2BYTE(REG_MHL_CBUS_3C);
4208
4209 if(!(reg_val &BIT(8))) // Received data
4210 {
4211 bindex = TRUE;
4212 }
4213
4214 *rccmd = reg_val & 0x00FF;
4215 *bIsCmdInData = FALSE;
4216
4217 for(uctemp = 0; uctemp <=(MHL_CBUS_DATA_SIZE +1); uctemp++) // offset+16bytes+EOF
4218 {
4219 reg_val = R2BYTE(REG_MHL_CBUS_3D +(uctemp *2));
4220
4221 if(reg_val & BIT(15))
4222 {
4223 rcdata[uctemp] = reg_val & 0x00FF;
4224
4225 if(((uctemp <= 2) ||(uctemp == (MHL_CBUS_DATA_SIZE +1))) && !(*bIsCmdInData))
4226 {
4227 *bIsCmdInData = (reg_val & BIT(8)) ? TRUE : FALSE;
4228 }
4229 }
4230 else
4231 {
4232 *rclen = uctemp;
4233 break;
4234 }
4235 }
4236
4237 // CTS 6.3.11.19
4238 if(uctemp >(MHL_CBUS_DATA_SIZE +1))
4239 {
4240 *rclen = MHL_CBUS_DATA_SIZE +2;
4241 }
4242
4243 W2BYTEMSK(REG_MHL_CBUS_3A, BIT(4), BIT(4)); // clear received FIFO
4244
4245 return bindex;
4246 }
4247
4248 //**************************************************************************
4249 // [Function Name]:
4250 // mdrv_mhl_CBusCheckBCHError()
4251 // [Description]:
4252 // MHL Cbus check BCH error
4253 // [Arguments]:
4254 //
4255 // [Return]:
4256 //
4257 //**************************************************************************
mhal_mhl_CBusCheckBCHError(void)4258 MS_BOOL mhal_mhl_CBusCheckBCHError(void)
4259 {
4260 MS_BOOL bindex = FALSE;
4261
4262 return bindex;
4263 }
4264
4265 //**************************************************************************
4266 // [Function Name]:
4267 // mhal_mhl_CablePlugProc()
4268 // [Description]
4269 //
4270 // [Arguments]:
4271 //
4272 // [Return]:
4273 //
4274 //**************************************************************************
mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect,stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus)4275 void mhal_mhl_CablePlugProc(MS_U8 ucCbusSelect, stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus)
4276 {
4277 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
4278
4279 #if(DMHL_LG_PRADA_PATCH)
4280 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
4281 #endif
4282
4283 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect, pMHLSignalStatus);
4284
4285 if(mhal_mhl_CheckInputPort(ucCbusSelect))
4286 {
4287 _mhal_mhl_AudioPathSelect(TRUE);
4288 }
4289
4290 _mhal_mhl_ForcePullDown100K(FALSE);
4291 }
4292
4293 //**************************************************************************
4294 // [Function Name]:
4295 // mhal_mhl_CableRemoveProc()
4296 // [Description]
4297 //
4298 // [Arguments]:
4299 //
4300 // [Return]:
4301 //
4302 //**************************************************************************
mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect,stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus)4303 void mhal_mhl_CableRemoveProc(MS_U8 ucCbusSelect, stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus)
4304 {
4305 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_HDMI_RTERM);
4306
4307 _mhal_mhl_HdmiBypassModeSetting(ucCbusSelect, pMHLSignalStatus);
4308
4309 #if(DMHL_LG_PRADA_PATCH)
4310 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
4311 #endif
4312
4313 if(mhal_mhl_CheckInputPort(ucCbusSelect))
4314 {
4315 _mhal_mhl_AudioPathSelect(FALSE);
4316 }
4317
4318 _mhal_mhl_ForcePullDown100K(TRUE);
4319 }
4320
4321 //**************************************************************************
4322 // [Function Name]:
4323 // mhal_mhl_CbusConnectProc()
4324 // [Description]
4325 //
4326 // [Arguments]:
4327 //
4328 // [Return]:
4329 //
4330 //**************************************************************************
mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)4331 void mhal_mhl_CbusConnectProc(MS_U8 ucCbusSelect)
4332 {
4333 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
4334
4335 #if(DMHL_LG_PRADA_PATCH)
4336 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, FALSE);
4337 #endif
4338
4339 mhal_mhl_CbusStucktoLow(TRUE);
4340 }
4341
4342 //**************************************************************************
4343 // [Function Name]:
4344 // mhal_mhl_CbusStucktoLowProc()
4345 // [Description]
4346 //
4347 // [Arguments]:
4348 //
4349 // [Return]:
4350 //
4351 //**************************************************************************
mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)4352 void mhal_mhl_CbusStucktoLowProc(MS_U8 ucCbusSelect)
4353 {
4354 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
4355
4356 #if(DMHL_LG_PRADA_PATCH)
4357 _mhal_mhl_AdjustCommonModeResistor(ucCbusSelect, TRUE);
4358 #endif
4359
4360 // Set short read address to 0x08
4361 _mhal_mhl_SetShortReadAddress(FALSE);
4362 }
4363
4364 //**************************************************************************
4365 // [Function Name]:
4366 // mhal_mhl_SourceChangeProc()
4367 // [Description]
4368 //
4369 // [Arguments]:
4370 //
4371 // [Return]:
4372 //
4373 //**************************************************************************
mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect,MS_U8 ucLinkRate)4374 void mhal_mhl_SourceChangeProc(MS_U8 ucCbusSelect, MS_U8 ucLinkRate)
4375 {
4376 MS_BOOL bLinkRate6GFlag = FALSE;
4377
4378 if(ucLinkRate == MHL_AV_LINK_600)
4379 {
4380 bLinkRate6GFlag = TRUE;
4381 }
4382
4383 if(mhal_mhl_CheckInputPort(ucCbusSelect))
4384 {
4385 _mhal_mhl_AudioPathSelect(TRUE);
4386 }
4387 else
4388 {
4389 _mhal_mhl_AudioPathSelect(FALSE);
4390 }
4391 }
4392
4393 //**************************************************************************
4394 // [Function Name]:
4395 // mhal_mhl_ClockModeSwitchProc()
4396 // [Description]
4397 //
4398 // [Arguments]:
4399 //
4400 // [Return]:
4401 //
4402 //**************************************************************************
mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect,MS_BOOL bPPmode,stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus)4403 void mhal_mhl_ClockModeSwitchProc(MS_U8 ucCbusSelect, MS_BOOL bPPmode, stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus)
4404 {
4405 if(bPPmode)
4406 {
4407 _mhal_mhl_MhlPackedPixelModeSetting(ucCbusSelect);
4408 }
4409 else
4410 {
4411 _mhal_mhl_Mhl24bitsModeSetting(ucCbusSelect, pMHLSignalStatus);
4412 }
4413 }
4414
4415 //**************************************************************************
4416 // [Function Name]:
4417 // mhal_mhl_CbusWakeupIntSetting()
4418 // [Description]
4419 //
4420 // [Arguments]:
4421 //
4422 // [Return]:
4423 //
4424 //**************************************************************************
mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect,MS_BOOL bFlag)4425 void mhal_mhl_CbusWakeupIntSetting(MS_U8 ucCbusSelect, MS_BOOL bFlag)
4426 {
4427 if(bFlag)
4428 {
4429 _mhal_mhl_CbusForceToStandby();
4430 mhal_mhl_CbusWakeupInterrupt(TRUE);
4431 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_SW_CHARGE);
4432 }
4433 else
4434 {
4435 _mhal_mhl_MHLForceToAttach();
4436 mhal_mhl_CbusWakeupInterrupt(FALSE);
4437 mhal_mhl_VbusCharge(ucCbusSelect, VBUS_HW_DETECT);
4438 }
4439 }
4440
4441 //**************************************************************************
4442 // [Function Name]:
4443 // mhal_mhl_RtermControlHWMode()
4444 // [Description]
4445 //
4446 // [Arguments]:
4447 //
4448 // [Return]:
4449 //
4450 //**************************************************************************
mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect,MS_BOOL bFlag)4451 void mhal_mhl_RtermControlHWMode(MS_U8 ucCbusSelect, MS_BOOL bFlag)
4452 {
4453 MS_U16 ustemp = mhal_mhl_CbusStatus();
4454
4455 if(!bFlag) // HW to SW control rterm
4456 {
4457 if((ustemp & BMASK(1:0)) == 0x03)
4458 {
4459 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_MHL_RTERM);
4460 }
4461 else
4462 {
4463 _mhal_mhl_RxRtermControl(ucCbusSelect, RX_RTERM_OFF);
4464 }
4465 }
4466
4467 _mhal_mhl_RtermHWControl(ucCbusSelect, bFlag);
4468 }
4469
4470 //**************************************************************************
4471 // [Function Name]:
4472 // mhal_mhl_PowerControl()
4473 // [Description]
4474 // MHL power control
4475 // [Arguments]:
4476 //
4477 // [Return]:
4478 //
4479 //**************************************************************************
mhal_mhl_LoadPowerOnTbl(void)4480 void mhal_mhl_LoadPowerOnTbl(void)
4481 {
4482 MS_U8 uctemp = 0;
4483
4484 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_ON_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
4485 {
4486 W2BYTEMSK(tMHL_POWER_ON_TABLE[uctemp].addr, tMHL_POWER_ON_TABLE[uctemp].databuf, tMHL_POWER_ON_TABLE[uctemp].mask);
4487 }
4488
4489 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
4490 {
4491 _mhal_mhl_RxRtermControl(uctemp, RX_HDMI_RTERM);
4492 }
4493 }
4494
mhal_mhl_LoadPowerStandbyTbl(void)4495 void mhal_mhl_LoadPowerStandbyTbl(void)
4496 {
4497 MS_U8 uctemp = 0;
4498
4499 //_mhal_mhl_CbusForceToStandby();
4500
4501 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_SAVING_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
4502 {
4503 W2BYTEMSK(tMHL_POWER_SAVING_TABLE[uctemp].addr, tMHL_POWER_SAVING_TABLE[uctemp].databuf, tMHL_POWER_SAVING_TABLE[uctemp].mask);
4504 }
4505
4506 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
4507 {
4508 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
4509 mhal_mhl_VbusCharge(uctemp, VBUS_SW_CHARGE);
4510 }
4511 }
4512
mhal_mhl_LoadPowerDownTbl(void)4513 void mhal_mhl_LoadPowerDownTbl(void)
4514 {
4515 MS_U8 uctemp = 0;
4516
4517 //_mhal_mhl_CbusForceToStandby();
4518
4519 for(uctemp = 0; uctemp <(sizeof(tMHL_POWER_DOWN_TABLE) /sizeof(msLoadTbl_S)); uctemp++)
4520 {
4521 W2BYTEMSK(tMHL_POWER_DOWN_TABLE[uctemp].addr, tMHL_POWER_DOWN_TABLE[uctemp].databuf, tMHL_POWER_DOWN_TABLE[uctemp].mask);
4522 }
4523
4524 for(uctemp = 0; uctemp < MHL_CBUS_SELECT_MASK; uctemp++)
4525 {
4526 _mhal_mhl_RxRtermControl(uctemp, RX_RTERM_OFF);
4527 }
4528 }
4529
4530 //**************************************************************************
4531 // [Function Name]:
4532 // mhal_mhl_SetHPD()
4533 // [Description]
4534 // config HPD in combo(MHL/HDMI) port A
4535 // [Arguments]:
4536 //
4537 // [Return]:
4538 //
4539 //**************************************************************************
mhal_mhl_SetHPD(MS_BOOL bflag)4540 void mhal_mhl_SetHPD(MS_BOOL bflag)
4541 {
4542 if(bflag) // HPD is high
4543 {
4544 W2BYTEMSK(REG_PM_MHL_CBUS_20, BIT(3), BMASK(4:3)); // [4]: output val, [3]: oen
4545 }
4546 else // hpd is low
4547 {
4548 W2BYTEMSK(REG_PM_MHL_CBUS_20, 0, BMASK(4:3)); // [4]: output val, [3]: oen
4549 }
4550 }
4551
4552 //**************************************************************************
4553 // [Function Name]:
4554 // mhal_mhl_GetDDCErrorCode()
4555 // [Description]
4556 // Get DDC error code
4557 // [Arguments]:
4558 //
4559 // [Return]:
4560 //
4561 //**************************************************************************
mhal_mhl_GetDDCErrorCode(void)4562 MS_U8 mhal_mhl_GetDDCErrorCode(void)
4563 {
4564 return (R2BYTE(REG_MHL_CBUS_21)>>8);
4565 }
4566
4567 #if(MHL_CBUS_OPERATION_MODE == MHL_CBUS_HW_REPLY_MODE)
4568 //**************************************************************************
4569 // [Function Name]:
4570 // mhal_mhl_CheckSRAMReceiveBuffer()
4571 // [Description]
4572 //
4573 // [Arguments]:
4574 //
4575 // [Return]:
4576 //
4577 //**************************************************************************
mhal_mhl_CheckSRAMReceiveBuffer(void)4578 MS_BOOL mhal_mhl_CheckSRAMReceiveBuffer(void)
4579 {
4580 return ((R2BYTE(REG_MHL_CBUS_10) &BIT(4)) ?FALSE: TRUE);
4581 }
4582
4583 //**************************************************************************
4584 // [Function Name]:
4585 // mhal_mhl_GetSRAMReceiveData()
4586 // [Description]
4587 //
4588 // [Arguments]:
4589 //
4590 // [Return]:
4591 //
4592 //**************************************************************************
mhal_mhl_GetSRAMReceiveData(void)4593 MS_U16 mhal_mhl_GetSRAMReceiveData(void)
4594 {
4595 W2BYTEMSK(REG_MHL_CBUS_10, BIT(15), BIT(15));
4596
4597 while((R2BYTE(REG_MHL_CBUS_10) & BIT(14)) == BIT(14));
4598
4599 return R2BYTE(REG_MHL_CBUS_0F);
4600 }
4601
4602 #endif
4603
4604 #if(DMHL_TEST_SIGNAL_SUPPORT)
4605 //**************************************************************************
4606 // [Function Name]:
4607 // mhal_mhl_AdjustCommonModeResistor()
4608 // [Description]:
4609 //
4610 // [Arguments]:
4611 //
4612 // [Return]:
4613 //
4614 //**************************************************************************
mhal_mhl_TestSignal(MS_BOOL bflag)4615 void mhal_mhl_TestSignal(MS_BOOL bflag)
4616 {
4617 if(bflag)
4618 {
4619 W2BYTEMSK(0x001106, BIT(10), BIT(10));
4620 }
4621 else
4622 {
4623 W2BYTEMSK(0x001106, 0, BIT(10));
4624 }
4625 }
4626
4627 #endif
4628
4629 //**************************************************************************
4630 // [Function Name]:
4631 // mhal_mhl_SetMainLinkRate()
4632 // [Description]
4633 //
4634 // [Arguments]:
4635 //
4636 // [Return]:
4637 //
4638 //**************************************************************************
mhal_mhl_SetMainLinkRate(MS_U8 ucCbusSelect,MS_U8 ucLinkRate)4639 void mhal_mhl_SetMainLinkRate(MS_U8 ucCbusSelect, MS_U8 ucLinkRate)
4640 {
4641 MS_BOOL bLinkRate6GFlag = FALSE;
4642
4643 _mhal_mhl_Version3PhyEnable(ucCbusSelect, TRUE);
4644
4645 switch(ucCbusSelect)
4646 {
4647 #if(MHL_FUNCTION_SUPPORT_PORTA)
4648 case MHL_CBUS_SELECT_PORTA:
4649 if(ucLinkRate == MHL_AV_LINK_600)
4650 {
4651 bLinkRate6GFlag = TRUE;
4652 }
4653 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4654 {
4655
4656 }
4657
4658 W2BYTEMSK(REG_COMBO_PHY1_P0_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4659
4660 break;
4661 #endif
4662
4663 #if(MHL_FUNCTION_SUPPORT_PORTB)
4664 case MHL_CBUS_SELECT_PORTB:
4665 if(ucLinkRate == MHL_AV_LINK_600)
4666 {
4667 bLinkRate6GFlag = TRUE;
4668 }
4669 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4670 {
4671
4672 }
4673
4674 W2BYTEMSK(REG_COMBO_PHY1_P1_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4675
4676 break;
4677 #endif
4678
4679 #if(MHL_FUNCTION_SUPPORT_PORTC)
4680 case MHL_CBUS_SELECT_PORTC:
4681 if(ucLinkRate == MHL_AV_LINK_600)
4682 {
4683 bLinkRate6GFlag = TRUE;
4684 }
4685 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4686 {
4687
4688 }
4689
4690 W2BYTEMSK(REG_COMBO_PHY1_P2_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4691
4692 break;
4693 #endif
4694
4695 #if(MHL_FUNCTION_SUPPORT_PORTD)
4696 case MHL_CBUS_SELECT_PORTD:
4697 if(ucLinkRate == MHL_AV_LINK_600)
4698 {
4699 bLinkRate6GFlag = TRUE;
4700 }
4701 else // MHL_AV_LINK_150 or MHL_AV_LINK_300
4702 {
4703
4704 }
4705
4706 W2BYTEMSK(REG_COMBO_PHY1_P3_0D_L, (ucLinkRate << 12), BMASK(13:12)); // [13:12]: Select MHL3 data rate
4707
4708 break;
4709 #endif
4710
4711 default:
4712 bLinkRate6GFlag = FALSE;
4713 break;
4714 };
4715
4716 _mhal_mhl_MHL30AutoEQSetting(ucCbusSelect);
4717 }
4718
4719 //**************************************************************************
4720 // [Function Name]:
4721 // mhal_mhl_GetECbusStatusFlag()
4722 // [Description]:
4723 //
4724 // [Arguments]:
4725 //
4726 // [Return]:
4727 //
4728 //**************************************************************************
mhal_mhl_GetECbusStatusFlag(void)4729 MS_U8 mhal_mhl_GetECbusStatusFlag(void)
4730 {
4731 MS_U8 ucTrainState = (R2BYTE(REG_MHL_ECBUS_PHY_69) >> 12);
4732 MS_U8 ucECbusStatusFlag = 0;
4733
4734 if(R2BYTE(REG_MHL_ECBUS_PHY_6F) &BIT(13)) // [13]: ECbus clock lock flag
4735 {
4736 ucECbusStatusFlag |= MHL_ECBUS_STATUS_CLOCK_LOCK;
4737 }
4738
4739 if((ucTrainState >= MHL_ECBUS_TRAIN_WAIT_RRCEIVE_COMMA2) && (ucTrainState <= MHL_ECBUS_TRAIN_DONE))//Whan state of REG_PM_MHL_CBUS2_56 is equla 3, than state of REG_PM_MHL_CBUS2_69[51:12] will from 1 to 7.
4740 {
4741 //W2BYTEMSK(REG_MHL_ECBUS_PHY_56, 0x0200, BMASK(15:0)); // for auto train
4742 #if(MHL_ECBUS_AUTO_TRAINING)
4743 W2BYTEMSK(REG_MHL_ECBUS_PHY_4A, 0, BIT(13));
4744 #endif
4745 }
4746
4747 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(7)) // REG_MHL_CBUS2_3A[7]
4748 {
4749 ucECbusStatusFlag |= MHL_ECBUS_STATUS_SLOT_SYNC_DONE;
4750 }
4751
4752 if(R2BYTE(REG_MHL_ECBUS_3A) &BIT(15)) // REG_MHL_CBUS2_3A[15]
4753 {
4754 ucECbusStatusFlag |= MHL_ECBUS_STATUS_EMSC_SYNC_DONE;
4755 }
4756
4757 return ucECbusStatusFlag;
4758 }
4759
4760 //**************************************************************************
4761 // [Function Name]:
4762 // mhal_mhl_ECbusEventProc()
4763 // [Description]
4764 //
4765 // [Arguments]:
4766 //
4767 // [Return]:
4768 //
4769 //**************************************************************************
mhal_mhl_ECbusEventProc(MS_U8 ucCbusSelect,MS_U8 ucECbusEvent,MS_BOOL bBISTEnableFlag,stMHL_BIST_MODE_INFO * pBISTParameterInfo)4770 void mhal_mhl_ECbusEventProc(MS_U8 ucCbusSelect, MS_U8 ucECbusEvent, MS_BOOL bBISTEnableFlag, stMHL_BIST_MODE_INFO *pBISTParameterInfo)
4771 {
4772 switch(ucECbusEvent)
4773 {
4774 case MHL_ECBUS_EVENT_PREPARE_MODE_UP:
4775 // Disable stuck to low interrupt
4776 mhal_mhl_CbusStucktoLow(FALSE);
4777 // Disable connect detect
4778 _mhal_mhl_CbusConnectCheckEnable(FALSE);
4779
4780 break;
4781
4782 case MHL_ECBUS_EVENT_MODE_UP_PROCESS:
4783 // Enable ECbus
4784 _mhal_mhl_ECbusEnableSetting(TRUE);
4785
4786 if(bBISTEnableFlag)
4787 {
4788 //_mhal_mhl_ECbusBISTSetting(TRUE, pBISTParameterInfo);
4789 _mhal_mhl_BISTECbusEnable(TRUE);
4790 //_mhal_mhl_ECbusStateOverwrite(TRUE);
4791 }
4792
4793 // Set short read address to 0x70
4794 _mhal_mhl_SetShortReadAddress(TRUE);
4795 // Enable ECbus state change IRQ
4796 _mhal_mhl_SetECbusStateChangeInterrupt(TRUE);
4797 // Enable eMSC receive IRQ
4798 _mhal_mhl_SetEMSCReceiveInterrupt(TRUE);
4799
4800 _mhal_mhl_ECbusModeUpProc();
4801
4802 mhal_mhl_SetMainLinkRate(ucCbusSelect, MHL_AV_LINK_150);
4803
4804 break;
4805
4806 case MHL_ECBUS_EVENT_PREPARE_MODE_DOWN:
4807
4808 break;
4809
4810 case MHL_ECBUS_EVENT_MODE_DOWN_PROCESS:
4811 case MHL_ECBUS_EVENT_STUCK_TO_LOW:
4812 // Enable connect detect
4813 _mhal_mhl_CbusConnectCheckEnable(TRUE);
4814 // Disable ECbus
4815 _mhal_mhl_ECbusEnableSetting(FALSE);
4816
4817 if(bBISTEnableFlag)
4818 {
4819 //_mhal_mhl_ECbusBISTSetting(FALSE, pBISTParameterInfo);
4820 }
4821
4822 // Clear short read address to 0x08
4823 _mhal_mhl_SetShortReadAddress(FALSE);
4824 // Disable ECbus state change IRQ
4825 _mhal_mhl_SetECbusStateChangeInterrupt(FALSE);
4826 // Disable eMSC receive IRQ
4827 _mhal_mhl_SetEMSCReceiveInterrupt(FALSE);
4828 // Disable MHL3 phy
4829 _mhal_mhl_Version3PhyEnable(ucCbusSelect, FALSE);
4830 // Reset all status
4831 W2BYTE(REG_MHL_ECBUS_34, 0xFFFF);
4832
4833 _mhal_mhl_CbusEngineReset();
4834
4835 break;
4836
4837 case MHL_ECBUS_EVENT_UNLOCK_RESET:
4838 //_mhal_mhl_ECbusDmuxEnable(FALSE);
4839 _mhal_mhl_ECbusStateReset();
4840
4841 break;
4842
4843 #if(MHL_ECBUS_COMMAND_PARSING)
4844 case MHL_ECBUS_EVENT_ECBUS_COMMAND_PARSING:
4845 _mhal_mhl_GetECbusCommand();
4846
4847 break;
4848
4849 #endif
4850
4851 case MHL_ECBUS_EVENT_BIST_TRIGGER:
4852 //_mhal_mhl_BISTECbusEnable(TRUE);
4853 //_mhal_mhl_SetECbusBISTTrigger(TRUE, pBISTParameterInfo->bBISTeCbusTxFlag, pBISTParameterInfo->bBISTeCbusRxFlag);
4854
4855 break;
4856
4857 default:
4858
4859 break;
4860 };
4861 }
4862
4863 //**************************************************************************
4864 // [Function Name]:
4865 // mhal_mhl_SetBISTParameterInfo()
4866 // [Description]
4867 //
4868 // [Arguments]:
4869 //
4870 // [Return]:
4871 //
4872 //**************************************************************************
mhal_mhl_SetBISTParameterInfo(MS_U8 ucCbusSelect,stMHL_BIST_MODE_INFO * pBISTParameterInfo)4873 void mhal_mhl_SetBISTParameterInfo(MS_U8 ucCbusSelect, stMHL_BIST_MODE_INFO *pBISTParameterInfo)
4874 {
4875 MS_U8 ucBISTeCbusPattern = pBISTParameterInfo->ucBISTeCbusPattern;
4876 MS_U8 ucBISTAVLinkRate = pBISTParameterInfo->ucBISTAVLinkRate;
4877 MS_U16 usBISTeCbusSettingValue = 0;
4878 MS_U16 usBISTAVLinkSettingValue = (pBISTParameterInfo->ucBISTAVLinkPattern << 8)| 0xFF;
4879
4880 if(ucBISTeCbusPattern > 0)
4881 {
4882 ucBISTeCbusPattern = ucBISTeCbusPattern -1;
4883 }
4884
4885 usBISTeCbusSettingValue = (ucBISTeCbusPattern << 12)| pBISTParameterInfo->usBISTeCbusPatternFixed;
4886
4887 W2BYTEMSK(REG_MHL_ECBUS_2B, usBISTeCbusSettingValue, BMASK(13:12)| BMASK(7:0)); // ecbus bist send pattern type, ecbus bist send fix pattern value
4888 W2BYTEMSK(REG_MHL_ECBUS_2F, usBISTeCbusSettingValue, BMASK(13:12)| BMASK(7:0)); // ecbus bist receive pattern type, ecbus bist receive fix pattern value
4889
4890 if(pBISTParameterInfo->ucBISTAVLinkRateRandomizer > 0)
4891 {
4892 usBISTAVLinkSettingValue = usBISTAVLinkSettingValue| BIT(15);
4893 }
4894
4895 switch(ucCbusSelect)
4896 {
4897 #if(MHL_FUNCTION_SUPPORT_PORTA)
4898 case MHL_CBUS_SELECT_PORTA:
4899 W2BYTE(REG_DVI_DTOP_DUAL_P0_74_L, pBISTParameterInfo->usBISTAVLinkFixed);
4900 W2BYTE(REG_DVI_DTOP_DUAL_P0_75_L, usBISTAVLinkSettingValue);
4901
4902 if(pBISTParameterInfo->ucBISTAVLinkPattern == MHL_BIST_LINK_PATTERN_FIXED10)
4903 {
4904 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_71_L, 0, BIT(0));
4905 }
4906 else
4907 {
4908 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_71_L, BIT(0), BIT(0));
4909 }
4910
4911 break;
4912 #endif
4913
4914 #if(MHL_FUNCTION_SUPPORT_PORTB)
4915 case MHL_CBUS_SELECT_PORTB:
4916 W2BYTE(REG_DVI_DTOP_DUAL_P1_74_L, pBISTParameterInfo->usBISTAVLinkFixed);
4917 W2BYTE(REG_DVI_DTOP_DUAL_P1_75_L, usBISTAVLinkSettingValue);
4918
4919 if(pBISTParameterInfo->ucBISTAVLinkPattern == MHL_BIST_LINK_PATTERN_FIXED10)
4920 {
4921 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_71_L, 0, BIT(0));
4922 }
4923 else
4924 {
4925 W2BYTEMSK(REG_DVI_DTOP_DUAL_P1_71_L, BIT(0), BIT(0));
4926 }
4927
4928 break;
4929 #endif
4930
4931 #if(MHL_FUNCTION_SUPPORT_PORTC)
4932 case MHL_CBUS_SELECT_PORTC:
4933 W2BYTE(REG_DVI_DTOP_DUAL_P2_74_L, pBISTParameterInfo->usBISTAVLinkFixed);
4934 W2BYTE(REG_DVI_DTOP_DUAL_P2_75_L, usBISTAVLinkSettingValue);
4935
4936 if(pBISTParameterInfo->ucBISTAVLinkPattern == MHL_BIST_LINK_PATTERN_FIXED10)
4937 {
4938 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_71_L, 0, BIT(0));
4939 }
4940 else
4941 {
4942 W2BYTEMSK(REG_DVI_DTOP_DUAL_P2_71_L, BIT(0), BIT(0));
4943 }
4944
4945 break;
4946 #endif
4947
4948 #if(MHL_FUNCTION_SUPPORT_PORTD)
4949 case MHL_CBUS_SELECT_PORTD:
4950 W2BYTE(REG_DVI_DTOP_DUAL_P3_74_L, pBISTParameterInfo->usBISTAVLinkFixed);
4951 W2BYTE(REG_DVI_DTOP_DUAL_P3_75_L, usBISTAVLinkSettingValue);
4952
4953 if(pBISTParameterInfo->ucBISTAVLinkPattern == MHL_BIST_LINK_PATTERN_FIXED10)
4954 {
4955 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_73_L, 0, BIT(0));
4956 }
4957 else
4958 {
4959 W2BYTEMSK(REG_DVI_DTOP_DUAL_P0_73_L, BIT(0), BIT(0));
4960 }
4961
4962 break;
4963 #endif
4964
4965 default:
4966
4967 break;
4968 };
4969
4970 if(ucBISTAVLinkRate > 0)
4971 {
4972 ucBISTAVLinkRate = ucBISTAVLinkRate -1;
4973 }
4974
4975 mhal_mhl_SetMainLinkRate(ucCbusSelect, ucBISTAVLinkRate);
4976 }
4977
4978 //**************************************************************************
4979 // [Function Name]:
4980 // mhal_mhl_GetBISTErrorCount()
4981 // [Description]
4982 //
4983 // [Arguments]:
4984 //
4985 // [Return]:
4986 //
4987 //**************************************************************************
mhal_mhl_GetBISTErrorCount(MS_U8 ucCbusSelect,stMHL_BIST_MODE_INFO * pBISTParameterInfo)4988 void mhal_mhl_GetBISTErrorCount(MS_U8 ucCbusSelect, stMHL_BIST_MODE_INFO *pBISTParameterInfo)
4989 {
4990 if(pBISTParameterInfo != NULL)
4991 {
4992 pBISTParameterInfo->usBISTeCbusErrorCount = _mhal_mhl_GetBISTECbusErrorCount();
4993 pBISTParameterInfo->usBISTAVLinkErrorCount = _mhal_mhl_GetBISTAVLinkErrorCount(ucCbusSelect);
4994
4995 _mhal_mhl_SetECbusBISTTrigger(FALSE, pBISTParameterInfo->bBISTeCbusTxFlag, pBISTParameterInfo->bBISTeCbusRxFlag);
4996 //_mhal_mhl_ECbusStateOverwrite(FALSE);
4997 _mhal_mhl_BISTECbusEnable(FALSE);
4998 _mhal_mhl_BISTAVLinkEnable(ucCbusSelect, FALSE);
4999 }
5000 }
5001
5002 //**************************************************************************
5003 // [Function Name]:
5004 // mhal_mhl_GetEMSCReceiveData()
5005 // [Description]
5006 //
5007 // [Arguments]:
5008 //
5009 // [Return]:
5010 //
5011 //**************************************************************************
mhal_mhl_GetEMSCReceiveData(MS_U8 * bReveiceEMSC)5012 void mhal_mhl_GetEMSCReceiveData(MS_U8 *bReveiceEMSC)
5013 {
5014 MS_U8 uctemp = 0;
5015 MS_U16 usEMSCFreeBuffer = 0;
5016
5017 usEMSCFreeBuffer = (R2BYTE(REG_MHL_ECBUS_24) &BMASK(9:0)); // REG_MHL_ECBUS_24[9:0]
5018
5019 usEMSCFreeBuffer = MHL_EMSC_DATA_SIZE - usEMSCFreeBuffer;
5020
5021 bReveiceEMSC[0] = usEMSCFreeBuffer;
5022
5023 #if(MHL_DEBUG_RECEIVE_EMSC)
5024 MHAL_MHL_MSG_INFO("** MHL eMSC length %d\r\n", usEMSCFreeBuffer);
5025 #endif
5026
5027 for(uctemp = 0; uctemp < usEMSCFreeBuffer; uctemp++)
5028 {
5029 bReveiceEMSC[uctemp +1] = _mhal_mhl_GetSRAMReceiveEMSCData();
5030
5031 if(uctemp == 1) // Check length remaining
5032 {
5033 usEMSCFreeBuffer = bReveiceEMSC[uctemp +1] +2;
5034 }
5035
5036 #if(MHL_DEBUG_RECEIVE_EMSC)
5037 MHAL_MHL_MSG_INFO("** MHL eMSC data %x\r\n", bReveiceEMSC[uctemp +1]);
5038 #endif
5039 }
5040
5041 W2BYTEMSK(REG_MHL_ECBUS_1C, usEMSCFreeBuffer, BMASK(9:0));
5042 W2BYTEMSK(REG_MHL_ECBUS_1C, BIT(15), BIT(15));
5043 }
5044
5045 //**************************************************************************
5046 // [Function Name]:
5047 // mhal_mhl_InsertEMSCSendData()
5048 // [Description]
5049 //
5050 // [Arguments]:
5051 //
5052 // [Return]:
5053 //
5054 //**************************************************************************
mhal_mhl_InsertEMSCSendData(MS_U8 ucLength,MS_U8 * bSendEMSC)5055 void mhal_mhl_InsertEMSCSendData(MS_U8 ucLength, MS_U8 *bSendEMSC)
5056 {
5057 MS_U8 uctemp = 0;
5058 MS_U16 usPayloadCRC = 0xFFFF;
5059
5060 if((ucLength > 0) && (bSendEMSC != NULL))
5061 {
5062 W2BYTEMSK(REG_MHL_ECBUS_1B, (ucLength -1), BMASK(9:0)); // Request command byte count
5063 W2BYTEMSK(REG_MHL_ECBUS_79, _mhal_mhl_GetEMSCTwoByteCRC(0, (ucLength -1)) , BMASK(2:0)); // byte count CRC
5064
5065 W2BYTEMSK(REG_MHL_ECBUS_21, 0, BMASK(9:0)); // SRAM address set 0
5066 W2BYTEMSK(REG_MHL_ECBUS_21, BIT(13), BIT(13)); // Trigger address
5067
5068 for(uctemp = 0; uctemp < ucLength; uctemp++)
5069 {
5070 _mhal_mhl_InsertSRAMSendEMSCData(bSendEMSC[uctemp]);
5071
5072 MHAL_MHL_MSG_INFO("** MHL payload value %x\r\n", bSendEMSC[uctemp]);
5073
5074 usPayloadCRC = _mhal_mhl_GetEMSCPayloadCRC(bSendEMSC[uctemp], usPayloadCRC);
5075 }
5076
5077 W2BYTEMSK(REG_MHL_ECBUS_19, BIT(15), BIT(15)); // eMSC payload CRC ove
5078 W2BYTE(REG_MHL_ECBUS_1A, (usPayloadCRC ^0xFFFF)); // eMSC payload CRC value
5079
5080 MHAL_MHL_MSG_INFO("** MHL payload CRC value %x\r\n", (usPayloadCRC ^0xFFFF));
5081
5082 W2BYTEMSK(REG_MHL_ECBUS_1B, BIT(15), BIT(15)); // REG_MHL_ECBUS2_1B[15]
5083 }
5084 }
5085
5086 //**************************************************************************
5087 // [Function Name]:
5088 // mhal_mhl_AutoEQEventProc()
5089 // [Description]
5090 //
5091 // [Arguments]:
5092 //
5093 // [Return]:
5094 //
5095 //**************************************************************************
mhal_mhl_AutoEQEventProc(MS_U8 ucCbusSelect,stMHL_SIGNAL_STATUS_INFO * pMHLSignalStatus)5096 void mhal_mhl_AutoEQEventProc(MS_U8 ucCbusSelect, stMHL_SIGNAL_STATUS_INFO *pMHLSignalStatus)
5097 {
5098 MS_BOOL bAutoEQTrigger = FALSE;
5099 MS_BOOL bAutoEQContinueFlag = FALSE;
5100
5101 if(pMHLSignalStatus->bAutoEnableFlag)
5102 {
5103 do
5104 {
5105 switch(pMHLSignalStatus->ucAutoEQState)
5106 {
5107 case MHL_AUTO_EQ_START:
5108 if(pMHLSignalStatus->ucStableCount >= MHL_AUTO_EQ_ENABLE_COUNTER)
5109 {
5110 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_ENABLE;
5111 }
5112 break;
5113
5114 case MHL_AUTO_EQ_ENABLE:
5115 _mhal_mhl_MHL30AutoEQEnable(ucCbusSelect, TRUE);
5116
5117 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_WAIT_DONE;
5118 bAutoEQTrigger = TRUE;
5119
5120 MHAL_MHL_MSG_INFO("** MHL auto EQ enable port %d\r\n", ucCbusSelect);
5121
5122 break;
5123
5124 case MHL_AUTO_EQ_WAIT_DONE:
5125 if(_mhal_mhl_GetAutoEQDoneFlag(ucCbusSelect))
5126 {
5127 MHAL_MHL_MSG_INFO("** MHL auto EQ done flag port %d\r\n", ucCbusSelect);
5128
5129 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_STABLE_DONE;
5130 }
5131 break;
5132
5133 case MHL_AUTO_EQ_STABLE_DONE:
5134 MHAL_MHL_MSG_INFO("** MHL auto EQ done completely port %d\r\n", ucCbusSelect);
5135
5136 pMHLSignalStatus->bAutoEnableFlag = FALSE;
5137
5138 break;
5139
5140 default:
5141
5142 break;
5143 };
5144 }while(bAutoEQContinueFlag);
5145
5146 if(bAutoEQTrigger)
5147 {
5148 _mhal_mhl_MHL3AutoEQTrigger(ucCbusSelect);
5149
5150 pMHLSignalStatus->ucAutoEQState = MHL_AUTO_EQ_WAIT_DONE;
5151 }
5152 }
5153 }
5154
5155 #endif // _MHAL_MHL_C_
5156
5157