1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef CEC_ANALOG_REG_H 96 #define CEC_ANALOG_REG_H 97 98 #include "cec_hwreg.h" 99 /******************************************************************************/ 100 /* Macro */ 101 /******************************************************************************/ 102 103 #ifndef UNUSED 104 #define UNUSED(x) ((x)=(x)) 105 #endif 106 107 /////////////////////////////////////////////////////// 108 // Scaler Bank 109 /////////////////////////////////////////////////////// 110 111 #define REG_BANK_RESET 0x00UL 112 #define REG_BANK_GOPINT 0x00UL 113 #define REG_BANK_IP1F2 0x01UL 114 #define REG_BANK_IP2F2 0x02UL 115 #define REG_BANK_IP1F1 0x03UL 116 #define REG_BANK_IP2F1 0x04UL 117 #define REG_BANK_OPM 0x05UL 118 #define REG_BANK_DNR 0x06UL 119 #define REG_BANK_OP1 0x07UL 120 #define REG_BANK_OP1PIP 0x08UL 121 #define REG_BANK_OP1HVSP 0x09UL 122 #define REG_BANK_FILM 0x0AUL //T2 123 #define REG_BANK_ELA 0x0BUL 124 #define REG_BANK_ACE 0x0CUL 125 #define REG_BANK_HD 0x0EUL 126 #define REG_BANK_S_VOP 0x0FUL 127 #define REG_BANK_VOP 0x10UL 128 #define REG_BANK_TCON 0x11UL 129 #define REG_BANK_SCMI 0x12UL //T2 130 #define REG_BANK_OD 0x16UL 131 #define REG_BANK_SRAM 0x17UL 132 #define REG_BANK_VIP 0x18UL 133 #define REG_BANK_VPS 0x19UL 134 #define REG_BANK_DLC 0x1AUL 135 #define REG_BANK_OP1PIPEXT 0x1BUL 136 #define REG_BANK_SmoothFilter 0x1CUL 137 #define REG_BANK_MFC 0x1DUL 138 #define REG_BANK_PIP 0x20UL 139 #define REG_BANK_EODI 0x21UL 140 #define REG_BANK_MADI 0x22UL 141 #define REG_BANK_HVSP 0x23UL 142 #define REG_BANK_DMS 0x26UL 143 #define REG_BANK_PRED 0x28UL 144 145 #define BK_SELECT_00 REG_SCALER_BASE 146 147 #define HIPART( u32x ) (((u32x) >> 16) & 0xFFFF) 148 #define LOPART( u32x ) ((u32x) & 0xFFFF) 149 150 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 151 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 152 153 /* Scaler */ 154 #define L_BK_GOPINT(x) BK_REG_L(REG_SCALER_BASE,x) 155 #define H_BK_GOPINT(x) BK_REG_H(REG_SCALER_BASE,x) 156 #define L_BK_SWRESET(x) BK_REG_L(REG_SCALER_BASE,x) 157 #define L_BK_IP1F2(x) BK_REG_L(REG_SCALER_BASE,x) 158 #define H_BK_IP1F2(x) BK_REG_H(REG_SCALER_BASE,x) 159 #define L_BK_IP2F2(x) BK_REG_L(REG_SCALER_BASE,x) 160 #define H_BK_IP2F2(x) BK_REG_H(REG_SCALER_BASE,x) 161 #define L_BK_IP1F1(x) BK_REG_L(REG_SCALER_BASE,x) 162 #define H_BK_IP1F1(x) BK_REG_H(REG_SCALER_BASE,x) 163 #define L_BK_IP2F1(x) BK_REG_L(REG_SCALER_BASE,x) 164 #define H_BK_IP2F1(x) BK_REG_H(REG_SCALER_BASE,x) 165 #define L_BK_OPM(x) BK_REG_L(REG_SCALER_BASE,x) 166 #define H_BK_OPM(x) BK_REG_H(REG_SCALER_BASE,x) 167 #define L_BK_DNR(x) BK_REG_L(REG_SCALER_BASE,x) 168 #define H_BK_DNR(x) BK_REG_H(REG_SCALER_BASE,x) 169 #define L_BK_OP1(x) BK_REG_L(REG_SCALER_BASE,x) 170 #define H_BK_OP1(x) BK_REG_H(REG_SCALER_BASE,x) 171 #define L_BK_OP1HVSP(x) BK_REG_L(REG_SCALER_BASE,x) 172 #define H_BK_OP1HVSP(x) BK_REG_H(REG_SCALER_BASE,x) 173 #define L_BK_ELA(x) BK_REG_L(REG_SCALER_BASE,x) 174 #define H_BK_ELA(x) BK_REG_H(REG_SCALER_BASE,x) 175 #define L_BK_ACE(x) BK_REG_L(REG_SCALER_BASE,x) 176 #define H_BK_ACE(x) BK_REG_H(REG_SCALER_BASE,x) 177 #define L_BK_HD(x) BK_REG_L(REG_SCALER_BASE,x) 178 #define H_BK_HD(x) BK_REG_H(REG_SCALER_BASE,x) 179 #define L_BK_S_VOP(x) BK_REG_L(REG_SCALER_BASE,x) 180 #define H_BK_S_VOP(x) BK_REG_H(REG_SCALER_BASE,x) 181 #define L_BK_VOP(x) BK_REG_L(REG_SCALER_BASE,x) 182 #define H_BK_VOP(x) BK_REG_H(REG_SCALER_BASE,x) 183 184 #define L_BK_SCMI(x) BK_REG_L(REG_SCALER_BASE,x) //SUPPORT_CHIP==T2 185 #define H_BK_SCMI(x) BK_REG_H(REG_SCALER_BASE,x) //SUPPORT_CHIP==T2 186 #define L_BK_OD(x) BK_REG_L(REG_SCALER_BASE,x) //SUPPORT_CHIP==T2 187 #define H_BK_OD(x) BK_REG_H(REG_SCALER_BASE,x) //SUPPORT_CHIP==T2 188 189 #define L_BK_OP1ZZ(x) BK_REG_L(REG_SCALER_BASE,x) 190 #define H_BK_OP1ZZ(x) BK_REG_H(REG_SCALER_BASE,x) 191 #define L_BK_VIP(x) BK_REG_L(REG_SCALER_BASE,x) 192 #define H_BK_VIP(x) BK_REG_H(REG_SCALER_BASE,x) 193 #define L_BK_VPS(x) BK_REG_L(REG_SCALER_BASE,x) 194 #define H_BK_VPS(x) BK_REG_H(REG_SCALER_BASE,x) 195 #define L_BK_DLC(x) BK_REG_L(REG_SCALER_BASE,x) 196 #define H_BK_DLC(x) BK_REG_H(REG_SCALER_BASE,x) 197 #define L_BK_OP1PIPEXT(x) BK_REG_L(REG_SCALER_BASE,x) 198 #define H_BK_OP1PIPEXT(x) BK_REG_H(REG_SCALER_BASE,x) 199 #define L_BK_SmoothFilter(x) BK_REG_L(REG_SCALER_BASE,x) 200 #define H_BK_SmoothFilter(x) BK_REG_H(REG_SCALER_BASE,x) 201 #define L_BK_MFC(x) BK_REG_L(REG_SCALER_BASE,x) 202 #define H_BK_MFC(x) BK_REG_H(REG_SCALER_BASE,x) 203 204 #define L_BK_EODI(x) BK_REG_L(REG_SCALER_BASE,x) 205 #define H_BK_EODI(x) BK_REG_H(REG_SCALER_BASE,x) 206 #define L_BK_MADI(x) BK_REG_L(REG_SCALER_BASE,x) 207 #define H_BK_MADI(x) BK_REG_H(REG_SCALER_BASE,x) 208 #define L_BK_PIP(x) BK_REG_L(REG_SCALER_BASE,x) 209 #define H_BK_PIP(x) BK_REG_H(REG_SCALER_BASE,x) 210 #define L_BK_HVSP(x) BK_REG_L(REG_SCALER_BASE,x) 211 #define H_BK_HVSP(x) BK_REG_H(REG_SCALER_BASE,x) 212 #define L_BK_PRED(x) BK_REG_L(REG_SCALER_BASE,x) 213 #define H_BK_PRED(x) BK_REG_H(REG_SCALER_BASE,x) 214 #define L_BK_FILM(x) BK_REG_L(REG_SCALER_BASE,x) 215 #define H_BK_FILM(x) BK_REG_H(REG_SCALER_BASE,x) 216 #define L_BK_DMS(x) BK_REG_L(REG_SCALER_BASE,x) 217 #define H_BK_DMS(x) BK_REG_H(REG_SCALER_BASE,x) 218 219 /* VE */ 220 #define L_BK_VE_ENC(x) BK_REG_L(REG_BASE_VE_ENCODER, x) 221 #define H_BK_VE_ENC(x) BK_REG_H(REG_BASE_VE_ENCODER, x) 222 #define L_BK_VE_SRC(x) BK_REG_L(REG_BASE_VE_SOURCE, x) 223 #define H_BK_VE_SRC(x) BK_REG_H(REG_BASE_VE_SOURCE, x) 224 225 226 /* LPLL */ 227 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 228 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 229 230 /* IP Mux */ 231 #define L_BK_IPMUX(x) BK_REG_L(REG_IPMUX_BASE, x) 232 #define H_BK_IPMUX(x) BK_REG_H(REG_IPMUX_BASE, x) 233 234 /* Chip Top */ 235 #define L_BK_CHIPTOP(x) BK_REG_L(REG_CHIPTOP_BASE, x) 236 #define H_BK_CHIPTOP(x) BK_REG_H(REG_CHIPTOP_BASE, x) 237 238 /* ADC */ 239 #define L_BK_ADC_ATOP(x) BK_REG_L(REG_ADC_ATOP_BASE, x) 240 #define H_BK_ADC_ATOP(x) BK_REG_H(REG_ADC_ATOP_BASE, x) 241 #define L_BK_ADC_DTOP(x) BK_REG_L(REG_ADC_DTOP_BASE, x) 242 #define H_BK_ADC_DTOP(x) BK_REG_H(REG_ADC_DTOP_BASE, x) 243 244 /* MOD */ 245 #define L_BK_MOD(x) BK_REG_L(REG_MOD_BASE, x) 246 #define H_BK_MOD(x) BK_REG_H(REG_MOD_BASE, x) 247 248 /* CEC */ 249 #define L_BK_CEC(x) BK_REG_L(REG_CEC_BASE, x) 250 #define H_BK_CEC(x) BK_REG_H(REG_CEC_BASE, x) 251 252 /* PM SLP */ 253 #define L_BK_PMSLP(x) BK_REG_L(REG_PM_SLP_BASE, x) 254 #define H_BK_PMSLP(x) BK_REG_H(REG_PM_SLP_BASE, x) 255 256 /* PM MCU */ 257 #define L_BK_PMMCU(x) BK_REG_L(REG_PM_MCU_BASE, x) 258 #define H_BK_PMMCU(x) BK_REG_H(REG_PM_MCU_BASE, x) 259 260 //------------------------------------------------------------------------------ 261 // Input source select 262 263 // BK_IP1F2_02 [2:0] 264 #define IP_INSSEL_ANALOG1 0x0000UL 265 #define IP_INSSEL_ANALOG2 0x0001UL 266 #define IP_INSSEL_ANALOG3 0x0002UL 267 #define IP_INSSEL_DVI 0x0003UL 268 #define IP_INSSEL_VIDEO 0x0004UL 269 #define IP_INSSEL_HDTV 0x0005UL 270 #define IP_INSSEL_HDMI 0x0007UL 271 272 #define IP_INSSEL_MASK BITMASK(2:0) 273 #define IP_VDOSEL_MASK BITMASK(1:0) 274 275 typedef enum 276 { 277 IP_CCIR656_A, 278 IP_MST_VD_A, 279 IP_CCIR601, 280 IP_MST_VD_B, // Don't use; RD's suggestion. 281 IP_CCIR656_B=0x20 282 } VDOSEL; 283 284 285 typedef enum 286 { 287 VE_IPMUX_ADC_A = 0, ///< ADC A 288 VE_IPMUX_HDMI_DVI = 1, ///< DVI 289 VE_IPMUX_VD = 2, ///< VD 290 VE_IPMUX_MVOP = 3, ///< MPEG/DC0 291 VE_IPMUX_SC_IP1 = 4, ///< Scaler IP1 output 292 VE_IPMUX_EXT_VD = 5, ///< External VD 293 VE_IPMUX_ADC_B = 6, ///< ADC B 294 } VE_IPMUX_TYPE; 295 296 typedef enum 297 { 298 AUTO_DETECT =0x00, 299 HV_SEPARATED =0x01, 300 COMPOSITE_SYNC =0x02, 301 SYNC_ON_GREEN =0x03 302 }STYPE; 303 304 typedef enum 305 { 306 CSYNC = 0, 307 SOG = 1 308 }COMP; 309 310 //------------------------------------------------------------------------------ 311 // ADC 312 313 #define ADC_AMUXA_MASK BITMASK(1:0) 314 #define ADC_YMUX_MASK BITMASK(3:0) 315 #define ADC_CMUX_MASK BITMASK(7:4) 316 317 318 //------------------------------------------------------------------------------ 319 // MUX 320 321 typedef enum 322 { 323 ADC_RGB1, 324 ADC_RGB2, 325 ADC_RGB3, 326 }AMUX_SEL; 327 328 typedef enum // For PC/YPbPr input mux 329 { 330 ANALOG_RGB0 = ADC_RGB1, 331 ANALOG_RGB1 = ADC_RGB2, 332 ANALOG_RGB2 = ADC_RGB3, 333 ANALOG_RGB_DUMMY, 334 }ANALOG_RGB; 335 336 typedef enum 337 { 338 MSVD_YMUX_CVBS0, 339 MSVD_YMUX_CVBS1, 340 MSVD_YMUX_CVBS2, 341 MSVD_YMUX_CVBS3, 342 343 MSVD_YMUX_Y0, 344 MSVD_YMUX_Y1, 345 MSVD_YMUX_C0, 346 MSVD_YMUX_C1, 347 348 MSVD_YMUX_SOG0 = 8, 349 MSVD_YMUX_SOG1, 350 MSVD_YMUX_SOG2, 351 352 MSVD_YMUX_G0 = 11, 353 MSVD_YMUX_G1 = 12, 354 MSVD_YMUX_G2 = 13, 355 MSVD_YMUX_CVBS4 = MSVD_YMUX_Y0, 356 MSVD_YMUX_CVBS5 = MSVD_YMUX_Y1, 357 MSVD_YMUX_CVBS6 = MSVD_YMUX_C0, 358 MSVD_YMUX_CVBS7 = MSVD_YMUX_C1, 359 MSVD_YMUX_NONE = 0xF, 360 361 MSVD_YMUX_DUMMY, 362 }MS_VD_YMUX; 363 364 typedef enum 365 { 366 MSVD_CMUX_CVBS0, 367 MSVD_CMUX_CVBS1, 368 MSVD_CMUX_CVBS2, 369 MSVD_CMUX_CVBS3, 370 371 MSVD_CMUX_Y0 = 4, 372 MSVD_CMUX_Y1, 373 MSVD_CMUX_C0, 374 MSVD_CMUX_C1, 375 376 MSVD_CMUX_SOG0 = 8, 377 MSVD_CMUX_SOG1, 378 MSVD_CMUX_SOG2, 379 380 MSVD_CMUX_R0 = 11, 381 MSVD_CMUX_R1 = 12, 382 MSVD_CMUX_R2 = 13, 383 MSVD_CMUX_CVBS4 = MSVD_CMUX_Y0, 384 MSVD_CMUX_CVBS5 = MSVD_CMUX_C0, 385 MSVD_CMUX_CVBS6 = MSVD_CMUX_Y1, 386 MSVD_CMUX_CVBS7 = MSVD_CMUX_C1, 387 MSVD_CMUX_NONE = 0xF, 388 389 MSVD_CMUX_DUMMY, 390 }MS_VD_CMUX; 391 392 //------------------------------------------------------------------------------ 393 // SCART 394 395 typedef enum // For specify scart RGB input 396 { 397 SCART_RGB0 = 0x00, 398 SCART_RGB1, 399 SCART_RGB2, 400 SCART_RGB_DUMMY, 401 }SCART_RGB; 402 403 typedef enum // 0x2580[5:4] 404 { 405 SCART_FB_NONE = 0x00, 406 SCART_FB0, 407 SCART_FB1, 408 SCART_FB2, 409 }SCART_FB; 410 411 #define SCART_RGB_NONE 0xFF 412 413 414 /////////////////////////////////////////////////////// 415 // MDHI bank 416 /////////////////////////////////////////////////////// 417 418 #define L(x) ((x) + 0) 419 #define H(x) ((x) + 1) 420 #define __REG_HDMI(idx) (REG_HDMI_BASE + (idx) * 2) 421 422 #define REG_HDMI_SYSCONFIG __REG_HDMI(0x00) 423 #define REG_HDMI_ST1 __REG_HDMI(0x01) 424 #define REG_HDMI_ST2 __REG_HDMI(0x02) 425 #define REG_HDMI_ERR1 __REG_HDMI(0x04) 426 #define REG_HDMI_CONFIG1 __REG_HDMI(0x06) 427 #define REG_HDMI_CONFIG2 __REG_HDMI(0x07) 428 #define REG_HDMI_CONFIG3 __REG_HDMI(0x08) 429 #define REG_HDMI_CONFIG4 __REG_HDMI(0x09) 430 #define REG_HDMI_CLK_CFG __REG_HDMI(0x0A) 431 #define REG_HDMI_TMCTRL __REG_HDMI(0x0B) 432 #define REG_HDMI_FREQ_CMPVAL1 __REG_HDMI(0x0C) 433 #define REG_HDMI_FREQ_CMPVAL2 __REG_HDMI(0x0D) 434 #define REG_HDMI_FREQ_CMPVAL3 __REG_HDMI(0x0E) 435 #define REG_HDMI_PKT_TYPE __REG_HDMI(0x10) 436 #define REG_HDMI_PCLK_FREQ __REG_HDMI(0x11) 437 #define REG_HDMI_AUDIO_CLK0 __REG_HDMI(0x12) 438 #define REG_HDMI_AUDIO_CLK1 __REG_HDMI(0x13) 439 #define REG_HDMI_AUDIO_CLK2 __REG_HDMI(0x14) 440 #define REG_HDMI_GCONTROL __REG_HDMI(0x15) 441 #define REG_HDMI_ACP_HB1 __REG_HDMI(0x16) 442 #define REG_HDMI_ACP_DATA0 __REG_HDMI(0x17) 443 #define REG_HDMI_ACP_DATA1 __REG_HDMI(0x18) 444 #define REG_HDMI_ACP_DATA2 __REG_HDMI(0x19) 445 #define REG_HDMI_ACP_DATA3 __REG_HDMI(0x1A) 446 #define REG_HDMI_ACP_DATA4 __REG_HDMI(0x1B) 447 #define REG_HDMI_ACP_DATA5 __REG_HDMI(0x1C) 448 #define REG_HDMI_ACP_DATA6 __REG_HDMI(0x1D) 449 #define REG_HDMI_ACP_DATA7 __REG_HDMI(0x1E) 450 #define REG_HDMI_ISRC_HB1 __REG_HDMI(0x1F) 451 #define REG_HDMI_ISRC_DATA0 __REG_HDMI(0x20) 452 #define REG_HDMI_ISRC_DATA1 __REG_HDMI(0x21) 453 #define REG_HDMI_ISRC_DATA2 __REG_HDMI(0x22) 454 #define REG_HDMI_ISRC_DATA3 __REG_HDMI(0x23) 455 #define REG_HDMI_ISRC_DATA4 __REG_HDMI(0x24) 456 #define REG_HDMI_ISRC_DATA5 __REG_HDMI(0x25) 457 #define REG_HDMI_ISRC_DATA6 __REG_HDMI(0x26) 458 #define REG_HDMI_ISRC_DATA7 __REG_HDMI(0x27) 459 #define REG_HDMI_ISRC_DATA8 __REG_HDMI(0x28) 460 #define REG_HDMI_ISRC_DATA9 __REG_HDMI(0x29) 461 #define REG_HDMI_ISRC_DATA10 __REG_HDMI(0x2A) 462 #define REG_HDMI_ISRC_DATA11 __REG_HDMI(0x2B) 463 #define REG_HDMI_ISRC_DATA12 __REG_HDMI(0x2C) 464 #define REG_HDMI_ISRC_DATA13 __REG_HDMI(0x2D) 465 #define REG_HDMI_ISRC_DATA14 __REG_HDMI(0x2E) 466 #define REG_HDMI_ISRC_DATA15 __REG_HDMI(0x2F) 467 #define REG_HDMI_VS_HDR0 __REG_HDMI(0x30) 468 #define REG_HDMI_VS_HDR1 __REG_HDMI(0x31) 469 #define REG_HDMI_VS_IF0 __REG_HDMI(0x32) 470 #define REG_HDMI_VS_IF1 __REG_HDMI(0x33) 471 #define REG_HDMI_VS_IF2 __REG_HDMI(0x34) 472 #define REG_HDMI_VS_IF3 __REG_HDMI(0x35) 473 #define REG_HDMI_VS_IF4 __REG_HDMI(0x36) 474 #define REG_HDMI_VS_IF5 __REG_HDMI(0x37) 475 #define REG_HDMI_VS_IF6 __REG_HDMI(0x38) 476 #define REG_HDMI_VS_IF7 __REG_HDMI(0x39) 477 #define REG_HDMI_VS_IF8 __REG_HDMI(0x3A) 478 #define REG_HDMI_VS_IF9 __REG_HDMI(0x3B) 479 #define REG_HDMI_VS_IF10 __REG_HDMI(0x3C) 480 #define REG_HDMI_VS_IF11 __REG_HDMI(0x3D) 481 #define REG_HDMI_VS_IF12 __REG_HDMI(0x3E) 482 #define REG_HDMI_VS_IF13 __REG_HDMI(0x3F) 483 #define REG_HDMI_AVI_IF0 __REG_HDMI(0x40) 484 #define REG_HDMI_AVI_IF1 __REG_HDMI(0x41) 485 #define REG_HDMI_AVI_IF2 __REG_HDMI(0x42) 486 #define REG_HDMI_AVI_IF3 __REG_HDMI(0x43) 487 #define REG_HDMI_AVI_IF4 __REG_HDMI(0x44) 488 #define REG_HDMI_AVI_IF5 __REG_HDMI(0x45) 489 #define REG_HDMI_AVI_IF6 __REG_HDMI(0x46) 490 #define REG_HDMI_SPD_IF0 __REG_HDMI(0x47) 491 #define REG_HDMI_SPD_IF1 __REG_HDMI(0x48) 492 #define REG_HDMI_SPD_IF2 __REG_HDMI(0x49) 493 #define REG_HDMI_SPD_IF3 __REG_HDMI(0x4A) 494 #define REG_HDMI_SPD_IF4 __REG_HDMI(0x4B) 495 #define REG_HDMI_SPD_IF5 __REG_HDMI(0x4C) 496 #define REG_HDMI_SPD_IF6 __REG_HDMI(0x4D) 497 #define REG_HDMI_SPD_IF7 __REG_HDMI(0x4E) 498 #define REG_HDMI_SPD_IF8 __REG_HDMI(0x4F) 499 #define REG_HDMI_SPD_IF9 __REG_HDMI(0x50) 500 #define REG_HDMI_SPD_IF10 __REG_HDMI(0x51) 501 #define REG_HDMI_SPD_IF11 __REG_HDMI(0x52) 502 #define REG_HDMI_SPD_IF12 __REG_HDMI(0x53) 503 #define REG_HDMI_AUDIO_IF0 __REG_HDMI(0x54) 504 #define REG_HDMI_AUDIO_IF1 __REG_HDMI(0x55) 505 #define REG_HDMI_AUDIO_IF2 __REG_HDMI(0x56) 506 #define REG_HDMI_MPEG_IF0 __REG_HDMI(0x57) 507 #define REG_HDMI_MPEG_IF1 __REG_HDMI(0x58) 508 #define REG_HDMI_MPEG_IF2 __REG_HDMI(0x59) 509 #define REG_HDMI_CS0 __REG_HDMI(0x5A) 510 #define REG_HDMI_CS1 __REG_HDMI(0x5B) 511 #define REG_HDMI_CS2 __REG_HDMI(0x5C) 512 #define REG_HDMI_PLL_CTRL1 __REG_HDMI(0x5D) 513 #define REG_HDMI_PLL_CTRL2 __REG_HDMI(0x5E) 514 #define REG_HDMI_PLL_CTRL3 __REG_HDMI(0x5F) 515 #define REG_HDMI_INT_MASK __REG_HDMI(0x60) 516 #define REG_HDMI_INT_STATUS __REG_HDMI(0x61) 517 #define REG_HDMI_INT_FORCE __REG_HDMI(0x62) 518 #define REG_HDMI_INT_CLEAR __REG_HDMI(0x63) 519 #define REG_HDMI_RESET_PACKET __REG_HDMI(0x64) 520 #define REG_HDMI_AUTO_MODE __REG_HDMI(0x65) 521 #define REG_HDMI_FRAME_RP_VAL __REG_HDMI(0x66) 522 #define REG_HDMI_CEC_CONFIG1 __REG_HDMI(0x67) 523 #define REG_HDMI_CEC_CONFIG2 __REG_HDMI(0x68) 524 #define REG_HDMI_CEC_CONFIG3 __REG_HDMI(0x69) 525 #define REG_HDMI_CEC_CONFIG4 __REG_HDMI(0x6A) 526 #define REG_HDMI_CEC_STATUS1 __REG_HDMI(0x6C) 527 #define REG_HDMI_CEC_TX_DATA0 __REG_HDMI(0x70) 528 #define REG_HDMI_CEC_TX_DATA1 __REG_HDMI(0x71) 529 #define REG_HDMI_CEC_RX_DATA0 __REG_HDMI(0x78) 530 #define REG_HDMI_CEC_RX_DATA1 __REG_HDMI(0x79) 531 532 533 #define __REG_HDCP(idx) (REG_HDCP_BASE + (idx) * 2) 534 535 #define REG_HDCP_00 __REG_HDCP(0x00) 536 #define REG_HDCP_STATUS __REG_HDCP(0x01) 537 #define REG_HDCP_02 __REG_HDCP(0x02) 538 #define REG_HDCP_03 __REG_HDCP(0x03) 539 540 #define REG_BANK_MACE 0x05UL 541 #define REG_BANK_COMB 0x06UL // VD Comb bank 542 543 //------------------------------------------------------------------------------ 544 // HDMI 545 546 #define MS_HDMI_ACP_PKT BIT11 547 #define MS_HDMI_ISRC1_PKT BIT10 548 #define MS_HDMI_ISRC2_PKT BIT9 549 #define MS_HDMI_NULL_PKT BIT8 550 #define MS_HDMI_VS_PKT BIT7 551 #define MS_HDMI_ACR_PKT BIT6 552 #define MS_HDMI_ASAMPLE_PKT BIT5 553 #define MS_HDMI_GC_PKT BIT4 554 #define MS_HDMI_AVI_PKT BIT3 555 #define MS_HDMI_SPD_PKT BIT2 556 #define MS_HDMI_AUI_PKT BIT1 557 #define MS_HDMI_MPEG_PKT BIT0 558 559 //------------------------------------------------------------------------------ 560 // DVI 561 562 typedef enum 563 { 564 DVI_SW_A, 565 DVI_SW_B, 566 }DVI_CH_SEL; 567 568 569 /////////////////////////////////////////////////////// 570 // AFEC bank 571 /////////////////////////////////////////////////////// 572 573 #define BK_AFEC_01 (AFEC_REG_BASE+0x01) 574 #define BK_AFEC_02 (AFEC_REG_BASE+0x02) 575 #define BK_AFEC_03 (AFEC_REG_BASE+0x03) 576 #define BK_AFEC_04 (AFEC_REG_BASE+0x04) 577 #define BK_AFEC_05 (AFEC_REG_BASE+0x05) 578 #define BK_AFEC_06 (AFEC_REG_BASE+0x06) 579 #define BK_AFEC_07 (AFEC_REG_BASE+0x07) 580 #define BK_AFEC_08 (AFEC_REG_BASE+0x08) 581 #define BK_AFEC_09 (AFEC_REG_BASE+0x09) 582 #define BK_AFEC_0A (AFEC_REG_BASE+0x0A) 583 #define BK_AFEC_0B (AFEC_REG_BASE+0x0B) 584 #define BK_AFEC_0C (AFEC_REG_BASE+0x0C) 585 #define BK_AFEC_0D (AFEC_REG_BASE+0x0D) 586 #define BK_AFEC_0E (AFEC_REG_BASE+0x0E) 587 #define BK_AFEC_0F (AFEC_REG_BASE+0x0F) 588 #define BK_AFEC_10 (AFEC_REG_BASE+0x10) 589 #define BK_AFEC_11 (AFEC_REG_BASE+0x11) 590 #define BK_AFEC_12 (AFEC_REG_BASE+0x12) 591 #define BK_AFEC_13 (AFEC_REG_BASE+0x13) 592 #define BK_AFEC_14 (AFEC_REG_BASE+0x14) 593 #define BK_AFEC_15 (AFEC_REG_BASE+0x15) 594 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) 595 #define BK_AFEC_17 (AFEC_REG_BASE+0x17) 596 #define BK_AFEC_18 (AFEC_REG_BASE+0x18) 597 #define BK_AFEC_19 (AFEC_REG_BASE+0x19) 598 #define BK_AFEC_1A (AFEC_REG_BASE+0x1A) 599 #define BK_AFEC_1B (AFEC_REG_BASE+0x1B) 600 #define BK_AFEC_1C (AFEC_REG_BASE+0x1C) 601 #define BK_AFEC_1D (AFEC_REG_BASE+0x1D) 602 #define BK_AFEC_1E (AFEC_REG_BASE+0x1E) 603 #define BK_AFEC_1F (AFEC_REG_BASE+0x1F) 604 #define BK_AFEC_20 (AFEC_REG_BASE+0x20) 605 #define BK_AFEC_21 (AFEC_REG_BASE+0x21) 606 #define BK_AFEC_22 (AFEC_REG_BASE+0x22) 607 #define BK_AFEC_23 (AFEC_REG_BASE+0x23) 608 #define BK_AFEC_24 (AFEC_REG_BASE+0x24) 609 #define BK_AFEC_25 (AFEC_REG_BASE+0x25) 610 #define BK_AFEC_26 (AFEC_REG_BASE+0x26) 611 #define BK_AFEC_27 (AFEC_REG_BASE+0x27) 612 #define BK_AFEC_28 (AFEC_REG_BASE+0x28) 613 #define BK_AFEC_29 (AFEC_REG_BASE+0x29) 614 #define BK_AFEC_2A (AFEC_REG_BASE+0x2A) 615 #define BK_AFEC_2B (AFEC_REG_BASE+0x2B) 616 #define BK_AFEC_2C (AFEC_REG_BASE+0x2C) 617 #define BK_AFEC_2D (AFEC_REG_BASE+0x2D) 618 #define BK_AFEC_2E (AFEC_REG_BASE+0x2E) 619 #define BK_AFEC_2F (AFEC_REG_BASE+0x2F) 620 #define BK_AFEC_30 (AFEC_REG_BASE+0x30) 621 #define BK_AFEC_31 (AFEC_REG_BASE+0x31) 622 #define BK_AFEC_32 (AFEC_REG_BASE+0x32) 623 #define BK_AFEC_33 (AFEC_REG_BASE+0x33) 624 #define BK_AFEC_34 (AFEC_REG_BASE+0x34) 625 #define BK_AFEC_35 (AFEC_REG_BASE+0x35) 626 #define BK_AFEC_36 (AFEC_REG_BASE+0x36) 627 #define BK_AFEC_37 (AFEC_REG_BASE+0x37) 628 #define BK_AFEC_38 (AFEC_REG_BASE+0x38) 629 #define BK_AFEC_39 (AFEC_REG_BASE+0x39) 630 #define BK_AFEC_3A (AFEC_REG_BASE+0x3A) 631 #define BK_AFEC_3B (AFEC_REG_BASE+0x3B) 632 #define BK_AFEC_3C (AFEC_REG_BASE+0x3C) 633 #define BK_AFEC_3D (AFEC_REG_BASE+0x3D) 634 #define BK_AFEC_3E (AFEC_REG_BASE+0x3E) 635 #define BK_AFEC_3F (AFEC_REG_BASE+0x3F) 636 #define BK_AFEC_40 (AFEC_REG_BASE+0x40) 637 #define BK_AFEC_41 (AFEC_REG_BASE+0x41) 638 #define BK_AFEC_42 (AFEC_REG_BASE+0x42) 639 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) 640 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) 641 #define BK_AFEC_45 (AFEC_REG_BASE+0x45) 642 #define BK_AFEC_46 (AFEC_REG_BASE+0x46) 643 #define BK_AFEC_47 (AFEC_REG_BASE+0x47) 644 #define BK_AFEC_48 (AFEC_REG_BASE+0x48) 645 #define BK_AFEC_49 (AFEC_REG_BASE+0x49) 646 #define BK_AFEC_4A (AFEC_REG_BASE+0x4A) 647 #define BK_AFEC_4B (AFEC_REG_BASE+0x4B) 648 #define BK_AFEC_4C (AFEC_REG_BASE+0x4C) 649 #define BK_AFEC_4D (AFEC_REG_BASE+0x4D) 650 #define BK_AFEC_4E (AFEC_REG_BASE+0x4E) 651 #define BK_AFEC_4F (AFEC_REG_BASE+0x4F) 652 #define BK_AFEC_50 (AFEC_REG_BASE+0x50) 653 #define BK_AFEC_51 (AFEC_REG_BASE+0x51) 654 #define BK_AFEC_52 (AFEC_REG_BASE+0x52) 655 #define BK_AFEC_53 (AFEC_REG_BASE+0x53) 656 #define BK_AFEC_54 (AFEC_REG_BASE+0x54) 657 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) 658 #define BK_AFEC_56 (AFEC_REG_BASE+0x56) 659 #define BK_AFEC_57 (AFEC_REG_BASE+0x57) 660 #define BK_AFEC_58 (AFEC_REG_BASE+0x58) 661 #define BK_AFEC_59 (AFEC_REG_BASE+0x59) 662 #define BK_AFEC_5A (AFEC_REG_BASE+0x5A) 663 #define BK_AFEC_5B (AFEC_REG_BASE+0x5B) 664 #define BK_AFEC_5C (AFEC_REG_BASE+0x5C) 665 #define BK_AFEC_5D (AFEC_REG_BASE+0x5D) 666 #define BK_AFEC_5E (AFEC_REG_BASE+0x5E) 667 #define BK_AFEC_5F (AFEC_REG_BASE+0x5F) 668 #define BK_AFEC_60 (AFEC_REG_BASE+0x60) 669 #define BK_AFEC_61 (AFEC_REG_BASE+0x61) 670 #define BK_AFEC_62 (AFEC_REG_BASE+0x62) 671 #define BK_AFEC_63 (AFEC_REG_BASE+0x63) 672 #define BK_AFEC_64 (AFEC_REG_BASE+0x64) 673 #define BK_AFEC_65 (AFEC_REG_BASE+0x65) 674 #define BK_AFEC_66 (AFEC_REG_BASE+0x66) 675 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) 676 #define BK_AFEC_68 (AFEC_REG_BASE+0x68) 677 #define BK_AFEC_69 (AFEC_REG_BASE+0x69) 678 #define BK_AFEC_6A (AFEC_REG_BASE+0x6A) 679 #define BK_AFEC_6B (AFEC_REG_BASE+0x6B) 680 #define BK_AFEC_6C (AFEC_REG_BASE+0x6C) 681 #define BK_AFEC_6D (AFEC_REG_BASE+0x6D) 682 #define BK_AFEC_6E (AFEC_REG_BASE+0x6E) 683 #define BK_AFEC_6F (AFEC_REG_BASE+0x6F) 684 #define BK_AFEC_70 (AFEC_REG_BASE+0x70) 685 #define BK_AFEC_71 (AFEC_REG_BASE+0x71) 686 #define BK_AFEC_72 (AFEC_REG_BASE+0x72) 687 #define BK_AFEC_73 (AFEC_REG_BASE+0x73) 688 #define BK_AFEC_74 (AFEC_REG_BASE+0x74) 689 #define BK_AFEC_75 (AFEC_REG_BASE+0x75) 690 #define BK_AFEC_76 (AFEC_REG_BASE+0x76) 691 #define BK_AFEC_77 (AFEC_REG_BASE+0x77) 692 #define BK_AFEC_78 (AFEC_REG_BASE+0x78) 693 #define BK_AFEC_79 (AFEC_REG_BASE+0x79) 694 #define BK_AFEC_7A (AFEC_REG_BASE+0x7A) 695 #define BK_AFEC_7B (AFEC_REG_BASE+0x7B) 696 #define BK_AFEC_7C (AFEC_REG_BASE+0x7C) 697 #define BK_AFEC_7D (AFEC_REG_BASE+0x7D) 698 #define BK_AFEC_7E (AFEC_REG_BASE+0x7E) 699 #define BK_AFEC_7F (AFEC_REG_BASE+0x7F) 700 #define BK_AFEC_80 (AFEC_REG_BASE+0x80) 701 #define BK_AFEC_81 (AFEC_REG_BASE+0x81) 702 #define BK_AFEC_82 (AFEC_REG_BASE+0x82) 703 #define BK_AFEC_83 (AFEC_REG_BASE+0x83) 704 #define BK_AFEC_84 (AFEC_REG_BASE+0x84) 705 #define BK_AFEC_85 (AFEC_REG_BASE+0x85) 706 #define BK_AFEC_86 (AFEC_REG_BASE+0x86) 707 #define BK_AFEC_87 (AFEC_REG_BASE+0x87) 708 #define BK_AFEC_88 (AFEC_REG_BASE+0x88) 709 #define BK_AFEC_89 (AFEC_REG_BASE+0x89) 710 #define BK_AFEC_8A (AFEC_REG_BASE+0x8A) 711 #define BK_AFEC_8B (AFEC_REG_BASE+0x8B) 712 #define BK_AFEC_8C (AFEC_REG_BASE+0x8C) 713 #define BK_AFEC_8D (AFEC_REG_BASE+0x8D) 714 #define BK_AFEC_8E (AFEC_REG_BASE+0x8E) 715 #define BK_AFEC_8F (AFEC_REG_BASE+0x8F) 716 #define BK_AFEC_90 (AFEC_REG_BASE+0x90) 717 #define BK_AFEC_91 (AFEC_REG_BASE+0x91) 718 #define BK_AFEC_92 (AFEC_REG_BASE+0x92) 719 #define BK_AFEC_93 (AFEC_REG_BASE+0x93) 720 #define BK_AFEC_94 (AFEC_REG_BASE+0x94) 721 #define BK_AFEC_95 (AFEC_REG_BASE+0x95) 722 #define BK_AFEC_96 (AFEC_REG_BASE+0x96) 723 #define BK_AFEC_97 (AFEC_REG_BASE+0x97) 724 #define BK_AFEC_98 (AFEC_REG_BASE+0x98) 725 #define BK_AFEC_99 (AFEC_REG_BASE+0x99) 726 #define BK_AFEC_9A (AFEC_REG_BASE+0x9A) 727 #define BK_AFEC_9B (AFEC_REG_BASE+0x9B) 728 #define BK_AFEC_9C (AFEC_REG_BASE+0x9C) 729 #define BK_AFEC_9D (AFEC_REG_BASE+0x9D) 730 #define BK_AFEC_9E (AFEC_REG_BASE+0x9E) 731 #define BK_AFEC_9F (AFEC_REG_BASE+0x9F) 732 #define BK_AFEC_A0 (AFEC_REG_BASE+0xA0) 733 #define BK_AFEC_A1 (AFEC_REG_BASE+0xA1) 734 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) 735 #define BK_AFEC_A3 (AFEC_REG_BASE+0xA3) 736 #define BK_AFEC_A4 (AFEC_REG_BASE+0xA4) 737 #define BK_AFEC_A5 (AFEC_REG_BASE+0xA5) 738 #define BK_AFEC_A6 (AFEC_REG_BASE+0xA6) 739 #define BK_AFEC_A7 (AFEC_REG_BASE+0xA7) 740 #define BK_AFEC_A8 (AFEC_REG_BASE+0xA8) 741 #define BK_AFEC_A9 (AFEC_REG_BASE+0xA9) 742 #define BK_AFEC_AA (AFEC_REG_BASE+0xAA) 743 #define BK_AFEC_AB (AFEC_REG_BASE+0xAB) 744 #define BK_AFEC_AC (AFEC_REG_BASE+0xAC) 745 #define BK_AFEC_AD (AFEC_REG_BASE+0xAD) 746 #define BK_AFEC_AE (AFEC_REG_BASE+0xAE) 747 #define BK_AFEC_AF (AFEC_REG_BASE+0xAF) 748 #define BK_AFEC_B0 (AFEC_REG_BASE+0xB0) 749 #define BK_AFEC_B1 (AFEC_REG_BASE+0xB1) 750 #define BK_AFEC_B2 (AFEC_REG_BASE+0xB2) 751 #define BK_AFEC_B3 (AFEC_REG_BASE+0xB3) 752 #define BK_AFEC_B4 (AFEC_REG_BASE+0xB4) 753 #define BK_AFEC_B5 (AFEC_REG_BASE+0xB5) 754 #define BK_AFEC_B6 (AFEC_REG_BASE+0xB6) 755 #define BK_AFEC_B7 (AFEC_REG_BASE+0xB7) 756 #define BK_AFEC_B8 (AFEC_REG_BASE+0xB8) 757 #define BK_AFEC_B9 (AFEC_REG_BASE+0xB9) 758 #define BK_AFEC_BA (AFEC_REG_BASE+0xBA) 759 #define BK_AFEC_BB (AFEC_REG_BASE+0xBB) 760 #define BK_AFEC_BC (AFEC_REG_BASE+0xBC) 761 #define BK_AFEC_BD (AFEC_REG_BASE+0xBD) 762 #define BK_AFEC_BE (AFEC_REG_BASE+0xBE) 763 #define BK_AFEC_BF (AFEC_REG_BASE+0xBF) 764 #define BK_AFEC_C0 (AFEC_REG_BASE+0xC0) 765 #define BK_AFEC_C1 (AFEC_REG_BASE+0xC1) 766 #define BK_AFEC_C2 (AFEC_REG_BASE+0xC2) 767 #define BK_AFEC_C3 (AFEC_REG_BASE+0xC3) 768 #define BK_AFEC_C4 (AFEC_REG_BASE+0xC4) 769 #define BK_AFEC_C5 (AFEC_REG_BASE+0xC5) 770 #define BK_AFEC_C6 (AFEC_REG_BASE+0xC6) 771 #define BK_AFEC_C7 (AFEC_REG_BASE+0xC7) 772 #define BK_AFEC_C8 (AFEC_REG_BASE+0xC8) 773 #define BK_AFEC_C9 (AFEC_REG_BASE+0xC9) 774 #define BK_AFEC_CA (AFEC_REG_BASE+0xCA) 775 #define BK_AFEC_CB (AFEC_REG_BASE+0xCB) 776 #define BK_AFEC_CC (AFEC_REG_BASE+0xCC) 777 #define BK_AFEC_CD (AFEC_REG_BASE+0xCD) 778 #define BK_AFEC_CE (AFEC_REG_BASE+0xCE) 779 #define BK_AFEC_CF (AFEC_REG_BASE+0xCF) 780 #define BK_AFEC_D0 (AFEC_REG_BASE+0xD0) 781 #define BK_AFEC_D1 (AFEC_REG_BASE+0xD1) 782 #define BK_AFEC_D2 (AFEC_REG_BASE+0xD2) 783 #define BK_AFEC_D3 (AFEC_REG_BASE+0xD3) 784 #define BK_AFEC_D4 (AFEC_REG_BASE+0xD4) 785 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) 786 #define BK_AFEC_D6 (AFEC_REG_BASE+0xD6) 787 #define BK_AFEC_D7 (AFEC_REG_BASE+0xD7) 788 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) 789 #define BK_AFEC_D9 (AFEC_REG_BASE+0xD9) 790 #define BK_AFEC_DA (AFEC_REG_BASE+0xDA) 791 #define BK_AFEC_DB (AFEC_REG_BASE+0xDB) 792 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) 793 #define BK_AFEC_DD (AFEC_REG_BASE+0xDD) 794 #define BK_AFEC_DE (AFEC_REG_BASE+0xDE) 795 #define BK_AFEC_DF (AFEC_REG_BASE+0xDF) 796 #define BK_AFEC_E0 (AFEC_REG_BASE+0xE0) 797 #define BK_AFEC_E1 (AFEC_REG_BASE+0xE1) 798 #define BK_AFEC_E2 (AFEC_REG_BASE+0xE2) 799 #define BK_AFEC_E3 (AFEC_REG_BASE+0xE3) 800 #define BK_AFEC_E4 (AFEC_REG_BASE+0xE4) 801 #define BK_AFEC_E5 (AFEC_REG_BASE+0xE5) 802 #define BK_AFEC_E6 (AFEC_REG_BASE+0xE6) 803 #define BK_AFEC_E7 (AFEC_REG_BASE+0xE7) 804 #define BK_AFEC_E8 (AFEC_REG_BASE+0xE8) 805 #define BK_AFEC_E9 (AFEC_REG_BASE+0xE9) 806 #define BK_AFEC_EA (AFEC_REG_BASE+0xEA) 807 #define BK_AFEC_EB (AFEC_REG_BASE+0xEB) 808 #define BK_AFEC_EC (AFEC_REG_BASE+0xEC) 809 #define BK_AFEC_ED (AFEC_REG_BASE+0xED) 810 #define BK_AFEC_EE (AFEC_REG_BASE+0xEE) 811 #define BK_AFEC_EF (AFEC_REG_BASE+0xEF) 812 #define BK_AFEC_F0 (AFEC_REG_BASE+0xF0) 813 #define BK_AFEC_F1 (AFEC_REG_BASE+0xF1) 814 #define BK_AFEC_F2 (AFEC_REG_BASE+0xF2) 815 #define BK_AFEC_F3 (AFEC_REG_BASE+0xF3) 816 #define BK_AFEC_F4 (AFEC_REG_BASE+0xF4) 817 #define BK_AFEC_F5 (AFEC_REG_BASE+0xF5) 818 #define BK_AFEC_F6 (AFEC_REG_BASE+0xF6) 819 #define BK_AFEC_F7 (AFEC_REG_BASE+0xF7) 820 #define BK_AFEC_F8 (AFEC_REG_BASE+0xF8) 821 #define BK_AFEC_F9 (AFEC_REG_BASE+0xF9) 822 #define BK_AFEC_FA (AFEC_REG_BASE+0xFA) 823 #define BK_AFEC_FB (AFEC_REG_BASE+0xFB) 824 #define BK_AFEC_FC (AFEC_REG_BASE+0xFC) 825 #define BK_AFEC_FD (AFEC_REG_BASE+0xFD) 826 #define BK_AFEC_FE (AFEC_REG_BASE+0xFE) 827 #define BK_AFEC_FF (AFEC_REG_BASE+0xFF) 828 829 830 //////////////////////////////////////////////////////////////////////////////// 831 // MACE bank 832 //////////////////////////////////////////////////////////////////////////////// 833 #define BK_MACE_01 0x01UL 834 #define BK_MACE_02 0x02UL 835 #define BK_MACE_03 0x03UL 836 #define BK_MACE_04 0x04UL 837 #define BK_MACE_05 0x05UL 838 #define BK_MACE_06 0x06UL 839 #define BK_MACE_07 0x07UL 840 #define BK_MACE_08 0x08UL 841 #define BK_MACE_09 0x09UL 842 #define BK_MACE_0A 0x0AUL 843 #define BK_MACE_0B 0x0BUL 844 #define BK_MACE_0C 0x0CUL 845 #define BK_MACE_0D 0x0DUL 846 #define BK_MACE_0E 0x0EUL 847 #define BK_MACE_0F 0x0FUL 848 #define BK_MACE_10 0x10UL 849 #define BK_MACE_11 0x11UL 850 #define BK_MACE_12 0x12UL 851 #define BK_MACE_13 0x13UL 852 #define BK_MACE_14 0x14UL 853 #define BK_MACE_15 0x15UL 854 #define BK_MACE_16 0x16UL 855 #define BK_MACE_17 0x17UL 856 #define BK_MACE_18 0x18UL 857 #define BK_MACE_19 0x19UL 858 #define BK_MACE_1A 0x1AUL 859 #define BK_MACE_1B 0x1BUL 860 #define BK_MACE_1C 0x1CUL 861 #define BK_MACE_1D 0x1DUL 862 #define BK_MACE_1E 0x1EUL 863 #define BK_MACE_1F 0x1FUL 864 #define BK_MACE_20 0x20UL 865 #define BK_MACE_21 0x21UL 866 #define BK_MACE_22 0x22UL 867 #define BK_MACE_23 0x23UL 868 #define BK_MACE_24 0x24UL 869 #define BK_MACE_25 0x25UL 870 #define BK_MACE_26 0x26UL 871 #define BK_MACE_27 0x27UL 872 #define BK_MACE_28 0x28UL 873 #define BK_MACE_29 0x29UL 874 #define BK_MACE_2A 0x2AUL 875 #define BK_MACE_2B 0x2BUL 876 #define BK_MACE_2C 0x2CUL 877 #define BK_MACE_2D 0x2DUL 878 #define BK_MACE_2E 0x2EUL 879 #define BK_MACE_2F 0x2FUL 880 #define BK_MACE_30 0x30UL 881 #define BK_MACE_31 0x31UL 882 #define BK_MACE_32 0x32UL 883 #define BK_MACE_33 0x33UL 884 #define BK_MACE_34 0x34UL 885 #define BK_MACE_35 0x35UL 886 #define BK_MACE_36 0x36UL 887 #define BK_MACE_37 0x37UL 888 #define BK_MACE_38 0x38UL 889 #define BK_MACE_39 0x39UL 890 #define BK_MACE_3A 0x3AUL 891 #define BK_MACE_3B 0x3BUL 892 #define BK_MACE_3C 0x3CUL 893 #define BK_MACE_3D 0x3DUL 894 #define BK_MACE_3E 0x3EUL 895 #define BK_MACE_3F 0x3FUL 896 #define BK_MACE_40 0x40UL 897 #define BK_MACE_41 0x41UL 898 #define BK_MACE_42 0x42UL 899 #define BK_MACE_43 0x43UL 900 #define BK_MACE_44 0x44UL 901 #define BK_MACE_45 0x45UL 902 #define BK_MACE_46 0x46UL 903 #define BK_MACE_47 0x47UL 904 #define BK_MACE_48 0x48UL 905 #define BK_MACE_49 0x49UL 906 #define BK_MACE_4A 0x4AUL 907 #define BK_MACE_4B 0x4BUL 908 #define BK_MACE_4C 0x4CUL 909 #define BK_MACE_4D 0x4DUL 910 #define BK_MACE_4E 0x4EUL 911 #define BK_MACE_4F 0x4FUL 912 #define BK_MACE_50 0x50UL 913 #define BK_MACE_51 0x51UL 914 #define BK_MACE_52 0x52UL 915 #define BK_MACE_53 0x53UL 916 #define BK_MACE_54 0x54UL 917 #define BK_MACE_55 0x55UL 918 #define BK_MACE_56 0x56UL 919 #define BK_MACE_57 0x57UL 920 #define BK_MACE_58 0x58UL 921 #define BK_MACE_59 0x59UL 922 #define BK_MACE_5A 0x5AUL 923 #define BK_MACE_5B 0x5BUL 924 #define BK_MACE_5C 0x5CUL 925 #define BK_MACE_5D 0x5DUL 926 #define BK_MACE_5E 0x5EUL 927 #define BK_MACE_5F 0x5FUL 928 #define BK_MACE_60 0x60UL 929 #define BK_MACE_61 0x61UL 930 #define BK_MACE_62 0x62UL 931 #define BK_MACE_63 0x63UL 932 #define BK_MACE_64 0x64UL 933 #define BK_MACE_65 0x65UL 934 #define BK_MACE_66 0x66UL 935 #define BK_MACE_67 0x67UL 936 #define BK_MACE_68 0x68UL 937 #define BK_MACE_69 0x69UL 938 #define BK_MACE_6A 0x6AUL 939 #define BK_MACE_6B 0x6BUL 940 #define BK_MACE_6C 0x6CUL 941 #define BK_MACE_6D 0x6DUL 942 #define BK_MACE_6E 0x6EUL 943 #define BK_MACE_6F 0x6FUL 944 #define BK_MACE_70 0x70UL 945 #define BK_MACE_71 0x71UL 946 #define BK_MACE_72 0x72UL 947 #define BK_MACE_73 0x73UL 948 #define BK_MACE_74 0x74UL 949 #define BK_MACE_75 0x75UL 950 #define BK_MACE_76 0x76UL 951 #define BK_MACE_77 0x77UL 952 #define BK_MACE_78 0x78UL 953 #define BK_MACE_79 0x79UL 954 #define BK_MACE_7A 0x7AUL 955 #define BK_MACE_7B 0x7BUL 956 #define BK_MACE_7C 0x7CUL 957 #define BK_MACE_7D 0x7DUL 958 #define BK_MACE_7E 0x7EUL 959 #define BK_MACE_7F 0x7FUL 960 #define BK_MACE_80 0x80UL 961 #define BK_MACE_81 0x81UL 962 #define BK_MACE_82 0x82UL 963 #define BK_MACE_83 0x83UL 964 #define BK_MACE_84 0x84UL 965 #define BK_MACE_85 0x85UL 966 #define BK_MACE_86 0x86UL 967 #define BK_MACE_87 0x87UL 968 #define BK_MACE_88 0x88UL 969 #define BK_MACE_89 0x89UL 970 #define BK_MACE_8A 0x8AUL 971 #define BK_MACE_8B 0x8BUL 972 #define BK_MACE_8C 0x8CUL 973 #define BK_MACE_8D 0x8DUL 974 #define BK_MACE_8E 0x8EUL 975 #define BK_MACE_8F 0x8FUL 976 #define BK_MACE_90 0x90UL 977 #define BK_MACE_91 0x91UL 978 #define BK_MACE_92 0x92UL 979 #define BK_MACE_93 0x93UL 980 #define BK_MACE_94 0x94UL 981 #define BK_MACE_95 0x95UL 982 #define BK_MACE_96 0x96UL 983 #define BK_MACE_97 0x97UL 984 #define BK_MACE_98 0x98UL 985 #define BK_MACE_99 0x99UL 986 #define BK_MACE_9A 0x9AUL 987 #define BK_MACE_9B 0x9BUL 988 #define BK_MACE_9C 0x9CUL 989 #define BK_MACE_9D 0x9DUL 990 #define BK_MACE_9E 0x9EUL 991 #define BK_MACE_9F 0x9FUL 992 #define BK_MACE_A0 0xA0UL 993 #define BK_MACE_A1 0xA1UL 994 #define BK_MACE_A2 0xA2UL 995 #define BK_MACE_A3 0xA3UL 996 #define BK_MACE_A4 0xA4UL 997 #define BK_MACE_A5 0xA5UL 998 #define BK_MACE_A6 0xA6UL 999 #define BK_MACE_A7 0xA7UL 1000 #define BK_MACE_A8 0xA8UL 1001 #define BK_MACE_A9 0xA9UL 1002 #define BK_MACE_AA 0xAAUL 1003 #define BK_MACE_AB 0xABUL 1004 #define BK_MACE_AC 0xACUL 1005 #define BK_MACE_AD 0xADUL 1006 #define BK_MACE_AE 0xAEUL 1007 #define BK_MACE_AF 0xAFUL 1008 #define BK_MACE_B0 0xB0UL 1009 #define BK_MACE_B1 0xB1UL 1010 #define BK_MACE_B2 0xB2UL 1011 #define BK_MACE_B3 0xB3UL 1012 #define BK_MACE_B4 0xB4UL 1013 #define BK_MACE_B5 0xB5UL 1014 #define BK_MACE_B6 0xB6UL 1015 #define BK_MACE_B7 0xB7UL 1016 #define BK_MACE_B8 0xB8UL 1017 #define BK_MACE_B9 0xB9UL 1018 #define BK_MACE_BA 0xBAUL 1019 #define BK_MACE_BB 0xBBUL 1020 #define BK_MACE_BC 0xBCUL 1021 #define BK_MACE_BD 0xBDUL 1022 #define BK_MACE_BE 0xBEUL 1023 #define BK_MACE_BF 0xBFUL 1024 #define BK_MACE_C0 0xC0UL 1025 #define BK_MACE_C1 0xC1UL 1026 #define BK_MACE_C2 0xC2UL 1027 #define BK_MACE_C3 0xC3UL 1028 #define BK_MACE_C4 0xC4UL 1029 #define BK_MACE_C5 0xC5UL 1030 #define BK_MACE_C6 0xC6UL 1031 #define BK_MACE_C7 0xC7UL 1032 #define BK_MACE_C8 0xC8UL 1033 #define BK_MACE_C9 0xC9UL 1034 #define BK_MACE_CA 0xCAUL 1035 #define BK_MACE_CB 0xCBUL 1036 #define BK_MACE_CC 0xCCUL 1037 #define BK_MACE_CD 0xCDUL 1038 #define BK_MACE_CE 0xCEUL 1039 #define BK_MACE_CF 0xCFUL 1040 #define BK_MACE_D0 0xD0UL 1041 #define BK_MACE_D1 0xD1UL 1042 #define BK_MACE_D2 0xD2UL 1043 #define BK_MACE_D3 0xD3UL 1044 #define BK_MACE_D4 0xD4UL 1045 #define BK_MACE_D5 0xD5UL 1046 #define BK_MACE_D6 0xD6UL 1047 #define BK_MACE_D7 0xD7UL 1048 #define BK_MACE_D8 0xD8UL 1049 #define BK_MACE_D9 0xD9UL 1050 #define BK_MACE_DA 0xDAUL 1051 #define BK_MACE_DB 0xDBUL 1052 #define BK_MACE_DC 0xDCUL 1053 #define BK_MACE_DD 0xDDUL 1054 #define BK_MACE_DE 0xDEUL 1055 #define BK_MACE_DF 0xDFUL 1056 #define BK_MACE_E0 0xE0UL 1057 #define BK_MACE_E1 0xE1UL 1058 #define BK_MACE_E2 0xE2UL 1059 #define BK_MACE_E3 0xE3UL 1060 #define BK_MACE_E4 0xE4UL 1061 #define BK_MACE_E5 0xE5UL 1062 #define BK_MACE_E6 0xE6UL 1063 #define BK_MACE_E7 0xE7UL 1064 #define BK_MACE_E8 0xE8UL 1065 #define BK_MACE_E9 0xE9UL 1066 #define BK_MACE_EA 0xEAUL 1067 #define BK_MACE_EB 0xEBUL 1068 #define BK_MACE_EC 0xECUL 1069 #define BK_MACE_ED 0xEDUL 1070 #define BK_MACE_EE 0xEEUL 1071 #define BK_MACE_EF 0xEFUL 1072 #define BK_MACE_F0 0xF0UL 1073 #define BK_MACE_F1 0xF1UL 1074 #define BK_MACE_F2 0xF2UL 1075 #define BK_MACE_F3 0xF3UL 1076 #define BK_MACE_F4 0xF4UL 1077 #define BK_MACE_F5 0xF5UL 1078 #define BK_MACE_F6 0xF6UL 1079 #define BK_MACE_F7 0xF7UL 1080 #define BK_MACE_F8 0xF8UL 1081 #define BK_MACE_F9 0xF9UL 1082 #define BK_MACE_FA 0xFAUL 1083 #define BK_MACE_FB 0xFBUL 1084 #define BK_MACE_FC 0xFCUL 1085 #define BK_MACE_FD 0xFDUL 1086 #define BK_MACE_FE 0xFEUL 1087 #define BK_MACE_FF 0xFFUL 1088 1089 1090 //////////////////////////////////////////////////////////////////////////////// 1091 // Comb filter bank 1092 //////////////////////////////////////////////////////////////////////////////// 1093 1094 #define BK_COMB_01 (COMB_REG_BASE+0x01) 1095 #define BK_COMB_02 (COMB_REG_BASE+0x02) 1096 #define BK_COMB_03 (COMB_REG_BASE+0x03) 1097 #define BK_COMB_04 (COMB_REG_BASE+0x04) 1098 #define BK_COMB_05 (COMB_REG_BASE+0x05) 1099 #define BK_COMB_06 (COMB_REG_BASE+0x06) 1100 #define BK_COMB_07 (COMB_REG_BASE+0x07) 1101 #define BK_COMB_08 (COMB_REG_BASE+0x08) 1102 #define BK_COMB_09 (COMB_REG_BASE+0x09) 1103 #define BK_COMB_0A (COMB_REG_BASE+0x0A) 1104 #define BK_COMB_0B (COMB_REG_BASE+0x0B) 1105 #define BK_COMB_0C (COMB_REG_BASE+0x0C) 1106 #define BK_COMB_0D (COMB_REG_BASE+0x0D) 1107 #define BK_COMB_0E (COMB_REG_BASE+0x0E) 1108 #define BK_COMB_0F (COMB_REG_BASE+0x0F) 1109 #define BK_COMB_10 (COMB_REG_BASE+0x10) 1110 #define BK_COMB_11 (COMB_REG_BASE+0x11) 1111 #define BK_COMB_12 (COMB_REG_BASE+0x12) 1112 #define BK_COMB_13 (COMB_REG_BASE+0x13) 1113 #define BK_COMB_14 (COMB_REG_BASE+0x14) 1114 #define BK_COMB_15 (COMB_REG_BASE+0x15) 1115 #define BK_COMB_16 (COMB_REG_BASE+0x16) 1116 #define BK_COMB_17 (COMB_REG_BASE+0x17) 1117 #define BK_COMB_18 (COMB_REG_BASE+0x18) 1118 #define BK_COMB_19 (COMB_REG_BASE+0x19) 1119 #define BK_COMB_1A (COMB_REG_BASE+0x1A) 1120 #define BK_COMB_1B (COMB_REG_BASE+0x1B) 1121 #define BK_COMB_1C (COMB_REG_BASE+0x1C) 1122 #define BK_COMB_1D (COMB_REG_BASE+0x1D) 1123 #define BK_COMB_1E (COMB_REG_BASE+0x1E) 1124 #define BK_COMB_1F (COMB_REG_BASE+0x1F) 1125 #define BK_COMB_20 (COMB_REG_BASE+0x20) 1126 #define BK_COMB_21 (COMB_REG_BASE+0x21) 1127 #define BK_COMB_22 (COMB_REG_BASE+0x22) 1128 #define BK_COMB_23 (COMB_REG_BASE+0x23) 1129 #define BK_COMB_24 (COMB_REG_BASE+0x24) 1130 #define BK_COMB_25 (COMB_REG_BASE+0x25) 1131 #define BK_COMB_26 (COMB_REG_BASE+0x26) 1132 #define BK_COMB_27 (COMB_REG_BASE+0x27) 1133 #define BK_COMB_28 (COMB_REG_BASE+0x28) 1134 #define BK_COMB_29 (COMB_REG_BASE+0x29) 1135 #define BK_COMB_2A (COMB_REG_BASE+0x2A) 1136 #define BK_COMB_2B (COMB_REG_BASE+0x2B) 1137 #define BK_COMB_2C (COMB_REG_BASE+0x2C) 1138 #define BK_COMB_2D (COMB_REG_BASE+0x2D) 1139 #define BK_COMB_2E (COMB_REG_BASE+0x2E) 1140 #define BK_COMB_2F (COMB_REG_BASE+0x2F) 1141 #define BK_COMB_30 (COMB_REG_BASE+0x30) 1142 #define BK_COMB_31 (COMB_REG_BASE+0x31) 1143 #define BK_COMB_32 (COMB_REG_BASE+0x32) 1144 #define BK_COMB_33 (COMB_REG_BASE+0x33) 1145 #define BK_COMB_34 (COMB_REG_BASE+0x34) 1146 #define BK_COMB_35 (COMB_REG_BASE+0x35) 1147 #define BK_COMB_36 (COMB_REG_BASE+0x36) 1148 #define BK_COMB_37 (COMB_REG_BASE+0x37) 1149 #define BK_COMB_38 (COMB_REG_BASE+0x38) 1150 #define BK_COMB_39 (COMB_REG_BASE+0x39) 1151 #define BK_COMB_3A (COMB_REG_BASE+0x3A) 1152 #define BK_COMB_3B (COMB_REG_BASE+0x3B) 1153 #define BK_COMB_3C (COMB_REG_BASE+0x3C) 1154 #define BK_COMB_3D (COMB_REG_BASE+0x3D) 1155 #define BK_COMB_3E (COMB_REG_BASE+0x3E) 1156 #define BK_COMB_3F (COMB_REG_BASE+0x3F) 1157 #define BK_COMB_40 (COMB_REG_BASE+0x40) 1158 #define BK_COMB_41 (COMB_REG_BASE+0x41) 1159 #define BK_COMB_42 (COMB_REG_BASE+0x42) 1160 #define BK_COMB_43 (COMB_REG_BASE+0x43) 1161 #define BK_COMB_44 (COMB_REG_BASE+0x44) 1162 #define BK_COMB_45 (COMB_REG_BASE+0x45) 1163 #define BK_COMB_46 (COMB_REG_BASE+0x46) 1164 #define BK_COMB_47 (COMB_REG_BASE+0x47) 1165 #define BK_COMB_48 (COMB_REG_BASE+0x48) 1166 #define BK_COMB_49 (COMB_REG_BASE+0x49) 1167 #define BK_COMB_4A (COMB_REG_BASE+0x4A) 1168 #define BK_COMB_4B (COMB_REG_BASE+0x4B) 1169 #define BK_COMB_4C (COMB_REG_BASE+0x4C) 1170 #define BK_COMB_4D (COMB_REG_BASE+0x4D) 1171 #define BK_COMB_4E (COMB_REG_BASE+0x4E) 1172 #define BK_COMB_4F (COMB_REG_BASE+0x4F) 1173 #define BK_COMB_50 (COMB_REG_BASE+0x50) 1174 #define BK_COMB_51 (COMB_REG_BASE+0x51) 1175 #define BK_COMB_52 (COMB_REG_BASE+0x52) 1176 #define BK_COMB_53 (COMB_REG_BASE+0x53) 1177 #define BK_COMB_54 (COMB_REG_BASE+0x54) 1178 #define BK_COMB_55 (COMB_REG_BASE+0x55) 1179 #define BK_COMB_56 (COMB_REG_BASE+0x56) 1180 #define BK_COMB_57 (COMB_REG_BASE+0x57) 1181 #define BK_COMB_58 (COMB_REG_BASE+0x58) 1182 #define BK_COMB_59 (COMB_REG_BASE+0x59) 1183 #define BK_COMB_5A (COMB_REG_BASE+0x5A) 1184 #define BK_COMB_5B (COMB_REG_BASE+0x5B) 1185 #define BK_COMB_5C (COMB_REG_BASE+0x5C) 1186 #define BK_COMB_5D (COMB_REG_BASE+0x5D) 1187 #define BK_COMB_5E (COMB_REG_BASE+0x5E) 1188 #define BK_COMB_5F (COMB_REG_BASE+0x5F) 1189 #define BK_COMB_60 (COMB_REG_BASE+0x60) 1190 #define BK_COMB_61 (COMB_REG_BASE+0x61) 1191 #define BK_COMB_62 (COMB_REG_BASE+0x62) 1192 #define BK_COMB_63 (COMB_REG_BASE+0x63) 1193 #define BK_COMB_64 (COMB_REG_BASE+0x64) 1194 #define BK_COMB_65 (COMB_REG_BASE+0x65) 1195 #define BK_COMB_66 (COMB_REG_BASE+0x66) 1196 #define BK_COMB_67 (COMB_REG_BASE+0x67) 1197 #define BK_COMB_68 (COMB_REG_BASE+0x68) 1198 #define BK_COMB_69 (COMB_REG_BASE+0x69) 1199 #define BK_COMB_6A (COMB_REG_BASE+0x6A) 1200 #define BK_COMB_6B (COMB_REG_BASE+0x6B) 1201 #define BK_COMB_6C (COMB_REG_BASE+0x6C) 1202 #define BK_COMB_6D (COMB_REG_BASE+0x6D) 1203 #define BK_COMB_6E (COMB_REG_BASE+0x6E) 1204 #define BK_COMB_6F (COMB_REG_BASE+0x6F) 1205 #define BK_COMB_70 (COMB_REG_BASE+0x70) 1206 #define BK_COMB_71 (COMB_REG_BASE+0x71) 1207 #define BK_COMB_72 (COMB_REG_BASE+0x72) 1208 #define BK_COMB_73 (COMB_REG_BASE+0x73) 1209 #define BK_COMB_74 (COMB_REG_BASE+0x74) 1210 #define BK_COMB_75 (COMB_REG_BASE+0x75) 1211 #define BK_COMB_76 (COMB_REG_BASE+0x76) 1212 #define BK_COMB_77 (COMB_REG_BASE+0x77) 1213 #define BK_COMB_78 (COMB_REG_BASE+0x78) 1214 #define BK_COMB_79 (COMB_REG_BASE+0x79) 1215 #define BK_COMB_7A (COMB_REG_BASE+0x7A) 1216 #define BK_COMB_7B (COMB_REG_BASE+0x7B) 1217 #define BK_COMB_7C (COMB_REG_BASE+0x7C) 1218 #define BK_COMB_7D (COMB_REG_BASE+0x7D) 1219 #define BK_COMB_7E (COMB_REG_BASE+0x7E) 1220 #define BK_COMB_7F (COMB_REG_BASE+0x7F) 1221 #define BK_COMB_80 (COMB_REG_BASE+0x80) 1222 #define BK_COMB_81 (COMB_REG_BASE+0x81) 1223 #define BK_COMB_82 (COMB_REG_BASE+0x82) 1224 #define BK_COMB_83 (COMB_REG_BASE+0x83) 1225 #define BK_COMB_84 (COMB_REG_BASE+0x84) 1226 #define BK_COMB_85 (COMB_REG_BASE+0x85) 1227 #define BK_COMB_86 (COMB_REG_BASE+0x86) 1228 #define BK_COMB_87 (COMB_REG_BASE+0x87) 1229 #define BK_COMB_88 (COMB_REG_BASE+0x88) 1230 #define BK_COMB_89 (COMB_REG_BASE+0x89) 1231 #define BK_COMB_8A (COMB_REG_BASE+0x8A) 1232 #define BK_COMB_8B (COMB_REG_BASE+0x8B) 1233 #define BK_COMB_8C (COMB_REG_BASE+0x8C) 1234 #define BK_COMB_8D (COMB_REG_BASE+0x8D) 1235 #define BK_COMB_8E (COMB_REG_BASE+0x8E) 1236 #define BK_COMB_8F (COMB_REG_BASE+0x8F) 1237 #define BK_COMB_90 (COMB_REG_BASE+0x90) 1238 #define BK_COMB_91 (COMB_REG_BASE+0x91) 1239 #define BK_COMB_92 (COMB_REG_BASE+0x92) 1240 #define BK_COMB_93 (COMB_REG_BASE+0x93) 1241 #define BK_COMB_94 (COMB_REG_BASE+0x94) 1242 #define BK_COMB_95 (COMB_REG_BASE+0x95) 1243 #define BK_COMB_96 (COMB_REG_BASE+0x96) 1244 #define BK_COMB_97 (COMB_REG_BASE+0x97) 1245 #define BK_COMB_98 (COMB_REG_BASE+0x98) 1246 #define BK_COMB_99 (COMB_REG_BASE+0x99) 1247 #define BK_COMB_9A (COMB_REG_BASE+0x9A) 1248 #define BK_COMB_9B (COMB_REG_BASE+0x9B) 1249 #define BK_COMB_9C (COMB_REG_BASE+0x9C) 1250 #define BK_COMB_9D (COMB_REG_BASE+0x9D) 1251 #define BK_COMB_9E (COMB_REG_BASE+0x9E) 1252 #define BK_COMB_9F (COMB_REG_BASE+0x9F) 1253 #define BK_COMB_A0 (COMB_REG_BASE+0xA0) 1254 #define BK_COMB_A1 (COMB_REG_BASE+0xA1) 1255 #define BK_COMB_A2 (COMB_REG_BASE+0xA2) 1256 #define BK_COMB_A3 (COMB_REG_BASE+0xA3) 1257 #define BK_COMB_A4 (COMB_REG_BASE+0xA4) 1258 #define BK_COMB_A5 (COMB_REG_BASE+0xA5) 1259 #define BK_COMB_A6 (COMB_REG_BASE+0xA6) 1260 #define BK_COMB_A7 (COMB_REG_BASE+0xA7) 1261 #define BK_COMB_A8 (COMB_REG_BASE+0xA8) 1262 #define BK_COMB_A9 (COMB_REG_BASE+0xA9) 1263 #define BK_COMB_AA (COMB_REG_BASE+0xAA) 1264 #define BK_COMB_AB (COMB_REG_BASE+0xAB) 1265 #define BK_COMB_AC (COMB_REG_BASE+0xAC) 1266 #define BK_COMB_AD (COMB_REG_BASE+0xAD) 1267 #define BK_COMB_AE (COMB_REG_BASE+0xAE) 1268 #define BK_COMB_AF (COMB_REG_BASE+0xAF) 1269 #define BK_COMB_B0 (COMB_REG_BASE+0xB0) 1270 #define BK_COMB_B1 (COMB_REG_BASE+0xB1) 1271 #define BK_COMB_B2 (COMB_REG_BASE+0xB2) 1272 #define BK_COMB_B3 (COMB_REG_BASE+0xB3) 1273 #define BK_COMB_B4 (COMB_REG_BASE+0xB4) 1274 #define BK_COMB_B5 (COMB_REG_BASE+0xB5) 1275 #define BK_COMB_B6 (COMB_REG_BASE+0xB6) 1276 #define BK_COMB_B7 (COMB_REG_BASE+0xB7) 1277 #define BK_COMB_B8 (COMB_REG_BASE+0xB8) 1278 #define BK_COMB_B9 (COMB_REG_BASE+0xB9) 1279 #define BK_COMB_BA (COMB_REG_BASE+0xBA) 1280 #define BK_COMB_BB (COMB_REG_BASE+0xBB) 1281 #define BK_COMB_BC (COMB_REG_BASE+0xBC) 1282 #define BK_COMB_BD (COMB_REG_BASE+0xBD) 1283 #define BK_COMB_BE (COMB_REG_BASE+0xBE) 1284 #define BK_COMB_BF (COMB_REG_BASE+0xBF) 1285 #define BK_COMB_C0 (COMB_REG_BASE+0xC0) 1286 #define BK_COMB_C1 (COMB_REG_BASE+0xC1) 1287 #define BK_COMB_C2 (COMB_REG_BASE+0xC2) 1288 #define BK_COMB_C3 (COMB_REG_BASE+0xC3) 1289 #define BK_COMB_C4 (COMB_REG_BASE+0xC4) 1290 #define BK_COMB_C5 (COMB_REG_BASE+0xC5) 1291 #define BK_COMB_C6 (COMB_REG_BASE+0xC6) 1292 #define BK_COMB_C7 (COMB_REG_BASE+0xC7) 1293 #define BK_COMB_C8 (COMB_REG_BASE+0xC8) 1294 #define BK_COMB_C9 (COMB_REG_BASE+0xC9) 1295 #define BK_COMB_CA (COMB_REG_BASE+0xCA) 1296 #define BK_COMB_CB (COMB_REG_BASE+0xCB) 1297 #define BK_COMB_CC (COMB_REG_BASE+0xCC) 1298 #define BK_COMB_CD (COMB_REG_BASE+0xCD) 1299 #define BK_COMB_CE (COMB_REG_BASE+0xCE) 1300 #define BK_COMB_CF (COMB_REG_BASE+0xCF) 1301 #define BK_COMB_D0 (COMB_REG_BASE+0xD0) 1302 #define BK_COMB_D1 (COMB_REG_BASE+0xD1) 1303 #define BK_COMB_D2 (COMB_REG_BASE+0xD2) 1304 #define BK_COMB_D3 (COMB_REG_BASE+0xD3) 1305 #define BK_COMB_D4 (COMB_REG_BASE+0xD4) 1306 #define BK_COMB_D5 (COMB_REG_BASE+0xD5) 1307 #define BK_COMB_D6 (COMB_REG_BASE+0xD6) 1308 #define BK_COMB_D7 (COMB_REG_BASE+0xD7) 1309 #define BK_COMB_D8 (COMB_REG_BASE+0xD8) 1310 #define BK_COMB_D9 (COMB_REG_BASE+0xD9) 1311 #define BK_COMB_DA (COMB_REG_BASE+0xDA) 1312 #define BK_COMB_DB (COMB_REG_BASE+0xDB) 1313 #define BK_COMB_DC (COMB_REG_BASE+0xDC) 1314 #define BK_COMB_DD (COMB_REG_BASE+0xDD) 1315 #define BK_COMB_DE (COMB_REG_BASE+0xDE) 1316 #define BK_COMB_DF (COMB_REG_BASE+0xDF) 1317 #define BK_COMB_E0 (COMB_REG_BASE+0xE0) 1318 #define BK_COMB_E1 (COMB_REG_BASE+0xE1) 1319 #define BK_COMB_E2 (COMB_REG_BASE+0xE2) 1320 #define BK_COMB_E3 (COMB_REG_BASE+0xE3) 1321 #define BK_COMB_E4 (COMB_REG_BASE+0xE4) 1322 #define BK_COMB_E5 (COMB_REG_BASE+0xE5) 1323 #define BK_COMB_E6 (COMB_REG_BASE+0xE6) 1324 #define BK_COMB_E7 (COMB_REG_BASE+0xE7) 1325 #define BK_COMB_E8 (COMB_REG_BASE+0xE8) 1326 #define BK_COMB_E9 (COMB_REG_BASE+0xE9) 1327 #define BK_COMB_EA (COMB_REG_BASE+0xEA) 1328 #define BK_COMB_EB (COMB_REG_BASE+0xEB) 1329 #define BK_COMB_EC (COMB_REG_BASE+0xEC) 1330 #define BK_COMB_ED (COMB_REG_BASE+0xED) 1331 #define BK_COMB_EE (COMB_REG_BASE+0xEE) 1332 #define BK_COMB_EF (COMB_REG_BASE+0xEF) 1333 #define BK_COMB_F0 (COMB_REG_BASE+0xF0) 1334 #define BK_COMB_F1 (COMB_REG_BASE+0xF1) 1335 #define BK_COMB_F2 (COMB_REG_BASE+0xF2) 1336 #define BK_COMB_F3 (COMB_REG_BASE+0xF3) 1337 #define BK_COMB_F4 (COMB_REG_BASE+0xF4) 1338 #define BK_COMB_F5 (COMB_REG_BASE+0xF5) 1339 #define BK_COMB_F6 (COMB_REG_BASE+0xF6) 1340 #define BK_COMB_F7 (COMB_REG_BASE+0xF7) 1341 #define BK_COMB_F8 (COMB_REG_BASE+0xF8) 1342 #define BK_COMB_F9 (COMB_REG_BASE+0xF9) 1343 #define BK_COMB_FA (COMB_REG_BASE+0xFA) 1344 #define BK_COMB_FB (COMB_REG_BASE+0xFB) 1345 #define BK_COMB_FC (COMB_REG_BASE+0xFC) 1346 #define BK_COMB_FD (COMB_REG_BASE+0xFD) 1347 #define BK_COMB_FE (COMB_REG_BASE+0xFE) 1348 #define BK_COMB_FF (COMB_REG_BASE+0xFF) 1349 1350 1351 //////////////////////////////////////////////////////////////////////////////// 1352 // SECAM register 1353 //////////////////////////////////////////////////////////////////////////////// 1354 #define BK_SECAM_01 (SCM_REG_BASE+0x01) 1355 #define BK_SECAM_02 (SCM_REG_BASE+0x02) 1356 #define BK_SECAM_03 (SCM_REG_BASE+0x03) 1357 #define BK_SECAM_04 (SCM_REG_BASE+0x04) 1358 #define BK_SECAM_05 (SCM_REG_BASE+0x05) 1359 #define BK_SECAM_06 (SCM_REG_BASE+0x06) 1360 #define BK_SECAM_07 (SCM_REG_BASE+0x07) 1361 #define BK_SECAM_08 (SCM_REG_BASE+0x08) 1362 #define BK_SECAM_09 (SCM_REG_BASE+0x09) 1363 #define BK_SECAM_0A (SCM_REG_BASE+0x0A) 1364 #define BK_SECAM_0B (SCM_REG_BASE+0x0B) 1365 #define BK_SECAM_0C (SCM_REG_BASE+0x0C) 1366 #define BK_SECAM_0D (SCM_REG_BASE+0x0D) 1367 #define BK_SECAM_0E (SCM_REG_BASE+0x0E) 1368 #define BK_SECAM_0F (SCM_REG_BASE+0x0F) 1369 #define BK_SECAM_10 (SCM_REG_BASE+0x10) 1370 #define BK_SECAM_11 (SCM_REG_BASE+0x11) 1371 #define BK_SECAM_12 (SCM_REG_BASE+0x12) 1372 #define BK_SECAM_13 (SCM_REG_BASE+0x13) 1373 #define BK_SECAM_14 (SCM_REG_BASE+0x14) 1374 #define BK_SECAM_15 (SCM_REG_BASE+0x15) 1375 #define BK_SECAM_16 (SCM_REG_BASE+0x16) 1376 #define BK_SECAM_17 (SCM_REG_BASE+0x17) 1377 #define BK_SECAM_18 (SCM_REG_BASE+0x18) 1378 #define BK_SECAM_19 (SCM_REG_BASE+0x19) 1379 #define BK_SECAM_1A (SCM_REG_BASE+0x1A) 1380 #define BK_SECAM_1B (SCM_REG_BASE+0x1B) 1381 #define BK_SECAM_1C (SCM_REG_BASE+0x1C) 1382 #define BK_SECAM_1D (SCM_REG_BASE+0x1D) 1383 #define BK_SECAM_1E (SCM_REG_BASE+0x1E) 1384 #define BK_SECAM_1F (SCM_REG_BASE+0x1F) 1385 #define BK_SECAM_20 (SCM_REG_BASE+0x20) 1386 #define BK_SECAM_21 (SCM_REG_BASE+0x21) 1387 #define BK_SECAM_22 (SCM_REG_BASE+0x22) 1388 #define BK_SECAM_23 (SCM_REG_BASE+0x23) 1389 #define BK_SECAM_24 (SCM_REG_BASE+0x24) 1390 #define BK_SECAM_25 (SCM_REG_BASE+0x25) 1391 #define BK_SECAM_26 (SCM_REG_BASE+0x26) 1392 #define BK_SECAM_27 (SCM_REG_BASE+0x27) 1393 #define BK_SECAM_28 (SCM_REG_BASE+0x28) 1394 #define BK_SECAM_29 (SCM_REG_BASE+0x29) 1395 #define BK_SECAM_2A (SCM_REG_BASE+0x2A) 1396 #define BK_SECAM_2B (SCM_REG_BASE+0x2B) 1397 #define BK_SECAM_2C (SCM_REG_BASE+0x2C) 1398 #define BK_SECAM_2D (SCM_REG_BASE+0x2D) 1399 #define BK_SECAM_2E (SCM_REG_BASE+0x2E) 1400 #define BK_SECAM_2F (SCM_REG_BASE+0x2F) 1401 #define BK_SECAM_30 (SCM_REG_BASE+0x30) 1402 #define BK_SECAM_31 (SCM_REG_BASE+0x31) 1403 #define BK_SECAM_32 (SCM_REG_BASE+0x32) 1404 #define BK_SECAM_33 (SCM_REG_BASE+0x33) 1405 #define BK_SECAM_34 (SCM_REG_BASE+0x34) 1406 #define BK_SECAM_35 (SCM_REG_BASE+0x35) 1407 #define BK_SECAM_36 (SCM_REG_BASE+0x36) 1408 #define BK_SECAM_37 (SCM_REG_BASE+0x37) 1409 #define BK_SECAM_38 (SCM_REG_BASE+0x38) 1410 #define BK_SECAM_39 (SCM_REG_BASE+0x39) 1411 #define BK_SECAM_3A (SCM_REG_BASE+0x3A) 1412 #define BK_SECAM_3B (SCM_REG_BASE+0x3B) 1413 #define BK_SECAM_3C (SCM_REG_BASE+0x3C) 1414 #define BK_SECAM_3D (SCM_REG_BASE+0x3D) 1415 #define BK_SECAM_3E (SCM_REG_BASE+0x3E) 1416 #define BK_SECAM_3F (SCM_REG_BASE+0x3F) 1417 1418 //////////////////////////////////////////////////////////////////////////////// 1419 // VBI register 1420 //////////////////////////////////////////////////////////////////////////////// 1421 #define BK_VBI_2A (VBI_REG_BASE+0x2A) 1422 #define BK_VBI_41 (VBI_REG_BASE+0x41) 1423 #define BK_VBI_45 (VBI_REG_BASE+0x45) 1424 #define BK_VBI_46 (VBI_REG_BASE+0x46) 1425 #define BK_VBI_4A (VBI_REG_BASE+0x4A) 1426 #define BK_VBI_4F (VBI_REG_BASE+0x4F) 1427 #define BK_VBI_50 (VBI_REG_BASE+0x50) 1428 #define BK_VBI_51 (VBI_REG_BASE+0x51) 1429 #define BK_VBI_55 (VBI_REG_BASE+0x55) 1430 #define BK_VBI_56 (VBI_REG_BASE+0x56) 1431 #define BK_VBI_57 (VBI_REG_BASE+0x57) 1432 #define BK_VBI_58 (VBI_REG_BASE+0x58) 1433 #define BK_VBI_59 (VBI_REG_BASE+0x59) 1434 #define BK_VBI_5A (VBI_REG_BASE+0x5A) 1435 #define BK_VBI_5B (VBI_REG_BASE+0x5B) 1436 #define BK_VBI_5C (VBI_REG_BASE+0x5C) 1437 #define BK_VBI_5D (VBI_REG_BASE+0x5D) 1438 #define BK_VBI_5E (VBI_REG_BASE+0x5E) 1439 #define BK_VBI_5F (VBI_REG_BASE+0x5F) 1440 #define BK_VBI_70 (VBI_REG_BASE+0x70) 1441 #define BK_VBI_71 (VBI_REG_BASE+0x71) 1442 #define BK_VBI_72 (VBI_REG_BASE+0x72) 1443 #define BK_VBI_77 (VBI_REG_BASE+0x77) 1444 #define BK_VBI_7C (VBI_REG_BASE+0x7C) 1445 #define BK_VBI_7D (VBI_REG_BASE+0x7D) 1446 #define BK_VBI_7E (VBI_REG_BASE+0x7E) 1447 #define BK_VBI_7F (VBI_REG_BASE+0x7F) 1448 #define BK_VBI_81 (VBI_REG_BASE+0x81) 1449 #define BK_VBI_82 (VBI_REG_BASE+0x82) 1450 #define BK_VBI_83 (VBI_REG_BASE+0x83) 1451 #define BK_VBI_86 (VBI_REG_BASE+0x86) 1452 #define BK_VBI_89 (VBI_REG_BASE+0x89) 1453 #define BK_VBI_8A (VBI_REG_BASE+0x8A) 1454 #define BK_VBI_8B (VBI_REG_BASE+0x8B) 1455 #define BK_VBI_8D (VBI_REG_BASE+0x8D) 1456 #define BK_VBI_91 (VBI_REG_BASE+0x91) 1457 #define BK_VBI_92 (VBI_REG_BASE+0x92) 1458 #define BK_VBI_99 (VBI_REG_BASE+0x99) 1459 #define BK_VBI_9A (VBI_REG_BASE+0x9A) 1460 #define BK_VBI_AD (VBI_REG_BASE+0xAD) 1461 #define BK_VBI_AE (VBI_REG_BASE+0xAE) 1462 #define BK_VBI_AF (VBI_REG_BASE+0xAF) 1463 #define BK_VBI_B7 (VBI_REG_BASE+0xB7) 1464 #define BK_VBI_B8 (VBI_REG_BASE+0xB8) 1465 #define BK_VBI_BB (VBI_REG_BASE+0xBB) 1466 #define BK_VBI_C4 (VBI_REG_BASE+0xC4) 1467 #define BK_VBI_CA (VBI_REG_BASE+0xCA) 1468 #define BK_VBI_CB (VBI_REG_BASE+0xCB) 1469 #define BK_VBI_CC (VBI_REG_BASE+0xCC) 1470 #define BK_VBI_CD (VBI_REG_BASE+0xCD) 1471 #define BK_VBI_CE (VBI_REG_BASE+0xCE) 1472 1473 #endif // ANALOG_REG_H 1474