1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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77 //<MStar Software>
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #include <string.h>
97 #include "MsTypes.h"
98 #include "halGOP.h"
99 #include "regGOP.h"
100 #include "halCHIP.h"
101 #include "drvSYS.h"
102
103
104 //------------------------------------------------------------------------------
105 // Driver Compiler Options
106 //------------------------------------------------------------------------------
107 #define HAL_GOP_DEBUGINFO(x) //x
108
109 //------------------------------------------------------------------------------
110 // Local Defines
111 //------------------------------------------------------------------------------
112 #define RIU ((unsigned short volatile *) pGOPHalLocal->u32_mmio_base)
113 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
114 #define GOP_READ2BYTE(addr) RIU[addr]
115 #define GOP_BANK_MASK 0x0F
116
117
118 //------------------------------------------------------------------------------
119 // Local Var
120 //------------------------------------------------------------------------------
121 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
122 {
123 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
124 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
125 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
126 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 2 */
127 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 3 */
128
129 };
130
131
132 GOP_CHIP_PROPERTY g_GopChipPro =
133 {
134 .bSetHSyncInverse = FALSE,
135 .bGop1GPalette = FALSE,
136 .bSetHPipeOfst = FALSE,
137 .bNeedCheckMVOP = FALSE,
138 .bNeedSetMUX1ToIP0 = FALSE,
139 .bNeedSetMUX3ToIP0 = FALSE,
140 .bNewMux = TRUE,
141 .bNewPalette = FALSE,
142 .bNewBwReg = TRUE,
143 .bGop2VStretch = TRUE,
144 .bIgnoreIPHPD = FALSE, //Uranus4 has handshack with XC, should not set HPD
145 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
146 .bhastilemode = FALSE,
147 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
148 .bAutoAdjustMirrorHSize = FALSE, //whether hw will auto adjust start addr when H mirror is enable
149 .bGOPWithVscale = {TRUE, TRUE, TRUE, TRUE}, //setting GOP with/without Vscale
150 .DwinVer = 0x1,
151 .bTstPatternAlpha = FALSE,
152 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
153 .bFRCSupport = FALSE, /*OC path*/
154 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
155 .bBnkForceWrite = FALSE, /*Direct Bank Force Write*/
156 .bPixelModeSupport = FALSE, /*Pixel Mode Support*/
157 .bScalingDownSupport= FALSE,
158 .b2Pto1PSupport= FALSE,
159 .bTLBSupport= {TRUE, FALSE, TRUE, FALSE, FALSE, FALSE},
160 .GOP_TestPattern_Vaild= E_GOP2,
161
162 #ifdef ENABLE_GOP_T3DPATCH
163 .GOP_PD = GOP_PD_T3D,
164 #else
165 .GOP_PD = 0x114,
166 #endif
167 .GOP_IP_PD = (-0x3),
168 .GOP_MVOP_PD = 0x6E,
169 .GOP_VE_PD = 0x89,
170 .GOP_MIXER_PD = 0x0,
171 .GOP_NonVS_PD_Offset = 0x0, //GOP without Vsacle might need add offset on pipedelay
172 .GOP_VE_V_Offset = 0x0,
173 .GOP_UHD_PD_Offset = 0x0,
174
175 .GOP_MUX_Delta = 0x1,
176 .GOP_Mux_Offset = {0x0, 0x9, 0xC, 0xF},
177 .GOP_Mux_FRC_offset= 0x0,
178 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3},
179 .WordUnit = GOP_WordUnit,
180 .TotalGwinNum = GOP_TotalGwinNum,
181 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
182 .enGOP3DType = E_DRV_3D_DUP_HALF,
183 };
184
185
186 //------------------------------------------------------------------------------
187 // Global Functions
188 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)189 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
190 {
191 GOP_TYPE->GOP0 = E_GOP0;
192 GOP_TYPE->GOP1 = E_GOP1;
193 GOP_TYPE->GOP2 = E_GOP2;
194 GOP_TYPE->GOP3 = E_GOP3;
195 GOP_TYPE->GOP4 = E_GOP4;
196 GOP_TYPE->GOP5 = E_GOP5;
197 GOP_TYPE->DWIN = E_GOP_Dwin;
198 GOP_TYPE->MIXER = E_GOP_MIXER;
199 }
200
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)201 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
202 {
203 MS_U32 u32BankOffSet = 0;
204
205 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
206
207 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
208 {
209 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
210 }
211 else
212 {
213 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
214 }
215
216 return GOP_SUCCESS;
217 }
218
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)219 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
220 {
221 MS_U32 u32BankOffSet =0;
222 MS_U32 u32BitMask=0,Regval=0;
223
224 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
225
226 switch(pinpon_mode)
227 {
228 case E_DRV_GOP_PINPON_G3D:
229 Regval = bEn << 5;
230 u32BitMask = GOP_BIT5;
231 break;
232 case E_DRV_GOP_PINPON_DWIN:
233 Regval = bEn << 6;
234 u32BitMask = GOP_BIT6;
235 break;
236 case E_DRV_GOP_PINPON_DIP:
237 Regval = bEn << 7;
238 u32BitMask = GOP_BIT7;
239 break;
240 default:
241 break;
242 }
243
244 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
245 return GOP_SUCCESS;
246 }
247
248
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)249 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
250 {
251 if (gop==0)
252 *pBnkOfst = GOP_4G_OFST<<16;
253 else if (gop==1)
254 *pBnkOfst = GOP_2G_OFST<<16;
255 else if (gop==2)
256 *pBnkOfst = GOP_1G_OFST<<16;
257 else if (gop==3)
258 *pBnkOfst = GOP_1GX_OFST<<16;
259 else if (gop==4)
260 *pBnkOfst = GOP_DW_OFST<<16;
261 else
262 return FALSE;
263
264 return TRUE;
265 }
266
HAL_GOP_GWIN_IsNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP)267 MS_BOOL HAL_GOP_GWIN_IsNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP)
268 {
269 return FALSE;
270 }
271
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)272 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
273 {
274 MS_U16 u16Mask = 0;
275
276 if (u16GopMask&GOP_BIT0)
277 {
278 u16Mask |= GOP_BIT12;
279 }
280 if (u16GopMask&GOP_BIT1)
281 {
282 u16Mask |= GOP_BIT13;
283 }
284 if (u16GopMask&GOP_BIT2)
285 {
286 u16Mask |= GOP_BIT15;
287 }
288 if (u16Mask != 0)
289 {
290 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask);
291 }
292
293 return GOP_SUCCESS;
294 }
295
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)296 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
297 {
298 switch(gop)
299 {
300 case E_GOP0:
301 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
302 break;
303 case E_GOP1:
304 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
305 break;
306 case E_GOP2:
307 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
308 break;
309 default:
310 break;
311 }
312 return GOP_SUCCESS;
313 }
314
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)315 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
316 {
317 MS_U16 u16GopAck = 0,reg_val =0;
318 switch(gop)
319 {
320 case E_GOP0:
321 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
322 if(reg_val&0x1000)
323 u16GopAck = FALSE;
324 else
325 u16GopAck = TRUE;
326 break;
327 case E_GOP1:
328 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
329 if(reg_val&0x2000)
330 u16GopAck = FALSE;
331 else
332 u16GopAck = TRUE;
333 break;
334 case E_GOP2:
335 case E_GOP3:
336 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
337 if(reg_val&0x8000)
338 u16GopAck = FALSE;
339 else
340 u16GopAck = TRUE;
341 break;
342 case E_GOP_Dwin:
343 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
344 if(reg_val&0x4000)
345 u16GopAck = FALSE;
346 else
347 u16GopAck = TRUE;
348 break;
349 default:
350 break;
351 }
352 return u16GopAck;
353 }
354
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)355 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
356 {
357 return GOP_FUN_NOT_SUPPORTED;
358 }
359
360 MS_BOOL bAddOffset = FALSE;
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)361 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
362 {
363 MS_U32 u32bankoff = 0;
364 MS_U16 chipid=0;
365 const SYS_Info *sys_info = NULL;
366
367 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
368 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15 ); //use new BW mode, enable couple LB
369 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, GOP_FIFO_BURST_ALL, GOP_FIFO_BURST_MASK ); //set GOP DMA Burst length to "32"
370 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, GOP_FIFO_THRESHOLD, GOP_REG_LW_MASK ); //set DMA FIFO threshold to 3/4 FIFO length
371 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, 0x200); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
372 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_DUMMY_22, 0x0, 0x200); //0: Vsync will use the same pipe delay as Hsync
373
374 // set VIP/VOP timing select, always select VOP should be OK.
375 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MULTI_ALPHA, GOP_BIT10, GOP_BIT10);
376
377 chipid=MDrv_SYS_GetChipID();
378 sys_info=MDrv_SYS_GetInfo();
379 if( ( bAddOffset == FALSE ) && ( chipid == CHIPID_MUSTANG_SERIES )){
380 pGOPHalLocal->pGopChipPro->GOP_PD += MUSTANG_PD_OFFSET;
381 bAddOffset = TRUE;
382 }
383 }
384
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)385 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
386 {
387 *pGOPHalLocal->pGopChipPro = g_GopChipPro;
388 }
389
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)390 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
391 {
392 if (u8GopNum==0)
393 {
394 return (MS_U8)MAX_GOP0_GWIN;
395 }
396 else if (u8GopNum==1)
397 {
398 return (MS_U8)MAX_GOP1_GWIN;
399 }
400 else if (u8GopNum==2)
401 {
402 return (MS_U8)MAX_GOP2_GWIN;
403 }
404 else if (u8GopNum==3)
405 {
406 return (MS_U8)MAX_GOP3_GWIN;
407 }
408 else
409 {
410 MS_ASSERT(0);
411 return 0xFF;
412 }
413 }
414
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)415 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
416 {
417 MS_U8 u8GWinId = 0;
418
419 //Adjust GWIN ID by different Chip
420
421 switch(u8Gop)
422 {
423 case E_GOP0:
424 u8GWinId = GOP0_GwinIdBase + u8Idx;
425 break;
426 case E_GOP1:
427 u8GWinId = GOP1_GwinIdBase + u8Idx;
428 break;
429 case E_GOP2:
430 u8GWinId = GOP2_GwinIdBase + u8Idx;
431 break;
432 case E_GOP3:
433 u8GWinId = GOP3_GwinIdBase + u8Idx;
434 break;
435 default:
436 break;
437 }
438 return u8GWinId;
439
440 }
441
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)442 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
443 {
444 switch(u8GOPNum)
445 {
446 case 0: // GOP4G
447 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
448 return GOP_SUCCESS;
449 case 1: // GOP2G
450 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
451 return GOP_SUCCESS;
452 case 2: // GOP1G
453 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
454 return GOP_SUCCESS;
455 case 3: // GOP1GX
456 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
457 return GOP_SUCCESS;
458 case 4: // GOPDWX
459 pGOPHalLocal->bank_offset = GOP_DW_OFST<<16;
460 return GOP_SUCCESS;
461 default:
462 MS_ASSERT(0);
463 return GOP_FAIL;
464 }
465 }
466
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)467 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
468 {
469 MS_U16 u16Bank;
470 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
471 u16Bank &= ~GOP_BANK_MASK;
472 u16Bank |= (u8bank&GOP_BANK_MASK);
473 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
474 }
475
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)476 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
477 {
478 MS_U16 u16GetBank;
479 u16GetBank = GOP_READ2BYTE(GOP_BAK_SEL);
480 return (u16GetBank&GOP_BANK_MASK);
481 }
482
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)483 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
484 {
485 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
486 MS_U32 bank;
487 MS_U32 direct_addr;
488
489 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
490
491 //* Gop driver should access another HW IP register
492 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
493 switch (u32addr & 0xFF00)
494 {
495 case GOP_REG_BASE:
496 {
497 bank = (u32addr & 0xF0000) >> 8;
498 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
499 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
500 break;
501 }
502 case SC1_REG_BASE:
503 {
504 if(g_GopChipPro.bXCDirrectBankSupport)
505 {
506 u16xcSubbank = (u32addr & 0xFF0000)>>8;
507 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
508 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
509 }
510 else
511 {
512 u16xcSubbank = (u32addr & 0xFF0000)>>16;
513 u16BankAddr = GOP_SC_BANKSEL+0;
514 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
515
516 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
517 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
518 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
519 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
520 }
521 break;
522 }
523 case GE_REG_BASE:
524 case CKG_REG_BASE:
525 case MIU_REG_BASE:
526 case MVOP_REG_BASE:
527 {
528 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
529 break;
530 }
531 default:
532 {
533 //Gop lib current do not support this HW ip base
534 MS_ASSERT(0);
535 *pu16ret =0;
536 break;
537 }
538 }
539 }
540
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)541 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
542 {
543 MS_U16 u16tmp=0;
544 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
545 MS_U32 bank;
546 MS_U32 direct_addr;
547
548 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u16addr, u16val));
549
550 if(mask!=0xffff)
551 {
552 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
553 u16tmp &= ~mask;
554 u16val &= mask;
555 u16val |= u16tmp;
556 }
557
558 //* Gop driver should access another HW IP register
559 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
560 switch (u32addr & 0xFF00)
561 {
562 case GOP_REG_BASE:
563 {
564 bank = (u32addr & 0xF0000) >> 8;
565 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
566 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
567 break;
568 }
569 case SC1_REG_BASE:
570 if(g_GopChipPro.bXCDirrectBankSupport)
571 { /*Derrick Bank*/
572 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
573 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
574 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
575 }
576 else
577 { /*Sub Bank*/
578 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
579 u16BankAddr = GOP_SC_BANKSEL+0;
580 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
581
582 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
583 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
584 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
585 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
586 }
587 break;
588 case GE_REG_BASE:
589 case CKG_REG_BASE:
590 case MIU_REG_BASE:
591 {
592 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
593 break;
594 }
595
596 default:
597 {
598 //Gop lib current do not support this HW ip base
599 MS_ASSERT(0);
600 break;
601 }
602
603 }
604 }
605
606
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)607 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
608 {
609 MS_U32 bank;
610 MS_U32 direct_addr;
611
612 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
613
614 //* Gop driver should access another HW IP register
615 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
616 switch (u32addr & 0xFF00)
617 {
618 case GOP_REG_BASE:
619 {
620 bank = (u32addr & 0xF0000) >> 8;
621 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
622 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
623 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
624 break;
625 }
626
627 case GE_REG_BASE:
628 case SC1_REG_BASE:
629 case CKG_REG_BASE:
630 {
631 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
632 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
633 break;
634 }
635
636 default:
637 {
638 //Gop lib current do not support this HW ip base
639 MS_ASSERT(0);
640 break;
641 }
642
643 }
644 }
645
646 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
647
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)648 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
649 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
650 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
651 {
652 MS_U8 i=0;
653 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",
654 u8Index, u8A, u8R, u8G, u8B));
655 /* Don't care high byte */
656 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
657
658 for(i =(GOP_WordUnit-1);i>4;i--)
659 {
660 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
661 }
662 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
663 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
664 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
665 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
666 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
667 *pREGMAP_Offset += GOP_WordUnit;
668
669 MsOS_FlushMemory(); //make sure cpu write data to dram
670
671 }
672
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)673 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
674 {
675 MS_U16 bpp=0;
676
677 switch ( fbFmt )
678 {
679 case E_DRV_GOP_COLOR_RGB555_BLINK :
680 case E_DRV_GOP_COLOR_RGB565 :
681 case E_DRV_GOP_COLOR_ARGB1555:
682 case E_DRV_GOP_COLOR_RGBA5551:
683 case E_DRV_GOP_COLOR_ARGB4444 :
684 case E_DRV_GOP_COLOR_RGBA4444 :
685 case E_DRV_GOP_COLOR_RGB555YUV422:
686 case E_DRV_GOP_COLOR_YUV422:
687 case E_DRV_GOP_COLOR_2266:
688 bpp = 16;
689 break;
690 case E_DRV_GOP_COLOR_ARGB8888 :
691 case E_DRV_GOP_COLOR_ABGR8888 :
692 bpp = 32;
693 break;
694
695 case E_DRV_GOP_COLOR_I8 :
696 bpp = 8;
697 break;
698
699 default :
700 //print err
701 MS_ASSERT(0);
702 bpp = 0xFFFF;
703 break;
704 }
705 return bpp;
706
707 }
708
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)709 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
710 {
711 MS_U16 regval;
712 /*For compatibility
713 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
714 MS_U8 u8coef_cpt = u8coef;
715
716 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
717 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
718 {
719 switch(u8coef)
720 {
721 case 0x0 :
722 u8coef_cpt = u8coef<<2;
723 break;
724 case 0x3f :
725 u8coef_cpt = ((u8coef<<2)|0x3);
726 break;
727 default:
728 u8coef_cpt = ((u8coef<<2)|0x1);
729 break;
730 }
731 }
732
733 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
734 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
735 {
736 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef_cpt&0xFC)<<6);
737 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x7f00);
738 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), (u8coef_cpt&0x03), 0x03);
739 }
740 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
741 else
742 {
743 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
744 {
745 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef_cpt&0xFC)<<6);
746 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x7f00);
747 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, (u8coef&0x03), 0x03);
748 }
749 else
750 {
751 printf("[%s]ERROR Invalid GwinID %d\n",__FUNCTION__,u8win);
752 }
753 }
754 }
755
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 addr)756 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 addr)
757 {
758 pGOPHalLocal->u32_mmio_base = addr;
759 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 addr)760 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 addr)
761 {
762 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 addr)763 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 addr)
764 {
765 }
766
767
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)768 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
769 {
770 /* GOP dst type:
771 0: IP (Main)
772 1: IP (Sub)
773 2: OP
774 3: MVOP
775 */
776 MS_U16 u16RegVal;
777
778 switch (eDstType)
779 {
780 case E_DRV_GOP_DST_IP0:
781 u16RegVal = 0x0;
782 break;
783
784 case E_DRV_GOP_DST_IP0_SUB:
785 u16RegVal = 0x1;
786 break;
787
788 case E_DRV_GOP_DST_OP0:
789 u16RegVal = 0x2;
790 break;
791
792 case E_DRV_GOP_DST_VOP:
793 u16RegVal = 0x3;
794 break;
795
796 default:
797 return GOP_FUN_NOT_SUPPORTED;
798 }
799
800 if(bOnlyCheck == FALSE)
801 {
802 if (GopNum==0)
803 {
804 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_CTRL1, u16RegVal, 0x0007);
805 return GOP_SUCCESS;
806 }
807 else if (GopNum==1)
808 {
809 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_CTRL1, u16RegVal, 0x0007);
810 return GOP_SUCCESS;
811 }
812 else if (GopNum==2)
813 {
814 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_CTRL1, u16RegVal, 0x0007);
815 return GOP_SUCCESS;
816 }
817 else if (GopNum==3)
818 {
819 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_CTRL1, u16RegVal, 0x0007);
820 return GOP_SUCCESS;
821 }
822 else
823 {
824 return GOP_INVALID_PARAMETERS;
825 }
826 }
827 return GOP_SUCCESS;
828 }
829
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)830 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
831 {
832 return GOP_FUN_NOT_SUPPORTED;
833 }
834
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)835 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
836 {
837 return GOP_FUN_NOT_SUPPORTED;
838 }
839
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)840 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
841 {
842 /*
843 OP path: support 4 mux (mux0/1/2/3) to blend with SC simultaneously
844 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
845 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
846 */
847 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3;
848 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gx<<(GOP_MUX_SHIFT*3))|(gop1g<<(GOP_MUX_SHIFT*2))|(gop2g<<(GOP_MUX_SHIFT*1))|gop4g), GOP_REG_WORD_MASK);
849 return GOP_SUCCESS;
850 }
851
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)852 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
853 {
854 MS_U16 u16GopMux=0;
855 if(eGopMux <4)
856 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
857 else
858 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
859
860 *u8GOPNum = (u16GopMux >> ((eGopMux%4)*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
861 }
862
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)863 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
864 {
865 switch(eGopMux)
866 {
867 case E_GOP_MUX0:
868 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
869 break;
870 case E_GOP_MUX1:
871 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
872 break;
873 case E_GOP_MUX2:
874 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
875 break;
876 case E_GOP_MUX3:
877 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
878 break;
879 case E_GOP_IP0_MUX:
880 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
881 break;
882 case E_GOP_IP1_MUX:
883 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_SUB_MUX_SHIFT, GOP_IP_SUB_MUX_MASK);
884 break;
885 case E_GOP_VOP0_MUX:
886 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
887 break;
888 case E_GOP_VOP1_MUX:
889 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
890 break;
891 default:
892 printf("[%s]ERROR mux setting\n",__FUNCTION__);
893 break;
894 }
895 }
896
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)897 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
898 {
899 /* GOP OP Path enable to SC Setting
900 : GOP OP Path blending with SC sequence
901 */
902 MS_U16 muxValue=0, regval=0;
903
904 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
905 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
906
907 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
908 {
909 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x8000):(regval & ~0x8000), 0x8000);
910 }
911 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux2
912 {
913 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x4000):(regval & ~0x4000), 0x4000);
914 }
915 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux3
916 {
917 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x2000):(regval & ~0x2000), 0x2000);
918 }
919 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux1
920 {
921 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x1000):(regval & ~0x1000), 0x1000);
922 }
923 else
924 {
925 return GOP_FAIL;
926 }
927 return GOP_SUCCESS;
928 }
929
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)930 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
931 {
932 return GOP_FUN_NOT_SUPPORTED;
933 }
934
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)935 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
936 {
937 /* GOP OP Path enable to SC Setting
938 A5: GOP OP Path blending with SC sequence
939 mux1-->mux0-->mux2-->mux3
940 */
941 MS_U16 muxValue=0, regval=0;
942
943 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
944 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
945 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
946 {
947 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
948 }
949 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
950 {
951 //printf("");
952 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
953 }
954 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
955 {
956 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
957 }
958 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
959 {
960 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
961 }
962 else
963 {
964 return GOP_FAIL;
965 }
966 return GOP_SUCCESS;
967 }
968
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)969 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
970 {
971 MS_U16 muxValue=0, regval=0;
972
973 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
974 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
975 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
976 {
977 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
978 }
979 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
980 {
981 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
982 }
983 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
984 {
985 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
986 }
987 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
988 {
989 *pbEnable = (regval & GOP_BIT12) == GOP_BIT12;
990 }
991 else
992 {
993 return GOP_FAIL;
994 }
995 return GOP_SUCCESS;
996 }
997
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)998 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
999 {
1000 MS_U16 MuxGop, muxValue=0, i;
1001 MS_U16 MuxShift;
1002
1003 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX1;
1004
1005 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1006 for (i=0; i<MAX_GOP_MUX;i++)
1007 {
1008 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1009 {
1010 MuxGop = (muxValue&GOP_MUX1_MASK)>> MuxShift; //save mux1 gop
1011
1012 muxValue &= ~GOP_MUX1_MASK; //clear mux1 setting
1013 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1014 muxValue |= ((gopNum<< MuxShift)|(MuxGop<<(i*GOP_MUX_SHIFT)));
1015 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1016 break;
1017 }
1018 }
1019
1020 return GOP_SUCCESS;
1021 }
1022
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1023 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1024 {
1025 /* GOP dst type:
1026 0: IP (Main)
1027 1: IP (Sub)
1028 2: OP
1029 3: MVOP
1030 */
1031
1032 switch(eDstType)
1033 {
1034 case E_DRV_GOP_DST_IP0:
1035
1036 if (gopNum==1)
1037 {
1038 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1039 }
1040 else if (gopNum ==2)
1041 {
1042 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1043 }
1044 else if (gopNum ==3)
1045 {
1046 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG2_MASK);
1047 }
1048 else if (gopNum==0)
1049 {
1050 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1051 }
1052 else
1053 {
1054 MS_ASSERT(0);
1055 return GOP_INVALID_PARAMETERS;
1056 }
1057 break;
1058
1059 case E_DRV_GOP_DST_IP0_SUB:
1060 if (gopNum==1)
1061 {
1062 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1063 }
1064 else if (gopNum==2)
1065 {
1066 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1067 }
1068 else if (gopNum==3)
1069 {
1070 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG2_MASK);
1071 }
1072 else if (gopNum==0)
1073 {
1074 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1075 }
1076 else
1077 {
1078 MS_ASSERT(0);
1079 return GOP_INVALID_PARAMETERS;
1080 }
1081 break;
1082
1083
1084 case E_DRV_GOP_DST_OP0:
1085 if (gopNum==1)
1086 {
1087 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1088 }
1089 else if (gopNum==2)
1090 {
1091 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1092 }
1093 else if (gopNum==3)
1094 {
1095 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG2_MASK);
1096 }
1097 else if (gopNum==0)
1098 {
1099 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1100 }
1101 else
1102 {
1103 MS_ASSERT(0);
1104 return GOP_INVALID_PARAMETERS;
1105 }
1106
1107 break;
1108
1109 case E_DRV_GOP_DST_VOP:
1110 if (gopNum==1)
1111 {
1112 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1113 }
1114 else if (gopNum ==2)
1115 {
1116 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1117 }
1118 else if (gopNum ==3)
1119 {
1120 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_IDCLK2, CKG_GOPG2_MASK);
1121 }
1122 else if (gopNum==0)
1123 {
1124 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1125 }
1126 else
1127 {
1128 MS_ASSERT(0);
1129 return GOP_INVALID_PARAMETERS;
1130 }
1131
1132 break;
1133 default:
1134 MS_ASSERT(0);
1135 return GOP_ENUM_NOT_SUPPORTED;
1136 }
1137 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1138 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1139
1140 return GOP_SUCCESS;
1141 }
1142
1143
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1144 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1145 {
1146 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1147 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1148 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1149 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1150 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1151 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1152 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1153 else
1154 return GOP_INVALID_PARAMETERS;
1155
1156 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1157 return GOP_SUCCESS;
1158 }
1159
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1160 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1161 {
1162 if (bEnable)
1163 {
1164 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1165 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1166 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1167 }
1168 else
1169 {
1170 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1171 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1172 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1173 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1174 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1175 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1176 }
1177
1178 return GOP_SUCCESS;
1179 }
1180
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1181 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1182 {
1183 return GOP_FUN_NOT_SUPPORTED;
1184 }
1185
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)1186 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
1187 {
1188 return GOP_FUN_NOT_SUPPORTED;
1189 }
1190
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)1191 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
1192 {
1193 return GOP_FUN_NOT_SUPPORTED;
1194 }
1195
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)1196 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
1197 {
1198 MS_U32 u32GopIdx;
1199
1200 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
1201 pGOPHalLocal->pHALShared = pHALShared;
1202
1203 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
1204 {
1205 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
1206 }
1207 pGOPHalLocal->pGopChipPro = &pHALShared->gopChipProperty;
1208 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
1209 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1210 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1211 {
1212 }
1213
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_U32 * u32Adr)1214 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_U32* u32Adr)
1215 {
1216 MS_U16 u16RegVal=0;
1217
1218 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
1219 if (gwinid<MAX_GOP0_GWIN) //gop0
1220 {
1221 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP0))==BIT(GOP_MIU_CLIENT_GOP0)) //MIU1
1222 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1223 }
1224 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
1225 {
1226 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP1))==BIT(GOP_MIU_CLIENT_GOP1)) //MIU1
1227 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1228 }
1229 else if (gwinid==(MAX_GOP0_GWIN+MAX_GOP1_GWIN)) //gop2
1230 {
1231 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP2))==BIT(GOP_MIU_CLIENT_GOP2)) //MIU1
1232 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1233 }
1234 else if (gwinid==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)) //gop3
1235 {
1236 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP3))==BIT(GOP_MIU_CLIENT_GOP3)) //MIU1
1237 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1238 }
1239 else
1240 {
1241 return GOP_FAIL;
1242 }
1243 return GOP_SUCCESS;
1244 }
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)1245 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
1246 {
1247 MS_U16 u16RegVal=0;
1248
1249 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
1250
1251 switch (gopnum)
1252 {
1253 case 0:
1254 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP0))==BIT(GOP_MIU_CLIENT_GOP0)? MIU_1:MIU_0);
1255 break;
1256
1257 case 1:
1258 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP1))==BIT(GOP_MIU_CLIENT_GOP1)? MIU_1:MIU_0);
1259 break;
1260
1261 case 2:
1262 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP2))==BIT(GOP_MIU_CLIENT_GOP2)? MIU_1:MIU_0);
1263 break;
1264
1265 case 3:
1266 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP3))==BIT(GOP_MIU_CLIENT_GOP3)? MIU_1:MIU_0);
1267 break;
1268 default:
1269 return 0xff;
1270 break;
1271 }
1272 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)1273 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
1274 {
1275 MS_U16 u16Regval=0;
1276 MS_U32 u32pBankOffSet=0;
1277 GOP_Result ret;
1278
1279 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
1280 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
1281
1282 switch (u16Regval&0x3)
1283 {
1284 case 0:
1285 *pGopDst = E_DRV_GOP_DST_IP0;
1286 ret = GOP_SUCCESS;
1287 break;
1288 case 1:
1289 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
1290 ret = GOP_SUCCESS;
1291 break;
1292 case 2:
1293 *pGopDst = E_DRV_GOP_DST_OP0;
1294 ret = GOP_SUCCESS;
1295 break;
1296 case 3:
1297 *pGopDst = E_DRV_GOP_DST_VOP;
1298 ret = GOP_SUCCESS;
1299 break;
1300 default:
1301 *pGopDst = E_DRV_GOP_DST_INVALID;
1302 ret = GOP_FAIL;
1303 break;
1304 }
1305
1306 return ret;
1307
1308 }
1309
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)1310 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
1311 {
1312 MS_U16 muxValue=0;
1313 MS_U16 u16RegVal= 0, u16RegMsk = 0;
1314
1315 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
1316
1317 /*
1318 mustang IP blending
1319 [15:8] IP Main blending
1320 [7:0] IP Sub blending
1321 ===========================================
1322 [10:8]/[2:0] No use
1323 [11]/[3] 0: Enable IP blending
1324 1: Disable IP blending
1325 [13:12]/[5:4] 2'b01 : Select GOP ips mux as source
1326 2'b10 : Select GOP ipm mux as source
1327 [15:14]/[7:6] 2'b00, 2'b01 : Select SUB timing for GOP
1328 2'b10, 2'b11 : Select Main timing for GOP
1329 */
1330 switch(ipSelGop)
1331 {
1332 case MS_DRV_IP0_SEL_GOP0:
1333 u16RegVal = GOP_BIT15 ;
1334 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
1335 u16RegVal |= IPMUX0_BLENDING_ENABLE;//mux0
1336 else
1337 u16RegVal |= IPMUX1_BLENDING_ENABLE;//mux1
1338 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
1339 u16RegMsk = GOP_REG_WORD_MASK;
1340 break;
1341 case MS_DRV_IP0_SEL_GOP1:
1342 u16RegVal = GOP_BIT15 ;
1343 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
1344 u16RegVal |= IPMUX0_BLENDING_ENABLE;//mux0
1345 else
1346 u16RegVal |= IPMUX1_BLENDING_ENABLE;//mux1
1347 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
1348 u16RegMsk = GOP_REG_WORD_MASK;
1349 break;
1350 case MS_DRV_IP0_SEL_GOP2:
1351 u16RegVal = GOP_BIT15 ;
1352 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
1353 u16RegVal |= IPMUX0_BLENDING_ENABLE;//mux0
1354 else
1355 u16RegVal |= IPMUX1_BLENDING_ENABLE;//mux1
1356 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
1357 u16RegMsk = GOP_REG_WORD_MASK;
1358 break;
1359 case MS_DRV_NIP_SEL_GOP0:
1360 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
1361 {
1362 u16RegVal = ~IPMUX0_BLENDING_ENABLE;//mux0
1363 u16RegMsk = IPMUX0_BLENDING_ENABLE;
1364 }
1365 else
1366 {
1367 u16RegVal = ~IPMUX1_BLENDING_ENABLE;//mux1
1368 u16RegMsk = IPMUX1_BLENDING_ENABLE;
1369 }
1370 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1371 break;
1372 case MS_DRV_NIP_SEL_GOP1:
1373 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
1374 {
1375 u16RegVal = ~IPMUX0_BLENDING_ENABLE;//mux0
1376 u16RegMsk = IPMUX0_BLENDING_ENABLE;
1377 }
1378 else
1379 {
1380 u16RegVal = ~IPMUX1_BLENDING_ENABLE;//mux1
1381 u16RegMsk = IPMUX1_BLENDING_ENABLE;
1382 }
1383 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1384 break;
1385 case MS_DRV_NIP_SEL_GOP2:
1386 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
1387 {
1388 u16RegVal = ~IPMUX0_BLENDING_ENABLE;//mux0
1389 u16RegMsk = IPMUX0_BLENDING_ENABLE;
1390 }
1391 else
1392 {
1393 u16RegVal = ~IPMUX1_BLENDING_ENABLE;//mux1
1394 u16RegMsk = IPMUX1_BLENDING_ENABLE;
1395 }
1396 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1397 break;
1398 case MS_DRV_MVOP_SEL:
1399 u16RegVal = GOP_BIT15 ;
1400 u16RegVal |= IPMUX0_BLENDING_ENABLE; //mux0
1401 u16RegVal |= GOP_BIT3; //Disable Sub IP blending
1402 u16RegMsk = GOP_REG_WORD_MASK;
1403 break;
1404 default:
1405 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
1406 break;
1407 }
1408 if(0 != u16RegMsk)
1409 {
1410 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
1411 }
1412 }
1413
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1414 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1415 {
1416 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1417 {
1418 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, 0, (GOP_BIT8|GOP_BIT9));
1419 }
1420 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1421 {
1422 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, (GOP_BIT8|GOP_BIT9), (GOP_BIT8|GOP_BIT9));
1423 }
1424 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1425 {
1426 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, (GOP_BIT8), (GOP_BIT8|GOP_BIT9));
1427 //enable scaler IP.
1428 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT12, GOP_BIT12|GOP_BIT13);
1429 // set GOPD to scaler ip OUT
1430 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, GOP_BIT15, GOP_BIT15);
1431 }
1432 else
1433 {
1434 return GOP_INVALID_PARAMETERS;
1435 }
1436
1437 return GOP_SUCCESS;
1438 }
1439
1440
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1441 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1442 {
1443 MS_U16 u16RegVal=0;
1444 MS_U16 mask_shift=0;
1445
1446
1447 if (GOP_MIU_CLIENT_DWIN >=0x10)
1448 {
1449 MS_CRITICAL_MSG(printf(" %s :DWIN is not support\n",__FUNCTION__));
1450 return GOP_FAIL;
1451 }
1452 else
1453 mask_shift = GOP_MIU_CLIENT_DWIN;
1454
1455 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
1456 return ((u16RegVal&(1<<mask_shift))? MIU_1:MIU_0);
1457
1458 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)1459 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
1460 {
1461 MS_U16 mask_shift=0;
1462
1463 if ( (miu>2) || (GOP_MIU_CLIENT_DWIN >= 0x10))
1464 {
1465 MS_CRITICAL_MSG(printf(" %s :DWIN is not support\n",__FUNCTION__));
1466 return GOP_FAIL;
1467 }
1468 else
1469 mask_shift = GOP_MIU_CLIENT_DWIN;
1470
1471 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miu<<mask_shift, 1<<mask_shift);
1472
1473 return GOP_SUCCESS;
1474
1475
1476 }
1477
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1478 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
1479 {
1480 if (bEnable)
1481 {
1482 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_ALPHA, GOP_BIT6, GOP_BIT6);
1483 }
1484 else
1485 {
1486 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_ALPHA, ~GOP_BIT6, GOP_BIT6);
1487 }
1488 return GOP_SUCCESS;
1489 }
1490
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)1491 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
1492 {
1493 return GOP_FUN_NOT_SUPPORTED;
1494 }
1495
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)1496 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
1497 {
1498 return GOP_FUN_NOT_SUPPORTED;
1499 }
1500
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)1501 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
1502 {
1503 return GOP_FUN_NOT_SUPPORTED;
1504 }
1505
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)1506 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
1507 {
1508 return GOP_FUN_NOT_SUPPORTED;
1509 }
1510
1511
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)1512 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
1513 {
1514 MS_U32 u32BankOffSet =0;
1515
1516 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
1517
1518 if (bEn)
1519 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
1520 else
1521 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
1522
1523 return GOP_SUCCESS;
1524 }
1525
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)1526 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
1527 {
1528 MS_U32 u32BankOffSet =0;
1529
1530 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
1531
1532 if (bEn)
1533 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
1534 else
1535 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
1536
1537 return GOP_SUCCESS;
1538 }
1539
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)1540 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
1541 {
1542 return GOP_FUN_NOT_SUPPORTED;
1543 }
1544
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_U32 u32SubAddr)1545 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_U32 u32SubAddr)
1546 {
1547 u32SubAddr /= GOP_WordUnit;
1548
1549 if(u8GOP == E_GOP2)
1550 {
1551 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1552 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1553 }
1554 else if(u8GOP == E_GOP1)
1555 {
1556 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1557 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1558 }
1559 else if(u8GOP == E_GOP0)
1560 {
1561 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1562 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1563 }
1564 else
1565 {
1566 return GOP_FUN_NOT_SUPPORTED;
1567 }
1568
1569 return GOP_SUCCESS;
1570
1571 }
1572
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)1573 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
1574 {
1575 return GOP_FUN_NOT_SUPPORTED;
1576 }
1577
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)1578 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
1579 {
1580 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1581 MS_U16 u16MVOPMirrorCfg = 0;
1582 MS_U16 u16ScalerMirrorCfg = 0;
1583
1584 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
1585 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
1586 if(bHorizontal) // Horizontal
1587 {
1588 if(u16MVOPMirrorCfg & GOP_BIT1)
1589 {
1590 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
1591 }
1592 else if(u16ScalerMirrorCfg & GOP_BIT12)
1593 {
1594 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1595 }
1596 }
1597 else //vertical
1598 {
1599 if(u16MVOPMirrorCfg & GOP_BIT0)
1600 {
1601 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
1602 }
1603 else if(u16ScalerMirrorCfg & GOP_BIT13)
1604 {
1605 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1606 }
1607 }
1608 return enMirrorType;
1609 }
1610
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)1611 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
1612 {
1613 return GOP_FUN_NOT_SUPPORTED;
1614 }
1615
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)1616 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
1617 {
1618 return GOP_FUN_NOT_SUPPORTED;
1619 }
1620
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)1621 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
1622 {
1623 return GOP_FUN_NOT_SUPPORTED;
1624 }
1625
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)1626 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
1627 {
1628 return GOP_FUN_NOT_SUPPORTED;
1629 }
1630
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)1631 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
1632 {
1633 return GOP_FUN_NOT_SUPPORTED;
1634 }
1635
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)1636 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
1637 {
1638 MS_U32 u32BankOffSet = 0;
1639 MS_BOOL bInverse = 0xFF;
1640 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1641
1642 switch (eDstType)
1643 {
1644 case E_DRV_GOP_DST_IP0:
1645 bInverse = TRUE;
1646 break;
1647 default:
1648 bInverse = FALSE;
1649 break;
1650 }
1651 if(bInverse == TRUE)
1652 {
1653 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 1<<4, 0x10);
1654 }
1655 else
1656 {
1657 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 0<<4, 0x10);
1658 }
1659 return GOP_SUCCESS;
1660 }
1661
1662 /********************************************************************************/
1663 ///Test Pattern
1664 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)1665 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
1666 {
1667 switch(u8GopNum)
1668 {
1669 case E_GOP0:
1670 return GOP_FUN_NOT_SUPPORTED;
1671 break;
1672 case E_GOP1:
1673 return GOP_SUCCESS;
1674 break;
1675 case E_GOP2:
1676 return GOP_FUN_NOT_SUPPORTED;
1677 break;
1678 case E_GOP3:
1679 return GOP_FUN_NOT_SUPPORTED;
1680 break;
1681 default:
1682 printf("[%s] ERROR GOP Num %d\n",__FUNCTION__,u8GopNum);
1683 return GOP_FAIL;
1684 }
1685 return GOP_FAIL;
1686
1687 }
1688
1689
1690 /********************************************************************************/
1691 ///GOP Scaling down (internal)
1692 /********************************************************************************/
1693
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)1694 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
1695 {
1696 return GOP_FUN_NOT_SUPPORTED;
1697 }
1698
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)1699 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
1700 {
1701 return GOP_FUN_NOT_SUPPORTED;
1702 }
1703
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)1704 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
1705 {
1706 MS_U32 u32BankOffSet=0;
1707
1708 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1709 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
1710 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
1711 return GOP_SUCCESS;
1712 }
1713
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)1714 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
1715 {
1716 return GOP_FUN_NOT_SUPPORTED;
1717 }
1718
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)1719 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
1720 {
1721 MS_U32 u32BankOffSet=0xFFFF;
1722
1723 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1724 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
1725
1726 return GOP_SUCCESS;
1727 }
1728
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U32 u32tlbaddr,MS_U32 u32size)1729 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U32 u32tlbaddr, MS_U32 u32size)
1730 {
1731 MS_U32 u32BankOffSet=0xFFFF;
1732 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1733
1734 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
1735 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
1736
1737 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u32tlbaddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
1738 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u32tlbaddr>>16, GOP_REG_WORD_MASK);
1739
1740 return GOP_SUCCESS;
1741 }
1742
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U32 u32tlbaddr)1743 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U32 u32tlbaddr)
1744 {
1745 MS_U32 u32BankOffSet=0xFFFF;
1746 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1747
1748 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u32tlbaddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
1749 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u32tlbaddr>>16, GOP_REG_WORD_MASK);
1750
1751 return GOP_SUCCESS;
1752 }
1753
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)1754 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
1755 {
1756 MS_U32 u32BankOffSet=0;
1757 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
1758
1759 if (u32GopIdx < MAX_GOP_SUPPORT)
1760 {
1761 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + (u16Addr<<1) +GOP_4G_CTRL0), u16Val);
1762 }
1763 else
1764 {
1765 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
1766 *u16Val = 0;
1767 }
1768 return GOP_SUCCESS;
1769 }
1770
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)1771 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
1772 {
1773 MS_U32 u32BankOffSet=0;
1774 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
1775
1776 if (u32GopIdx < MAX_GOP_SUPPORT)
1777 {
1778 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + (u16Addr<<1) +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
1779 }
1780 else
1781 {
1782 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
1783 }
1784 return GOP_SUCCESS;
1785 }
1786
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)1787 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
1788 {
1789 switch(u32PowerState)
1790 {
1791 case E_POWER_SUSPEND:
1792 {
1793 //CLK
1794 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
1795 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
1796 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
1797 if(g_GopChipPro.TotalGwinNum > 4)
1798 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
1799
1800
1801 //SRAM
1802 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
1803 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
1804 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
1805
1806 //XC
1807 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
1808 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
1809 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
1810 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
1811 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
1812 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
1813 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
1814 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
1815 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
1816 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
1817 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
1818 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[11]));
1819 }
1820 break;
1821 case E_POWER_RESUME:
1822 {
1823 //CLK
1824 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
1825 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
1826 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
1827 if(g_GopChipPro.TotalGwinNum > 4)
1828 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
1829
1830 //SRAM
1831 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
1832 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
1833 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
1834
1835 //XC
1836 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
1837 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
1838 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
1839 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
1840 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
1841 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
1842 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
1843 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
1844 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
1845 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
1846 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
1847 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[11], GOP_REG_WORD_MASK);
1848 }
1849 break;
1850 default:
1851 break;
1852 }
1853 return GOP_SUCCESS;
1854 }
1855
1856