1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 // Debug Log
120 #include "ULog.h"
121 MS_U32 u32GOPDbgLevel_hal;
122
123 // Debug Logs, level form low(INFO) to high(FATAL, always show)
124 // Function information, ex function entry
125 #define GOP_H_INFO(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_HIGH) {ULOGI("GOP HAL", x, ##args);}
126 // Warning, illegal paramter but can be self fixed in functions
127 #define GOP_H_WARN(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_HIGH) {ULOGW("GOP HAL", x, ##args);}
128 // Need debug, illegal paramter.
129 #define GOP_H_DBUG(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_MED) {ULOGD("GOP HAL", x, ##args);}
130 // Error, function will be terminated but system not crash
131 #define GOP_H_ERR(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_LOW) {ULOGE("GOP HAL", x, ##args);}
132 // Critical, system crash. (ex. assert)
133 #define GOP_H_FATAL(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_LOW){ULOGF("GOP HAL", x, ##args);}
134
135 #define GOP_ASSERT(_bool_){\
136 if ( ! ( _bool_ ) )\
137 {\
138 GOP_H_FATAL("\033[35m UTOPIA ASSERT: %s, %s %s %d\033[35m\n", #_bool_, __FILE__, __PRETTY_FUNCTION__, __LINE__);\
139 }\
140 }
141
142 //------------------------------------------------------------------------------
143 // Local Var
144 //------------------------------------------------------------------------------
145 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
146 {
147 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
148 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
149 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
150 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
151 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
152 };
153 #ifdef GOP_CMDQ_ENABLE
154 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
155 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
156
157 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
158 extern MS_BOOL bAFBCMIUSelect[MAX_GOP_SUPPORT];
159 #endif
160 GOP_CHIP_PROPERTY g_GopChipPro =
161 {
162 .bSetHSyncInverse = FALSE,
163 .bGop1GPalette = FALSE,
164 .bSetHPipeOfst = FALSE,
165 .bNeedCheckMVOP = FALSE,
166 .bNeedSetMUX1ToIP0 = FALSE,
167 .bNeedSetMUX3ToIP0 = FALSE,
168 .bNewMux = TRUE,
169 .bNewPalette = TRUE,
170 .bNewBwReg = TRUE,
171 .bGop2VStretch = TRUE,
172 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
173 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
174 .bhastilemode = TRUE,
175 .bInitNotEnableGOPToSC = TRUE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
176 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
177 .bGOPWithVscale = {TRUE, TRUE, TRUE, TRUE, FALSE}, //setting GOP with/without Vscale
178 .bGOPWithScaleDown = {TRUE, FALSE, TRUE, FALSE, FALSE},
179
180 .bDWINSupport = FALSE,
181 .DwinVer = 0x1,
182 .bTstPatternAlpha = TRUE,
183 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
184 .bFRCSupport = FALSE, /*OC path*/
185 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
186 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
187 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
188 .bScalingDownSupport= TRUE,
189 .b2Pto1PSupport= TRUE,
190 .bTLBSupport= {TRUE, TRUE, TRUE, TRUE, FALSE, FALSE},
191 .GOP_TestPattern_Vaild= E_GOP0,
192 .bInternalMIUSelect= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
193 .bAFBC_Support= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE}, // disable GOP before AFBC patch implement
194
195 #ifdef ENABLE_GOP_T3DPATCH
196 .GOP_PD = GOP_PD_T3D,
197 #else
198 .GOP_PD = 0x170,
199 #endif
200
201 .GOP_HDR_OP_PD = 0x0,
202 .GOP_IP_PD = 0x00,
203 .GOP_MVOP_PD = 0x69,
204 .GOP_VE_PD = 0x89,
205 .GOP_MIXER_PD = 0x0,
206 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
207 .GOP_NonVS_DualOpPD_Offset= 0x6,
208 .GOP_VE_V_Offset = 0x0,
209 .GOP_DUAL_OP_PD = 0x63,
210
211 .GOP_MUX_Delta = 0x1,
212 .GOP_Mux_Offset = {0x0, 0x42, 0x36, 0x3C, 0x48},
213 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX1, E_GOP_MUX4},
214 .GOP_MapLayer2DualOpMux = {E_GOP_DUALRATE_OP_MUX0, E_GOP_DUALRATE_OP_MUX1, E_GOP_DUALRATE_OP_MUX2},
215 .GOP_Mux_FRC_offset= 0x13,
216 .GOP_DualRateMux_Offset = {0x0, 0x6, 0xC},
217 .GOP_REF_POSITION_X = 0x418,
218
219 .WordUnit = GOP_WordUnit,
220 .TotalGwinNum = GOP_TotalGwinNum,
221 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
222 .enGOP3DType = E_DRV_3D_DUP_FULL,
223 .bOpInterlace = FALSE,
224 .bAFBCMIUSelDoubleBuffer = TRUE,
225 .bAFBC_Merge_GOP_Trig = TRUE,
226 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, FALSE, TRUE, FALSE},
227 .bGOPNeedSplitMode4DualRate = {FALSE, FALSE, FALSE, FALSE, TRUE},
228 .bGOPAutoClkGating = TRUE,
229 };
230
231 typedef struct
232 {
233 MS_U8 u8Gop;
234 MS_U8 mainGop;
235 MS_U8 subGop;
236 } GOP_4K120_COMBINE_PAIRS;
237
238 static const GOP_4K120_COMBINE_PAIRS gop_4k120_pairs[] =
239 {
240 {E_GOP0, E_GOP0, E_GOP3},
241 {E_GOP1, E_GOP2, E_GOP1},
242 {E_GOP2, E_GOP2, E_GOP1},
243 {E_GOP3, E_GOP0, E_GOP3},
244 {E_GOP4, E_GOP4, E_GOP4},
245 };
246
247 const MS_U8 GOP_4K120MUX_IDX_TABLE[GOP_4K120_MUX_COUNT] = {E_GOP0, E_GOP2, E_GOP4};
248
249 static const int GOP4_SPLITMODE_MAX_HSIZE = 256;
250 static const int GOP4_SPLITMODE_MAX_VSIZE = 512;
251
252 static MS_BOOL Hal_get4K120CombinedGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 * main_gop, MS_U8 * sub_gop);
253 static GOP_Result Hal_Ctrl4K120GopMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable);
254 static MS_U16 _findMuxNumberByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType dst_type, MS_U8 u8Gop);
255
256 //------------------------------------------------------------------------------
257 // Global Functions
258 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)259 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
260 {
261 GOP_TYPE->GOP0 = E_GOP0;
262 GOP_TYPE->GOP1 = E_GOP1;
263 GOP_TYPE->GOP2 = E_GOP2;
264 GOP_TYPE->GOP3 = E_GOP3;
265 GOP_TYPE->GOP4 = E_GOP4;
266 GOP_TYPE->GOP5 = E_GOP5;
267 GOP_TYPE->DWIN = E_GOP_Dwin;
268 GOP_TYPE->MIXER = E_GOP_MIXER;
269 }
270
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)271 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
272 {
273 MS_U32 u32BankOffSet = 0;
274
275 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
276
277 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
278 {
279 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
280 }
281 else
282 {
283 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
284 }
285
286 return GOP_SUCCESS;
287 }
288
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)289 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
290 {
291 MS_U32 u32BankOffSet =0;
292 MS_U32 u32BitMask,Regval;
293
294 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
295
296 switch(pinpon_mode)
297 {
298 default:
299 case E_DRV_GOP_PINPON_G3D:
300 Regval = bEn << 5;
301 u32BitMask = GOP_BIT5;
302 break;
303 case E_DRV_GOP_PINPON_DWIN:
304 Regval = bEn << 6;
305 u32BitMask = GOP_BIT6;
306 break;
307 case E_DRV_GOP_PINPON_DIP:
308 Regval = bEn << 7;
309 u32BitMask = GOP_BIT7;
310 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
311 break;
312 case E_DRV_GOP_PINPON_DWIN0:
313 Regval = bEn << 7;
314 u32BitMask = GOP_BIT7;
315 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
316 break;
317 case E_DRV_GOP_PINPON_DWIN1:
318 Regval = bEn << 7;
319 u32BitMask = GOP_BIT7;
320 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
321 break;
322 break;
323 }
324
325 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
326 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
327 MS_U32 u32CombineBankOffSet = 0x0;
328
329 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOPNum, &u8_mainGop, &u8_combinedGop) )
330 {
331 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
332 return GOP_FAIL;
333 }
334 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
335 {
336 _GetBnkOfstByGop(u8_combinedGop, &u32CombineBankOffSet);
337 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet+GOP_4G_CTRL1, 0x4100, GOP_REG_HW_MASK);
338 }
339
340 return GOP_SUCCESS;
341 }
342
343
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)344 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
345 {
346 if (gop==E_GOP0)
347 *pBnkOfst = GOP_4G_OFST<<16;
348 else if (gop==E_GOP1)
349 *pBnkOfst = GOP_2G_OFST<<16;
350 else if (gop==E_GOP2)
351 *pBnkOfst = GOP_1G_OFST<<16;
352 else if (gop==E_GOP3)
353 *pBnkOfst = GOP_1GX_OFST<<16;
354 else if (gop==E_GOP4)
355 *pBnkOfst = GOP_1GS0_OFST<<16;
356 else if (gop==E_GOP_MIXER)
357 *pBnkOfst = 0xD<<16;
358 else
359 return FALSE;
360
361 return TRUE;
362 }
363
_dumpGopNumFromBnkOffset(MS_U8 * gop,MS_U16 * subBnkOfst,MS_U32 pBnkOfst)364 MS_BOOL _dumpGopNumFromBnkOffset(MS_U8 * gop, MS_U16 * subBnkOfst, MS_U32 pBnkOfst)
365 {
366 MS_U32 subbnk = 0x0;
367 pBnkOfst = pBnkOfst >> 8;
368
369 if ((pBnkOfst >= GOP_4G_OFST) && (pBnkOfst < GOP_2G_OFST))
370 {
371 *gop = E_GOP0;
372 subbnk = pBnkOfst - GOP_4G_OFST;
373 }
374 else if ((pBnkOfst >= GOP_2G_OFST) && (pBnkOfst < GOP_1G_OFST))
375 {
376 *gop = E_GOP1;
377 subbnk = pBnkOfst - GOP_2G_OFST;
378 }
379 else if ((pBnkOfst >= GOP_1G_OFST) && (pBnkOfst < GOP_1GX_OFST))
380 {
381 *gop = E_GOP2;
382 subbnk = pBnkOfst - GOP_1G_OFST;
383 }
384 else if ((pBnkOfst >= GOP_1GX_OFST) && (pBnkOfst < GOP_1GS0_OFST))
385 {
386 *gop = E_GOP3;
387 subbnk = pBnkOfst - GOP_1GX_OFST;
388 }
389 else if ((pBnkOfst >= GOP_1GS0_OFST) || (pBnkOfst < GOP_1GS1_OFST))
390 {
391 *gop = E_GOP4;
392 subbnk = pBnkOfst - GOP_1GS0_OFST;
393 }
394 else
395 {
396 return FALSE;
397 }
398
399 *subBnkOfst = (MS_U16)(subbnk << 8);
400 return TRUE;
401 }
402
_isGopCommonRegs(MS_U16 reg)403 static MS_BOOL _isGopCommonRegs(MS_U16 reg)
404 {
405 MS_BOOL ret;
406
407 if ((reg >= (GOP_MUX_IPVOP & 0xFF)) && (reg <= (GOP_BAK_SEL & 0xFF)))
408 {
409 ret = TRUE;
410 }
411 else
412 {
413 ret = FALSE;
414 }
415
416 return ret;
417 }
418
_getLayerFromOpmux(Gop_MuxSel eGopMux)419 MS_U32 _getLayerFromOpmux(Gop_MuxSel eGopMux)
420 {
421 MS_U32 u32Layer = 0xFFFF;
422 int i=0;
423
424 for (i=0; i<MAX_GOP_MUX; i++)
425 {
426 if (g_GopChipPro.GOP_MapLayer2Mux[i] == eGopMux)
427 {
428 u32Layer = i;
429 break;
430 }
431 }
432
433 return u32Layer;
434 }
435
_SetDualOpMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel eGopMux,MS_U8 u8GOPNum)436 void _SetDualOpMux(GOP_CTX_HAL_LOCAL*pGOPHalLocal, Gop_MuxSel eGopMux, MS_U8 u8GOPNum)
437 {
438 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
439
440 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOPNum, &u8_mainGop, &u8_combinedGop) )
441 {
442 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
443 return;
444 }
445
446 // if GOP0 on 4K120 mode, GOP3 can't set to other destination
447 if ((u8GOPNum == u8_combinedGop) && (u8_mainGop != E_GOP4))
448 {
449 GOP_H_ERR("[%s]GOP%d can't set to other mode when GOP%d is on 4K@120\n",
450 __FUNCTION__, u8_combinedGop, u8_mainGop);
451 return;
452 }
453
454 if (u8_mainGop == E_GOP0)
455 {
456 // for GOP0+GOP3
457 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 0 , GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
458 }
459 else if (u8_mainGop == E_GOP2)
460 {
461 // for GOP1+GOOP2
462 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 1 << (GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)) , GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
463 }
464 else if (u8_mainGop == E_GOP4)
465 {
466 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 2 << (GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)) , GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
467 }
468 }
469
_isAfbcFunctionEnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8AfbcCore)470 MS_BOOL _isAfbcFunctionEnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8AfbcCore)
471 {
472 MS_U16 reg_val = 0x0;
473 HAL_GOP_Read16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(u8AfbcCore), ®_val);
474
475 return (reg_val & GOP_BIT0) ? TRUE : FALSE;
476 }
477
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)478 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
479 {
480 MS_U16 u16Mask0 = 0;
481 MS_U16 u16Mask1 = 0;
482 MS_U16 u16GopIdx = 0;
483 MS_U8 u8_mainGop =INVAILD_GOP_NUM, u8_combinedGop =INVAILD_GOP_NUM;
484 MS_U16 u16GopDst = 0x0;
485 MS_U32 u32MainBnkOfst = 0x0;
486
487 for (u16GopIdx = 0; u16GopIdx < MAX_GOP_SUPPORT; u16GopIdx++)
488 {
489 if ((u16GopMask | (1<<u16GopIdx))!=0)
490 {
491 break;
492 }
493 }
494
495 if (u16GopMask&GOP_BIT0)
496 {
497 u16Mask0 |= GOP_BIT12;
498 }
499 if (u16GopMask&GOP_BIT1)
500 {
501 u16Mask0 |= GOP_BIT13;
502 }
503 if (u16GopMask&GOP_BIT2)
504 {
505 u16Mask0 |= GOP_BIT14;
506 }
507 if (u16GopMask&GOP_BIT3)
508 {
509 u16Mask0 |= GOP_BIT15;
510 }
511 if (u16GopMask&GOP_BIT4)
512 {
513 u16Mask1 |= GOP_BIT4;
514 }
515
516 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, (MS_U8)u16GopIdx, &u8_mainGop, &u8_combinedGop) )
517 {
518 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
519 return GOP_FAIL;
520 }
521 _GetBnkOfstByGop(u8_mainGop, &u32MainBnkOfst);
522 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBnkOfst + GOP_4G_CTRL1, &u16GopDst);
523
524 if (u16Mask0 & (GOP_BIT12 | GOP_BIT15))
525 {
526 if ((u16GopDst & 0xf) == 0xB) //E_DRV_GOP_DST_OP_DUAL_RATE
527 {
528 u16Mask0 |= (GOP_BIT12 | GOP_BIT15);
529 }
530 }
531 if (u16Mask0 & (GOP_BIT13 | GOP_BIT14))
532 {
533 if ((u16GopDst & 0xf) == 0xB) //E_DRV_GOP_DST_OP_DUAL_RATE
534 {
535 u16Mask0 |= (GOP_BIT13 | GOP_BIT14);
536 }
537 }
538
539 if (u16Mask0 != 0)
540 {
541 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
542 }
543 if (u16Mask1 != 0)
544 {
545 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
546 }
547
548 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
549 {
550 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
551 }
552 return GOP_SUCCESS;
553 }
554
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)555 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
556 {
557 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
558 MS_U16 u16GopDst = 0x0;
559 MS_U32 u32MainBnkOfst = 0x0;
560
561 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
562 {
563 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
564 return GOP_FAIL;
565 }
566 _GetBnkOfstByGop(u8_mainGop, &u32MainBnkOfst);
567 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBnkOfst + GOP_4G_CTRL1, &u16GopDst);
568
569 if ((u16GopDst & 0xf) == 0xB) //E_DRV_GOP_DST_OP_DUAL_RATE
570 {
571 switch (u8_mainGop)
572 {
573 case E_GOP0:
574 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, (GOP_BIT12 | GOP_BIT15), (GOP_BIT12 | GOP_BIT15));
575 break;
576 case E_GOP2:
577 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, (GOP_BIT13 | GOP_BIT14), (GOP_BIT13 | GOP_BIT14));
578 break;
579 case E_GOP4:
580 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
581 break;
582 default:
583 break;
584 }
585 }
586 else
587 {
588 switch(gop)
589 {
590 case E_GOP0:
591 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
592 break;
593 case E_GOP1:
594 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
595 break;
596 case E_GOP2:
597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
598 break;
599 case E_GOP3:
600 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
601 break;
602 case E_GOP4:
603 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
604 break;
605 default:
606 break;
607 }
608 }
609
610 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
611 {
612 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
613 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
614 }
615 return GOP_SUCCESS;
616 }
617
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)618 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
619 {
620 MS_U16 u16GopAck = FALSE, reg_val =0;
621 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
622
623 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
624 {
625 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
626 return u16GopAck;
627 }
628
629 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
630 {
631 switch (u8_mainGop)
632 {
633 case E_GOP0:
634 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
635 if ((reg_val&GOP_BIT12) || (reg_val&GOP_BIT15))
636 u16GopAck = FALSE;
637 else
638 u16GopAck = TRUE;
639 break;
640 case E_GOP2:
641 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
642 if ((reg_val&GOP_BIT13) || (reg_val&GOP_BIT14))
643 u16GopAck = FALSE;
644 else
645 u16GopAck = TRUE;
646 break;
647 case E_GOP4:
648 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
649 if(reg_val&GOP_BIT4)
650 u16GopAck = FALSE;
651 else
652 u16GopAck = TRUE;
653 break;
654 default:
655 break;
656 }
657 }
658 else
659 {
660 switch(gop)
661 {
662 case E_GOP0:
663 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
664 if(reg_val&GOP_BIT12)
665 u16GopAck = FALSE;
666 else
667 u16GopAck = TRUE;
668 break;
669 case E_GOP1:
670 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
671 if(reg_val&GOP_BIT13)
672 u16GopAck = FALSE;
673 else
674 u16GopAck = TRUE;
675 break;
676 case E_GOP2:
677 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
678 if(reg_val&GOP_BIT14)
679 u16GopAck = FALSE;
680 else
681 u16GopAck = TRUE;
682 break;
683 case E_GOP3:
684 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
685 if(reg_val&GOP_BIT15)
686 u16GopAck = FALSE;
687 else
688 u16GopAck = TRUE;
689 break;
690 case E_GOP4:
691 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
692 if(reg_val&GOP_BIT4)
693 u16GopAck = FALSE;
694 else
695 u16GopAck = TRUE;
696 break;
697 default:
698 break;
699 }
700 }
701 return u16GopAck;
702 }
703
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)704 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
705 {
706 MS_U32 u32BankOffSet;
707
708 if (u8GOP < 3) /* only GOP0~GOP2 can support two linebuufer mode */
709 {
710 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
711 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_TWO_LINEBUFFER, bEnable?GOP_BIT12:0, GOP_BIT12);
712 }
713
714 return GOP_SUCCESS;
715 }
716
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)717 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
718 {
719 MS_U32 u32bankoff = 0;
720 MS_U16 mask_shift=0xFF;
721 MS_U16 u16RegVal=0xFF;
722 MS_U8 u8MIUSel=0xF;
723 MS_U8 u8Core=0;
724
725 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
726 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
727
728 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDFD0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32", set DMA FIFO threhold to "0xD0"
729
730 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
731 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
732
733 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
734
735 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
736 {
737 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
738
739 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK);
740 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, GOP_BIT2);
741 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, GOP_BIT8|GOP_BIT10|GOP_BIT12, (GOP_BIT8|GOP_BIT9)|(GOP_BIT10|GOP_BIT11)|(GOP_BIT12|GOP_BIT13));
742 }
743
744 /* enable GOP clock */
745 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
746 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
747
748 switch(u8GOPNum)
749 {
750 case E_GOP0:
751 mask_shift = GOP_MIU_CLIENT_GOP0;
752 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
753 break;
754 case E_GOP1:
755 mask_shift = GOP_MIU_CLIENT_GOP1;
756 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
757 break;
758 case E_GOP2:
759 mask_shift = GOP_MIU_CLIENT_GOP2;
760 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
761 break;
762 case E_GOP3:
763 mask_shift = GOP_MIU_CLIENT_GOP3;
764 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
765 break;
766 case E_GOP4:
767 mask_shift = GOP_MIU_CLIENT_GOP4;
768 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, 0, CKG_GOPG4_DISABLE_CLK_MASK); /* GOP 4 */
769 break;
770 case E_GOP_Dwin:
771 mask_shift = GOP_MIU_CLIENT_DWIN;
772 break;
773 default:
774 mask_shift = 0xFF;
775 break;
776 }
777 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
778 {
779 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
780 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
781 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
782 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
783 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
784 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(0), GOP_BIT4, GOP_BIT4); //quick_preload_0
785 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(1), GOP_BIT4, GOP_BIT4); //quick_preload_1
786 }
787
788
789 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
790 {
791 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
792 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
793 #ifdef GOP_MIU_GROUP2
794 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
795 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
796 #endif
797
798 // Maserati Bug, AFBC disable need set bit15 = 1
799 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_MUX4_4K120, GOP_BIT7, GOP_BIT7 );
800
801 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
802 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
803 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
804 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
805 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
806 {
807 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
808 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
809 }
810 }
811
812 //OC_RM_alpha
813 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
814 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
815 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
816
817 // set VIP/VOP timing select, always select VOP should be OK.
818 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_VIP_VOP_TIMING_SEL, GOP_BIT10, GOP_BIT10);
819
820 // Set Gwin priority, prio0 : Gwin0; prio1:Gwin1, so set GOP_BIT4
821 if(u8GOPNum == E_GOP0 || u8GOPNum == E_GOP1)
822 {
823 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff + GOP_4G_PRI0, GOP_BIT4, (GOP_BIT0 | GOP_BIT1 | GOP_BIT4 | GOP_BIT5 ));
824 }
825
826 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOP_HSYNC_START, g_GopChipPro.GOP_REF_POSITION_X, 0x1FFF);
827 }
828
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)829 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
830 {
831 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
832 }
833
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)834 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
835 {
836 switch(u8GopNum)
837 {
838 case E_GOP0:
839 return (MS_U8)MAX_GOP0_GWIN;
840 break;
841 case E_GOP1:
842 return (MS_U8)MAX_GOP1_GWIN;
843 break;
844 case E_GOP2:
845 return (MS_U8)MAX_GOP2_GWIN;
846 break;
847 case E_GOP3:
848 return (MS_U8)MAX_GOP3_GWIN;
849 break;
850 case E_GOP4:
851 return (MS_U8)MAX_GOP4_GWIN;
852 break;
853 default:
854 GOP_ASSERT(0);
855 return 0xFF;
856 break;
857 }
858 }
859
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)860 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
861 {
862 MS_U8 u8GWinId = 0;
863
864 //Adjust GWIN ID by different Chip
865
866 switch(u8Gop)
867 {
868 case E_GOP0:
869 u8GWinId = GOP0_GwinIdBase + u8Idx;
870 break;
871 case E_GOP1:
872 u8GWinId = GOP1_GwinIdBase + u8Idx;
873 break;
874 case E_GOP2:
875 u8GWinId = GOP2_GwinIdBase + u8Idx;
876 break;
877 case E_GOP3:
878 u8GWinId = GOP3_GwinIdBase + u8Idx;
879 break;
880 case E_GOP4:
881 u8GWinId = GOP4_GwinIdBase + u8Idx;
882 break;
883 default:
884 break;
885 }
886 return u8GWinId;
887
888 }
889
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)890 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
891 {
892 switch(u8GOPNum)
893 {
894 case E_GOP0: // GOP4G
895 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
896 return GOP_SUCCESS;
897 case E_GOP1: // GOP2G
898 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
899 return GOP_SUCCESS;
900 case E_GOP2: // GOP1G
901 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
902 return GOP_SUCCESS;
903 case E_GOP3: // GOP1GX
904 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
905 return GOP_SUCCESS;
906 case E_GOP4: // GOP1GS
907 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
908 return GOP_SUCCESS;
909 default:
910 GOP_ASSERT(0);
911 return GOP_FAIL;
912 }
913 }
914
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)915 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
916 {
917 MS_U16 u16Bank;
918 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
919 u16Bank &= ~BMASK(3:0);
920 u16Bank |= (u8bank&BMASK(3:0));
921 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
922 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
923 u16Bank &= ~GOP_BIT4;
924 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
925 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
926 }
927
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)928 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
929 {
930 MS_U16 u16GetBank;
931 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
932 return (u16GetBank&GOP_BANK_MASK);
933 }
934
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)935 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
936 {
937 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
938 MS_U32 bank;
939 MS_U32 direct_addr;
940
941 GOP_H_INFO("HAL_GOP_Read16Reg[%td]\n", (ptrdiff_t)u32addr);
942
943 //* Gop driver should access another HW IP register
944 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
945 switch (u32addr & 0xFF00)
946 {
947 case GOP_REG_BASE:
948 {
949 bank = (u32addr & 0xFF0000) >> 8;
950
951 if(bank==0xE00)//GOP4: 0x121B00
952 {
953 bank=GOP_REG_GOP4_BK_OFFSET;
954 }
955 else if(bank==0xF00)//GWIN4: 0x121E00
956 {
957 bank=GOP_REG_GOP4_GW_OFFSET;
958 }
959 else if(bank==0x1000)//GOP4_ST
960 {
961 bank=GOP_REG_GOP4_ST_OFFSET;
962 }
963 else if(bank==0x3100)//AFBC
964 {
965 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
966 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
967 break;
968 }
969
970 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
971 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
972 break;
973 }
974 case SC1_REG_BASE:
975 {
976 if(g_GopChipPro.bXCDirrectBankSupport)
977 {
978 u16xcSubbank = (u32addr & 0xFF0000)>>8;
979 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
980 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
981 }
982 else
983 {
984 u16xcSubbank = (u32addr & 0xFF0000)>>16;
985 u16BankAddr = GOP_SC_BANKSEL+0;
986 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
987
988 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
989 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
990 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
991 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
992 }
993 break;
994 }
995 case GE_REG_BASE:
996 case CKG_REG_BASE:
997 case MIU0_REG_BASE:
998 case MIU_REG_BASE:
999 case MVOP_REG_BASE:
1000 {
1001 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
1002 break;
1003 }
1004 #ifdef GOP_MIU_GROUP2
1005 case (MIU2_REG_BASE & 0xFF00):
1006 {
1007 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1008 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
1009
1010 break;
1011 }
1012 #endif
1013 default:
1014 {
1015 //Gop lib current do not support this HW ip base
1016 GOP_ASSERT(0);
1017 *pu16ret =0;
1018 break;
1019 }
1020 }
1021 }
1022
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)1023 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
1024 {
1025 MS_U16 u16tmp=0;
1026 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
1027 MS_U32 bank;
1028 MS_U32 direct_addr;
1029
1030 MS_U8 u8_gop =INVAILD_GOP_NUM;
1031 MS_U8 u8_mainGop =INVAILD_GOP_NUM, u8_combinedGop =INVAILD_GOP_NUM;
1032 MS_U16 u16SubBnkOfst = 0x0;
1033 MS_U16 u16GopDst = 0x0;
1034 MS_U32 u32MainBnkOfst = 0x0;
1035
1036 GOP_H_INFO("HAL_GOP_Write16Reg[%04tx] = %04x\n", (ptrdiff_t)u32addr, u16val);
1037
1038 if(mask!=0xffff)
1039 {
1040 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
1041 u16tmp &= ~mask;
1042 u16val &= mask;
1043 u16val |= u16tmp;
1044 }
1045
1046 //* Gop driver should access another HW IP register
1047 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
1048 switch (u32addr & 0xFF00)
1049 {
1050 case GOP_REG_BASE:
1051 {
1052 bank = (u32addr & 0xFF0000) >> 8;
1053
1054 if(bank==0xE00)//GOP4: 0x121B00
1055 {
1056 bank=GOP_REG_GOP4_BK_OFFSET;
1057 }
1058 else if(bank==0xF00)//GWIN4: 0x121E00
1059 {
1060 bank=GOP_REG_GOP4_GW_OFFSET;
1061 }
1062 else if(bank==0x1000) //GOP4_ST
1063 {
1064 bank=GOP_REG_GOP4_ST_OFFSET;
1065 }
1066 else if(bank==0x3100)//AFBC
1067 {
1068 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1069 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1070 break;
1071 }
1072 else if (bank==0x7000)// Manual Crop
1073 {
1074 direct_addr = MANUAL_CROP_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1075 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1076 break;
1077 }
1078
1079
1080 if( FALSE == _dumpGopNumFromBnkOffset(&u8_gop, &u16SubBnkOfst, bank) )
1081 {
1082 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1083 return;
1084 }
1085
1086 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8_gop, &u8_mainGop, &u8_combinedGop) )
1087 {
1088 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1089 return;
1090 }
1091
1092 _GetBnkOfstByGop(u8_mainGop, &u32MainBnkOfst);
1093 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBnkOfst + GOP_4G_CTRL1, &u16GopDst);
1094 if ((u8_gop == u8_mainGop) &&
1095 ((u16GopDst & 0xf) == 0xB) &&
1096 (_isGopCommonRegs(u32addr & 0xFF) == FALSE) // combined register only the set once
1097 )
1098 {
1099 // to combine GOP0&GOP3, GOP1&GOP2
1100 MS_U8 u8_Copy2Gop = (u8_gop == u8_mainGop) ? u8_combinedGop : u8_mainGop;
1101 MS_U32 CopyGopbkofst = 0x0;
1102
1103 _GetBnkOfstByGop(u8_Copy2Gop, &CopyGopbkofst);
1104 CopyGopbkofst = (CopyGopbkofst >> 8) + u16SubBnkOfst;
1105
1106 direct_addr = GOP_REG_DIRECT_BASE + CopyGopbkofst + (u32addr & 0xFF);
1107 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1108 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
1109 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1110 }
1111 else
1112 {
1113 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
1114 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1115 }
1116 break;
1117 }
1118 case SC1_REG_BASE:
1119 if(g_GopChipPro.bXCDirrectBankSupport)
1120 { /*Derrick Bank*/
1121 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
1122 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
1123 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1124 }
1125 else
1126 { /*Sub Bank*/
1127 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
1128 u16BankAddr = GOP_SC_BANKSEL+0;
1129 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
1130
1131 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
1132 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
1133 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
1134 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
1135 }
1136 break;
1137 case GE_REG_BASE:
1138 case CKG_REG_BASE:
1139 case MIU0_REG_BASE:
1140 case MIU_REG_BASE:
1141 {
1142 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
1143 break;
1144 }
1145 #ifdef GOP_MIU_GROUP2
1146 case (MIU2_REG_BASE & 0xFF00):
1147 {
1148 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1149 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1150 break;
1151 }
1152 #endif
1153 default:
1154 {
1155 //Gop lib current do not support this HW ip base
1156 GOP_ASSERT(0);
1157 break;
1158 }
1159
1160 }
1161 }
1162
1163
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)1164 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
1165 {
1166 HAL_GOP_Write16Reg(pGOPHalLocal, u32addr, (MS_U16)(u32val&0xFFFF), 0xffff);
1167 HAL_GOP_Write16Reg(pGOPHalLocal, u32addr+2, (MS_U16)((u32val&0xFFFF0000)>>16), 0xffff);
1168 }
1169
1170 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
1171
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)1172 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
1173 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
1174 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
1175 {
1176 MS_U8 i=0;
1177 GOP_H_INFO("GOP_Write32Pal : i= %02x, ARGB = %02x,%02x,%02x,%02x\n",u8Index, u8A, u8R, u8G, u8B);
1178
1179 /* Don't care high byte */
1180 GOP_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
1181
1182 for(i =(GOP_WordUnit-1);i>4;i--)
1183 {
1184 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
1185 }
1186 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
1187 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
1188 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
1189 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
1190 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
1191 *pREGMAP_Offset += GOP_WordUnit;
1192
1193 MsOS_FlushMemory(); //make sure cpu write data to dram
1194
1195 }
1196
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)1197 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
1198 {
1199 MS_U16 bpp=0;
1200
1201 switch ( fbFmt )
1202 {
1203 case E_DRV_GOP_COLOR_RGB555_BLINK :
1204 case E_DRV_GOP_COLOR_RGB565 :
1205 case E_DRV_GOP_COLOR_ARGB1555:
1206 case E_DRV_GOP_COLOR_RGBA5551:
1207 case E_DRV_GOP_COLOR_ARGB4444 :
1208 case E_DRV_GOP_COLOR_RGBA4444 :
1209 case E_DRV_GOP_COLOR_RGB555YUV422:
1210 case E_DRV_GOP_COLOR_YUV422:
1211 case E_DRV_GOP_COLOR_2266:
1212 bpp = 16;
1213 break;
1214 case E_DRV_GOP_COLOR_ARGB8888 :
1215 case E_DRV_GOP_COLOR_ABGR8888 :
1216 bpp = 32;
1217 break;
1218
1219 case E_DRV_GOP_COLOR_I8 :
1220 bpp = 8;
1221 break;
1222
1223 default :
1224 //print err
1225 GOP_ASSERT(0);
1226 bpp = 0xFFFF;
1227 break;
1228 }
1229 return bpp;
1230
1231 }
1232
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)1233 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
1234 {
1235 MS_U16 regval;
1236 /*For compatibility
1237 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
1238 MS_U8 u8coef_cpt = u8coef;
1239
1240 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
1241 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
1242 {
1243 switch(u8coef)
1244 {
1245 case 0x0 :
1246 u8coef_cpt = u8coef<<2;
1247 break;
1248 case 0x3f :
1249 u8coef_cpt = ((u8coef<<2)|0x3);
1250 break;
1251 default:
1252 u8coef_cpt = ((u8coef<<2)|0x1);
1253 break;
1254 }
1255 }
1256
1257 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1258 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1259 {
1260 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1261 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1262 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1263 }
1264 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1265 else
1266 {
1267 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1268 {
1269 regval = (MS_U16)(bEnable?(1<<14):0);
1270 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1271 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1272 }
1273 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1274 {
1275 regval = (MS_U16)(bEnable?(1<<14):0);
1276 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1277 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1278 }
1279 else
1280 {
1281 regval = (MS_U16)(bEnable?(1<<14):0);
1282 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1283 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1284 }
1285 }
1286 }
1287
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1288 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1289 {
1290 pGOPHalLocal->va_mmio_base = addr;
1291 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1292 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1293 {
1294 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1295 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1296 {
1297 }
1298
1299
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1300 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1301 {
1302 /*A5 GOP dst type:
1303 1: IP (Main)
1304 0: IP (Sub)
1305 2: OP
1306 3: MVOP
1307 4: MVOP (Sub)
1308 6: FRC
1309 11: InsideFRC
1310 */
1311 MS_U8 i=0, Cnt=0;
1312 MS_U16 u16RegVal;
1313 MS_U32 u32BankOffSet;
1314 DRV_GOPDstType pGopDst;
1315 MS_BOOL bEnable;
1316 MS_U16 u16HSyncMask=GOP_BIT14;
1317 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1318
1319 if( GopNum >= MAX_GOP_SUPPORT)
1320 {
1321 return GOP_INVALID_PARAMETERS;
1322 }
1323
1324 switch (eDstType)
1325 {
1326 case E_DRV_GOP_DST_IP0:
1327 u16RegVal = 0x0;
1328 bEnable = FALSE;
1329 u16HSyncMask=0;
1330 break;
1331
1332 case E_DRV_GOP_DST_IP0_SUB:
1333 u16RegVal = 0x1;
1334 bEnable = FALSE;
1335 u16HSyncMask=0;
1336 break;
1337
1338 case E_DRV_GOP_DST_OP0:
1339 u16RegVal = 0x2;
1340 bEnable = FALSE;
1341 u16HSyncMask=GOP_BIT14;
1342 break;
1343
1344 case E_DRV_GOP_DST_VOP:
1345 u16RegVal = 0x3;
1346 bEnable = FALSE;
1347 u16HSyncMask=GOP_BIT14;
1348 break;
1349
1350 case E_DRV_GOP_DST_VOP_SUB:
1351 u16RegVal = 0x4;
1352 bEnable = FALSE;
1353 u16HSyncMask=GOP_BIT14;
1354 break;
1355
1356 case E_DRV_GOP_DST_FRC:
1357 u16RegVal = 0x6;
1358 bEnable = TRUE;
1359 u16HSyncMask=GOP_BIT14;
1360 break;
1361
1362 case E_DRV_GOP_DST_VE:
1363 u16RegVal = 0x7;
1364 bEnable = TRUE;
1365 u16HSyncMask=GOP_BIT14;
1366 break;
1367 case E_DRV_GOP_DST_DIP:
1368 u16RegVal = 0x8;
1369 bEnable = TRUE;
1370 u16HSyncMask=GOP_BIT14;
1371 break;
1372 case E_DRV_GOP_DST_OP_DUAL_RATE:
1373 u16RegVal = 0xB;
1374 bEnable = FALSE;
1375 u16HSyncMask=0x0;
1376 break;
1377 default:
1378 return GOP_FUN_NOT_SUPPORTED;
1379 }
1380 if(bOnlyCheck == FALSE)
1381 {
1382 Hal_get4K120CombinedGOP(pGOPHalLocal, GopNum, &u8_mainGop, &u8_combinedGop);
1383 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1384 {
1385 pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] = eDstType;
1386 pGOPHalLocal->pHALShared->GOP_Dst[u8_combinedGop] = eDstType;
1387 }
1388 else
1389 {
1390 pGOPHalLocal->pHALShared->GOP_Dst[GopNum] = eDstType;
1391 }
1392
1393 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1394 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1395 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
1396
1397 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1398 {
1399 MS_U32 u32SubBnkOffSet=0;
1400 _GetBnkOfstByGop(u8_combinedGop, &u32SubBnkOffSet);
1401 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBnkOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
1402 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBnkOffSet+GOP_4G_BW, GOP_DMA_ACCESS_HIGH_PRIORITY, GOP_REG_HW_MASK);
1403 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBnkOffSet+GOP_4G_BW, GOP_FIFO_BURST_ALL, GOP_FIFO_BURST_MASK);
1404 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBnkOffSet+GOP_4G_BW, GOP_FIFO_THRESHOLD, GOP_REG_LW_MASK);
1405 }
1406
1407 //For Bypass
1408 for(i=0; i<MAX_GOP_SUPPORT ;i++)
1409 {
1410 HAL_GOP_GetGOPDst(pGOPHalLocal, i, &pGopDst);
1411 if(pGopDst == E_DRV_GOP_DST_FRC)
1412 {
1413 Cnt++;
1414 }
1415 }
1416
1417 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1418 {
1419 Hal_Ctrl4K120GopMode(pGOPHalLocal, GopNum, TRUE);
1420 Hal_SetCropWindow(pGOPHalLocal, GopNum, EN_GOP_CROP_ENABLE);
1421 }
1422 else
1423 {
1424 Hal_Ctrl4K120GopMode(pGOPHalLocal, GopNum, FALSE);
1425 Hal_SetCropWindow(pGOPHalLocal, GopNum, EN_GOP_CROP_DISABLE);
1426 }
1427
1428 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1429 }
1430 return GOP_SUCCESS;
1431 }
1432
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1433 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1434 {
1435 return GOP_FUN_NOT_SUPPORTED;
1436 }
1437
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1438 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1439 {
1440 return GOP_FUN_NOT_SUPPORTED;
1441 }
1442
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1443 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1444 {
1445 /*T8
1446 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1447 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1448 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1449 */
1450 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1451 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1452 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
1453 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1454
1455 // 4k120_mux0: GOP0+GOP3
1456 // 4k120_mux1: GOP2+GOP1
1457 // 4k120_mux2: GOP4
1458 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 0x24, 0x3F);
1459
1460 return GOP_SUCCESS;
1461 }
1462
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1463 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1464 {
1465 MS_U16 u16GopMux=0;
1466
1467 switch(eGopMux)
1468 {
1469 case E_GOP_MUX0:
1470 case E_GOP_MUX1:
1471 case E_GOP_MUX2:
1472 case E_GOP_MUX3:
1473 case E_GOP_MUX4:
1474 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1475 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1476 break;
1477 case E_GOP_IP0_MUX:
1478 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1479 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1480 break;
1481 case E_GOP_IP0_SUB_MUX:
1482 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1483 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1484 break;
1485 case E_GOP_VOP0_MUX:
1486 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1487 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1488 break;
1489 case E_GOP_VOP0_SUB_MUX:
1490 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1491 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1492 break;
1493 case E_GOP_Mix_MUX0:
1494 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1495 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1496 break;
1497 case E_GOP_Mix_MUX1:
1498 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1499 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1500 break;
1501 case E_GOP_VE0_MUX:
1502 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1503 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1504 break;
1505 case E_GOP_VE1_MUX:
1506 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1507 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1508 break;
1509 case E_GOP_DIP_MUX:
1510 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1511 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1512 break;
1513 case E_GOP_FRC_MUX0:
1514 case E_GOP_FRC_MUX1:
1515 case E_GOP_FRC_MUX2:
1516 case E_GOP_FRC_MUX3:
1517 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1518 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1519 break;
1520 case E_GOP_BYPASS_MUX0:
1521 break;
1522
1523 case E_GOP_DUALRATE_OP_MUX0:
1524 case E_GOP_DUALRATE_OP_MUX1:
1525 case E_GOP_DUALRATE_OP_MUX2:
1526 {
1527 MS_U8 mux_sel_idx;
1528 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_4K120, &u16GopMux);
1529
1530 mux_sel_idx = (u16GopMux >> ((eGopMux-E_GOP_DUALRATE_OP_MUX0)*GOP_4K120_MUX_SHIFT))& GOP_4K120_REGMUX_MASK;
1531 if (mux_sel_idx < GOP_4K120_MUX_COUNT)
1532 {
1533 *u8GOPNum = GOP_4K120MUX_IDX_TABLE[mux_sel_idx];
1534 }
1535 else
1536 {
1537 *u8GOPNum = MAX_GOP_DualMUX_Num;
1538 }
1539 }
1540 break;
1541 case E_GOP_IP1_MUX:
1542 case E_GOP_VOP1_MUX:
1543 case E_GOP_OP1_MUX:
1544 case E_GOP_GS_MUX:
1545 // to prevent warning log
1546 break;
1547 default:
1548 GOP_H_ERR("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1549 break;
1550 }
1551 }
1552
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1553 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1554 {
1555 MS_U16 u16Ret[4]={0};
1556
1557 switch(eGopMux)
1558 {
1559 case E_GOP_MUX0:
1560 case E_GOP_MUX1:
1561 case E_GOP_MUX2:
1562 case E_GOP_MUX3:
1563 case E_GOP_MUX4:
1564 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1565
1566 // get layer from op mux
1567 MS_U32 u32Layer = _getLayerFromOpmux(eGopMux);
1568 if (u32Layer == 0xFFFF)
1569 {
1570 GOP_H_ERR("can't get layer from mux = %d !!", (MS_U16)eGopMux);
1571 break;
1572 }
1573
1574 // set dual op mux
1575 _SetDualOpMux(pGOPHalLocal, g_GopChipPro.GOP_MapLayer2DualOpMux[u32Layer], u8GOPNum);
1576 break;
1577
1578 case E_GOP_DUALRATE_OP_MUX0:
1579 case E_GOP_DUALRATE_OP_MUX1:
1580 case E_GOP_DUALRATE_OP_MUX2:
1581 _SetDualOpMux(pGOPHalLocal, eGopMux, u8GOPNum);
1582 break;
1583
1584 case E_GOP_IP0_MUX:
1585 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1586 break;
1587 case E_GOP_IP1_MUX:
1588 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_SUB_MUX_SHIFT, GOP_IP_SUB_MUX_MASK);
1589 break;
1590 case E_GOP_VOP0_MUX:
1591 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1592 break;
1593 case E_GOP_VOP1_MUX:
1594 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1595 break;
1596 case E_GOP_Mix_MUX0:
1597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1598 break;
1599 case E_GOP_Mix_MUX1:
1600 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1601 break;
1602 case E_GOP_VE0_MUX:
1603 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1604 break;
1605 case E_GOP_VE1_MUX:
1606 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1607 break;
1608 case E_GOP_DIP_MUX:
1609 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1610 break;
1611 case E_GOP_FRC_MUX0:
1612 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1613 break;
1614 case E_GOP_FRC_MUX1:
1615 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1616 break;
1617 case E_GOP_FRC_MUX2:
1618 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1619 break;
1620 case E_GOP_FRC_MUX3:
1621 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1622 break;
1623 case E_GOP_BYPASS_MUX0:
1624 //Check MUX is using? Checking from priority high to low
1625 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1626 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1627 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1628 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1629
1630 //Checking if un-use
1631 if((u16Ret[0] & GOP_BIT0) ==0)
1632 {
1633 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1634 }
1635 else if((u16Ret[1] & GOP_BIT0) ==0)
1636 {
1637 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1638 }
1639 else if((u16Ret[2] & GOP_BIT0) ==0)
1640 {
1641 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1642 }
1643 else if((u16Ret[3] & GOP_BIT0) ==0)
1644 {
1645 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1646 }
1647 else
1648 {
1649 GOP_H_ERR("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1650 }
1651 break;
1652 break;
1653 default:
1654 GOP_H_ERR("[%s]ERROR mux setting\n",__FUNCTION__);
1655 break;
1656 }
1657 }
1658
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1659 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1660 {
1661 /* GOP OP Path enable to SC Setting
1662 A5: GOP OP Path blending with SC sequence
1663 mux1-->mux0-->mux2-->mux3
1664 */
1665 MS_U16 muxValue=0, regval=0;
1666
1667 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1668 MS_U16 u164K2KMuxValue=0;
1669 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1670 MS_U8 mux_need_ctrl = 0;
1671
1672 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1673 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1674
1675 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1676 {
1677 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1678 }
1679
1680 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1681 {
1682 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1683 }
1684
1685 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1686 {
1687 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1688 }
1689
1690 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1691 {
1692 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1693 }
1694
1695 if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1696 {
1697 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1698 }
1699
1700 /*For FRC mux switch*/
1701 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1702 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1703 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1704 {
1705 /* Switch FRC blending */
1706 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1707 }
1708
1709 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1710 {
1711 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1712 }
1713
1714 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1715 {
1716 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1717 }
1718
1719 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1720 {
1721 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1722 }
1723
1724 Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop);
1725
1726 if (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst)
1727 {
1728 // disable the xc OP blending mux of sub GOP
1729 if (u8_combinedGop== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1730 {
1731 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT15), GOP_BIT15);
1732 }
1733 else if (u8_combinedGop== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1734 {
1735 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT12), GOP_BIT12);
1736 }
1737 else if (u8_combinedGop== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1738 {
1739 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT14), GOP_BIT14);
1740 }
1741 else if (u8_combinedGop== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1742 {
1743 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT13), GOP_BIT13);
1744 }
1745 else if (u8_combinedGop== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4)))
1746 {
1747 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT11), GOP_BIT11);
1748 }
1749 }
1750
1751 mux_need_ctrl = _findMuxNumberByGOP(pGOPHalLocal, pGopDst, u8_mainGop);
1752 if (GOP_4K120MUX_MUX0 == mux_need_ctrl)
1753 {
1754 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN0, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1755 }
1756 else if (GOP_4K120MUX_MUX1 == mux_need_ctrl)
1757 {
1758 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN1, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1759 }
1760 else if (GOP_4K120MUX_MUX2 == mux_need_ctrl)
1761 {
1762 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN2, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1763 }
1764
1765 return GOP_SUCCESS;
1766 }
1767
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1768 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1769 {
1770 MS_U32 u32pBankOffSet=0;
1771 MS_U16 u16Regval;
1772
1773 if(g_GopChipPro.b2Pto1PSupport)
1774 {
1775 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1776 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1777 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |0x0800):(u16Regval & ~0x0800), 0x0800);
1778 }
1779 return GOP_SUCCESS;
1780 }
1781
_IsGopInDualOpMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum,Gop_MuxSel * corr_mux)1782 static MS_BOOL _IsGopInDualOpMux(GOP_CTX_HAL_LOCAL* pGOPHalLocal, MS_U8 u8GopNum, Gop_MuxSel * corr_mux)
1783 {
1784 MS_U8 i=0x0;
1785 MS_U8 mux_val = 0x0;
1786 for (i=0; i<GOP_4K120_MUX_COUNT; i++)
1787 {
1788 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &mux_val, (Gop_MuxSel)i + E_GOP_DUALRATE_OP_MUX0);
1789 if (((u8GopNum == E_GOP0) && (mux_val == 0)) ||
1790 ((u8GopNum == E_GOP2) && (mux_val == 1)) ||
1791 ((u8GopNum == E_GOP4) && (mux_val == 2)))
1792 {
1793 *corr_mux = (Gop_MuxSel)i;
1794 return TRUE;
1795 }
1796 }
1797 return FALSE;
1798 }
1799
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1800 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1801 {
1802 /* GOP OP Path enable to SC Setting
1803 A5: GOP OP Path blending with SC sequence
1804 mux1-->mux0-->mux2-->mux3
1805 */
1806 MS_U16 muxValue=0, regval=0;
1807 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1808
1809 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1810 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1811 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1812 {
1813 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1814 }
1815 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1816 {
1817 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1818 }
1819 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1820 {
1821 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1822 }
1823 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1824 {
1825 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1826 }
1827 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1828 {
1829 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1830 }
1831 else
1832 {
1833 return GOP_FAIL;
1834 }
1835
1836 if( TRUE == Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop) )
1837 {
1838 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
1839 {
1840 MS_U16 mux4mainGop;
1841 MS_U16 mux4combinedGop;
1842 Gop_MuxSel mux_value = E_GOP_MUX_INVAILD;
1843 MS_U32 reg_num = 0x0;
1844
1845 mux4mainGop = _findMuxNumberByGOP(pGOPHalLocal, pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop], u8_mainGop);
1846 mux4combinedGop = _findMuxNumberByGOP(pGOPHalLocal, pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop], u8_combinedGop);
1847
1848 if ((mux4mainGop == INVALID_GOP_MUX_VAL) || (mux4combinedGop == INVALID_GOP_MUX_VAL))
1849 {
1850 return GOP_FAIL;
1851 }
1852
1853 if (_IsGopInDualOpMux(pGOPHalLocal, mux4mainGop, &mux_value) == TRUE)
1854 {
1855 if (mux_value == 0)
1856 {
1857 reg_num = GOP_SC_4K120_EN0;
1858 }
1859 else if (mux_value == 1)
1860 {
1861 reg_num = GOP_SC_4K120_EN1;
1862 }
1863 else if (mux_value == 2)
1864 {
1865 reg_num = GOP_SC_4K120_EN2;
1866 }
1867
1868 HAL_GOP_Write16Reg(pGOPHalLocal, reg_num, (bEnable == TRUE) ? GOP_BIT10 : ~GOP_BIT10, GOP_BIT10);
1869 }
1870 }
1871 }
1872
1873 return GOP_SUCCESS;
1874 }
1875
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1876 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1877 {
1878 MS_U16 muxValue=0, regval=0;
1879 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1880
1881 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop) )
1882 {
1883 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1884 return GOP_FAIL;
1885 }
1886
1887 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
1888 {
1889 gopNum = u8_mainGop;
1890 }
1891
1892 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1893 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1894 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1895 {
1896 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
1897 }
1898 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1899 {
1900 *pbEnable = (regval & GOP_BIT12) == GOP_BIT12;
1901 }
1902 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1903 {
1904 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
1905 }
1906 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1907 {
1908 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
1909 }
1910 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1911 {
1912 *pbEnable = (regval & GOP_BIT14) == GOP_BIT14;
1913 }
1914 else
1915 {
1916 return GOP_FAIL;
1917 }
1918 return GOP_SUCCESS;
1919 }
1920
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1921 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1922 {
1923 /*T8
1924 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1925 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1926 */
1927 MS_U16 Mux3Gop, muxValue=0, i;
1928 MS_U16 MuxShift;
1929
1930 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1931
1932 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1933 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1934 {
1935 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1936 {
1937 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1938
1939 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1940 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1941 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1942 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1943 break;
1944 }
1945 }
1946 return GOP_SUCCESS;
1947 }
1948
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1949 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1950 {
1951 /*T8 GOP dst type:
1952 0: IP (Main)
1953 1: IP (Sub)
1954 2: OP
1955 3: MVOP
1956 */
1957
1958 /* Monaco clkgen setting */
1959 /******************
1960 0: odclk
1961 1: idclk_f2 (ipm)
1962 2: idclk_f1 (ips)
1963 3: ocmixer
1964 4: ve
1965 5 : mvop main
1966 6 : mvop sub
1967 ******************/
1968 switch(eDstType)
1969 {
1970 case E_DRV_GOP_DST_IP0:
1971
1972 if (gopNum==E_GOP1)
1973 {
1974 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1975 }
1976 else if (gopNum ==E_GOP2)
1977 {
1978 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1979 }
1980 else if (gopNum ==E_GOP3)
1981 {
1982 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1983 }
1984 else if (gopNum ==E_GOP4)
1985 {
1986 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1987 }
1988 else if (gopNum==E_GOP0)
1989 {
1990 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1991 }
1992 else
1993 {
1994 GOP_ASSERT(0);
1995 return GOP_INVALID_PARAMETERS;
1996 }
1997 break;
1998
1999 case E_DRV_GOP_DST_IP0_SUB:
2000 if (gopNum==E_GOP1)
2001 {
2002 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
2003 }
2004 else if (gopNum==E_GOP2)
2005 {
2006 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
2007 }
2008 else if (gopNum==E_GOP3)
2009 {
2010 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG3_MASK);
2011 }
2012 else if (gopNum ==E_GOP4)
2013 {
2014 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK1, CKG_GOPG4_MASK);
2015 }
2016 else if (gopNum==E_GOP0)
2017 {
2018 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
2019 }
2020 else
2021 {
2022 GOP_ASSERT(0);
2023 return GOP_INVALID_PARAMETERS;
2024 }
2025 break;
2026
2027
2028 case E_DRV_GOP_DST_OP0:
2029 if (gopNum==E_GOP1)
2030 {
2031 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
2032 }
2033 else if (gopNum==E_GOP2)
2034 {
2035 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
2036 }
2037 else if (gopNum==E_GOP3)
2038 {
2039 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
2040 }
2041 else if (gopNum ==E_GOP4)
2042 {
2043 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
2044 }
2045 else if (gopNum==E_GOP0)
2046 {
2047 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
2048 }
2049 else
2050 {
2051 GOP_ASSERT(0);
2052 return GOP_INVALID_PARAMETERS;
2053 }
2054 break;
2055 case E_DRV_GOP_DST_DIP:
2056 if (gopNum==E_GOP1)
2057 {
2058 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_FCLK, CKG_GOPG1_MASK);
2059 }
2060 else if (gopNum==E_GOP2)
2061 {
2062 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_FCLK, CKG_GOPG2_MASK);
2063 }
2064 else if (gopNum==E_GOP3)
2065 {
2066 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_FCLK, CKG_GOPG3_MASK);
2067 }
2068 else if (gopNum ==E_GOP4)
2069 {
2070 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_FCLK, CKG_GOPG4_MASK);
2071 }
2072 else if (gopNum==E_GOP0)
2073 {
2074 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_FCLK, CKG_GOPG0_MASK);
2075 }
2076 else
2077 {
2078 GOP_ASSERT(0);
2079 return GOP_INVALID_PARAMETERS;
2080 }
2081
2082 break;
2083
2084 case E_DRV_GOP_DST_VOP:
2085 if (gopNum==E_GOP1)
2086 {
2087 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
2088 }
2089 else if (gopNum ==E_GOP2)
2090 {
2091 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
2092 }
2093 else if (gopNum ==E_GOP3)
2094 {
2095 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
2096 }
2097 else if (gopNum ==E_GOP4)
2098 {
2099 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
2100 }
2101 else if (gopNum==E_GOP0)
2102 {
2103 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
2104 }
2105 else
2106 {
2107 GOP_ASSERT(0);
2108 return GOP_INVALID_PARAMETERS;
2109 }
2110
2111 break;
2112 case E_DRV_GOP_DST_FRC:
2113 if (gopNum==E_GOP1)
2114 {
2115 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
2116 }
2117 else if (gopNum==E_GOP0)
2118 {
2119 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
2120 }
2121 else if (gopNum==E_GOP2)
2122 {
2123 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
2124 }
2125 else if (gopNum==E_GOP3)
2126 {
2127 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
2128 }
2129 else if (gopNum ==E_GOP4)
2130 {
2131 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
2132 }
2133 else
2134 {
2135 GOP_ASSERT(0);
2136 return GOP_INVALID_PARAMETERS;
2137 }
2138
2139 break;
2140
2141 case E_DRV_GOP_DST_MIXER2VE:
2142 //HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_VECLK, CKG_GOPMIXER_MASK);
2143
2144 if(gopNum == 0)
2145 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
2146 else if(gopNum == 1)
2147 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
2148 else if(gopNum == 2)
2149 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
2150 else if(gopNum == 3)
2151 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
2152 else if(gopNum == 4)
2153 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
2154
2155 break;
2156
2157 case E_DRV_GOP_DST_VE:
2158 if(gopNum == 0)
2159 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
2160 else if(gopNum == 1)
2161 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
2162 else if(gopNum == 2)
2163 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
2164 else if(gopNum == 3)
2165 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
2166 else if(gopNum == 4)
2167 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
2168 break;
2169 case E_DRV_GOP_DST_OP_DUAL_RATE:
2170 {
2171 MS_U8 u8_mainGop=0, u8_combinedGop=0;
2172
2173 Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop);
2174 if (u8_mainGop == E_GOP0)
2175 {
2176 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK);
2177 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK);
2178
2179 // for GOP0+GOP3
2180 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
2181 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
2182 }
2183 else if (u8_mainGop == E_GOP2)
2184 {
2185 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK);
2186 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK);
2187
2188 // for GOP1+GOOP2
2189 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
2190 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
2191 }
2192 else if (u8_mainGop == E_GOP4)
2193 {
2194 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
2195 }
2196 }
2197 break;
2198 default:
2199 GOP_ASSERT(0);
2200 return GOP_ENUM_NOT_SUPPORTED;
2201 }
2202 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
2203 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
2204
2205 return GOP_SUCCESS;
2206 }
2207
2208
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2209 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2210 {
2211 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
2212 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
2213 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
2214 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
2215 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
2216 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
2217 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
2218 else
2219 return GOP_INVALID_PARAMETERS;
2220
2221 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
2222 return GOP_SUCCESS;
2223 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2224 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
2225 {
2226 if (bEnable)
2227 {
2228 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
2229 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
2230 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
2231 }
2232 else
2233 {
2234 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
2235 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
2236 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
2237 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
2238 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
2239 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
2240 }
2241
2242 return GOP_SUCCESS;
2243 }
2244
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)2245 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
2246 {
2247 return GOP_FUN_NOT_SUPPORTED;
2248 }
2249
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)2250 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
2251 {
2252 return GOP_FUN_NOT_SUPPORTED;
2253 }
2254
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2255 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
2256 {
2257 return GOP_FUN_NOT_SUPPORTED;
2258 }
2259
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2260 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2261 {
2262 MS_U32 u32GopIdx;
2263
2264 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2265 pGOPHalLocal->pHALShared = pHALShared;
2266
2267 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2268 {
2269 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2270 }
2271 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
2272 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2273 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2274 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2275 {
2276 }
2277
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2278 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2279 {
2280 MS_U8 u8Miu=0xff;
2281 MS_U8 u8GOP=0;
2282
2283 if (gwinid<MAX_GOP0_GWIN) //gop0
2284 {
2285 u8GOP=0;
2286 }
2287 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
2288 {
2289 u8GOP=1;
2290 }
2291 else if (gwinid==GOP2_GwinIdBase) //gop2
2292 {
2293 u8GOP=2;
2294 }
2295 else if (gwinid==GOP3_GwinIdBase) //gop3
2296 {
2297 u8GOP=3;
2298 }
2299 else if (gwinid==GOP4_GwinIdBase) //gop4
2300 {
2301 u8GOP=4;
2302 }
2303 else
2304 {
2305 return GOP_FAIL;
2306 }
2307
2308 u8Miu = HAL_GOP_GetMIUDst(pGOPHalLocal, u8GOP);
2309
2310 if (u8Miu <= 2)
2311 {
2312 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2313 }
2314 else
2315 {
2316 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
2317 return GOP_FAIL;
2318 }
2319 return GOP_SUCCESS;
2320 }
2321
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2322 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2323 {
2324 MS_U8 u8Miu=0xff;
2325 MS_U16 u16RegVal_L=0;
2326 MS_U32 u32BnkOfst=0xFFFF;
2327 #ifdef GOP_MIU_GROUP2
2328 MS_U16 u16RegVal_H=0;
2329 #endif
2330
2331 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2332 {
2333 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2334 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2335
2336 u8Miu= u16RegVal_L&(GOP_BIT1|GOP_BIT0) ;
2337 }
2338 else
2339 {
2340 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal_L);
2341
2342 #ifdef GOP_MIU_GROUP2
2343 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2344 #endif
2345 switch (gopnum)
2346 {
2347 case 0:
2348 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2349 #ifdef GOP_MIU_GROUP2
2350 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2351 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2352 #else
2353 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2354 #endif
2355 break;
2356 case 1:
2357 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2358 #ifdef GOP_MIU_GROUP2
2359 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2360 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2361 #else
2362 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2363 #endif
2364 break;
2365
2366 case 2:
2367 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2368 #ifdef GOP_MIU_GROUP2
2369 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2370 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2371 #else
2372 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2373 #endif
2374 break;
2375
2376 case 3:
2377 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2378 #ifdef GOP_MIU_GROUP2
2379 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2380 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2381 #else
2382 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2383 #endif
2384 break;
2385 case 4:
2386 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
2387 #ifdef GOP_MIU_GROUP2
2388 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
2389 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
2390 #else
2391 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
2392 #endif
2393 break;
2394 default:
2395 return 0xff;
2396 break;
2397 }
2398
2399 if(u8Miu > MAX_GOP_MIUSEL )
2400 {
2401 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
2402 return 0xff;
2403 }
2404
2405 }
2406 return u8Miu;
2407 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2408 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2409 {
2410 MS_U16 u16Regval;
2411 MS_U32 u32pBankOffSet=0;
2412 GOP_Result ret;
2413
2414 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2415 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2416
2417 switch (u16Regval&GOP_DST_MASK)
2418 {
2419 case 0:
2420 *pGopDst = E_DRV_GOP_DST_IP0;
2421 ret = GOP_SUCCESS;
2422 break;
2423 case 1:
2424 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
2425 ret = GOP_SUCCESS;
2426 break;
2427 case 2:
2428 *pGopDst = E_DRV_GOP_DST_OP0;
2429 ret = GOP_SUCCESS;
2430 break;
2431 case 3:
2432 *pGopDst = E_DRV_GOP_DST_VOP;
2433 ret = GOP_SUCCESS;
2434 break;
2435 case 4:
2436 *pGopDst = E_DRV_GOP_DST_VOP_SUB;
2437 ret = GOP_SUCCESS;
2438 break;
2439 case 6:
2440 *pGopDst = E_DRV_GOP_DST_FRC;
2441 ret = GOP_SUCCESS;
2442 break;
2443 case 0xB:
2444 *pGopDst = E_DRV_GOP_DST_OP_DUAL_RATE;
2445 ret = GOP_SUCCESS;
2446 break;
2447 case 8:
2448 *pGopDst = E_DRV_GOP_DST_DIP;
2449 ret = GOP_SUCCESS;
2450 break;
2451 default:
2452 *pGopDst = E_DRV_GOP_DST_INVALID;
2453 ret = GOP_FAIL;
2454 break;
2455 }
2456
2457 return ret;
2458
2459 }
2460
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2461 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2462 {
2463 MS_U16 muxValue=0;
2464 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2465
2466 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2467
2468 switch(ipSelGop)
2469 {
2470 case MS_DRV_IP0_SEL_GOP0:
2471 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2472 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2473 u16RegVal |= GOP_BIT12;//mux0
2474 else
2475 u16RegVal |= GOP_BIT13;//mux1
2476 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2477 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2478 break;
2479
2480 case MS_DRV_IP0_SEL_GOP1:
2481 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2482 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2483 u16RegVal |= GOP_BIT12;//mux0
2484 else
2485 u16RegVal |= GOP_BIT13;//mux1
2486 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2487 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2488 break;
2489 case MS_DRV_IP0_SEL_GOP2:
2490 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2491 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2492 u16RegVal |= GOP_BIT12;//mux0
2493 else
2494 u16RegVal |= GOP_BIT13;//mux1
2495 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2496 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2497 break;
2498
2499 case MS_DRV_NIP_SEL_GOP0:
2500 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2501 {
2502 u16RegVal = ~GOP_BIT12;//mux0
2503 u16RegMsk = GOP_BIT12;
2504 }
2505 else
2506 {
2507 u16RegVal = ~GOP_BIT13;//mux1
2508 u16RegMsk = GOP_BIT13;
2509 }
2510 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2511 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2512 break;
2513
2514 case MS_DRV_NIP_SEL_GOP1:
2515 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2516 {
2517 u16RegVal = ~GOP_BIT12;//mux0
2518 u16RegMsk = GOP_BIT12;
2519 }
2520 else
2521 {
2522 u16RegVal = ~GOP_BIT13;//mux1
2523 u16RegMsk = GOP_BIT13;
2524 }
2525 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2526 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2527
2528 break;
2529 case MS_DRV_NIP_SEL_GOP2:
2530 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2531 {
2532 u16RegVal = ~GOP_BIT12;//mux0
2533 u16RegMsk = GOP_BIT12;
2534 }
2535 else
2536 {
2537 u16RegVal = ~GOP_BIT13;//mux1
2538 u16RegMsk = GOP_BIT13;
2539 }
2540 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2541 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2542
2543 break;
2544 case MS_DRV_MVOP_SEL:
2545 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2546 u16RegVal |= GOP_BIT12; //mux0
2547 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2548 break;
2549 default:
2550 GOP_H_ERR("[%s] ERROR invalid source select\n",__FUNCTION__);
2551 break;
2552 }
2553 if(0 != u16RegMsk)
2554 {
2555 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2556 }
2557 }
2558
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2559 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2560 {
2561 return GOP_FUN_NOT_SUPPORTED;
2562 }
2563
2564
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2565 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2566 {
2567 return GOP_FUN_NOT_SUPPORTED;
2568 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2569 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2570 {
2571 return GOP_FUN_NOT_SUPPORTED;
2572 }
2573
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2574 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2575 {
2576 return GOP_FUN_NOT_SUPPORTED;
2577 }
2578
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2579 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2580 {
2581 return GOP_FUN_NOT_SUPPORTED;
2582 }
2583
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2584 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2585 {
2586 return GOP_FUN_NOT_SUPPORTED;
2587 }
2588
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2589 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2590 {
2591 return GOP_FUN_NOT_SUPPORTED;
2592 }
2593
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2594 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2595 {
2596 return GOP_FUN_NOT_SUPPORTED;
2597 }
2598
2599
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2600 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2601 {
2602 MS_U32 u32BankOffSet =0;
2603
2604 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2605
2606 if (bEn)
2607 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2608 else
2609 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2610
2611 return GOP_SUCCESS;
2612 }
2613
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2614 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2615 {
2616 MS_U32 u32BankOffSet =0;
2617
2618 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2619
2620 if (bEn)
2621 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2622 else
2623 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2624
2625 return GOP_SUCCESS;
2626 }
2627
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2628 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2629 {
2630 MS_U16 u16Val =0x0;
2631 if (u8win < GOP1_GwinIdBase)
2632 {
2633 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2634 *pEnable = (MS_BOOL)(u16Val>>15);
2635 }
2636 else if (u8win < GOP2_GwinIdBase)
2637 {
2638 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2639 *pEnable = (MS_BOOL)(u16Val>>15);
2640 }
2641 else if (u8win < GOP3_GwinIdBase)
2642 {
2643 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2644 *pEnable = (MS_BOOL)(u16Val>>15);
2645 }
2646 else if (u8win < GOP4_GwinIdBase)
2647 {
2648 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2649 *pEnable = (MS_BOOL)(u16Val>>15);
2650 }
2651 else if (u8win < GOP5_GwinIdBase)
2652 {
2653 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2654 *pEnable = (MS_BOOL)(u16Val>>15);
2655 }
2656 else
2657 {
2658 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2659 return GOP_INVALID_PARAMETERS;
2660 }
2661
2662 return GOP_SUCCESS;
2663 }
2664
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2665 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2666 {
2667 MS_U16 u16Val = bEnable << 15;
2668 if (u8win < GOP1_GwinIdBase)
2669 {
2670 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2671 }
2672 else if (u8win < GOP2_GwinIdBase)
2673 {
2674 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2675 }
2676 else if (u8win < GOP3_GwinIdBase)
2677 {
2678 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2679 }
2680 else if (u8win < GOP4_GwinIdBase)
2681 {
2682 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2683 }
2684 else if (u8win < GOP5_GwinIdBase)
2685 {
2686 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2687 }
2688 else
2689 {
2690 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2691 return GOP_INVALID_PARAMETERS;
2692 }
2693 return GOP_SUCCESS;
2694 }
2695
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2696 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2697 {
2698 MS_U16 u16Reg = 0;
2699 MS_U32 u32WordBase = 0;
2700 MS_U32 u32BankOffSet=0;
2701
2702 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2703
2704 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2705
2706 if(u16Reg & GOP_BIT7)
2707 {
2708 u32WordBase = 1;
2709 }
2710 else
2711 {
2712 u32WordBase = GOP_WordUnit;
2713 }
2714
2715 u32SubAddr /= u32WordBase;
2716
2717 if(u8GOP == E_GOP2)
2718 {
2719 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2720 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2721 }
2722 else if(u8GOP == E_GOP3)
2723 {
2724 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2725 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2726
2727 }
2728 else if(u8GOP == E_GOP4)
2729 {
2730 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2731 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2732 }
2733 else if(u8GOP == E_GOP1)
2734 {
2735 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2736 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2737 }
2738 else //gop0
2739 {
2740 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2741 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2742 }
2743
2744 return GOP_SUCCESS;
2745
2746 }
2747
2748 //------------------------------------------------------------------------------
2749 /// Set VE output with OSD
2750 /// @return none
2751 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2752 GOP_Result HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2753 {
2754 #ifndef MSOS_TYPE_LINUX_KERNEL
2755 MS_U32 u32Reg = GOP_VE_TVS_OSD_EN;
2756 MS_U16 u16Val = BIT(2)|BIT(3);
2757
2758 if( EN_OSD_0 == eOSD)
2759 {
2760 u32Reg = GOP_VE_TVS_OSD_EN;
2761 }
2762 else if( EN_OSD_1 == eOSD)
2763 {
2764 u32Reg = GOP_VE_TVS_OSD1_EN;
2765 }
2766
2767 if(bEnable) // enable OSD
2768 {
2769 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, ~u16Val, u16Val);
2770 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(5), BIT(5));
2771 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(1), BIT(1));
2772 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(0), BIT(0));
2773 }
2774 else // disable OSD
2775 {
2776 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, 0x0, BIT(0));
2777 }
2778 #endif
2779 return GOP_SUCCESS;
2780 }
2781
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2782 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2783 {
2784 MS_U16 regval = 0x0;
2785
2786 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2787 // there are only 2 mux, the 3rd gop will be set to 2nd mux(osd1).
2788 if((gopNum != (regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8)>>6)) && (gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9)))
2789 {
2790 // if have to overwrite one, overwriting INIT VALUE is better.
2791 if (VE_MUX_INIT_VALUE == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2792 {
2793 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6), (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2794 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2795 }
2796 else
2797 {
2798 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2799 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2800 }
2801 }
2802 else if(gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9))
2803 {
2804 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2805 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2806 }
2807 else
2808 {
2809 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6) , (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2810 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2811 }
2812 return GOP_SUCCESS;
2813
2814 }
2815
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2816 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2817 {
2818 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2819 MS_U16 u16MVOPMirrorCfg = 0;
2820 MS_U16 u16ScalerMirrorCfg = 0;
2821
2822 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2823 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2824 if(bHorizontal) // Horizontal
2825 {
2826 if(u16MVOPMirrorCfg & GOP_BIT1)
2827 {
2828 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2829 }
2830 else if(u16ScalerMirrorCfg & GOP_BIT12)
2831 {
2832 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2833 }
2834 }
2835 else //vertical
2836 {
2837 if(u16MVOPMirrorCfg & GOP_BIT0)
2838 {
2839 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2840 }
2841 else if(u16ScalerMirrorCfg & GOP_BIT13)
2842 {
2843 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2844 }
2845 }
2846 return enMirrorType;
2847 }
2848
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2849 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2850 {
2851 MS_U32 u32BankOffSet =0;
2852
2853 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2854 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2855 return GOP_SUCCESS;
2856 }
2857
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2858 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2859 {
2860 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2861 MS_U16 u16Val=0;
2862 MS_U16 u16Mux[MAX_GOP_MUX];
2863
2864 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2865 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2866 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2867 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2868 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2869 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2870
2871 switch(u8GOP)
2872 {
2873 case E_GOP0:
2874 case E_GOP1:
2875 case E_GOP2:
2876 case E_GOP3:
2877 case E_GOP4:
2878 for(i=0; i<MAX_GOP_MUX; i++)
2879 {
2880 if(u8GOP == u16Mux[i])
2881 {
2882 eGopMux = i;
2883 if(eGopMux == 4)
2884 {
2885 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2886 }
2887 else
2888 {
2889 FRCMuxOffset = 12 + eGopMux;
2890 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2891 }
2892 }
2893 }
2894 break;
2895 default:
2896 return GOP_FAIL;
2897 break;
2898 }
2899
2900 return GOP_SUCCESS;
2901 }
2902
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2903 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2904 {
2905 return GOP_FUN_NOT_SUPPORTED;
2906 }
2907
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2908 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2909 {
2910 return GOP_FUN_NOT_SUPPORTED;
2911 }
2912
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2913 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2914 {
2915 return GOP_FUN_NOT_SUPPORTED;
2916 }
2917
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2918 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2919 {
2920 return GOP_FUN_NOT_SUPPORTED;
2921 }
2922
2923 /********************************************************************************/
2924 ///Test Pattern
2925 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)2926 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
2927 {
2928 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
2929 {
2930 return GOP_SUCCESS;
2931 }
2932 else
2933 {
2934 return GOP_FAIL;
2935 }
2936
2937 }
2938
2939
2940 /********************************************************************************/
2941 ///GOP Scaling down (internal)
2942 /********************************************************************************/
2943
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2944 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
2945 {
2946 MS_U16 u16MG_mask=0;
2947 MS_U16 u16Val=0;
2948 MS_U16 u16LB_mask=0;
2949 MS_U16 u16enable=0;
2950
2951 if(u8GOP==0)
2952 {
2953 u16MG_mask=CKG_GOPG0_MG_MASK;
2954 u16Val=GOP_BIT2;
2955 u16LB_mask=CKG_LB_SRAM1_MASK;
2956 u16enable=GOP_BIT2;
2957 }
2958 else if(u8GOP==2)
2959 {
2960 u16MG_mask=CKG_GOPG2_MG_MASK;
2961 u16Val=GOP_BIT6;
2962 u16LB_mask=CKG_LB_SRAM2_MASK;
2963 u16enable=GOP_BIT6;
2964 }
2965 else
2966 {
2967 GOP_H_ERR("[%s] Error message GOP not support scaling down!!",__FUNCTION__);
2968 return GOP_FAIL;
2969 }
2970 if(bEn==TRUE)
2971 {
2972 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, u16Val, u16MG_mask);
2973 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, u16enable, u16LB_mask);
2974 }
2975 else
2976 {
2977 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, u16MG_mask);
2978 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, u16LB_mask);
2979 }
2980 return TRUE;
2981 }
2982
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2983 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2984 {
2985 MS_U32 ratio;
2986 MS_U32 u32BankOffSet=0xFFFF;
2987 MS_U16 u16VScalReg;
2988
2989 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2990 if(bEnable ==TRUE)
2991 {
2992 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, &u16VScalReg);
2993 if( u16VScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2994 {
2995 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2996 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2997 }
2998 //Set scaling down ratio
2999 ratio = (dst * 0x100000) / src;
3000 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, ratio);
3001 }
3002 else
3003 {
3004 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, 0);
3005 }
3006
3007 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3008 {
3009 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3010 }
3011 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, bEnable , GOP_BIT0);
3012 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_H_OUTPUTSIZE, dst, GOP_REG_WORD_MASK);
3013
3014 return GOP_SUCCESS;
3015
3016 }
3017
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3018 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3019 {
3020 MS_U32 ratio =0;
3021 MS_U32 u32BankOffSet=0xFFFF;
3022 MS_U16 u16HScalReg;
3023
3024 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3025 if(bEnable ==TRUE)
3026 {
3027 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, &u16HScalReg);
3028 if( u16HScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
3029 {
3030 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, 0x1000 , GOP_REG_WORD_MASK);
3031 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
3032 }
3033 ratio = (dst * 0x100000) / src;
3034 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, ratio);
3035 }
3036 else
3037 {
3038 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, 0);
3039 }
3040
3041 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3042 {
3043 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3044 }
3045 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, (bEnable<<4) , GOP_BIT4);
3046 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SVM_VEND, dst, GOP_REG_WORD_MASK);
3047
3048 return GOP_SUCCESS;
3049
3050 }
3051
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)3052 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
3053 {
3054 MS_U32 u32BankOffSet=0;
3055
3056 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3057 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
3058 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
3059 return GOP_SUCCESS;
3060 }
3061
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)3062 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
3063 {
3064 MS_U32 u32BankOffSet=0;
3065 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3066
3067 if (u32GopIdx < MAX_GOP_SUPPORT)
3068 {
3069 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
3070 }
3071 else
3072 {
3073 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3074 *u16Val = 0;
3075 }
3076 return GOP_SUCCESS;
3077 }
3078
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)3079 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
3080 {
3081 MS_U32 u32BankOffSet=0;
3082 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3083
3084 if (u32GopIdx < MAX_GOP_SUPPORT)
3085 {
3086 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
3087 }
3088 else
3089 {
3090 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3091 }
3092 return GOP_SUCCESS;
3093 }
3094
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)3095 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
3096 {
3097 switch(u32PowerState)
3098 {
3099 case E_POWER_SUSPEND:
3100 {
3101 //CLK
3102 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
3103 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
3104 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
3105 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
3106 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
3107 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
3108
3109 //SRAM
3110 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
3111 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
3112 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
3113
3114 //XC
3115 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
3116 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
3117 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
3118 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
3119 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
3120 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
3121 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
3122 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
3123 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
3124 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
3125 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
3126 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
3127 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
3128 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[13]));
3129 }
3130 break;
3131 case E_POWER_RESUME:
3132 {
3133 //CLK
3134 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
3135 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
3136 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
3137 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
3138 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
3139 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
3140
3141 //SRAM
3142 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
3143 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
3144 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
3145
3146 //XC
3147 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3148 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3149 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3150 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3151 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3152 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3153 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3154 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3155 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3156 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3157 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3158 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3159 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3160 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[13], GOP_BIT11);
3161 }
3162 break;
3163 default:
3164 break;
3165 }
3166 return GOP_SUCCESS;
3167 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3168 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3169 {
3170 return GOP_FUN_NOT_SUPPORTED;
3171 }
3172
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3173 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3174 {
3175 MS_U32 u32BankOffSet=0xFFFF;
3176
3177 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3178 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3179 return GOP_SUCCESS;
3180 }
3181
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3182 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3183 {
3184 MS_U32 u32BankOffSet=0xFFFF;
3185 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3186 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3187 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3188
3189 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3190 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3191 return GOP_SUCCESS;
3192 }
3193
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3194 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3195 {
3196 MS_U32 u32BankOffSet=0xFFFF;
3197 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3198
3199 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3200 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3201
3202 return GOP_SUCCESS;
3203 }
3204
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3205 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3206 {
3207 MS_U32 u32BankOffSet=0xFFFF;
3208 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3209
3210 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
3211 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
3212 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
3213
3214 return GOP_SUCCESS;
3215 }
3216
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3217 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3218 {
3219 MS_U32 u32BankOffSet=0xFFFF;
3220 MS_U16 mask_shift=0xFF;
3221 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
3222 MS_U32 u32CombineBankOffSet=0xFFFF;
3223
3224 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3225
3226
3227 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP]==TRUE)
3228 {
3229 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, (GOP_BIT0|GOP_BIT1));//GWIN Palette MIU Select
3230 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, (GOP_BIT2|GOP_BIT3));//GWIN MIU Select
3231 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, (GOP_BIT4|GOP_BIT5));//GWIN_3D MIU Select
3232 }
3233 else
3234 {
3235 switch(u8GOP)
3236 {
3237 case E_GOP0:
3238 mask_shift = GOP_MIU_CLIENT_GOP0;
3239 break;
3240 case E_GOP1:
3241 mask_shift = GOP_MIU_CLIENT_GOP1;
3242 break;
3243 case E_GOP2:
3244 mask_shift = GOP_MIU_CLIENT_GOP2;
3245 break;
3246 case E_GOP3:
3247 mask_shift = GOP_MIU_CLIENT_GOP3;
3248 break;
3249 case E_GOP4:
3250 mask_shift = GOP_MIU_CLIENT_GOP4;
3251 break;
3252 case E_GOP_Dwin:
3253 mask_shift = GOP_MIU_CLIENT_DWIN;
3254 break;
3255 default:
3256 mask_shift = 0xFF;
3257 MS_CRITICAL_MSG(GOP_H_DBUG("ERROR gop miu client\n"));
3258 break;
3259 }
3260
3261 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3262 #ifdef GOP_MIU_GROUP2
3263 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3264 #endif
3265
3266 }
3267
3268 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop) )
3269 {
3270 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3271 return GOP_FAIL;
3272 }
3273 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
3274 {
3275 if(u8GOP != u8_mainGop)
3276 u8GOP = u8_mainGop;
3277 else
3278 u8GOP = u8_combinedGop;
3279 _GetBnkOfstByGop(u8GOP, &u32CombineBankOffSet);
3280
3281 switch(u8GOP)
3282 {
3283 case E_GOP0:
3284 mask_shift = GOP_MIU_CLIENT_GOP0;
3285 break;
3286 case E_GOP1:
3287 mask_shift = GOP_MIU_CLIENT_GOP1;
3288 break;
3289 case E_GOP2:
3290 mask_shift = GOP_MIU_CLIENT_GOP2;
3291 break;
3292 case E_GOP3:
3293 mask_shift = GOP_MIU_CLIENT_GOP3;
3294 break;
3295 case E_GOP4:
3296 mask_shift = GOP_MIU_CLIENT_GOP4;
3297 break;
3298 case E_GOP_Dwin:
3299 mask_shift = GOP_MIU_CLIENT_DWIN;
3300 break;
3301 default:
3302 mask_shift = 0xFF;
3303 MS_CRITICAL_MSG(GOP_H_DBUG("ERROR gop miu client\n"));
3304 break;
3305 }
3306
3307 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP]==TRUE)
3308 {
3309 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Set Control MIU select by GOP itself
3310 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
3311 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
3312 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
3313 }
3314 else
3315 {
3316
3317 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3318 #ifdef GOP_MIU_GROUP2
3319 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3320 #endif
3321
3322 }
3323
3324 }
3325
3326
3327 return GOP_SUCCESS;
3328 }
3329
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)3330 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
3331 {
3332 MS_U16 reg_val = 0;
3333
3334 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_INTERLACE, ®_val);
3335 if(reg_val & BIT(11))
3336 *bInterlace = TRUE;
3337 else
3338 *bInterlace = FALSE;
3339 return GOP_SUCCESS;
3340 }
3341
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)3342 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
3343 {
3344 *pbHDREnable= FALSE;
3345 return GOP_FUN_NOT_SUPPORTED;
3346 }
3347
Hal_get4K120CombinedGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * main_gop,MS_U8 * sub_gop)3348 static MS_BOOL Hal_get4K120CombinedGOP(
3349 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3350 MS_U8 u8GOP,
3351 MS_U8 * main_gop,
3352 MS_U8 * sub_gop)
3353 {
3354 if ((NULL == main_gop) || (NULL == sub_gop))
3355 {
3356 return FALSE;
3357 }
3358
3359 if (u8GOP >= MAX_GOP_SUPPORT)
3360 {
3361 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOP);
3362 return FALSE;
3363 }
3364
3365 *main_gop = gop_4k120_pairs[u8GOP].mainGop;
3366 *sub_gop = gop_4k120_pairs[u8GOP].subGop;
3367
3368 return TRUE;
3369 }
3370
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3371 GOP_Result Hal_SetCropWindow(
3372 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3373 MS_U8 u8GOP,
3374 EN_GOP_CROP_CTL crop_mode
3375 )
3376 {
3377 MS_U32 u32MainBankOffSet=0xFFFF;
3378 MS_U32 u32CombineBankOffSet=0xFFFF;
3379 MS_U8 u8_mainGop, u8_combinedGop;
3380 MS_U16 crop_hstart;
3381 MS_U16 crop_hend;
3382 MS_U16 crop_vstart;
3383 MS_U16 crop_vend;
3384 MS_U16 gop_stretch_width = 0x0;
3385 MS_U16 gop_stretch_height = 0x0;
3386 MS_U16 u16Gop_stretch_vstart = 0x0;
3387 MS_U16 u16HScalingRatio = 0x0;
3388 MS_U16 u16VScalingRatio = 0x0;
3389
3390 if (FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop))
3391 {
3392 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3393 return GOP_INVALID_PARAMETERS;
3394 }
3395
3396 if (u8GOP != u8_mainGop)
3397 {
3398 return GOP_ENUM_NOT_SUPPORTED;
3399 }
3400
3401 if (E_GOP4 == u8_mainGop)
3402 {
3403 // no crop for GOP4
3404 return GOP_ENUM_NOT_SUPPORTED;
3405 }
3406
3407 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
3408 _GetBnkOfstByGop(u8_combinedGop, &u32CombineBankOffSet);
3409
3410 if (EN_GOP_CROP_DISABLE == crop_mode)
3411 {
3412 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT4);
3413 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT4);
3414 }
3415 else
3416 {
3417 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT5); // use precal mode
3418
3419 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_HSZ, &gop_stretch_width);
3420 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_VSZ, &gop_stretch_height);
3421 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_VSTR, &u16Gop_stretch_vstart);
3422 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_HSTRCH, &u16HScalingRatio);
3423 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_VSTRCH, &u16VScalingRatio);
3424
3425 // crop left part
3426 crop_hstart = 0x0;
3427 crop_hend = (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] != 0) ?
3428 ((pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] >> 1) - 1) : 0x77F;
3429 crop_vstart = 0x0;
3430 crop_vend = (u16VScalingRatio != 0) ? ((SCALING_MULITPLIER * (MS_U32)gop_stretch_height) / u16VScalingRatio + u16Gop_stretch_vstart) : 0x870;
3431 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_HSTART, crop_hstart, GOP_REG_WORD_MASK);
3432 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_HEND, crop_hend, GOP_REG_WORD_MASK);
3433 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_VSTART, crop_vstart, GOP_REG_WORD_MASK);
3434 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_VEND, crop_vend, GOP_REG_WORD_MASK);
3435
3436 // crop right part
3437 crop_hstart = (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] != 0) ?
3438 (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] >> 1): 0x780;
3439 crop_hend = (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] != 0) ?
3440 (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] - 1): 0xeff;
3441 crop_vstart = 0x0;
3442 crop_vend = (u16VScalingRatio != 0) ? ((SCALING_MULITPLIER * (MS_U32)gop_stretch_height) / u16VScalingRatio + u16Gop_stretch_vstart) : 0x870;
3443 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_HSTART, crop_hstart, GOP_REG_WORD_MASK);
3444 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_HEND, crop_hend, GOP_REG_WORD_MASK);
3445 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_VSTART, crop_vstart, GOP_REG_WORD_MASK);
3446 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_VEND, crop_vend, GOP_REG_WORD_MASK);
3447
3448 #if ENABLE_MANUAL_CROP==1
3449 MS_U16 u16ManualCropHstart = 0x0, u16ManualCropHend = 0x0;
3450
3451 u16ManualCropHstart = 0x0;
3452 u16ManualCropHend = gop_stretch_width - 1;
3453 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHSTART(u8_mainGop), u16ManualCropHstart, GOP_REG_WORD_MASK);
3454 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHEND(u8_mainGop), u16ManualCropHend, GOP_REG_WORD_MASK);
3455
3456 u16ManualCropHstart = gop_stretch_width - 2;
3457 u16ManualCropHend = (gop_stretch_width<<1) - 1;
3458 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHSTART(u8_combinedGop), u16ManualCropHstart, GOP_REG_WORD_MASK);
3459 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHEND(u8_combinedGop), u16ManualCropHend, GOP_REG_WORD_MASK);
3460
3461 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_PRECALDONE(u8_mainGop), GOP_BIT0, GOP_BIT0);
3462 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_PRECALDONE(u8_combinedGop), GOP_BIT0, GOP_BIT0);
3463
3464 // if afbc enable, use manual crop mode
3465 MS_U8 u8afbc_core_number = 0x0;
3466 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8_mainGop, &u8afbc_core_number);
3467 if (_isAfbcFunctionEnabled(pGOPHalLocal, u8afbc_core_number))
3468 {
3469 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MANUAL_CROP1, GOP_BIT4 | GOP_BIT5, GOP_BIT4 | GOP_BIT5);
3470 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4 | GOP_BIT5, GOP_BIT4 | GOP_BIT5);
3471 }
3472 #endif
3473
3474 // crop enable
3475 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4, GOP_BIT4);
3476 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4, GOP_BIT4);
3477 }
3478
3479 return GOP_SUCCESS;
3480 }
3481
Hal_Ctrl4K120GopMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3482 static GOP_Result Hal_Ctrl4K120GopMode(
3483 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3484 MS_U8 u8GOP,
3485 MS_BOOL bEnable
3486 )
3487 {
3488 MS_U32 u32MainBankOffSet=0xFFFF;
3489 MS_U32 u32SubBankOffSet=0xFFFF;
3490 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
3491 MS_U8 miuClient4MainGop = 0, miuClient4SubGop = 0;
3492
3493 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop) )
3494 {
3495 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3496 return GOP_FAIL;
3497 }
3498
3499 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
3500 _GetBnkOfstByGop(u8_combinedGop, &u32SubBankOffSet);
3501
3502 // enable GOP to 4K120 mode
3503 if ((E_GOP0 == u8_mainGop) || (E_GOP2 == u8_mainGop))
3504 {
3505 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MIU_SEL, (TRUE == bEnable) ? GOP_BIT8 : ~GOP_BIT8, GOP_BIT8);
3506 }
3507
3508 if (E_GOP3 == u8_combinedGop)
3509 {
3510 if (TRUE == bEnable)
3511 {
3512 // set GOP3 v-stretch method to duplicate mode
3513 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet + GOP_4G_YUV_SWAP, 0, GOP_BIT9);
3514 }
3515 else if (FALSE == bEnable)
3516 {
3517 // restore GOP3 v-stretch method to duplicate mode
3518 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet + GOP_4G_YUV_SWAP, GOP_BIT9, GOP_BIT9);
3519 }
3520 }
3521
3522 if ((E_GOP0 == u8_mainGop) || (E_GOP2 == u8_mainGop))
3523 {
3524 // crop trigger & GOP trigger tie together
3525 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BOT_HS, GOP_BIT12, GOP_BIT12);
3526 }
3527
3528 if ((bEnable == TRUE) && (E_GOP1 == u8_combinedGop))
3529 {
3530 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet+GOP_4G_CTRL1, 0x4100, GOP_REG_HW_MASK);
3531 }
3532
3533 #ifdef GOP_SUPPORT_SPLIT_MODE
3534 if (E_GOP4 == u8_mainGop)
3535 {
3536 if ((bEnable == TRUE))
3537 {
3538 MS_U16 gwin_width, gwin_height;
3539 MS_U16 gwin_hstart, gwin_hend;
3540 MS_U16 gwin_vstart, gwin_vend;
3541
3542 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_HSTR, &gwin_hstart);
3543 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_HEND, &gwin_hend);
3544 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_VSTR, &gwin_vstart);
3545 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_VEND, &gwin_vend);
3546
3547 gwin_width = (gwin_hend > gwin_hstart) ? gwin_hend - gwin_hstart : 0;
3548 gwin_height = (gwin_vend > gwin_vstart) ? gwin_vend - gwin_vstart : 0;
3549
3550 // change the mouse moving method to split shift mode
3551 // 1. gwin size must smaller than 512 * 256
3552 if (gwin_width > GOP4_SPLITMODE_MAX_HSIZE)
3553 {
3554 gwin_hstart = 0;
3555 gwin_hend = GOP4_SPLITMODE_MAX_HSIZE;
3556 gwin_width = GOP4_SPLITMODE_MAX_HSIZE;
3557
3558 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3559 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3560 }
3561 if (gwin_height > GOP4_SPLITMODE_MAX_VSIZE)
3562 {
3563 gwin_vstart = 0;
3564 gwin_vend = GOP4_SPLITMODE_MAX_VSIZE;
3565 gwin_height = GOP4_SPLITMODE_MAX_VSIZE;
3566
3567 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3568 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3569 }
3570
3571 // 2. move to gwin hstart = 0 because pipe shift tie with GWIN position.
3572 gwin_hend -= gwin_hstart;
3573 gwin_hstart = 0;
3574 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3575 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3576
3577 // 2. sync GOP4 stretch window & gwin size
3578 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_HSZ, GOP_SPLIT_SUPPORT_MAXW/GOP_STRETCH_WIDTH_UNIT, GOP_REG_WORD_MASK);
3579
3580 // 3. garband = 0
3581 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_SLPIT_GUARDBAND, 0, GOP_REG_WORD_MASK);
3582
3583 // 4. each L/R size of OP, unit: 2pix (when 2p engine), reg_op_hsize = target timing / 2
3584 // but 4k@120 always on 2P mode
3585 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_SPLIT_LRSZ, (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8GOP] >> 1), GOP_REG_WORD_MASK);
3586
3587 // 5. enable split mode
3588 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MULTI_ALPHA, GOP_BIT15, GOP_BIT15);
3589 }
3590 else
3591 {
3592 // 5. disable split mode
3593 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MULTI_ALPHA, 0x0, GOP_BIT15);
3594 }
3595 }
3596
3597 #endif
3598
3599 if (TRUE == bEnable)
3600 {
3601 // if on 4K@120 mode, we need to sync the MIU client
3602 miuClient4MainGop = HAL_GOP_GetMIUDst(pGOPHalLocal, u8_mainGop);
3603 miuClient4SubGop = HAL_GOP_GetMIUDst(pGOPHalLocal, u8_combinedGop);
3604 if (miuClient4MainGop != miuClient4SubGop)
3605 {
3606 HAL_GOP_Set_MIU(pGOPHalLocal, u8_combinedGop, miuClient4MainGop);
3607 }
3608 }
3609
3610 return GOP_SUCCESS;
3611 }
3612
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3613 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3614 {
3615 GOP_Result ret = GOP_SUCCESS;
3616
3617 switch(u8GOP)
3618 {
3619 case E_GOP0:
3620 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3621 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3622 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VSTR(u8win), vstart, GOP_REG_WORD_MASK);
3623 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VEND(u8win), vend, GOP_REG_WORD_MASK);
3624 break;
3625
3626 case E_GOP1:
3627 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3628 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3629 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VSTR(u8win), vstart, GOP_REG_WORD_MASK); // 1 pixel
3630 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VEND(u8win), vend, GOP_REG_WORD_MASK); // 1 pixel
3631 break;
3632
3633 case E_GOP2:
3634 case E_GOP3:
3635 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HSTR:GOP_1GX_HSTR, hstart, GOP_REG_WORD_MASK); // word pixels
3636 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HEND:GOP_1GX_HEND, hend, GOP_REG_WORD_MASK); // word pixels
3637 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VSTR:GOP_1GX_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3638 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VEND:GOP_1GX_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3639 break;
3640
3641 case E_GOP4:
3642 if (pGOPHalLocal->pHALShared->GOP_Dst[u8GOP] == E_DRV_GOP_DST_OP_DUAL_RATE)
3643 {
3644 MS_U32 u32BankOffSet;
3645 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3646
3647 // read the gwin hstart+hend might be a bad method
3648 // using varaiable directly
3649 MS_U16 win_hsz = (hend > hstart) ? hend - hstart : 0;
3650 MS_U16 win_vsz = (vend > vstart) ? vend - vstart : 0;
3651 MS_U16 gwin_hstart, gwin_hend;
3652 MS_U16 gwin_hsz;
3653 MS_U16 u16GopHScaleRatio;
3654
3655 if ((win_hsz > GOP4_SPLITMODE_MAX_HSIZE) || (win_vsz > GOP4_SPLITMODE_MAX_VSIZE))
3656 {
3657 // not support bigger than GOP4_SPLITMODE_MAX_HSIZE
3658 GOP_H_DBUG("cursor not support bigger than size : (%d, %d), set value : (%d, %d) \n", GOP4_SPLITMODE_MAX_HSIZE, GOP4_SPLITMODE_MAX_VSIZE, win_hsz, win_vsz);
3659 break;
3660 }
3661
3662 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_HSTR, &gwin_hstart);
3663 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_HSTR, &gwin_hend);
3664 gwin_hsz = (gwin_hend > gwin_hstart) ? gwin_hend - gwin_hstart : 0;
3665
3666 if (win_hsz != gwin_hsz) // gwin size changed
3667 {
3668 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, 0, GOP_REG_WORD_MASK);
3669 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, win_hsz, GOP_REG_WORD_MASK);
3670 }
3671
3672 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_HSTRCH, &u16GopHScaleRatio);
3673 hstart = (MS_U16)(((MS_U32)hstart * SCALING_MULITPLIER) / u16GopHScaleRatio);
3674 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_SLPIT_SHIFT_PIPE, hstart, GOP_REG_WORD_MASK);
3675
3676 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3677 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3678 }
3679 else
3680 {
3681 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, hstart, GOP_REG_WORD_MASK);
3682 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, hend, GOP_REG_WORD_MASK);
3683 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3684 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3685 }
3686 break;
3687
3688 default:
3689 GOP_H_DBUG("invalid Gwin number:%d\n",u8win);
3690 break;
3691 }
3692
3693 return ret;
3694 }
3695
_findMuxNumberByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType dst_type,MS_U8 u8Gop)3696 static MS_U16 _findMuxNumberByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType dst_type, MS_U8 u8Gop)
3697 {
3698 MS_U16 ret_mux = INVALID_GOP_MUX_VAL;
3699
3700 if (E_DRV_GOP_DST_OP_DUAL_RATE == dst_type)
3701 {
3702 MS_U16 finding_mux_value = 0xFFFF;
3703 MS_U16 muxValue;
3704
3705 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_4K120, &muxValue);
3706
3707 if (E_GOP0 == u8Gop)
3708 {
3709 finding_mux_value = GOP_4K120MUX_MUX0;
3710 }
3711 else if (E_GOP2 == u8Gop)
3712 {
3713 finding_mux_value = GOP_4K120MUX_MUX1;
3714 }
3715 else if (E_GOP4 == u8Gop)
3716 {
3717 finding_mux_value = GOP_4K120MUX_MUX2;
3718 }
3719
3720 if (finding_mux_value == ((muxValue & GOP_4K120_MUX0_MASK) >> (GOP_4K120_MUX_SHIFT*0)))
3721 {
3722 ret_mux = GOP_4K120MUX_MUX0;
3723 }
3724 else if (finding_mux_value == ((muxValue & GOP_4K120_MUX1_MASK) >> (GOP_4K120_MUX_SHIFT*1)))
3725 {
3726 ret_mux = GOP_4K120MUX_MUX1;
3727 }
3728 else if (finding_mux_value == ((muxValue & GOP_4K120_MUX2_MASK) >> (GOP_4K120_MUX_SHIFT*2)))
3729 {
3730 ret_mux = GOP_4K120MUX_MUX2;
3731 }
3732 }
3733
3734 return ret_mux;
3735 }
3736
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3737 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3738 {
3739 if(u8GOP==0)
3740 {
3741 *u8Core=0;
3742 }
3743 else
3744 {
3745 *u8Core=1;
3746 }
3747 return GOP_SUCCESS;
3748 }
3749
3750 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3751 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3752 {
3753 MS_U16 u16xcSubbank=0;
3754 MS_U32 bank;
3755 MS_U32 direct_addr;
3756
3757 switch (u32addr & 0xFF00)
3758 {
3759 case GOP_REG_BASE:
3760 {
3761 bank = (u32addr & 0xFF0000) >> 8;
3762
3763 if(bank==0xE00)//GOP4: 0x121B00
3764 {
3765 bank=GOP_REG_GOP4_BK_OFFSET;
3766 }
3767 else if(bank==0xF00)//GWIN4: 0x121E00
3768 {
3769 bank=GOP_REG_GOP4_GW_OFFSET;
3770 }
3771 else if(bank==0x1000) //GOP4_ST
3772 {
3773 bank=GOP_REG_GOP4_ST_OFFSET;
3774 }
3775
3776 if(bank==0x3100)//AFBC
3777 {
3778 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3779 }
3780 else
3781 {
3782 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3783 }
3784 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3785 cmdq_struct[(*number)].destionation_value = u16val;
3786 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3787 cmdq_struct[(*number)].operation = 0x57;
3788 (*number)++;
3789 break;
3790 }
3791 case SC1_REG_BASE:
3792 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3793 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3794
3795 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3796 cmdq_struct[(*number)].destionation_value = u16val;
3797 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3798 cmdq_struct[(*number)].operation = 0x57;
3799 (*number)++;
3800 break;
3801 case GE_REG_BASE:
3802 case CKG_REG_BASE:
3803 case MIU_REG_BASE:
3804 {
3805 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3806 cmdq_struct[(*number)].destionation_value = u16val;
3807 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3808 cmdq_struct[(*number)].operation = 0x57;
3809 (*number)++;
3810 break;
3811 }
3812 #ifdef GOP_MIU_GROUP2
3813 case (MIU2_REG_BASE & 0xFF00):
3814 {
3815 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3816
3817 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3818 cmdq_struct[(*number)].destionation_value = u16val;
3819 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3820 cmdq_struct[(*number)].operation = 0x57;
3821 (*number)++;
3822 break;
3823 }
3824 #endif
3825 default:
3826 {
3827 //Gop lib current do not support this HW ip base
3828 GOP_ASSERT(0);
3829 break;
3830 }
3831
3832 }
3833 return GOP_SUCCESS;
3834 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3835 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3836 {
3837 MS_U32 u32BankOffSet;
3838 MS_U16 u16RegVal1 = 0;
3839 MS_BOOL bCheckValidGop = FALSE;
3840 MS_U8 u8CheckTimeCnt = 0;
3841 MS_U8 u8CurrentCmdGop = 0;
3842
3843 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3844 {
3845 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3846 {
3847 u8CurrentCmdGop = 0;
3848 }
3849 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3850 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3851 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3852 {
3853 bCheckValidGop = FALSE;
3854 }
3855 else
3856 {
3857 bCheckValidGop = TRUE;
3858 break;
3859 }
3860
3861 // if current gop not init, use next gop instead, check order 0->2->1->3
3862 switch (u8CurrentCmdGop)
3863 {
3864 case 0:
3865 u8CurrentCmdGop = 2;
3866 break;
3867 case 1:
3868 u8CurrentCmdGop = 0;
3869 break;
3870 case 2:
3871 u8CurrentCmdGop = 3;
3872 break;
3873 case 3:
3874 u8CurrentCmdGop = 1;
3875 break;
3876 default:
3877 u8CurrentCmdGop = 0;
3878 break;
3879 }
3880 u8CheckTimeCnt++;
3881 }
3882 if (!bCheckValidGop)
3883 {
3884 GOP_H_DBUG("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3885 }
3886
3887 *u32GopIdx = u8CurrentCmdGop;
3888 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3889 (*number)++;
3890 return GOP_SUCCESS;
3891 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3892 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3893 {
3894 CH_Struct ch_fire;
3895 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3896 MS_U16 u16ret = 0,u16ret1 = 0;
3897 int i = 0;
3898
3899
3900 _GetBnkOfstByGop(0, &u32BankOffSet);
3901 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3902 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3903 #if 0 //for Debug
3904 for(i=0;i<(*number);i++)
3905 {
3906 GOP_H_INFO("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3907 }
3908 #endif
3909 ch_fire.Command_Number = *number;
3910 ch_fire.Pointer_To_CAFArray = target;
3911 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3912 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3913 {
3914 Receive_Return_Value = 0;
3915 MDrv_CMDQ_Printf_Crash_Command();
3916 }
3917
3918 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3919 MsOS_DelayTask(1);
3920 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3921 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3922
3923 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3924 timer1 = MsOS_GetSystemTime();
3925 timer2 = MsOS_GetSystemTime();
3926 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3927 {
3928 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3929 MsOS_DelayTask(1);
3930 timer2 = MsOS_GetSystemTime();
3931 }
3932 if(u16ret1 != (u16ret+1))
3933 {
3934 GOP_H_DBUG("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3935 MDrv_CMDQ_Printf_Crash_Command();
3936 }
3937 return GOP_SUCCESS;
3938 }
3939
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3940 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3941 {
3942 CAF_Struct fire_struct[24];
3943 MS_U32 u32BankOffSet;
3944 MS_U32 number = 0;
3945 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3946 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3947 MS_U32 fireGOP=0;
3948
3949 _GetBnkOfstByGop(gop, &u32BankOffSet);
3950
3951 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3952 #ifdef GOP_MIU_GROUP2
3953 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3954 #endif
3955 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3956 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3957
3958 switch(gop)
3959 {
3960 case E_GOP0:
3961 {
3962 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3963 break;
3964 }
3965 case E_GOP1:
3966 {
3967 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3968 break;
3969 }
3970 case E_GOP2:
3971 {
3972 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3973 break;
3974 }
3975 case E_GOP3:
3976 {
3977 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3978 break;
3979 }
3980 case E_GOP4:
3981 {
3982 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3983 break;
3984 }
3985 default:
3986 {
3987 GOP_ASSERT(0);
3988 break;
3989 }
3990 }
3991 if(bMIUSelect[gop] == TRUE)
3992 {
3993 if(u16MIUSelect[gop] == 0)
3994 {
3995 u16RegVal1 &= ~(1<<u16MiuClient);
3996 u16RegVal3 &= ~(1<<u16MiuClient);
3997 }
3998 else if(u16MIUSelect[gop] == 1)
3999 {
4000 u16RegVal1 |= (1<<u16MiuClient);
4001 u16RegVal3 &= ~(1<<u16MiuClient);
4002 }
4003 else if(u16MIUSelect[gop] == 2)
4004 {
4005 u16RegVal1 &= ~(1<<u16MiuClient);
4006 u16RegVal3 |= (1<<u16MiuClient);
4007 }
4008 else if(u16MIUSelect[gop] == 3)
4009 {
4010 u16RegVal1 |= (1<<u16MiuClient);
4011 u16RegVal3 |= (1<<u16MiuClient);
4012 }
4013 bMIUSelect[gop] = FALSE;
4014 }
4015
4016 if(bAFBCMIUSelect[gop] == TRUE)
4017 {
4018 bAFBCMIUSelect[gop] = FALSE;
4019 }
4020 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4021 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4022 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
4023
4024 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
4025 {
4026 if(bAFBCMIUSelect[gop] == TRUE)
4027 {
4028 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
4029 bAFBCMIUSelect[gop] = FALSE;
4030 }
4031 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
4032 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
4033 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
4034 }
4035 #ifdef GOP_MIU_GROUP2
4036 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
4037 #endif
4038
4039 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
4040 return GOP_SUCCESS;
4041 }
4042
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)4043 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
4044 {
4045 CAF_Struct fire_struct[24];
4046 MS_U32 u32BankOffSet=0;
4047 MS_U32 number = 0;
4048 MS_U8 gop=0;
4049 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
4050 MS_U16 u16RegMiu=0,u16RegCoreEna=0;
4051 MS_U32 fireGOP=0;
4052 MS_U16 bMiuChanged = FALSE;
4053 MS_U32 u32MainBankOffSet=0xFFFF;
4054 MS_U32 u32SubBankOffSet=0xFFFF;
4055 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
4056 MS_U8 miuClient4MainGop = 0, miuClient4SubGop = 0;
4057
4058 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
4059 #ifdef GOP_MIU_GROUP2
4060 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
4061 #endif
4062 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
4063
4064 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
4065 {
4066 switch(gop)
4067 {
4068 case E_GOP0:
4069 {
4070 u16MiuClient = GOP_MIU_CLIENT_GOP0;
4071 break;
4072 }
4073 case E_GOP1:
4074 {
4075 u16MiuClient = GOP_MIU_CLIENT_GOP1;
4076 break;
4077 }
4078 case E_GOP2:
4079 {
4080 u16MiuClient = GOP_MIU_CLIENT_GOP2;
4081 break;
4082 }
4083 case E_GOP3:
4084 {
4085 u16MiuClient = GOP_MIU_CLIENT_GOP3;
4086 break;
4087 }
4088 case E_GOP4:
4089 {
4090 u16MiuClient = GOP_MIU_CLIENT_GOP4;
4091 break;
4092 }
4093 default:
4094 {
4095 continue;
4096 }
4097 }
4098
4099 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
4100 {
4101 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
4102 return GOP_FAIL;
4103 }
4104 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
4105 _GetBnkOfstByGop(u8_combinedGop, &u32SubBankOffSet);
4106
4107 if ((gop == u8_combinedGop) && (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE))
4108 {
4109 continue;
4110 }
4111
4112 if( ( u16GopMask & (1<<gop) ) )
4113 {
4114 _GetBnkOfstByGop(gop, &u32BankOffSet);
4115 if(bMIUSelect[gop] == TRUE)
4116 {
4117 if(u16MIUSelect[gop] == 0)
4118 {
4119 u16RegVal1 &= ~(1<<u16MiuClient);
4120 u16RegVal3 &= ~(1<<u16MiuClient);
4121 }
4122 else if(u16MIUSelect[gop] == 1)
4123 {
4124 u16RegVal1 |= (1<<u16MiuClient);
4125 u16RegVal3 &= ~(1<<u16MiuClient);
4126 }
4127 else if(u16MIUSelect[gop] == 2)
4128 {
4129 u16RegVal1 &= ~(1<<u16MiuClient);
4130 u16RegVal3 |= (1<<u16MiuClient);
4131 }
4132 else if(u16MIUSelect[gop] == 3)
4133 {
4134 u16RegVal1 |= (1<<u16MiuClient);
4135 u16RegVal3 |= (1<<u16MiuClient);
4136 }
4137 bMIUSelect[gop] = FALSE;
4138 bMiuChanged = TRUE;
4139 }
4140
4141 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
4142 {
4143 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
4144 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32MainBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4145 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32MainBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4146 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32SubBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4147 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32SubBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4148 }
4149 else
4150 {
4151 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
4152 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4153 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4154 }
4155 }
4156 if(bAFBCMIUSelect[gop] == TRUE)
4157 {
4158 bAFBCMIUSelect[gop] = FALSE;
4159 }
4160 }
4161
4162 if(g_GopChipPro.bAFBC_Merge_GOP_Trig == FALSE)
4163 {
4164 if(g_GopChipPro.bAFBCMIUSelDoubleBuffer == FALSE)
4165 {
4166 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
4167 }
4168 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
4169 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
4170 }
4171
4172 if (TRUE == bMiuChanged)
4173 {
4174 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
4175 #ifdef GOP_MIU_GROUP2
4176 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
4177 #endif
4178 }
4179
4180 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
4181 return GOP_SUCCESS;
4182 }
4183 #endif
4184
HAL_GOP_SetDbgLevel(EN_GOP_DEBUG_LEVEL level)4185 GOP_Result HAL_GOP_SetDbgLevel(EN_GOP_DEBUG_LEVEL level)
4186 {
4187 u32GOPDbgLevel_hal= level;
4188 return GOP_SUCCESS;
4189 }
4190
4191