1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_GOP_H_ 96 #define _REG_GOP_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 102 103 //------------------------------------------------------------------------------------------------- 104 // Macro and Define 105 //------------------------------------------------------------------------------------------------- 106 //---------------------------------------------------------------------------- 107 // HW IP Reg Base Adr 108 //---------------------------------------------------------------------------- 109 #define GOP_REG_BASE 0x1F00UL 110 #define GE_REG_BASE 0x2800UL 111 #define SC1_REG_BASE 0x2F00UL 112 #define CKG_REG_BASE 0x0B00UL 113 #define MIU0_REG_BASE 0x0600UL 114 #define MIU_REG_BASE 0x1200UL 115 #define MIU2_REG_BASE 0x162000 116 #define MVOP_REG_BASE 0x1400UL 117 #define SC1_DIRREG_BASE 0x130000UL 118 119 //---------------------------------------------------------------------------- 120 // Scaler Reg 121 //---------------------------------------------------------------------------- 122 #define XC_REG(bk, reg) (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 123 124 #define REG_SC_BK00_00_L XC_REG(0x00, 0x00) 125 #define REG_SC_BK00_05_L XC_REG(0x00, 0x05) 126 #define REG_SC_BK00_06_L XC_REG(0x00, 0x06) 127 #define REG_SC_BK01_02_L XC_REG(0x01, 0x02) 128 #define REG_SC_BK01_05_L XC_REG(0x01, 0x05) 129 #define REG_SC_BK01_1E_L XC_REG(0x01, 0x1E) 130 #define REG_SC_BK01_21_L XC_REG(0x01, 0x21) 131 #define REG_SC_BK02_5F_L XC_REG(0x02, 0x5F) 132 #define REG_SC_BK0F_2B_L XC_REG(0x0F, 0x2B) 133 #define REG_SC_BK10_23_L XC_REG(0x10, 0x23) 134 #define REG_SC_BK10_5B_L XC_REG(0x10, 0x5B) 135 #define REG_SC_BK12_03_L XC_REG(0x12, 0x03) 136 #define REG_SC_BK37_22_L XC_REG(0x37, 0x22) 137 #define REG_SC_BK37_24_L XC_REG(0x37, 0x24) 138 #define REG_SC_BK37_28_L XC_REG(0x37, 0x28) 139 #define REG_SC_BK3D_0D_L XC_REG(0x3D, 0x0D) 140 #define REG_SC_BK40_22_L XC_REG(0x40, 0x22) 141 #define REG_SC_BK40_23_L XC_REG(0x40, 0x23) 142 #define REG_SC_BK40_24_L XC_REG(0x40, 0x24) 143 #define REG_SC_BK40_25_L XC_REG(0x40, 0x25) 144 #define REG_SC_BK7F_10_L XC_REG(0x7F, 0x10) 145 #define REG_SC_BK7F_11_L XC_REG(0x7F, 0x11) 146 147 #define REG_SC_BK80_05_L XC_REG(0x80, 0x05) 148 149 #define GOP_SC_BANKSEL REG_SC_BK00_00_L 150 #define GOP_SC_CHANNELSYNC REG_SC_BK00_05_L 151 #define GOP_SC1_CHANNELSYNC REG_SC_BK80_05_L 152 #define GOP_SC_GOPEN REG_SC_BK00_06_L 153 #define GOP_SC_IP_SYNC REG_SC_BK01_02_L 154 #define GOP_SC_IP_MAIN_HSTART REG_SC_BK01_05_L 155 #define GOP_SC_IP_MAIN_INTERLACE REG_SC_BK01_1E_L 156 #define GOP_SC_IP_MAIN_USR_INTERLACE REG_SC_BK01_21_L 157 #define GOP_SC_IP2GOP_SRCSEL REG_SC_BK02_5F_L 158 #define GOP_SC_OSD_CHECK_ALPHA REG_SC_BK0F_2B_L 159 #define GOP_SC_VOPNBL REG_SC_BK10_23_L 160 #define GOP_SC_GOPENMODE1 REG_SC_BK10_5B_L 161 #define GOP_SC_MIRRORCFG REG_SC_BK12_03_L 162 #define GOP_SC_OCMIXER REG_SC_BK37_22_L 163 #define GOP_SC_OCMISC REG_SC_BK37_24_L 164 #define GOP_SC_OCALPHA REG_SC_BK37_28_L 165 #define GOP_SC_GOPSC_SRAM_CTRL REG_SC_BK3D_0D_L 166 #define GOP_SC_FRC_LAYER1_L_EN REG_SC_BK40_22_L 167 #define GOP_SC_FRC_LAYER1_R_EN REG_SC_BK40_23_L 168 #define GOP_SC_FRC_LAYER2_L_EN REG_SC_BK40_24_L 169 #define GOP_SC_FRC_LAYER2_R_EN REG_SC_BK40_25_L 170 #define GOP_SC_MIU_SEL REG_SC_BK7F_10_L 171 #define GOP_SC_MIU_IP_SEL REG_SC_BK7F_11_L 172 173 //---------------------------------------------------------------------------- 174 // MVOP Reg 175 //---------------------------------------------------------------------------- 176 #define GOP_MVOP_MIRRORCFG (MVOP_REG_BASE+0x76) 177 178 179 180 //---------------------------------------------------------------------------- 181 // GE Reg 182 //---------------------------------------------------------------------------- 183 #define GOP_GE_FMT_BLT (GE_REG_BASE+(0x01*2)) 184 #define GOP_GE_EN_CMDQ BIT(0) 185 #define GOP_GE_EN_VCMDQ BIT(1) 186 187 #define GOP_GE_VQ_FIFO_STATUS_L (GE_REG_BASE+(0x04*2)) 188 #define GOP_GE_VQ_FIFO_STATUS_H (GE_REG_BASE+(0x05*2)) 189 190 #define GOP_GE_STATUS (GE_REG_BASE+(0x07*2)) 191 #define GOP_GE_BUSY BIT(0) 192 #define GOP_GE_CMDQ1_STATUS BMASK(7:3) 193 #define GOP_GE_CMDQ2_STATUS BMASK(15:11) 194 195 #define GOP_GE_TAG (GE_REG_BASE+(0x2C*2)) 196 197 #define GOP_GE_DBBASE0 (GE_REG_BASE+(0x26*2)) 198 #define GOP_GE_DBBASE1 (GE_REG_BASE+(0x27*2)) 199 #define GOP_GE_DBPIT (GE_REG_BASE+(0x33*2)) 200 #define GOP_GE_FBFMT (GE_REG_BASE+(0x34*2)) 201 #define GOP_GE_SRCW (GE_REG_BASE+(0x6e*2)) 202 #define GOP_GE_SRCH (GE_REG_BASE+(0x6f*2)) 203 204 205 //---------------------------------------------------------------------------- 206 // ChipTop Reg 207 //---------------------------------------------------------------------------- 208 /* GOP0 and GOP1 CLK */ 209 #define GOP_GOPCLK (CKG_REG_BASE+(0x40<<1)) 210 #define CKG_GOPG0_DISABLE_CLK ~(GOP_BIT0) 211 #define CKG_GOPG0_ODCLK (0<<2) 212 #define CKG_GOPG0_IDCLK2 (1 << 2) 213 #define CKG_GOPG0_IDCLK1 (2 << 2) 214 #define CKG_GOPG0_OCC_FRCCLK (3 << 2) 215 #define CKG_GOPG0_MIXERCLK_VE (4 << 2) 216 #define CKG_GOPG0_FCLK (8 << 2) 217 #define CKG_GOPG0_DISABLE_CLK_MASK (GOP_BIT0) 218 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 219 220 #define CKG_GOPG1_DISABLE_CLK ~(GOP_BIT8) 221 #define CKG_GOPG1_ODCLK (0 << 10) 222 #define CKG_GOPG1_IDCLK2 (1 << 10) 223 #define CKG_GOPG1_IDCLK1 (2 << 10) 224 #define CKG_GOPG1_OCC_FRCCLK (3 << 10) 225 #define CKG_GOPG1_MIXERCLK_VE (4 << 10) 226 #define CKG_GOPG1_FCLK (8 << 10) 227 #define CKG_GOPG1_DISABLE_CLK_MASK (GOP_BIT8) 228 #define CKG_GOPG1_MASK (GOP_BIT13 | GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 229 230 #define CKG_GOPG0_SCALING (CKG_REG_BASE+0x88) 231 #define CKG_GOPG0_MG (CKG_REG_BASE+0xFE) 232 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2) 233 #define CKG_GOPG2_MG_MASK (GOP_BIT7 | GOP_BIT6) 234 235 /* GOP2 and GOPDWIN CLK */ 236 #define GOP_GOP2CLK (CKG_REG_BASE+(0x41<<1)) 237 #define CKG_GOPG2_DISABLE_CLK ~(GOP_BIT0) 238 #define CKG_GOPG2_ODCLK (0<<2) 239 #define CKG_GOPG2_IDCLK2 (1 << 2) 240 #define CKG_GOPG2_IDCLK1 (2 << 2) 241 #define CKG_GOPG2_OCC_FRCCLK (3 << 2) 242 #define CKG_GOPG2_MIXERCLK_VE (4 << 2) 243 #define CKG_GOPG2_FCLK (8 << 2) 244 #define CKG_GOPG2_DISABLE_CLK_MASK (GOP_BIT0) 245 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 246 247 #define CKG_GOPD_CLK_IDCLK2 (0 << 10) 248 #define CKG_GOPD_CLK_ODCLK (1 << 10) 249 #define CKG_GOPD_CLK_DC0CLK (2 << 10) 250 #define CKG_GOPD_CLK_SUBDC0CLK (3 << 10) 251 #define CKG_GOPD_CLK_MIXERCLK_VE (4 << 10) 252 #define CKG_GOPD_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 253 254 255 /* GOP3 CLK*/ 256 #define GOP_GOP3CLK (CKG_REG_BASE+(0x42<<1)) 257 #define CKG_GOPG3_ODCLK (0<<2) 258 #define CKG_GOPG3_IDCLK2 (1 << 2) 259 #define CKG_GOPG3_IDCLK1 (2 << 2) 260 #define CKG_GOPG3_OCC_FRCCLK (3 << 2) 261 #define CKG_GOPG3_MIXERCLK_VE (4 << 2) 262 #define CKG_GOPG3_FCLK (8 << 2) 263 #define CKG_GOPG3_DISABLE_CLK_MASK (GOP_BIT0) 264 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 265 #define CKG_GOPD_DISABLE_CLK ~(GOP_BIT8) 266 267 268 /* GOP4 CLK*/ 269 #define GOP_GOP4CLK (CKG_REG_BASE+(0x7E<<1)) 270 #define CKG_GOPG4_ODCLK (0 << 10) 271 #define CKG_GOPG4_IDCLK2 (1 << 10) 272 #define CKG_GOPG4_IDCLK1 (2 << 10) 273 #define CKG_GOPG4_OCC_FRCCLK (3 << 10) 274 #define CKG_GOPG4_MIXERCLK_VE (4 << 10) 275 #define CKG_GOPG4_FCLK (9 << 10) 276 #define CKG_GOPG4_DISABLE_CLK_MASK (GOP_BIT8) 277 #define CKG_GOPG4_MASK (GOP_BIT13 |GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 278 279 280 /* SRAM CLK */ 281 #define GOP_SRAMCLK (CKG_REG_BASE+(0x43<<1)) 282 #define CKG_SRAM0_DISABLE_CLK (GOP_BIT0) 283 #define CKG_SRAM1_DISABLE_CLK (GOP_BIT8) 284 #define CKG_SRAM0_MASK (GOP_BIT0|GOP_BIT1) 285 #define CKG_SRAM1_MASK (GOP_BIT8|GOP_BIT9) 286 287 /* LINE BUFFER SRAM CLK */ 288 #define GOP_LB_SRAMCLK (CKG_REG_BASE+(0x45<<1)) 289 #define CKG_LB_SRAM1_DISABLE_CLK (GOP_BIT0) /*GOP1*/ 290 #define CKG_LB_SRAM2_DISABLE_CLK (GOP_BIT4) /*GOP2*/ 291 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3) 292 #define CKG_LB_SRAM2_MASK (GOP_BIT6|GOP_BIT7) 293 //---------------------------------------------------------------------------- 294 // MIU Reg 295 //---------------------------------------------------------------------------- 296 #define GOP_CLIENT_REG 0x7E 297 #define GOP_MIU_GROUP (MIU0_REG_BASE+(GOP_CLIENT_REG*2)) 298 #define GOP_MIU_GROUP1 (MIU_REG_BASE+(GOP_CLIENT_REG*2)) 299 300 /*Define each gop miu clint bit*/ 301 #define GOP_MIU_CLIENT_DWIN 0xFF 302 #define GOP_MIU_CLIENT_GOP0 0x5 303 #define GOP_MIU_CLIENT_GOP1 0x6 304 #define GOP_MIU_CLIENT_GOP2 0x7 305 #define GOP_MIU_CLIENT_GOP3 0x8 306 #define GOP_MIU_CLIENT_GOP4 0x6 307 #define GOP_MIU_CLIENT_GOP5 0xff 308 309 //---------------------------------------------------------------------------- 310 // VE Reg 311 //---------------------------------------------------------------------------- 312 #define GOP_VE_TVS_OSD_EN 0x60 313 #define GOP_VE_TVS_OSD1_EN 0x61 314 315 //---------------------------------------------------------------------------- 316 // GOP Reg 317 //---------------------------------------------------------------------------- 318 #define GOP_REG(bk, reg) (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 319 #define __GOP_REG(reg) (GOP_REG_BASE+(reg) * 2) 320 #define GOP_REG_DIRECT_BASE (0x120200) 321 #define GOP_REG_GOP4_BK_OFFSET 0x1900 322 #define GOP_REG_GOP4_GW_OFFSET 0x1C00 323 #define GOP_REG_GOP4_ST_OFFSET 0x1D00 324 325 #define GOP_REG_VAL(x) (1<<x) 326 327 //MUX Setting 328 #define GOP_MUX_SHIFT 0x3 329 #define GOP_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 330 #define GOP_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 331 #define GOP_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 332 #define GOP_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 333 #define GOP_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 334 #define GOP_MUX4_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*4)) 335 336 //IP and VOP MUX Setting 337 #define GOP_IP_MAIN_MUX_SHIFT 0 338 #define GOP_IP_MAIN_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_MAIN_MUX_SHIFT 339 #define GOP_IP_SUB_MUX_SHIFT 3 340 #define GOP_IP_SUB_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_SUB_MUX_SHIFT 341 #define GOP_IP_VOP0_MUX_SHIFT 6 342 #define GOP_IP_VOP0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP0_MUX_SHIFT 343 #define GOP_IP_VOP1_MUX_SHIFT 9 344 #define GOP_IP_VOP1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP1_MUX_SHIFT 345 346 347 //IP and VOP MUX Setting 348 #define GOP_Mix_MUX0_SHIFT 0 349 #define GOP_Mix_MUX0_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX0_SHIFT 350 #define GOP_Mix_MUX1_SHIFT 3 351 #define GOP_Mix_MUX1_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX1_SHIFT 352 #define GOP_VE0_MUX_SHIFT 6 353 #define GOP_VE0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE0_MUX_SHIFT 354 #define GOP_VE1_MUX_SHIFT 9 355 #define GOP_VE1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE1_MUX_SHIFT 356 357 358 //4k2k FRC MUX Setting 359 #define GOP_FRC_MUX_SHIFT 0x3 360 #define GOP_FRC_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 361 #define GOP_FRC_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 362 #define GOP_FRC_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 363 #define GOP_FRC_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 364 #define GOP_FRC_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 365 366 // for gwin color format mask 367 #define GOP_REG_COLORTYPE_MASK BMASK(4:0) 368 #define GOP_REG_COLORTYPE_SHIFT 4 369 370 //DIP Setting 371 #define GOP_DIP_MUX_SHIFT 12 372 #define GOP_DIP_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_DIP_MUX_SHIFT 373 374 #define GOP_BANK_OFFSET 0x3 375 #define GOP_4G_OFST 0x0 376 #define GOP_2G_OFST (0x1*GOP_BANK_OFFSET) 377 #define GOP_1G_OFST (0x2*GOP_BANK_OFFSET) 378 #define GOP_1GX_OFST (0x3*GOP_BANK_OFFSET) 379 #define GOP_DW_OFST (0x4*GOP_BANK_OFFSET) 380 #define GOP_1GS0_OFST 0xE 381 #define GOP_1GS1_OFST 0x11 382 #define GOP_AFBC_OFST 0x31 383 384 #define GOP_OFFSET_WR 8 385 #define GOP_VAL_WR GOP_REG_VAL(GOP_OFFSET_WR) 386 #define GOP_OFFSET_FWR 9 387 #define GOP_VAL_FWR GOP_REG_VAL(GOP_OFFSET_FWR) 388 #define GOP_OFFSET_FCLR 11 389 #define GOP_VAL_FCL GOP_REG_VAL(GOP_OFFSET_FCLR) 390 #define GOP4G_OFFSET_WR_ACK 12 391 #define GOP4G_VAL_WR_ACK GOP_REG_VAL(GOP4G_OFFSET_WR_ACK) 392 #define GOP2G_OFFSET_WR_ACK 13 393 #define GOP2G_VAL_WR_ACK GOP_REG_VAL(GOP2G_OFFSET_WR_ACK) 394 #define GOPD_OFFSET_WR_ACK 14 395 #define GOPD_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 396 #define GOP1G_OFFSET_WR_ACK 15 397 #define GOP1G_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 398 #define GOP_VAL_ACK(x) GOP_REG_VAL(GOP4G_OFFSET_WR_ACK+x) 399 400 #define GOP_4G_CTRL0 GOP_REG(GOP_4G_OFST, 0x00) 401 #define GOP_4G_CTRL1 GOP_REG(GOP_4G_OFST, 0x01) 402 #define GOP_4G_RATE GOP_REG(GOP_4G_OFST, 0x02) 403 #define GOP_4G_PALDATA_L GOP_REG(GOP_4G_OFST, 0x03) 404 #define GOP_4G_PALDATA_H GOP_REG(GOP_4G_OFST, 0x04) 405 #define GOP_4G_PALCTRL GOP_REG(GOP_4G_OFST, 0x05) 406 #define GOP_4G_REGDMA_END GOP_REG(GOP_4G_OFST, 0x06) 407 #define GOP_4G_REGDMA_STR GOP_REG(GOP_4G_OFST, 0x07) 408 #define GOP_4G_INT GOP_REG(GOP_4G_OFST, 0x08) 409 #define GOP_4G_HWSTATE GOP_REG(GOP_4G_OFST, 0x09) 410 #define GOP_4G_SVM_HSTR GOP_REG(GOP_4G_OFST, 0x0a) 411 #define GOP_4G_SVM_HEND GOP_REG(GOP_4G_OFST, 0x0b) 412 #define GOP_4G_SVM_VSTR GOP_REG(GOP_4G_OFST, 0x0c) 413 #define GOP_4G_SVM_VEND GOP_REG(GOP_4G_OFST, 0x0d) 414 #define GOP_4G_RDMA_HT GOP_REG(GOP_4G_OFST, 0x0e) 415 #define GOP_4G_HS_PIPE GOP_REG(GOP_4G_OFST, 0x0f) 416 #define GOP_4G_SLOW GOP_REG(GOP_4G_OFST, 0x10) 417 #define GOP_4G_BRI GOP_REG(GOP_4G_OFST, 0x11) 418 #define GOP_4G_CON GOP_REG(GOP_4G_OFST, 0x12) 419 #define GOP_4G_BW GOP_REG(GOP_4G_OFST, 0x19) 420 #define GOP_4G_NEW_BW GOP_REG(GOP_4G_OFST, 0x1C) 421 #define GOP_4G_SRAM_BORROW GOP_REG(GOP_4G_OFST, 0x1D) 422 #define GOP_4G_3D_MIDDLE GOP_REG(GOP_4G_OFST, 0x1E) 423 #define GOP_4G_MIU_SEL GOP_REG(GOP_4G_OFST, 0x1F) 424 #define GOP_4G_PRI0 GOP_REG(GOP_4G_OFST, 0x20) 425 #define GOP_4G_BOT_HS GOP_REG(GOP_4G_OFST, 0x23) 426 #define GOP_4G_TRSCLR_L GOP_REG(GOP_4G_OFST, 0x24) 427 #define GOP_4G_TRSCLR_H GOP_REG(GOP_4G_OFST, 0x25) 428 #define GOP_4G_TRSCLR_TUV_L GOP_REG(GOP_4G_OFST, 0x26) 429 #define GOP_4G_TRSCLR_TUV_H GOP_REG(GOP_4G_OFST, 0x27) 430 #define GOP_4G_YUV_SWAP GOP_REG(GOP_4G_OFST, 0x28) 431 #define GOP_4G_STRCH_HSZ GOP_REG(GOP_4G_OFST, 0x30) 432 #define GOP_4G_STRCH_VSZ GOP_REG(GOP_4G_OFST, 0x31) 433 #define GOP_4G_STRCH_HSTR GOP_REG(GOP_4G_OFST, 0x32) 434 #define GOP_4G_STRCH_VSTR GOP_REG(GOP_4G_OFST, 0x34) 435 #define GOP_4G_HSTRCH GOP_REG(GOP_4G_OFST, 0x35) 436 #define GOP_4G_VSTRCH GOP_REG(GOP_4G_OFST, 0x36) 437 #define GOP_4G_HSTRCH_INI GOP_REG(GOP_4G_OFST, 0x38) 438 #define GOP_4G_VSTRCH_INI GOP_REG(GOP_4G_OFST, 0x39) 439 #define GOP_4G_HVSTRCHMD GOP_REG(GOP_4G_OFST, 0x3a) 440 #define GOP_4G_OLDADDR GOP_REG(GOP_4G_OFST, 0x3b) 441 #define GOP_4G_MULTI_ALPHA GOP_REG(GOP_4G_OFST, 0x3c) 442 #define GOP_4G_TWO_LINEBUFFER GOP_4G_MULTI_ALPHA 443 #define GOP_4G_HW_USAGE GOP_REG(GOP_4G_OFST, 0x40) 444 #define GOP_4G_BANK_FWR GOP_REG(GOP_4G_OFST, 0x50) 445 #define GOP_4G_BANK_HVAILDSIZE GOP_REG(GOP_4G_OFST, 0x52) 446 #define GOP_4G_BANK_VVAILDSIZE GOP_REG(GOP_4G_OFST, 0x53) 447 #define GOP_4G_SCALING_H_OUTPUTSIZE GOP_REG(GOP_4G_OFST, 0x56) 448 #define GOP_4G_SCALING_HRATIO_L GOP_REG(GOP_4G_OFST, 0x59) //GOP scaling down ratio dst / out * 2^20 449 #define GOP_4G_SCALING_HRATIO_H GOP_REG(GOP_4G_OFST, 0x5A) 450 #define GOP_4G_SCALING_CFG GOP_REG(GOP_4G_OFST, 0x5B) 451 #define GOP_4G_SCALING_VRATIO_L GOP_REG(GOP_4G_OFST, 0x5C) //GOP scaling down ratio dst / out * 2^20 452 #define GOP_4G_SCALING_VRATIO_H GOP_REG(GOP_4G_OFST, 0x5D) 453 454 455 #define GOP_4G_RBLK0_VOFFL GOP_REG(GOP_4G_OFST, 0x60) 456 #define GOP_4G_RBLK0_VOFFH GOP_REG(GOP_4G_OFST, 0x61) 457 #define GOP_4G_RBLK1_VOFFL GOP_REG(GOP_4G_OFST, 0x62) 458 #define GOP_4G_RBLK1_VOFFH GOP_REG(GOP_4G_OFST, 0x63) 459 #define GOP_4G_RBLK2_VOFFL GOP_REG(GOP_4G_OFST, 0x64) 460 #define GOP_4G_RBLK2_VOFFH GOP_REG(GOP_4G_OFST, 0x65) 461 #define GOP_4G_RBLK3_VOFFL GOP_REG(GOP_4G_OFST, 0x66) 462 #define GOP_4G_RBLK3_VOFFH GOP_REG(GOP_4G_OFST, 0x67) 463 #define GOP_4G_RBLK0_HOFF GOP_REG(GOP_4G_OFST, 0x70) 464 #define GOP_4G_RBLK1_HOFF GOP_REG(GOP_4G_OFST, 0x71) 465 #define GOP_4G_RBLK2_HOFF GOP_REG(GOP_4G_OFST, 0x72) 466 #define GOP_4G_RBLK3_HOFF GOP_REG(GOP_4G_OFST, 0x73) 467 #define GOP_4G_REGDMA_EN GOP_REG(GOP_4G_OFST, 0x78) 468 #define GOP_MUX_IPVOP __GOP_REG(0x77) 469 #define GOP_MUX4_MIX_VE __GOP_REG(0x7B) 470 #define GOP_BAK_SEL_EX __GOP_REG(0x7C) 471 #define GOP_MUX_4K2K __GOP_REG(0x7D) 472 #define GOP_MUX __GOP_REG(0x7e) 473 #define GOP_BAK_SEL __GOP_REG(0x7f) 474 475 #define GOP_4G_GWIN0_CTRL(id) GOP_REG(GOP_4G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP0_GWIN))) 476 #define GOP_4G_DRAM_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP0_GWIN))) 477 #define GOP_4G_DRAM_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP0_GWIN))) 478 #define GOP_4G_DEL_PIXEL(id) GOP_REG(GOP_4G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 479 #define GOP_4G_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP0_GWIN))) 480 #define GOP_4G_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP0_GWIN))) 481 #define GOP_4G_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP0_GWIN))) 482 #define GOP_4G_GWIN_MIDDLE(id) GOP_REG(GOP_4G_OFST+1, 0x07 + (0x20*((id)%MAX_GOP0_GWIN))) 483 #define GOP_4G_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP0_GWIN))) 484 #define GOP_4G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_4G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP0_GWIN))) 485 #define GOP_4G_GWIN_ALPHA01(id) GOP_REG(GOP_4G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP0_GWIN))) 486 #define GOP_4G_DRAM_VSTR_L(id) GOP_REG(GOP_4G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP0_GWIN))) 487 #define GOP_4G_DRAM_VSTR_H(id) GOP_REG(GOP_4G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP0_GWIN))) 488 #define GOP_4G_DRAM_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x0E + (0x20*((id)%MAX_GOP0_GWIN))) 489 #define GOP_4G_DRAM_RBLK_SIZE_L(id) GOP_REG(GOP_4G_OFST+1, 0x10 + (0x20*((id)%MAX_GOP0_GWIN))) 490 #define GOP_4G_DRAM_RBLK_SIZE_H(id) GOP_REG(GOP_4G_OFST+1, 0x11 + (0x20*((id)%MAX_GOP0_GWIN))) 491 #define GOP_4G_DRAM_RLEN_L(id) GOP_REG(GOP_4G_OFST+1, 0x12 + (0x20*((id)%MAX_GOP0_GWIN))) 492 #define GOP_4G_DRAM_RLEN_H(id) GOP_REG(GOP_4G_OFST+1, 0x13 + (0x20*((id)%MAX_GOP0_GWIN))) 493 #define GOP_4G_DRAM_HVSTOP_L(id) GOP_REG(GOP_4G_OFST+1, 0x14 + (0x20*((id)%MAX_GOP0_GWIN))) 494 #define GOP_4G_DRAM_HVSTOP_H(id) GOP_REG(GOP_4G_OFST+1, 0x15 + (0x20*((id)%MAX_GOP0_GWIN))) 495 #define GOP_4G_DRAM_FADE(id) GOP_REG(GOP_4G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP0_GWIN))) 496 #define GOP_4G_BG_CLR(id) GOP_REG(GOP_4G_OFST+1, 0x18 + (0x20*((id)%MAX_GOP0_GWIN))) 497 #define GOP_4G_BG_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x19 + (0x20*((id)%MAX_GOP0_GWIN))) 498 #define GOP_4G_BG_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x1a + (0x20*((id)%MAX_GOP0_GWIN))) 499 #define GOP_4G_BG_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x1C + (0x20*((id)%MAX_GOP0_GWIN))) 500 #define GOP_4G_BG_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x1D + (0x20*((id)%MAX_GOP0_GWIN))) 501 #define GOP_4G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP0_GWIN))) 502 #define GOP_4G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP0_GWIN))) 503 504 505 #define GOP_2G_CTRL0 GOP_REG(GOP_2G_OFST, 0x00) 506 #define GOP_2G_CTRL1 GOP_REG(GOP_2G_OFST, 0x01) 507 #define GOP_2G_RATE GOP_REG(GOP_2G_OFST, 0x02) 508 #define GOP_2G_PALDATA_L GOP_REG(GOP_2G_OFST, 0x03) 509 #define GOP_2G_PALDATA_H GOP_REG(GOP_2G_OFST, 0x04) 510 #define GOP_2G_PALCTRL GOP_REG(GOP_2G_OFST, 0x05) 511 #define GOP_2G_REGDMA_END GOP_REG(GOP_2G_OFST, 0x06) 512 #define GOP_2G_REGDMA_STR GOP_REG(GOP_2G_OFST, 0x07) 513 #define GOP_2G_INT GOP_REG(GOP_2G_OFST, 0x08) 514 #define GOP_2G_HWSTATE GOP_REG(GOP_2G_OFST, 0x09) 515 #define GOP_2G_RDMA_HT GOP_REG(GOP_2G_OFST, 0x0e) 516 #define GOP_2G_HS_PIPE GOP_REG(GOP_2G_OFST, 0x0f) 517 #define GOP_2G_SLOW GOP_REG(GOP_2G_OFST, 0x10) 518 #define GOP_2G_BRI GOP_REG(GOP_2G_OFST, 0x11) 519 #define GOP_2G_CON GOP_REG(GOP_2G_OFST, 0x12) 520 #define GOP_2G_BW GOP_REG(GOP_2G_OFST, 0x19) 521 #define GOP_2G_3D_MIDDLE GOP_REG(GOP_2G_OFST, 0x1E) 522 #define GOP_2G_PRI0 GOP_REG(GOP_2G_OFST, 0x20) 523 #define GOP_2G_TRSCLR_L GOP_REG(GOP_2G_OFST, 0x24) 524 #define GOP_2G_TRSCLR_H GOP_REG(GOP_2G_OFST, 0x25) 525 #define GOP_2G_STRCH_HSZ GOP_REG(GOP_2G_OFST, 0x30) 526 #define GOP_2G_STRCH_VSZ GOP_REG(GOP_2G_OFST, 0x31) 527 #define GOP_2G_STRCH_HSTR GOP_REG(GOP_2G_OFST, 0x32) 528 #define GOP_2G_STRCH_VSTR GOP_REG(GOP_2G_OFST, 0x34) 529 #define GOP_2G_HSTRCH GOP_REG(GOP_2G_OFST, 0x35) 530 #define GOP_2G_VSTRCH GOP_REG(GOP_2G_OFST, 0x36) 531 #define GOP_2G_HSTRCH_INI GOP_REG(GOP_2G_OFST, 0x38) 532 #define GOP_2G_VSTRCH_INI GOP_REG(GOP_2G_OFST, 0x39) 533 #define GOP_2G_HVStrch_MD GOP_REG(GOP_2G_OFST, 0x3a) 534 #define GOP_2G_OLDADDR GOP_REG(GOP_2G_OFST, 0x3b) 535 #define GOP_2G_MULTI_ALPHA GOP_REG(GOP_2G_OFST, 0x3c) 536 #define GOP_2G_REGDMA_EN GOP_REG(GOP_2G_OFST, 0x78) 537 538 539 #define GOP_2G_GWIN0_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 540 #define GOP_2G_GWIN_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 541 #define GOP_2G_DRAM_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP1_GWIN))) 542 #define GOP_2G_DRAM_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP1_GWIN))) 543 #define GOP_2G_DEL_PIXEL(id) GOP_REG(GOP_2G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 544 #define GOP_2G_HSTR(id) GOP_REG(GOP_2G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP1_GWIN))) 545 #define GOP_2G_HEND(id) GOP_REG(GOP_2G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP1_GWIN))) 546 #define GOP_2G_VSTR(id) GOP_REG(GOP_2G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP1_GWIN))) 547 #define GOP_2G_VEND(id) GOP_REG(GOP_2G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP1_GWIN))) 548 #define GOP_2G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_2G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP1_GWIN))) 549 #define GOP_2G_GWIN_ALPHA01(id) GOP_REG(GOP_2G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP1_GWIN))) 550 #define GOP_2G_DRAM_VSTR_L(id) GOP_REG(GOP_2G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP1_GWIN))) 551 #define GOP_2G_DRAM_VSTR_H(id) GOP_REG(GOP_2G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP1_GWIN))) 552 #define GOP_2G_DRAM_FADE(id) GOP_REG(GOP_2G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP1_GWIN))) 553 #define GOP_2G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP1_GWIN))) 554 #define GOP_2G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP1_GWIN))) 555 556 // DWIN reg 557 #define GOP_DW_CTL0_EN GOP_REG(GOP_DW_OFST, 0x00) 558 #define GOP_DWIN_EN (0x00) 559 #define GOP_DWIN_EN_VAL GOP_REG_VAL(GOP_DWIN_EN) 560 #define GOP_DWIN_SHOT (0x07) 561 #define GOP_DWIN_SHOT_VAL GOP_REG_VAL(GOP_DWIN_SHOT) 562 563 #define GOP_DW_LSTR_WBE GOP_REG(GOP_DW_OFST, 0x01) 564 #define GOP_DW_INT_MASK GOP_REG(GOP_DW_OFST, 0x02) 565 #define GOP_DW_DEBUG GOP_REG(GOP_DW_OFST, 0x03) 566 #define GOP_DW_ALPHA GOP_REG(GOP_DW_OFST, 0x04) 567 #define GOP_DW_BW GOP_REG(GOP_DW_OFST, 0x05) 568 #define GOP_DW_VSTR GOP_REG(GOP_DW_OFST, 0x10) 569 #define GOP_DW_HSTR GOP_REG(GOP_DW_OFST, 0x11) 570 #define GOP_DW_VEND GOP_REG(GOP_DW_OFST, 0x12) 571 #define GOP_DW_HEND GOP_REG(GOP_DW_OFST, 0x13) 572 #define GOP_DW_HSIZE GOP_REG(GOP_DW_OFST, 0x14) 573 #define GOP_DW_JMPLEN GOP_REG(GOP_DW_OFST, 0x15) 574 #define GOP_DW_DSTR_L GOP_REG(GOP_DW_OFST, 0x16) 575 #define GOP_DW_DSTR_H GOP_REG(GOP_DW_OFST, 0x17) 576 #define GOP_DW_UB_L GOP_REG(GOP_DW_OFST, 0x18) 577 #define GOP_DW_UB_H GOP_REG(GOP_DW_OFST, 0x19) 578 579 #define GOP_DW_PON_DSTR_L GOP_REG(GOP_DW_OFST, 0x1a) 580 #define GOP_DW_PON_DSTR_H GOP_REG(GOP_DW_OFST, 0x1b) 581 #define GOP_DW_PON_UB_L GOP_REG(GOP_DW_OFST, 0x1c) 582 #define GOP_DW_PON_UB_H GOP_REG(GOP_DW_OFST, 0x1d) 583 #define GOP_DW_FRAME_CTRL GOP_REG(GOP_DW_OFST, 0x30) 584 585 #define GOP_1G_CTRL0 GOP_REG(GOP_1G_OFST, 0x00) 586 #define GOP_1G_CTRL1 GOP_REG(GOP_1G_OFST, 0x01) 587 #define GOP_1G_RATE GOP_REG(GOP_1G_OFST, 0x02) 588 #define GOP_1G_PALDATA_L GOP_REG(GOP_1G_OFST, 0x03) 589 #define GOP_1G_PALDATA_H GOP_REG(GOP_1G_OFST, 0x04) 590 #define GOP_1G_PALCTRL GOP_REG(GOP_1G_OFST, 0x05) 591 #define GOP_1G_REGDMA_END GOP_REG(GOP_1G_OFST, 0x06) 592 #define GOP_1G_REGDMA_STR GOP_REG(GOP_1G_OFST, 0x07) 593 #define GOP_1G_INT GOP_REG(GOP_1G_OFST, 0x08) 594 #define GOP_1G_HWSTATE GOP_REG(GOP_1G_OFST, 0x09) 595 #define GOP_1G_RDMA_HT GOP_REG(GOP_1G_OFST, 0x0e) 596 #define GOP_1G_HS_PIPE GOP_REG(GOP_1G_OFST, 0x0f) 597 #define GOP_1G_BRI GOP_REG(GOP_1G_OFST, 0x11) 598 #define GOP_1G_CON GOP_REG(GOP_1G_OFST, 0x12) 599 #define GOP_1G_BW GOP_REG(GOP_1G_OFST, 0x19) 600 #define GOP_1G_3D_MIDDLE GOP_REG(GOP_1G_OFST, 0x1E) 601 #define GOP_1G_TRSCLR_L GOP_REG(GOP_1G_OFST, 0x24) 602 #define GOP_1G_TRSCLR_H GOP_REG(GOP_1G_OFST, 0x25) 603 #define GOP_1G_STRCH_HSZ GOP_REG(GOP_1G_OFST, 0x30) 604 #define GOP_1G_STRCH_VSZ GOP_REG(GOP_1G_OFST, 0x31) 605 #define GOP_1G_STRCH_HSTR GOP_REG(GOP_1G_OFST, 0x32) 606 #define GOP_1G_STRCH_VSTR GOP_REG(GOP_1G_OFST, 0x34) 607 #define GOP_1G_HSTRCH GOP_REG(GOP_1G_OFST, 0x35) 608 #define GOP_1G_HSTRCH_INI GOP_REG(GOP_1G_OFST, 0x38) 609 #define GOP_1G_VSTRCH_INI GOP_REG(GOP_1G_OFST, 0x39) 610 #define GOP_1G_HStrch_MD GOP_REG(GOP_1G_OFST, 0x3a) 611 #define GOP_1G_OLDADDR GOP_REG(GOP_1G_OFST, 0x3b) 612 #define GOP_1G_MULTI_ALPHA GOP_REG(GOP_1G_OFST, 0x3c) 613 614 #define GOP_1G_GWIN0_CTRL GOP_REG(GOP_1G_OFST+1, 0x0) 615 #define GOP_1G_DRAM_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1) 616 #define GOP_1G_DRAM_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x2) 617 #define GOP_1G_DEL_PIXEL GOP_REG(GOP_1G_OFST+1, 0x3) 618 #define GOP_1G_HSTR GOP_REG(GOP_1G_OFST+1, 0x4) 619 #define GOP_1G_HEND GOP_REG(GOP_1G_OFST+1, 0x5) 620 #define GOP_1G_VSTR GOP_REG(GOP_1G_OFST+1, 0x6) 621 #define GOP_1G_VEND GOP_REG(GOP_1G_OFST+1, 0x8) 622 #define GOP_1G_DRAM_RBLK_HSIZE GOP_REG(GOP_1G_OFST+1, 0x9) 623 #define GOP_1G_GWIN_ALPHA01 GOP_REG(GOP_1G_OFST+1, 0xA) 624 #define GOP_1G_DRAM_VSTR_L GOP_REG(GOP_1G_OFST+1, 0x0C) 625 #define GOP_1G_DRAM_VSTR_H GOP_REG(GOP_1G_OFST+1, 0x0D) 626 #define GOP_1G_DRAM_FADE GOP_REG(GOP_1G_OFST+1, 0x16) 627 #define GOP_1G_3DOSD_SUB_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1E) 628 #define GOP_1G_3DOSD_SUB_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x1F) 629 630 #define GOP_1GX_CTRL0 GOP_REG(GOP_1GX_OFST, 0x00) 631 #define GOP_1GX_CTRL1 GOP_REG(GOP_1GX_OFST, 0x01) 632 #define GOP_1GX_RATE GOP_REG(GOP_1GX_OFST, 0x02) 633 #define GOP_1GX_PALDATA_L GOP_REG(GOP_1GX_OFST, 0x03) 634 #define GOP_1GX_PALDATA_H GOP_REG(GOP_1GX_OFST, 0x04) 635 #define GOP_1GX_PALCTRL GOP_REG(GOP_1GX_OFST, 0x05) 636 #define GOP_1GX_REGDMA_END GOP_REG(GOP_1GX_OFST, 0x06) 637 #define GOP_1GX_REGDMA_STR GOP_REG(GOP_1GX_OFST, 0x07) 638 #define GOP_1GX_INT GOP_REG(GOP_1GX_OFST, 0x08) 639 #define GOP_1GX_HWSTATE GOP_REG(GOP_1GX_OFST, 0x09) 640 #define GOP_1GX_RDMA_HT GOP_REG(GOP_1GX_OFST, 0x0e) 641 #define GOP_1GX_HS_PIPE GOP_REG(GOP_1GX_OFST, 0x0f) 642 #define GOP_1GX_BRI GOP_REG(GOP_1GX_OFST, 0x11) 643 #define GOP_1GX_CON GOP_REG(GOP_1GX_OFST, 0x12) 644 #define GOP_1GX_BW GOP_REG(GOP_1GX_OFST, 0x19) 645 #define GOP_1GX_3D_MIDDLE GOP_REG(GOP_1GX_OFST, 0x1E) 646 #define GOP_1GX_TRSCLR_L GOP_REG(GOP_1GX_OFST, 0x24) 647 #define GOP_1GX_TRSCLR_H GOP_REG(GOP_1GX_OFST, 0x25) 648 #define GOP_1GX_STRCH_HSZ GOP_REG(GOP_1GX_OFST, 0x30) 649 #define GOP_1GX_STRCH_VSZ GOP_REG(GOP_1GX_OFST, 0x31) 650 #define GOP_1GX_STRCH_HSTR GOP_REG(GOP_1GX_OFST, 0x32) 651 #define GOP_1GX_STRCH_VSTR GOP_REG(GOP_1GX_OFST, 0x34) 652 #define GOP_1GX_HSTRCH GOP_REG(GOP_1GX_OFST, 0x35) 653 #define GOP_1GX_HSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x38) 654 #define GOP_1GX_VSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x39) 655 #define GOP_1GX_HStrch_MD GOP_REG(GOP_1GX_OFST, 0x3a) 656 #define GOP_1GX_OLDADDR GOP_REG(GOP_1GX_OFST, 0x3b) 657 #define GOP_1GX_MULTI_ALPHA GOP_REG(GOP_1GX_OFST, 0x3c) 658 659 #define GOP_1GX_GWIN0_CTRL GOP_REG(GOP_1GX_OFST+1, 0x00) 660 #define GOP_1GX_DRAM_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x01) 661 #define GOP_1GX_DRAM_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x02) 662 #define GOP_1GX_DEL_PIXEL GOP_REG(GOP_1GX_OFST+1, 0x03) 663 #define GOP_1GX_HSTR GOP_REG(GOP_1GX_OFST+1, 0x04) 664 #define GOP_1GX_HEND GOP_REG(GOP_1GX_OFST+1, 0x05) 665 #define GOP_1GX_VSTR GOP_REG(GOP_1GX_OFST+1, 0x06) 666 #define GOP_1GX_VEND GOP_REG(GOP_1GX_OFST+1, 0x08) 667 #define GOP_1GX_DRAM_RBLK_HSIZE GOP_REG(GOP_1GX_OFST+1, 0x09) 668 #define GOP_1GX_GWIN_ALPHA01 GOP_REG(GOP_1GX_OFST+1, 0x0A) 669 #define GOP_1GX_DRAM_VSTR_L GOP_REG(GOP_1GX_OFST+1, 0x0C) 670 #define GOP_1GX_DRAM_VSTR_H GOP_REG(GOP_1GX_OFST+1, 0x0D) 671 #define GOP_1GX_DRAM_FADE GOP_REG(GOP_1GX_OFST+1, 0x16) 672 #define GOP_1GX_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x1E) 673 #define GOP_1GX_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x1F) 674 675 #define GOP_1GS0_CTRL0 GOP_REG(GOP_1GS0_OFST, 0x00) 676 #define GOP_1GS0_CTRL1 GOP_REG(GOP_1GS0_OFST, 0x01) 677 #define GOP_1GS0_RATE GOP_REG(GOP_1GS0_OFST, 0x02) 678 #define GOP_1GS0_PALDATA_L GOP_REG(GOP_1GS0_OFST, 0x03) 679 #define GOP_1GS0_PALDATA_H GOP_REG(GOP_1GS0_OFST, 0x04) 680 #define GOP_1GS0_PALCTRL GOP_REG(GOP_1GS0_OFST, 0x05) 681 #define GOP_1GS0_REGDMA_END GOP_REG(GOP_1GS0_OFST, 0x06) 682 #define GOP_1GS0_REGDMA_STR GOP_REG(GOP_1GS0_OFST, 0x07) 683 #define GOP_1GS0_INT GOP_REG(GOP_1GS0_OFST, 0x08) 684 #define GOP_1GS0_HWSTATE GOP_REG(GOP_1GS0_OFST, 0x09) 685 #define GOP_1GS0_RDMA_HT GOP_REG(GOP_1GS0_OFST, 0x0e) 686 #define GOP_1GS0_HS_PIPE GOP_REG(GOP_1GS0_OFST, 0x0f) 687 #define GOP_1GS0_BRI GOP_REG(GOP_1GS0_OFST, 0x11) 688 #define GOP_1GS0_CON GOP_REG(GOP_1GS0_OFST, 0x12) 689 #define GOP_1GS0_BW GOP_REG(GOP_1GS0_OFST, 0x19) 690 #define GOP_1GS0_TRSCLR_L GOP_REG(GOP_1GS0_OFST, 0x24) 691 #define GOP_1GS0_TRSCLR_H GOP_REG(GOP_1GS0_OFST, 0x25) 692 #define GOP_1GS0_STRCH_HSZ GOP_REG(GOP_1GS0_OFST, 0x30) 693 #define GOP_1GS0_STRCH_VSZ GOP_REG(GOP_1GS0_OFST, 0x31) 694 #define GOP_1GS0_STRCH_HSTR GOP_REG(GOP_1GS0_OFST, 0x32) 695 #define GOP_1GS0_STRCH_VSTR GOP_REG(GOP_1GS0_OFST, 0x34) 696 #define GOP_1GS0_HSTRCH GOP_REG(GOP_1GS0_OFST, 0x35) 697 #define GOP_1GS0_HSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x38) 698 #define GOP_1GS0_VSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x39) 699 #define GOP_1GS0_HVStrch_MD GOP_REG(GOP_1GS0_OFST, 0x3a) 700 #define GOP_1GS0_OLDADDR GOP_REG(GOP_1GS0_OFST, 0x3b) 701 #define GOP_1GS0_MULTI_ALPHA GOP_REG(GOP_1GS0_OFST, 0x3c) 702 703 #define GOP_1GS0_GWIN0_CTRL GOP_REG(GOP_1GS0_OFST+1, 0x00) 704 #define GOP_1GS0_DRAM_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x01) 705 #define GOP_1GS0_DRAM_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x02) 706 #define GOP_1GS0_DEL_PIXEL GOP_REG(GOP_1GS0_OFST+1, 0x03) 707 #define GOP_1GS0_HSTR GOP_REG(GOP_1GS0_OFST+1, 0x04) 708 #define GOP_1GS0_HEND GOP_REG(GOP_1GS0_OFST+1, 0x05) 709 #define GOP_1GS0_VSTR GOP_REG(GOP_1GS0_OFST+1, 0x06) 710 #define GOP_1GS0_VEND GOP_REG(GOP_1GS0_OFST+1, 0x08) 711 #define GOP_1GS0_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS0_OFST+1, 0x09) 712 #define GOP_1GS0_GWIN_ALPHA01 GOP_REG(GOP_1GS0_OFST+1, 0x0A) 713 #define GOP_1GS0_DRAM_VSTR_L GOP_REG(GOP_1GS0_OFST+1, 0x0C) 714 #define GOP_1GS0_DRAM_VSTR_H GOP_REG(GOP_1GS0_OFST+1, 0x0D) 715 #define GOP_1GS0_DRAM_FADE GOP_REG(GOP_1GS0_OFST+1, 0x16) 716 #define GOP_1GS0_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x1E) 717 #define GOP_1GS0_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x1F) 718 719 #define GOP_1GS1_CTRL0 GOP_REG(GOP_1GS1_OFST, 0x00) 720 #define GOP_1GS1_CTRL1 GOP_REG(GOP_1GS1_OFST, 0x01) 721 #define GOP_1GS1_RATE GOP_REG(GOP_1GS1_OFST, 0x02) 722 #define GOP_1GS1_PALDATA_L GOP_REG(GOP_1GS1_OFST, 0x03) 723 #define GOP_1GS1_PALDATA_H GOP_REG(GOP_1GS1_OFST, 0x04) 724 #define GOP_1GS1_PALCTRL GOP_REG(GOP_1GS1_OFST, 0x05) 725 #define GOP_1GS1_REGDMA_END GOP_REG(GOP_1GS1_OFST, 0x06) 726 #define GOP_1GS1_REGDMA_STR GOP_REG(GOP_1GS1_OFST, 0x07) 727 #define GOP_1GS1_INT GOP_REG(GOP_1GS1_OFST, 0x08) 728 #define GOP_1GS1_HWSTATE GOP_REG(GOP_1GS1_OFST, 0x09) 729 #define GOP_1GS1_RDMA_HT GOP_REG(GOP_1GS1_OFST, 0x0e) 730 #define GOP_1GS1_HS_PIPE GOP_REG(GOP_1GS1_OFST, 0x0f) 731 #define GOP_1GS1_BRI GOP_REG(GOP_1GS1_OFST, 0x11) 732 #define GOP_1GS1_CON GOP_REG(GOP_1GS1_OFST, 0x12) 733 #define GOP_1GS1_BW GOP_REG(GOP_1GS1_OFST, 0x19) 734 #define GOP_1GS1_TRSCLR_L GOP_REG(GOP_1GS1_OFST, 0x24) 735 #define GOP_1GS1_TRSCLR_H GOP_REG(GOP_1GS1_OFST, 0x25) 736 #define GOP_1GS1_STRCH_HSZ GOP_REG(GOP_1GS1_OFST, 0x30) 737 #define GOP_1GS1_STRCH_VSZ GOP_REG(GOP_1GS1_OFST, 0x31) 738 #define GOP_1GS1_STRCH_HSTR GOP_REG(GOP_1GS1_OFST, 0x32) 739 #define GOP_1GS1_STRCH_VSTR GOP_REG(GOP_1GS1_OFST, 0x34) 740 #define GOP_1GS1_HSTRCH GOP_REG(GOP_1GS1_OFST, 0x35) 741 #define GOP_1GS1_HSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x38) 742 #define GOP_1GS1_VSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x39) 743 #define GOP_1GS1_HVStrch_MD GOP_REG(GOP_1GS1_OFST, 0x3a) 744 #define GOP_1GS1_OLDADDR GOP_REG(GOP_1GS1_OFST, 0x3b) 745 #define GOP_1GS1_MULTI_ALPHA GOP_REG(GOP_1GS1_OFST, 0x3c) 746 747 #define GOP_1GS1_GWIN0_CTRL GOP_REG(GOP_1GS1_OFST+1, 0x00) 748 #define GOP_1GS1_DRAM_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x01) 749 #define GOP_1GS1_DRAM_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x02) 750 #define GOP_1GS1_DEL_PIXEL GOP_REG(GOP_1GS1_OFST+1, 0x03) 751 #define GOP_1GS1_HSTR GOP_REG(GOP_1GS1_OFST+1, 0x04) 752 #define GOP_1GS1_HEND GOP_REG(GOP_1GS1_OFST+1, 0x05) 753 #define GOP_1GS1_VSTR GOP_REG(GOP_1GS1_OFST+1, 0x06) 754 #define GOP_1GS1_VEND GOP_REG(GOP_1GS1_OFST+1, 0x08) 755 #define GOP_1GS1_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS1_OFST+1, 0x09) 756 #define GOP_1GS1_GWIN_ALPHA01 GOP_REG(GOP_1GS1_OFST+1, 0x0A) 757 #define GOP_1GS1_DRAM_VSTR_L GOP_REG(GOP_1GS1_OFST+1, 0x0C) 758 #define GOP_1GS1_DRAM_VSTR_H GOP_REG(GOP_1GS1_OFST+1, 0x0D) 759 #define GOP_1GS1_DRAM_FADE GOP_REG(GOP_1GS1_OFST+1, 0x16) 760 #define GOP_1GS1_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x1E) 761 #define GOP_1GS1_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x1F) 762 //------------------------------------------------------------------------------------------------- 763 // Type and Structure 764 //------------------------------------------------------------------------------------------------- 765 766 //---------------------------------------------------------------------------- 767 // GOP Test Pattern Reg 768 //---------------------------------------------------------------------------- 769 #define REG_TSTCLR_EN GOP_REG(GOP_4G_OFST, 0x00) 770 #define REG_TSTCLR_ALPHA_EN GOP_REG(GOP_4G_OFST+2, 0x00) 771 #define REG_TLB_TAG_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x2C) 772 #define REG_TLB_TAG_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x2D) 773 #define REG_TLB_TAG_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x2E) 774 #define REG_TLB_TAG_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x2F) 775 #define REG_TSTCLR_ALPHA GOP_REG(GOP_4G_OFST+2, 0x40) 776 #define REG_R_STC GOP_REG(GOP_4G_OFST+2, 0x41) 777 #define REG_G_STC GOP_REG(GOP_4G_OFST+2, 0x48) 778 #define REG_B_STC GOP_REG(GOP_4G_OFST+2, 0x49) 779 #define REG_TSTCLR_HDUP GOP_REG(GOP_4G_OFST+2, 0x01) 780 #define REG_TSTCLR_VDUP GOP_REG(GOP_4G_OFST+2, 0x01) 781 #define REG_HR_INC GOP_REG(GOP_4G_OFST+2, 0x42) 782 #define REG_HR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x42) 783 #define REG_HG_INC GOP_REG(GOP_4G_OFST+2, 0x43) 784 #define REG_HG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x43) 785 #define REG_HB_INC GOP_REG(GOP_4G_OFST+2, 0x44) 786 #define REG_HB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x44) 787 #define REG_HR_STEP GOP_REG(GOP_4G_OFST+2, 0x4A) 788 #define REG_HG_STEP GOP_REG(GOP_4G_OFST+2, 0x4B) 789 #define REG_HB_STEP GOP_REG(GOP_4G_OFST+2, 0x4C) 790 #define REG_VR_INC GOP_REG(GOP_4G_OFST+2, 0x45) 791 #define REG_VR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x45) 792 #define REG_VG_INC GOP_REG(GOP_4G_OFST+2, 0x46) 793 #define REG_VG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x46) 794 #define REG_VB_INC GOP_REG(GOP_4G_OFST+2, 0x47) 795 #define REG_VB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x47) 796 #define REG_VR_STEP GOP_REG(GOP_4G_OFST+2, 0x4D) 797 #define REG_VG_STEP GOP_REG(GOP_4G_OFST+2, 0x4E) 798 #define REG_VB_STEP GOP_REG(GOP_4G_OFST+2, 0x4F) 799 #define REG_TLB_BASE_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x58) 800 #define REG_TLB_BASE_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x59) 801 #define REG_TLB_BASE_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x5A) 802 #define REG_TLB_BASE_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x5B) 803 804 #define MASK_TSTCLR_EN GOP_BIT6 805 #define MASK_TSTCLR_ALPHA_EN GOP_BIT1 806 #define MASK_TSTCLR_ALPHA BMASK(11:8)|BMASK(3:0) 807 #define MASK_RGB_STC_VALID BMASK(7:0) 808 #define MASK_R_STC BMASK(11:8)|BMASK(3:0) 809 #define MASK_G_STC BMASK(11:8)|BMASK(3:0) 810 #define MASK_B_STC BMASK(11:8)|BMASK(3:0) 811 #define MASK_INI_TSTCLR_EN GOP_BIT0 812 #define MASK_TSTCLR_HDUP BMASK(3:2) 813 #define MASK_TSTCLR_VDUP BMASK(1:0) 814 #define MASK_HR_INC BMASK(10:8)|BMASK(3:0) 815 #define MASK_HR_INC_SIGNZ GOP_BIT11 816 #define MASK_HG_INC BMASK(10:8)|BMASK(3:0) 817 #define MASK_HG_INC_SIGNZ GOP_BIT11 818 #define MASK_HB_INC BMASK(10:8)|BMASK(3:0) 819 #define MASK_HB_INC_SIGNZ GOP_BIT11 820 #define MASK_HR_STEP BMASK(11:8)|BMASK(3:0) 821 #define MASK_HG_STEP BMASK(11:8)|BMASK(3:0) 822 #define MASK_HB_STEP BMASK(11:8)|BMASK(3:0) 823 #define MASK_VR_INC BMASK(10:8)|BMASK(3:0) 824 #define MASK_VR_INC_SIGNZ GOP_BIT11 825 #define MASK_VG_INC BMASK(10:8)|BMASK(3:0) 826 #define MASK_VG_INC_SIGNZ GOP_BIT11 827 #define MASK_VB_INC BMASK(10:8)|BMASK(3:0) 828 #define MASK_VB_INC_SIGNZ GOP_BIT11 829 #define MASK_VR_STEP BMASK(11:8)|BMASK(3:0) 830 #define MASK_VG_STEP BMASK(11:8)|BMASK(3:0) 831 #define MASK_VB_STEP BMASK(11:8)|BMASK(3:0) 832 833 #define SHIFT_TSTCLR_EN 6 834 #define SHIFT_TSTCLR_ALPHA_EN 1 835 #define SHIFT_TSTCLR_ALPHA 8 836 #define SHIFT_R_STC 0 837 #define SHIFT_G_STC 0 838 #define SHIFT_B_STC 0 839 #define SHIFT_INI_TSTCLR_EN 0 840 #define SHIFT_TSTCLR_HDUP 2 841 #define SHIFT_TSTCLR_VDUP 0 842 #define SHIFT_HR_INC 0 843 #define SHIFT_HR_INC_SIGNZ 11 844 #define SHIFT_HG_INC 0 845 #define SHIFT_HG_INC_SIGNZ 11 846 #define SHIFT_HB_INC 0 847 #define SHIFT_HB_INC_SIGNZ 11 848 #define SHIFT_HR_STEP 0 849 #define SHIFT_HG_STEP 0 850 #define SHIFT_HB_STEP 0 851 #define SHIFT_VR_INC 0 852 #define SHIFT_VR_INC_SIGNZ 11 853 #define SHIFT_VG_INC 0 854 #define SHIFT_VG_INC_SIGNZ 11 855 #define SHIFT_VB_INC 0 856 #define SHIFT_VB_INC_SIGNZ 11 857 #define SHIFT_VR_STEP 0 858 #define SHIFT_VG_STEP 0 859 #define SHIFT_VB_STEP 0 860 861 862 //---------------------------------------------------------------------------- 863 // GOP AFBC Reg 864 //---------------------------------------------------------------------------- 865 #define REG_AFBC_CORE_EN(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x00+(0x20*id)) 866 #define REG_AFBC_ADDR_L(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x01+(0x20*id)) 867 #define REG_AFBC_ADDR_H(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x02+(0x20*id)) 868 #define REG_AFBC_FMT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0C+(0x20*id)) 869 #define REG_AFBC_WIDTH(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0A+(0x20*id)) 870 #define REG_AFBC_HEIGHT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0B+(0x20*id)) 871 #define REG_AFBC_RESP(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0F+(0x20*id)) 872 #define REG_AFBC_PRELOAD GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x30) 873 #define REG_AFBC_MIU GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x43) 874 #define REG_AFBC_DEBUG(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x44+(0x20*id)) 875 #define REG_AFBC_READCNT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x4C+(0x20*id)) 876 #define REG_AFBC_TRIGGER GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x50) 877 878 #endif // _REG_GOP_H_ 879