1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #include <string.h>
97 #include "MsTypes.h"
98 #include "halGOP.h"
99 #include "regGOP.h"
100 #include "halCHIP.h"
101 #include "drvSYS.h"
102
103
104 //------------------------------------------------------------------------------
105 // Driver Compiler Options
106 //------------------------------------------------------------------------------
107 #define HAL_GOP_DEBUGINFO(x) //x
108
109 //------------------------------------------------------------------------------
110 // Local Defines
111 //------------------------------------------------------------------------------
112 #define RIU ((unsigned short volatile *) pGOPHalLocal->u32_mmio_base)
113 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
114 #define GOP_READ2BYTE(addr) RIU[addr]
115 #define GOP_BANK_MASK 0x0F
116
117
118 //------------------------------------------------------------------------------
119 // Local Var
120 //------------------------------------------------------------------------------
121 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
122 {
123 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
124 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
125 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
126 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 2 */
127 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 3 */
128
129 };
130
131
132 GOP_CHIP_PROPERTY g_GopChipPro =
133 {
134 .bSetHSyncInverse = TRUE,
135 .bGop1GPalette = FALSE,
136 .bSetHPipeOfst = FALSE,
137 .bNeedCheckMVOP = FALSE,
138 .bNeedSetMUX1ToIP0 = TRUE,
139 .bNeedSetMUX3ToIP0 = FALSE,
140 .bNewMux = FALSE,
141 .bNewPalette = FALSE,
142 .bNewBwReg = TRUE,
143 .bGop2VStretch = TRUE,
144 .bIgnoreIPHPD = FALSE, //Uranus4 has handshack with XC, should not set HPD
145 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
146 .bhastilemode = FALSE,
147 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
148 .bAutoAdjustMirrorHSize = FALSE, //whether hw will auto adjust start addr when H mirror is enable
149 .bGOPWithVscale = {TRUE, TRUE, TRUE, TRUE}, //setting GOP with/without Vscale
150 .DwinVer = 0x1,
151 .bTstPatternAlpha = FALSE,
152 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
153 .bFRCSupport = FALSE, /*OC path*/
154 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
155 .bBnkForceWrite = FALSE, /*Direct Bank Force Write*/
156 .bPixelModeSupport = FALSE, /*Pixel Mode Support*/
157 .bScalingDownSupport= FALSE,
158 .b2Pto1PSupport= FALSE,
159 .bTLBSupport= {TRUE, FALSE, TRUE, FALSE, FALSE, FALSE},
160 .GOP_TestPattern_Vaild= E_GOP2,
161
162 #ifdef ENABLE_GOP_T3DPATCH
163 .GOP_PD = GOP_PD_T3D,
164 #else
165 .GOP_PD = 0x114,
166 #endif
167 .GOP_IP_PD = (-0x3),
168 .GOP_MVOP_PD = 0x6E,
169 .GOP_VE_PD = 0x89,
170 .GOP_MIXER_PD = 0x0,
171 .GOP_NonVS_PD_Offset = 0x0, //GOP without Vsacle might need add offset on pipedelay
172 .GOP_VE_V_Offset = 0x0,
173 .GOP_UHD_PD_Offset = 0x0,
174
175 .GOP_MUX_Delta = 0x1,
176 .GOP_Mux_Offset = {0x0, 0xF, 0x9, 0xC},
177 .GOP_Mux_FRC_offset= 0x0,
178 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX1},
179 .WordUnit = GOP_WordUnit,
180 .TotalGwinNum = GOP_TotalGwinNum,
181 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
182 .enGOP3DType = E_DRV_3D_DUP_HALF,
183 };
184
185
186 //------------------------------------------------------------------------------
187 // Global Functions
188 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)189 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
190 {
191 GOP_TYPE->GOP0 = E_GOP0;
192 GOP_TYPE->GOP1 = E_GOP1;
193 GOP_TYPE->GOP2 = E_GOP2;
194 GOP_TYPE->GOP3 = E_GOP3;
195 GOP_TYPE->GOP4 = E_GOP4;
196 GOP_TYPE->GOP5 = E_GOP5;
197 GOP_TYPE->DWIN = E_GOP_Dwin;
198 GOP_TYPE->MIXER = E_GOP_MIXER;
199 }
200
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)201 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
202 {
203 MS_U32 u32BankOffSet = 0;
204
205 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
206
207 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
208 {
209 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
210 }
211 else
212 {
213 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
214 }
215
216 return GOP_SUCCESS;
217 }
218
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)219 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
220 {
221 MS_U32 u32BankOffSet =0;
222 MS_U32 u32BitMask=0,Regval=0;
223
224 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
225
226 switch(pinpon_mode)
227 {
228 case E_DRV_GOP_PINPON_G3D:
229 Regval = bEn << 5;
230 u32BitMask = GOP_BIT5;
231 break;
232 case E_DRV_GOP_PINPON_DWIN:
233 Regval = bEn << 6;
234 u32BitMask = GOP_BIT6;
235 break;
236 case E_DRV_GOP_PINPON_DIP:
237 Regval = bEn << 7;
238 u32BitMask = GOP_BIT7;
239 break;
240 default:
241 break;
242 }
243
244 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
245 return GOP_SUCCESS;
246 }
247
248
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)249 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
250 {
251 if (gop==0)
252 *pBnkOfst = GOP_4G_OFST<<16;
253 else if (gop==1)
254 *pBnkOfst = GOP_2G_OFST<<16;
255 else if (gop==2)
256 *pBnkOfst = GOP_1G_OFST<<16;
257 else if (gop==3)
258 *pBnkOfst = GOP_1GX_OFST<<16;
259 else if (gop==4)
260 *pBnkOfst = GOP_DW_OFST<<16;
261 else
262 return FALSE;
263
264 return TRUE;
265 }
266
HAL_GOP_GWIN_IsNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP)267 MS_BOOL HAL_GOP_GWIN_IsNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP)
268 {
269 return FALSE;
270 }
271
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)272 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
273 {
274 MS_U16 u16Mask = 0;
275
276 if (u16GopMask&GOP_BIT0)
277 {
278 u16Mask |= GOP_BIT12;
279 }
280 if (u16GopMask&GOP_BIT1)
281 {
282 u16Mask |= GOP_BIT13;
283 }
284 if (u16GopMask&GOP_BIT2)
285 {
286 u16Mask |= GOP_BIT15;
287 }
288 if (u16Mask != 0)
289 {
290 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask);
291 }
292
293 return GOP_SUCCESS;
294 }
295
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)296 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
297 {
298 switch(gop)
299 {
300 case E_GOP0:
301 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
302 break;
303 case E_GOP1:
304 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
305 break;
306 case E_GOP2:
307 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
308 break;
309 default:
310 break;
311 }
312 return GOP_SUCCESS;
313 }
314
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)315 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
316 {
317 MS_U16 u16GopAck = 0,reg_val =0;
318 switch(gop)
319 {
320 case E_GOP0:
321 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
322 if(reg_val&0x1000)
323 u16GopAck = FALSE;
324 else
325 u16GopAck = TRUE;
326 break;
327 case E_GOP1:
328 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
329 if(reg_val&0x2000)
330 u16GopAck = FALSE;
331 else
332 u16GopAck = TRUE;
333 break;
334 case E_GOP2:
335 case E_GOP3:
336 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
337 if(reg_val&0x8000)
338 u16GopAck = FALSE;
339 else
340 u16GopAck = TRUE;
341 break;
342 case E_GOP_Dwin:
343 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
344 if(reg_val&0x4000)
345 u16GopAck = FALSE;
346 else
347 u16GopAck = TRUE;
348 break;
349 default:
350 break;
351 }
352 return u16GopAck;
353 }
354
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)355 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
356 {
357 return GOP_FUN_NOT_SUPPORTED;
358 }
359
360 MS_BOOL bAddOffset = FALSE;
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)361 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
362 {
363 MS_U32 u32bankoff = 0;
364 MS_U16 chipid=0;
365 const SYS_Info *sys_info = NULL;
366
367 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
368 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15 ); //use new BW mode, enable couple LB
369 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, GOP_FIFO_BURST_ALL, GOP_FIFO_BURST_MASK ); //set GOP DMA Burst length to "32"
370 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, GOP_FIFO_THRESHOLD, GOP_REG_LW_MASK ); //set DMA FIFO threshold to 3/4 FIFO length
371 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, 0x200); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
372 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_DUMMY_22, 0x0, 0x200); //0: Vsync will use the same pipe delay as Hsync
373
374 chipid=MDrv_SYS_GetChipID();
375 sys_info=MDrv_SYS_GetInfo();
376 if( ( bAddOffset == FALSE ) && ( chipid == CHIPID_MUNICH_SERIES ) && ( sys_info->Chip.Version == CHIPVER_MALDIVES ) ){
377 pGOPHalLocal->pGopChipPro->GOP_PD += MALDIVES_PD_OFFSET;
378 bAddOffset = TRUE;
379 }
380 }
381
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)382 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
383 {
384 *pGOPHalLocal->pGopChipPro = g_GopChipPro;
385 }
386
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)387 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
388 {
389 if (u8GopNum==0)
390 {
391 return (MS_U8)MAX_GOP0_GWIN;
392 }
393 else if (u8GopNum==1)
394 {
395 return (MS_U8)MAX_GOP1_GWIN;
396 }
397 else if (u8GopNum==2)
398 {
399 return (MS_U8)MAX_GOP2_GWIN;
400 }
401 else if (u8GopNum==3)
402 {
403 return (MS_U8)MAX_GOP3_GWIN;
404 }
405 else
406 {
407 MS_ASSERT(0);
408 return 0xFF;
409 }
410 }
411
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)412 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
413 {
414 MS_U8 u8GWinId = 0;
415
416 //Adjust GWIN ID by different Chip
417
418 switch(u8Gop)
419 {
420 case E_GOP0:
421 u8GWinId = GOP0_GwinIdBase + u8Idx;
422 break;
423 case E_GOP1:
424 u8GWinId = GOP1_GwinIdBase + u8Idx;
425 break;
426 case E_GOP2:
427 u8GWinId = GOP2_GwinIdBase + u8Idx;
428 break;
429 case E_GOP3:
430 u8GWinId = GOP3_GwinIdBase + u8Idx;
431 break;
432 default:
433 break;
434 }
435 return u8GWinId;
436
437 }
438
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)439 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
440 {
441 switch(u8GOPNum)
442 {
443 case 0: // GOP4G
444 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
445 return GOP_SUCCESS;
446 case 1: // GOP2G
447 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
448 return GOP_SUCCESS;
449 case 2: // GOP1G
450 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
451 return GOP_SUCCESS;
452 case 3: // GOP1GX
453 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
454 return GOP_SUCCESS;
455 case 4: // GOPDWX
456 pGOPHalLocal->bank_offset = GOP_DW_OFST<<16;
457 return GOP_SUCCESS;
458 default:
459 MS_ASSERT(0);
460 return GOP_FAIL;
461 }
462 }
463
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)464 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
465 {
466 MS_U16 u16Bank;
467 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
468 u16Bank &= ~GOP_BANK_MASK;
469 u16Bank |= (u8bank&GOP_BANK_MASK);
470 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
471 }
472
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)473 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
474 {
475 MS_U16 u16GetBank;
476 u16GetBank = GOP_READ2BYTE(GOP_BAK_SEL);
477 return (u16GetBank&GOP_BANK_MASK);
478 }
479
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)480 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
481 {
482 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
483 MS_U32 bank;
484 MS_U32 direct_addr;
485
486 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
487
488 //* Gop driver should access another HW IP register
489 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
490 switch (u32addr & 0xFF00)
491 {
492 case GOP_REG_BASE:
493 {
494 bank = (u32addr & 0xF0000) >> 8;
495 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
496 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
497 break;
498 }
499 case SC1_REG_BASE:
500 {
501 if(g_GopChipPro.bXCDirrectBankSupport)
502 {
503 u16xcSubbank = (u32addr & 0xFF0000)>>8;
504 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
505 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
506 }
507 else
508 {
509 u16xcSubbank = (u32addr & 0xFF0000)>>16;
510 u16BankAddr = GOP_SC_BANKSEL+0;
511 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
512
513 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
514 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
515 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
516 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
517 }
518 break;
519 }
520 case GE_REG_BASE:
521 case CKG_REG_BASE:
522 case MIU_REG_BASE:
523 case MVOP_REG_BASE:
524 {
525 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
526 break;
527 }
528 default:
529 {
530 //Gop lib current do not support this HW ip base
531 MS_ASSERT(0);
532 *pu16ret =0;
533 break;
534 }
535 }
536 }
537
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)538 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
539 {
540 MS_U16 u16tmp=0;
541 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
542 MS_U32 bank;
543 MS_U32 direct_addr;
544
545 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u16addr, u16val));
546
547 if(mask!=0xffff)
548 {
549 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
550 u16tmp &= ~mask;
551 u16val &= mask;
552 u16val |= u16tmp;
553 }
554
555 //* Gop driver should access another HW IP register
556 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
557 switch (u32addr & 0xFF00)
558 {
559 case GOP_REG_BASE:
560 {
561 bank = (u32addr & 0xF0000) >> 8;
562 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
563 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
564 break;
565 }
566 case SC1_REG_BASE:
567 if(g_GopChipPro.bXCDirrectBankSupport)
568 { /*Derrick Bank*/
569 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
570 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
571 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
572 }
573 else
574 { /*Sub Bank*/
575 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
576 u16BankAddr = GOP_SC_BANKSEL+0;
577 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
578
579 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
580 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
581 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
582 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
583 }
584 break;
585 case GE_REG_BASE:
586 case CKG_REG_BASE:
587 case MIU_REG_BASE:
588 {
589 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
590 break;
591 }
592
593 default:
594 {
595 //Gop lib current do not support this HW ip base
596 MS_ASSERT(0);
597 break;
598 }
599
600 }
601 }
602
603
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)604 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
605 {
606 MS_U32 bank;
607 MS_U32 direct_addr;
608
609 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
610
611 //* Gop driver should access another HW IP register
612 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
613 switch (u32addr & 0xFF00)
614 {
615 case GOP_REG_BASE:
616 {
617 bank = (u32addr & 0xF0000) >> 8;
618 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
619 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
620 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
621 break;
622 }
623
624 case GE_REG_BASE:
625 case SC1_REG_BASE:
626 case CKG_REG_BASE:
627 {
628 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
629 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
630 break;
631 }
632
633 default:
634 {
635 //Gop lib current do not support this HW ip base
636 MS_ASSERT(0);
637 break;
638 }
639
640 }
641 }
642
643 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
644
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)645 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
646 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
647 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
648 {
649 MS_U8 i=0;
650 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",
651 u8Index, u8A, u8R, u8G, u8B));
652 /* Don't care high byte */
653 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
654
655 for(i =(GOP_WordUnit-1);i>4;i--)
656 {
657 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
658 }
659 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
660 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
661 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
662 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
663 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
664 *pREGMAP_Offset += GOP_WordUnit;
665
666 MsOS_FlushMemory(); //make sure cpu write data to dram
667
668 }
669
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)670 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
671 {
672 MS_U16 bpp=0;
673
674 switch ( fbFmt )
675 {
676 case E_DRV_GOP_COLOR_RGB555_BLINK :
677 case E_DRV_GOP_COLOR_RGB565 :
678 case E_DRV_GOP_COLOR_ARGB1555:
679 case E_DRV_GOP_COLOR_RGBA5551:
680 case E_DRV_GOP_COLOR_ARGB4444 :
681 case E_DRV_GOP_COLOR_RGBA4444 :
682 case E_DRV_GOP_COLOR_RGB555YUV422:
683 case E_DRV_GOP_COLOR_YUV422:
684 case E_DRV_GOP_COLOR_2266:
685 bpp = 16;
686 break;
687 case E_DRV_GOP_COLOR_ARGB8888 :
688 case E_DRV_GOP_COLOR_ABGR8888 :
689 bpp = 32;
690 break;
691
692 case E_DRV_GOP_COLOR_I8 :
693 bpp = 8;
694 break;
695
696 default :
697 //print err
698 MS_ASSERT(0);
699 bpp = 0xFFFF;
700 break;
701 }
702 return bpp;
703
704 }
705
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)706 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
707 {
708 MS_U16 regval;
709 /*For compatibility
710 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
711 MS_U8 u8coef_cpt = u8coef;
712
713 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
714 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
715 {
716 switch(u8coef)
717 {
718 case 0x0 :
719 u8coef_cpt = u8coef<<2;
720 break;
721 case 0x3f :
722 u8coef_cpt = ((u8coef<<2)|0x3);
723 break;
724 default:
725 u8coef_cpt = ((u8coef<<2)|0x1);
726 break;
727 }
728 }
729
730 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
731 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
732 {
733 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef_cpt&0xFC)<<6);
734 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x7f00);
735 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), (u8coef_cpt&0x03), 0x03);
736 }
737 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
738 else
739 {
740 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
741 {
742 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef_cpt&0xFC)<<6);
743 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x7f00);
744 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, (u8coef&0x03), 0x03);
745 }
746 else
747 {
748 printf("[%s]ERROR Invalid GwinID %d\n",__FUNCTION__,u8win);
749 }
750 }
751 }
752
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 addr)753 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 addr)
754 {
755 pGOPHalLocal->u32_mmio_base = addr;
756 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 addr)757 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 addr)
758 {
759 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 addr)760 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 addr)
761 {
762 }
763
764
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)765 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
766 {
767 /* GOP dst type:
768 0: IP (Main)
769 1: IP (Sub)
770 2: OP
771 3: MVOP
772 */
773 MS_U16 u16RegVal;
774
775 switch (eDstType)
776 {
777 case E_DRV_GOP_DST_IP0:
778 u16RegVal = 0x0;
779 break;
780
781 case E_DRV_GOP_DST_IP0_SUB:
782 u16RegVal = 0x1;
783 break;
784
785 case E_DRV_GOP_DST_OP0:
786 u16RegVal = 0x2;
787 break;
788
789 case E_DRV_GOP_DST_VOP:
790 u16RegVal = 0x3;
791 break;
792
793 default:
794 return GOP_FUN_NOT_SUPPORTED;
795 }
796
797 if(bOnlyCheck == FALSE)
798 {
799 if (GopNum==0)
800 {
801 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_CTRL1, u16RegVal, 0x0007);
802 return GOP_SUCCESS;
803 }
804 else if (GopNum==1)
805 {
806 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_CTRL1, u16RegVal, 0x0007);
807 return GOP_SUCCESS;
808 }
809 else if (GopNum==2)
810 {
811 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_CTRL1, u16RegVal, 0x0007);
812 return GOP_SUCCESS;
813 }
814 else if (GopNum==3)
815 {
816 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_CTRL1, u16RegVal, 0x0007);
817 return GOP_SUCCESS;
818 }
819 else
820 {
821 return GOP_INVALID_PARAMETERS;
822 }
823 }
824 return GOP_SUCCESS;
825 }
826
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)827 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
828 {
829 return GOP_FUN_NOT_SUPPORTED;
830 }
831
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)832 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
833 {
834 return GOP_FUN_NOT_SUPPORTED;
835 }
836
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)837 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
838 {
839 /*
840 OP path: support 4 mux (mux0/1/2/3) to blend with SC simultaneously
841 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
842 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
843 */
844 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3;
845 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
846 return GOP_SUCCESS;
847 }
848
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)849 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
850 {
851 MS_U16 u16GopMux=0;
852 if(eGopMux <4)
853 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
854 else
855 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
856
857 *u8GOPNum = (u16GopMux >> ((eGopMux%4)*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
858 }
859
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)860 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
861 {
862 switch(eGopMux)
863 {
864 case E_GOP_MUX0:
865 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
866 break;
867 case E_GOP_MUX1:
868 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
869 break;
870 case E_GOP_MUX2:
871 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
872 break;
873 case E_GOP_MUX3:
874 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
875 break;
876 case E_GOP_IP0_MUX:
877 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
878 break;
879 case E_GOP_IP1_MUX:
880 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_SUB_MUX_SHIFT, GOP_IP_SUB_MUX_MASK);
881 break;
882 case E_GOP_VOP0_MUX:
883 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
884 break;
885 case E_GOP_VOP1_MUX:
886 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
887 break;
888 default:
889 printf("[%s]ERROR mux setting\n",__FUNCTION__);
890 break;
891 }
892 }
893
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)894 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
895 {
896 /* GOP OP Path enable to SC Setting
897 : GOP OP Path blending with SC sequence
898 */
899 MS_U16 muxValue=0, regval=0;
900
901 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
902 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
903
904 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
905 {
906 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x8000):(regval & ~0x8000), 0x8000);
907 }
908 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
909 {
910 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x4000):(regval & ~0x4000), 0x4000);
911 }
912 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
913 {
914 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x2000):(regval & ~0x2000), 0x2000);
915 }
916 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
917 {
918 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |0x1000):(regval & ~0x1000), 0x1000);
919 }
920 else
921 {
922 return GOP_FAIL;
923 }
924 return GOP_SUCCESS;
925 }
926
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)927 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
928 {
929 return GOP_FUN_NOT_SUPPORTED;
930 }
931
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)932 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
933 {
934 /* GOP OP Path enable to SC Setting
935 A5: GOP OP Path blending with SC sequence
936 mux1-->mux0-->mux2-->mux3
937 */
938 MS_U16 muxValue=0, regval=0;
939
940 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
941 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
942 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
943 {
944 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
945 }
946 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
947 {
948 //printf("");
949 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
950 }
951 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
952 {
953 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
954 }
955 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
956 {
957 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
958 }
959 else
960 {
961 return GOP_FAIL;
962 }
963 return GOP_SUCCESS;
964 }
965
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)966 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
967 {
968 MS_U16 muxValue=0, regval=0;
969
970 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
971 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
972 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
973 {
974 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
975 }
976 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
977 {
978 *pbEnable = (regval & GOP_BIT12) == GOP_BIT12;
979 }
980 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
981 {
982 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
983 }
984 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
985 {
986 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
987 }
988 else
989 {
990 return GOP_FAIL;
991 }
992 return GOP_SUCCESS;
993 }
994
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)995 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
996 {
997 MS_U16 MuxGop, muxValue=0, i;
998 MS_U16 MuxShift;
999
1000 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX1;
1001
1002 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1003 for (i=0; i<MAX_GOP_MUX;i++)
1004 {
1005 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1006 {
1007 MuxGop = (muxValue&GOP_MUX1_MASK)>> MuxShift; //save mux1 gop
1008
1009 muxValue &= ~GOP_MUX1_MASK; //clear mux1 setting
1010 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1011 muxValue |= ((gopNum<< MuxShift)|(MuxGop<<(i*GOP_MUX_SHIFT)));
1012 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1013 break;
1014 }
1015 }
1016
1017 return GOP_SUCCESS;
1018 }
1019
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1020 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1021 {
1022 /* GOP dst type:
1023 0: IP (Main)
1024 1: IP (Sub)
1025 2: OP
1026 3: MVOP
1027 */
1028
1029 switch(eDstType)
1030 {
1031 case E_DRV_GOP_DST_IP0:
1032
1033 if (gopNum==1)
1034 {
1035 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1036 }
1037 else if (gopNum ==2)
1038 {
1039 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1040 }
1041 else if (gopNum ==3)
1042 {
1043 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG2_MASK);
1044 }
1045 else if (gopNum==0)
1046 {
1047 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1048 }
1049 else
1050 {
1051 MS_ASSERT(0);
1052 return GOP_INVALID_PARAMETERS;
1053 }
1054 break;
1055
1056 case E_DRV_GOP_DST_IP0_SUB:
1057 if (gopNum==1)
1058 {
1059 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1060 }
1061 else if (gopNum==2)
1062 {
1063 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1064 }
1065 else if (gopNum==3)
1066 {
1067 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG2_MASK);
1068 }
1069 else if (gopNum==0)
1070 {
1071 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1072 }
1073 else
1074 {
1075 MS_ASSERT(0);
1076 return GOP_INVALID_PARAMETERS;
1077 }
1078 break;
1079
1080
1081 case E_DRV_GOP_DST_OP0:
1082 if (gopNum==1)
1083 {
1084 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1085 }
1086 else if (gopNum==2)
1087 {
1088 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1089 }
1090 else if (gopNum==3)
1091 {
1092 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG2_MASK);
1093 }
1094 else if (gopNum==0)
1095 {
1096 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1097 }
1098 else
1099 {
1100 MS_ASSERT(0);
1101 return GOP_INVALID_PARAMETERS;
1102 }
1103
1104 break;
1105
1106 case E_DRV_GOP_DST_VOP:
1107 if (gopNum==1)
1108 {
1109 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1110 }
1111 else if (gopNum ==2)
1112 {
1113 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1114 }
1115 else if (gopNum ==3)
1116 {
1117 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_IDCLK2, CKG_GOPG2_MASK);
1118 }
1119 else if (gopNum==0)
1120 {
1121 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1122 }
1123 else
1124 {
1125 MS_ASSERT(0);
1126 return GOP_INVALID_PARAMETERS;
1127 }
1128
1129 break;
1130 default:
1131 MS_ASSERT(0);
1132 return GOP_ENUM_NOT_SUPPORTED;
1133 }
1134 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1135 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1136
1137 return GOP_SUCCESS;
1138 }
1139
1140
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1141 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1142 {
1143 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1144 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1145 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1146 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1147 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1148 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1149 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1150 else
1151 return GOP_INVALID_PARAMETERS;
1152
1153 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1154 return GOP_SUCCESS;
1155 }
1156
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1157 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1158 {
1159 if (bEnable)
1160 {
1161 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1162 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1163 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1164 }
1165 else
1166 {
1167 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1168 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1169 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1170 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1171 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1172 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1173 }
1174
1175 return GOP_SUCCESS;
1176 }
1177
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1178 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1179 {
1180 return GOP_FUN_NOT_SUPPORTED;
1181 }
1182
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)1183 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
1184 {
1185 return GOP_FUN_NOT_SUPPORTED;
1186 }
1187
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)1188 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
1189 {
1190 return GOP_FUN_NOT_SUPPORTED;
1191 }
1192
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)1193 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
1194 {
1195 MS_U32 u32GopIdx;
1196
1197 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
1198 pGOPHalLocal->pHALShared = pHALShared;
1199
1200 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
1201 {
1202 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
1203 }
1204 pGOPHalLocal->pGopChipPro = &pHALShared->gopChipProperty;
1205 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
1206 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1207 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1208 {
1209 }
1210
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_U32 * u32Adr)1211 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_U32* u32Adr)
1212 {
1213 MS_U16 u16RegVal=0;
1214
1215 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
1216 if (gwinid<MAX_GOP0_GWIN) //gop0
1217 {
1218 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP0))==BIT(GOP_MIU_CLIENT_GOP0)) //MIU1
1219 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1220 }
1221 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
1222 {
1223 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP1))==BIT(GOP_MIU_CLIENT_GOP1)) //MIU1
1224 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1225 }
1226 else if (gwinid==(MAX_GOP0_GWIN+MAX_GOP1_GWIN)) //gop2
1227 {
1228 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP2))==BIT(GOP_MIU_CLIENT_GOP2)) //MIU1
1229 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1230 }
1231 else if (gwinid==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)) //gop3
1232 {
1233 if ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP3))==BIT(GOP_MIU_CLIENT_GOP3)) //MIU1
1234 * u32Adr = (* u32Adr|HAL_MIU1_BASE);
1235 }
1236 else
1237 {
1238 return GOP_FAIL;
1239 }
1240 return GOP_SUCCESS;
1241 }
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)1242 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
1243 {
1244 MS_U16 u16RegVal=0;
1245
1246 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
1247
1248 switch (gopnum)
1249 {
1250 case 0:
1251 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP0))==BIT(GOP_MIU_CLIENT_GOP0)? MIU_1:MIU_0);
1252 break;
1253
1254 case 1:
1255 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP1))==BIT(GOP_MIU_CLIENT_GOP1)? MIU_1:MIU_0);
1256 break;
1257
1258 case 2:
1259 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP2))==BIT(GOP_MIU_CLIENT_GOP2)? MIU_1:MIU_0);
1260 break;
1261
1262 case 3:
1263 return ((u16RegVal&BIT(GOP_MIU_CLIENT_GOP3))==BIT(GOP_MIU_CLIENT_GOP3)? MIU_1:MIU_0);
1264 break;
1265 default:
1266 return 0xff;
1267 break;
1268 }
1269 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)1270 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
1271 {
1272 MS_U16 u16Regval=0;
1273 MS_U32 u32pBankOffSet=0;
1274 GOP_Result ret;
1275
1276 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
1277 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
1278
1279 switch (u16Regval&0x3)
1280 {
1281 case 0:
1282 *pGopDst = E_DRV_GOP_DST_IP0;
1283 ret = GOP_SUCCESS;
1284 break;
1285 case 1:
1286 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
1287 ret = GOP_SUCCESS;
1288 break;
1289 case 2:
1290 *pGopDst = E_DRV_GOP_DST_OP0;
1291 ret = GOP_SUCCESS;
1292 break;
1293 case 3:
1294 *pGopDst = E_DRV_GOP_DST_VOP;
1295 ret = GOP_SUCCESS;
1296 break;
1297 default:
1298 *pGopDst = E_DRV_GOP_DST_INVALID;
1299 ret = GOP_FAIL;
1300 break;
1301 }
1302
1303 return ret;
1304
1305 }
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)1306 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
1307 {
1308 MS_U16 muxValue=0;
1309 MS_U16 u16RegVal= 0, u16RegMsk = 0;
1310
1311 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1312
1313 switch(ipSelGop)
1314 {
1315 case MS_DRV_IP0_SEL_GOP0:
1316 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1317 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
1318 u16RegVal |= GOP_BIT12;//mux0
1319 else
1320 u16RegVal |= GOP_BIT13;//mux1
1321 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1322 break;
1323 case MS_DRV_IP0_SEL_GOP1:
1324 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1325 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
1326 u16RegVal |= GOP_BIT12;//mux0
1327 else
1328 u16RegVal |= GOP_BIT13;//mux1
1329 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1330 break;
1331 case MS_DRV_IP0_SEL_GOP2:
1332 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1333 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
1334 u16RegVal |= GOP_BIT12;//mux0
1335 else
1336 u16RegVal |= GOP_BIT13;//mux1
1337 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1338 break;
1339 case MS_DRV_NIP_SEL_GOP0:
1340 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
1341 {
1342 u16RegVal = ~GOP_BIT12;//mux0
1343 u16RegMsk = GOP_BIT12;
1344 }
1345 else
1346 {
1347 u16RegVal = ~GOP_BIT13;//mux1
1348 u16RegMsk = GOP_BIT13;
1349 }
1350 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1351 break;
1352 case MS_DRV_NIP_SEL_GOP1:
1353 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
1354 {
1355 u16RegVal = ~GOP_BIT12;//mux0
1356 u16RegMsk = GOP_BIT12;
1357 }
1358 else
1359 {
1360 u16RegVal = ~GOP_BIT13;//mux1
1361 u16RegMsk = GOP_BIT13;
1362 }
1363 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1364 break;
1365 case MS_DRV_NIP_SEL_GOP2:
1366 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
1367 {
1368 u16RegVal = ~GOP_BIT12;//mux0
1369 u16RegMsk = GOP_BIT12;
1370 }
1371 else
1372 {
1373 u16RegVal = ~GOP_BIT13;//mux1
1374 u16RegMsk = GOP_BIT13;
1375 }
1376 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
1377 break;
1378 case MS_DRV_MVOP_SEL:
1379 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
1380 u16RegVal |= GOP_BIT12; //mux0
1381 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
1382 break;
1383 default:
1384 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
1385 break;
1386 }
1387 if(0 != u16RegMsk)
1388 {
1389 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
1390 }
1391 }
1392
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1393 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1394 {
1395 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1396 {
1397 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, 0, (GOP_BIT8|GOP_BIT9));
1398 }
1399 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1400 {
1401 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, (GOP_BIT8|GOP_BIT9), (GOP_BIT8|GOP_BIT9));
1402 }
1403 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1404 {
1405 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_CTL0_EN, (GOP_BIT8), (GOP_BIT8|GOP_BIT9));
1406 //enable scaler IP.
1407 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT12, GOP_BIT12|GOP_BIT13);
1408 // set GOPD to scaler ip OUT
1409 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, GOP_BIT15, GOP_BIT15);
1410 }
1411 else
1412 {
1413 return GOP_INVALID_PARAMETERS;
1414 }
1415
1416 return GOP_SUCCESS;
1417 }
1418
1419
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1420 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1421 {
1422 MS_U16 u16RegVal=0;
1423 MS_U16 mask_shift=0;
1424
1425
1426 if (GOP_MIU_CLIENT_DWIN >=0x10)
1427 {
1428 MS_CRITICAL_MSG(printf(" %s :DWIN is not support\n",__FUNCTION__));
1429 return GOP_FAIL;
1430 }
1431 else
1432 mask_shift = GOP_MIU_CLIENT_DWIN;
1433
1434 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
1435 return ((u16RegVal&(1<<mask_shift))? MIU_1:MIU_0);
1436
1437 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)1438 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
1439 {
1440 MS_U16 mask_shift=0;
1441
1442 if ( (miu>2) || (GOP_MIU_CLIENT_DWIN >= 0x10))
1443 {
1444 MS_CRITICAL_MSG(printf(" %s :DWIN is not support\n",__FUNCTION__));
1445 return GOP_FAIL;
1446 }
1447 else
1448 mask_shift = GOP_MIU_CLIENT_DWIN;
1449
1450 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miu<<mask_shift, 1<<mask_shift);
1451
1452 return GOP_SUCCESS;
1453
1454
1455 }
1456
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1457 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
1458 {
1459 if (bEnable)
1460 {
1461 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_ALPHA, GOP_BIT6, GOP_BIT6);
1462 }
1463 else
1464 {
1465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_DW_ALPHA, ~GOP_BIT6, GOP_BIT6);
1466 }
1467 return GOP_SUCCESS;
1468 }
1469
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)1470 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
1471 {
1472 return GOP_FUN_NOT_SUPPORTED;
1473 }
1474
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)1475 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
1476 {
1477 return GOP_FUN_NOT_SUPPORTED;
1478 }
1479
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)1480 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
1481 {
1482 return GOP_FUN_NOT_SUPPORTED;
1483 }
1484
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)1485 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
1486 {
1487 return GOP_FUN_NOT_SUPPORTED;
1488 }
1489
1490
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)1491 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
1492 {
1493 MS_U32 u32BankOffSet =0;
1494
1495 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
1496
1497 if (bEn)
1498 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
1499 else
1500 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
1501
1502 return GOP_SUCCESS;
1503 }
1504
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)1505 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
1506 {
1507 MS_U32 u32BankOffSet =0;
1508
1509 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
1510
1511 if (bEn)
1512 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
1513 else
1514 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
1515
1516 return GOP_SUCCESS;
1517 }
1518
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)1519 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
1520 {
1521 return GOP_FUN_NOT_SUPPORTED;
1522 }
1523
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_U32 u32SubAddr)1524 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_U32 u32SubAddr)
1525 {
1526 u32SubAddr /= GOP_WordUnit;
1527
1528 if(u8GOP == E_GOP2)
1529 {
1530 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1531 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1532 }
1533 else if(u8GOP == E_GOP1)
1534 {
1535 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1536 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1537 }
1538 else if(u8GOP == E_GOP0)
1539 {
1540 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
1541 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
1542 }
1543 else
1544 {
1545 return GOP_FUN_NOT_SUPPORTED;
1546 }
1547
1548 return GOP_SUCCESS;
1549
1550 }
1551
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)1552 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
1553 {
1554 return GOP_FUN_NOT_SUPPORTED;
1555 }
1556
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)1557 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
1558 {
1559 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1560 MS_U16 u16MVOPMirrorCfg = 0;
1561 MS_U16 u16ScalerMirrorCfg = 0;
1562
1563 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
1564 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
1565 if(bHorizontal) // Horizontal
1566 {
1567 if(u16MVOPMirrorCfg & GOP_BIT1)
1568 {
1569 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
1570 }
1571 else if(u16ScalerMirrorCfg & GOP_BIT12)
1572 {
1573 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1574 }
1575 }
1576 else //vertical
1577 {
1578 if(u16MVOPMirrorCfg & GOP_BIT0)
1579 {
1580 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
1581 }
1582 else if(u16ScalerMirrorCfg & GOP_BIT13)
1583 {
1584 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
1585 }
1586 }
1587 return enMirrorType;
1588 }
1589
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)1590 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
1591 {
1592 return GOP_FUN_NOT_SUPPORTED;
1593 }
1594
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)1595 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
1596 {
1597 return GOP_FUN_NOT_SUPPORTED;
1598 }
1599
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)1600 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
1601 {
1602 return GOP_FUN_NOT_SUPPORTED;
1603 }
1604
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)1605 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
1606 {
1607 return GOP_FUN_NOT_SUPPORTED;
1608 }
1609
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)1610 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
1611 {
1612 return GOP_FUN_NOT_SUPPORTED;
1613 }
1614
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)1615 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
1616 {
1617 MS_U32 u32BankOffSet = 0;
1618 MS_BOOL bInverse = 0xFF;
1619 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1620
1621 switch (eDstType)
1622 {
1623 case E_DRV_GOP_DST_IP0:
1624 bInverse = TRUE;
1625 break;
1626 default:
1627 bInverse = FALSE;
1628 break;
1629 }
1630 if(bInverse == TRUE)
1631 {
1632 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 1<<4, 0x10);
1633 }
1634 else
1635 {
1636 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 0<<4, 0x10);
1637 }
1638 return GOP_SUCCESS;
1639 }
1640
1641 /********************************************************************************/
1642 ///Test Pattern
1643 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)1644 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
1645 {
1646 switch(u8GopNum)
1647 {
1648 case E_GOP0:
1649 return GOP_FUN_NOT_SUPPORTED;
1650 break;
1651 case E_GOP1:
1652 return GOP_SUCCESS;
1653 break;
1654 case E_GOP2:
1655 return GOP_FUN_NOT_SUPPORTED;
1656 break;
1657 case E_GOP3:
1658 return GOP_FUN_NOT_SUPPORTED;
1659 break;
1660 default:
1661 printf("[%s] ERROR GOP Num %d\n",__FUNCTION__,u8GopNum);
1662 return GOP_FAIL;
1663 }
1664 return GOP_FAIL;
1665
1666 }
1667
1668
1669 /********************************************************************************/
1670 ///GOP Scaling down (internal)
1671 /********************************************************************************/
1672
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)1673 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
1674 {
1675 return GOP_FUN_NOT_SUPPORTED;
1676 }
1677
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)1678 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
1679 {
1680 return GOP_FUN_NOT_SUPPORTED;
1681 }
1682
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)1683 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
1684 {
1685 MS_U32 u32BankOffSet=0;
1686
1687 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1688 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
1689 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
1690 return GOP_SUCCESS;
1691 }
1692
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)1693 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
1694 {
1695 return GOP_FUN_NOT_SUPPORTED;
1696 }
1697
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)1698 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
1699 {
1700 MS_U32 u32BankOffSet=0xFFFF;
1701
1702 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1703 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
1704
1705 return GOP_SUCCESS;
1706 }
1707
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U32 u32tlbaddr,MS_U32 u32size)1708 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U32 u32tlbaddr, MS_U32 u32size)
1709 {
1710 MS_U32 u32BankOffSet=0xFFFF;
1711 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1712
1713 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
1714 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
1715
1716 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u32tlbaddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
1717 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u32tlbaddr>>16, GOP_REG_WORD_MASK);
1718
1719 return GOP_SUCCESS;
1720 }
1721
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U32 u32tlbaddr)1722 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U32 u32tlbaddr)
1723 {
1724 MS_U32 u32BankOffSet=0xFFFF;
1725 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
1726
1727 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u32tlbaddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
1728 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u32tlbaddr>>16, GOP_REG_WORD_MASK);
1729
1730 return GOP_SUCCESS;
1731 }
1732
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)1733 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
1734 {
1735 MS_U32 u32BankOffSet=0;
1736 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
1737
1738 if (u32GopIdx < MAX_GOP_SUPPORT)
1739 {
1740 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + (u16Addr<<1) +GOP_4G_CTRL0), u16Val);
1741 }
1742 else
1743 {
1744 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
1745 *u16Val = 0;
1746 }
1747 return GOP_SUCCESS;
1748 }
1749
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)1750 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
1751 {
1752 MS_U32 u32BankOffSet=0;
1753 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
1754
1755 if (u32GopIdx < MAX_GOP_SUPPORT)
1756 {
1757 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + (u16Addr<<1) +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
1758 }
1759 else
1760 {
1761 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
1762 }
1763 return GOP_SUCCESS;
1764 }
1765
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)1766 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
1767 {
1768 switch(u32PowerState)
1769 {
1770 case E_POWER_SUSPEND:
1771 {
1772 //CLK
1773 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
1774 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
1775 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
1776 if(g_GopChipPro.TotalGwinNum > 4)
1777 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
1778
1779
1780 //SRAM
1781 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
1782 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
1783 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
1784
1785 //XC
1786 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
1787 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
1788 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
1789 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
1790 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
1791 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
1792 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
1793 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
1794 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
1795 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
1796 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
1797 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[11]));
1798 }
1799 break;
1800 case E_POWER_RESUME:
1801 {
1802 //CLK
1803 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
1804 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
1805 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
1806 if(g_GopChipPro.TotalGwinNum > 4)
1807 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
1808
1809 //SRAM
1810 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
1811 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
1812 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
1813
1814 //XC
1815 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
1816 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
1817 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
1818 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
1819 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
1820 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
1821 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
1822 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
1823 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
1824 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
1825 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
1826 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[11], GOP_REG_WORD_MASK);
1827 }
1828 break;
1829 default:
1830 break;
1831 }
1832 return GOP_SUCCESS;
1833 }
1834
1835