1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108 #define HAL_GOP_DEBUGINFO(x) //x
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 //------------------------------------------------------------------------------
120 // Local Var
121 //------------------------------------------------------------------------------
122 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
123 {
124 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
125 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
126 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
127 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
128 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
129 };
130 #ifdef GOP_CMDQ_ENABLE
131 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
132 extern MS_U8 bMIUSelect[MAX_GOP_SUPPORT];
133 extern Gop_MuxSel u16GopMuxChanged[MAX_GOP_SUPPORT];
134 extern MS_U32 u32GopPipeDelay[MAX_GOP_SUPPORT];
135 extern MS_BOOL bGopUseOsdAlpha[MAX_GOP_SUPPORT];
136 #endif
137 GOP_CHIP_PROPERTY g_GopChipPro =
138 {
139 .bSetHSyncInverse = FALSE,
140 .bGop1GPalette = FALSE,
141 .bSetHPipeOfst = FALSE,
142 .bNeedCheckMVOP = FALSE,
143 .bNeedSetMUX1ToIP0 = FALSE,
144 .bNeedSetMUX3ToIP0 = FALSE,
145 .bNewMux = TRUE,
146 .bNewPalette = TRUE,
147 .bNewBwReg = TRUE,
148 .bGop2VStretch = TRUE,
149 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
150 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
151 .bhastilemode = TRUE,
152 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
153 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
154 .bGOPWithVscale = {TRUE, TRUE, TRUE, FALSE, FALSE}, //setting GOP with/without Vscale
155 .bGOPWithScaleDown = {TRUE, FALSE, TRUE, FALSE, FALSE},
156
157 .bDWINSupport = FALSE,
158 .DwinVer = 0x1,
159 .bTstPatternAlpha = TRUE,
160 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
161 .bFRCSupport = FALSE, /*OC path*/
162 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
163 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
164 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
165 .bScalingDownSupport= TRUE,
166 .b2Pto1PSupport= TRUE,
167 .bTLBSupport= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE},
168 .GOP_TestPattern_Vaild= E_GOP0,
169 .bInternalMIUSelect= {TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
170
171 #ifdef ENABLE_GOP_T3DPATCH
172 .GOP_PD = GOP_PD_T3D,
173 #else
174 .GOP_PD = 0x134,
175 #endif
176 .GOP_UHD_PD_Offset = 0x0,
177 .GOP_IP_PD = 0x00,
178 .GOP_MVOP_PD = 0x69,
179 .GOP_VE_PD = 0x89,
180 .GOP_MIXER_PD = 0x0,
181 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
182 .GOP_VE_V_Offset = 0x0,
183
184 .GOP_MUX_Delta = 0x1,
185 .GOP_Mux_Offset = {0x0, 0x12, 0x6, 0xC, 0x18},
186 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX1, E_GOP_MUX4},
187 .GOP_Mux_FRC_offset= 0x13,
188
189 .WordUnit = GOP_WordUnit,
190 .TotalGwinNum = GOP_TotalGwinNum,
191 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
192 .enGOP3DType = E_DRV_3D_DUP_FULL,
193 };
194
195
196 //------------------------------------------------------------------------------
197 // Global Functions
198 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)199 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
200 {
201 GOP_TYPE->GOP0 = E_GOP0;
202 GOP_TYPE->GOP1 = E_GOP1;
203 GOP_TYPE->GOP2 = E_GOP2;
204 GOP_TYPE->GOP3 = E_GOP3;
205 GOP_TYPE->GOP4 = E_GOP4;
206 GOP_TYPE->GOP5 = E_GOP5;
207 GOP_TYPE->DWIN = E_GOP_Dwin;
208 GOP_TYPE->MIXER = E_GOP_MIXER;
209 }
210
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)211 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
212 {
213 MS_U32 u32BankOffSet = 0;
214
215 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
216
217 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
218 {
219 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
220 }
221 else
222 {
223 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
224 }
225
226 return GOP_SUCCESS;
227 }
228
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)229 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
230 {
231 MS_U32 u32BankOffSet =0;
232 MS_U32 u32BitMask,Regval;
233
234 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
235
236 switch(pinpon_mode)
237 {
238 default:
239 case E_DRV_GOP_PINPON_G3D:
240 Regval = bEn << 5;
241 u32BitMask = GOP_BIT5;
242 break;
243 case E_DRV_GOP_PINPON_DWIN:
244 Regval = bEn << 6;
245 u32BitMask = GOP_BIT6;
246 break;
247 case E_DRV_GOP_PINPON_DIP:
248 Regval = bEn << 7;
249 u32BitMask = GOP_BIT7;
250 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
251 break;
252 case E_DRV_GOP_PINPON_DWIN0:
253 Regval = bEn << 7;
254 u32BitMask = GOP_BIT7;
255 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
256 break;
257 case E_DRV_GOP_PINPON_DWIN1:
258 Regval = bEn << 7;
259 u32BitMask = GOP_BIT7;
260 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
261 break;
262 break;
263 }
264
265 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
266 return GOP_SUCCESS;
267 }
268
269
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)270 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
271 {
272 if(gop >= MAX_GOP_SUPPORT)
273 {
274 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
275 return FALSE;
276 }
277
278 if (gop==E_GOP0)
279 *pBnkOfst = GOP_4G_OFST<<16;
280 else if (gop==E_GOP1)
281 *pBnkOfst = GOP_2G_OFST<<16;
282 else if (gop==E_GOP2)
283 *pBnkOfst = GOP_1G_OFST<<16;
284 else if (gop==E_GOP3)
285 *pBnkOfst = GOP_1GX_OFST<<16;
286 else if (gop==E_GOP4)
287 *pBnkOfst = GOP_1GS0_OFST<<16;
288 else if (gop==E_GOP_MIXER)
289 *pBnkOfst = 0xD<<16;
290 else
291 return FALSE;
292
293 return TRUE;
294 }
295
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)296 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
297 {
298 MS_U16 u16Mask0 = 0;
299 MS_U16 u16Mask1 = 0;
300 if (u16GopMask&GOP_BIT0)
301 {
302 u16Mask0 |= GOP_BIT12;
303 }
304 if (u16GopMask&GOP_BIT1)
305 {
306 u16Mask0 |= GOP_BIT13;
307 }
308 if (u16GopMask&GOP_BIT2)
309 {
310 u16Mask0 |= GOP_BIT14;
311 }
312 if (u16GopMask&GOP_BIT3)
313 {
314 u16Mask0 |= GOP_BIT15;
315 }
316 if (u16GopMask&GOP_BIT4)
317 {
318 u16Mask1 |= GOP_BIT4;
319 }
320 if (u16Mask0 != 0)
321 {
322 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
323 }
324 if (u16Mask1 != 0)
325 {
326 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
327 }
328 return GOP_SUCCESS;
329 }
330
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)331 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
332 {
333 if(gop >= MAX_GOP_SUPPORT)
334 {
335 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
336 return GOP_FAIL;
337 }
338
339 switch(gop)
340 {
341 case E_GOP0:
342 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
343 break;
344 case E_GOP1:
345 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
346 break;
347 case E_GOP2:
348 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
349 break;
350 case E_GOP3:
351 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
352 break;
353 case E_GOP4:
354 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
355 break;
356 default:
357 break;
358 }
359 return GOP_SUCCESS;
360 }
361
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)362 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
363 {
364 MS_U16 u16GopAck = 0,reg_val =0;
365
366 if(gop >= MAX_GOP_SUPPORT)
367 {
368 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
369 return FALSE;
370 }
371
372 switch(gop)
373 {
374 case E_GOP0:
375 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
376 if(reg_val&GOP_BIT12)
377 u16GopAck = FALSE;
378 else
379 u16GopAck = TRUE;
380 break;
381 case E_GOP1:
382 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
383 if(reg_val&GOP_BIT13)
384 u16GopAck = FALSE;
385 else
386 u16GopAck = TRUE;
387 break;
388 case E_GOP2:
389 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
390 if(reg_val&GOP_BIT14)
391 u16GopAck = FALSE;
392 else
393 u16GopAck = TRUE;
394 break;
395 case E_GOP3:
396 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
397 if(reg_val&GOP_BIT15)
398 u16GopAck = FALSE;
399 else
400 u16GopAck = TRUE;
401 break;
402 case E_GOP4:
403 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
404 if(reg_val&GOP_BIT4)
405 u16GopAck = FALSE;
406 else
407 u16GopAck = TRUE;
408 break;
409 default:
410 break;
411 }
412 return u16GopAck;
413 }
414
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)415 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
416 {
417 MS_U32 u32BankOffSet;
418
419 if (u8GOP < 3) /* only GOP0~GOP2 can support two linebuufer mode */
420 {
421 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
422 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_TWO_LINEBUFFER, bEnable?GOP_BIT12:0, GOP_BIT12);
423 }
424
425 return GOP_SUCCESS;
426 }
427
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)428 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
429 {
430 MS_U32 u32bankoff = 0;
431 MS_U16 mask_shift=0xFF;
432 MS_U16 u16RegVal=0xFF;
433 MS_U8 u8MIUSel=0xF;
434
435 if(u8GOPNum >= MAX_GOP_SUPPORT)
436 {
437 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
438 return;
439 }
440
441 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
442 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
443
444 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDFD0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32", set DMA FIFO threhold to "0xD0"
445
446 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
447 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
448
449 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
450
451 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
452 {
453 if(u8GOPNum == 0)
454 {
455 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT13|GOP_BIT14);
456 }
457 else
458 {
459 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT14);
460 }
461 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
462
463 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK);
464 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, GOP_BIT2);
465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, GOP_BIT8|GOP_BIT10|GOP_BIT12, (GOP_BIT8|GOP_BIT9)|(GOP_BIT10|GOP_BIT11)|(GOP_BIT12|GOP_BIT13));
466 }
467
468 /* enable GOP clock */
469 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
470 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
471
472 switch(u8GOPNum)
473 {
474 case E_GOP0:
475 mask_shift = GOP_MIU_CLIENT_GOP0;
476 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
477 break;
478 case E_GOP1:
479 mask_shift = GOP_MIU_CLIENT_GOP1;
480 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
481 break;
482 case E_GOP2:
483 mask_shift = GOP_MIU_CLIENT_GOP2;
484 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
485 break;
486 case E_GOP3:
487 mask_shift = GOP_MIU_CLIENT_GOP3;
488 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
489 break;
490 case E_GOP4:
491 mask_shift = GOP_MIU_CLIENT_GOP4;
492 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, 0, CKG_GOPG4_DISABLE_CLK_MASK); /* GOP 4 */
493 break;
494 case E_GOP5:
495 mask_shift = GOP_MIU_CLIENT_GOP5;
496 break;
497 case E_GOP_Dwin:
498 mask_shift = GOP_MIU_CLIENT_DWIN;
499 break;
500 default:
501 mask_shift = 0xFF;
502 break;
503 }
504
505
506 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
507 {
508 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal);
509 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
510 #ifdef GOP_MIU_GROUP2
511 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
512 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
513 #endif
514 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
515 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
516 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
517 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
518 }
519 #ifdef GOP_HW_MIUSEL_PATCH
520 else
521 {
522 if(u8GOPNum == E_GOP2)
523 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 0, 1<<GOP_MIU_CLIENT_GOP2);
524 }
525 #endif
526
527 //OC_RM_alpha
528 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
529 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
530 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
531
532 // set VIP/VOP timing select, always select VOP should be OK.
533 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_VIP_VOP_TIMING_SEL, GOP_BIT10, GOP_BIT10);
534 }
535
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)536 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
537 {
538 *pGOPHalLocal->pGopChipPro = g_GopChipPro;
539 }
540
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)541 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
542 {
543 switch(u8GopNum)
544 {
545 case E_GOP0:
546 return (MS_U8)MAX_GOP0_GWIN;
547 break;
548 case E_GOP1:
549 return (MS_U8)MAX_GOP1_GWIN;
550 break;
551 case E_GOP2:
552 return (MS_U8)MAX_GOP2_GWIN;
553 break;
554 case E_GOP3:
555 return (MS_U8)MAX_GOP3_GWIN;
556 break;
557 case E_GOP4:
558 return (MS_U8)MAX_GOP4_GWIN;
559 break;
560 default:
561 MS_ASSERT(0);
562 return 0xFF;
563 break;
564 }
565 }
566
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)567 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
568 {
569 MS_U8 u8GWinId = 0;
570
571 //Adjust GWIN ID by different Chip
572 if(u8Gop >= MAX_GOP_SUPPORT)
573 {
574 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8Gop);
575 MS_ASSERT(0);
576 return 0xFF;
577 }
578
579 switch(u8Gop)
580 {
581 case E_GOP0:
582 u8GWinId = GOP0_GwinIdBase + u8Idx;
583 break;
584 case E_GOP1:
585 u8GWinId = GOP1_GwinIdBase + u8Idx;
586 break;
587 case E_GOP2:
588 u8GWinId = GOP2_GwinIdBase + u8Idx;
589 break;
590 case E_GOP3:
591 u8GWinId = GOP3_GwinIdBase + u8Idx;
592 break;
593 case E_GOP4:
594 u8GWinId = GOP4_GwinIdBase + u8Idx;
595 break;
596 default:
597 break;
598 }
599 return u8GWinId;
600
601 }
602
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)603 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
604 {
605 if(u8GOPNum >= MAX_GOP_SUPPORT)
606 {
607 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
608 MS_ASSERT(0);
609 return 0xFF;
610 }
611
612 switch(u8GOPNum)
613 {
614 case E_GOP0: // GOP4G
615 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
616 return GOP_SUCCESS;
617 case E_GOP1: // GOP2G
618 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
619 return GOP_SUCCESS;
620 case E_GOP2: // GOP1G
621 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
622 return GOP_SUCCESS;
623 case E_GOP3: // GOP1GX
624 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
625 return GOP_SUCCESS;
626 case E_GOP4: // GOP1GS
627 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
628 return GOP_SUCCESS;
629 default:
630 MS_ASSERT(0);
631 return GOP_FAIL;
632 }
633 }
634
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)635 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
636 {
637 MS_U16 u16Bank;
638 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
639 u16Bank &= ~BMASK(3:0);
640 u16Bank |= (u8bank&BMASK(3:0));
641 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
642 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
643 u16Bank &= ~GOP_BIT4;
644 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
645 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
646 }
647
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)648 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
649 {
650 MS_U16 u16GetBank;
651 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
652 return (u16GetBank&GOP_BANK_MASK);
653 }
654
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)655 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
656 {
657 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
658 MS_U32 bank;
659 MS_U32 direct_addr;
660
661 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
662
663 //* Gop driver should access another HW IP register
664 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
665 switch (u32addr & 0xFF00)
666 {
667 case GOP_REG_BASE:
668 {
669 bank = (u32addr & 0xFF0000) >> 8;
670
671 if(bank==0xE00)//GOP4: 0x121B00
672 {
673 bank=GOP_REG_GOP4_BK_OFFSET;
674 }
675 else if(bank==0xF00)//GWIN4: 0x121E00
676 {
677 bank=GOP_REG_GOP4_GW_OFFSET;
678 }
679 else if(bank==0x1000)//GOP4_ST
680 {
681 bank=GOP_REG_GOP4_ST_OFFSET;
682 }
683
684 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
685 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
686 break;
687 }
688 case SC1_REG_BASE:
689 {
690 if(g_GopChipPro.bXCDirrectBankSupport)
691 {
692 u16xcSubbank = (u32addr & 0xFF0000)>>8;
693 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
694 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
695 }
696 else
697 {
698 u16xcSubbank = (u32addr & 0xFF0000)>>16;
699 u16BankAddr = GOP_SC_BANKSEL+0;
700 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
701
702 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
703 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
704 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
705 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
706 }
707 break;
708 }
709 case GE_REG_BASE:
710 case CKG_REG_BASE:
711 case MIU0_REG_BASE:
712 case MIU_REG_BASE:
713 case MVOP_REG_BASE:
714 {
715 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
716 break;
717 }
718 #ifdef GOP_MIU_GROUP2
719 case (MIU2_REG_BASE & 0xFF00):
720 {
721 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
722 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
723
724 break;
725 }
726 #endif
727 default:
728 {
729 //Gop lib current do not support this HW ip base
730 MS_ASSERT(0);
731 *pu16ret =0;
732 break;
733 }
734 }
735 }
736
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)737 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
738 {
739 MS_U16 u16tmp=0;
740 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
741 MS_U32 bank;
742 MS_U32 direct_addr;
743
744 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u32addr, u16val));
745
746 if(mask!=0xffff)
747 {
748 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
749 u16tmp &= ~mask;
750 u16val &= mask;
751 u16val |= u16tmp;
752 }
753
754 //* Gop driver should access another HW IP register
755 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
756 switch (u32addr & 0xFF00)
757 {
758 case GOP_REG_BASE:
759 {
760 bank = (u32addr & 0xFF0000) >> 8;
761
762 if(bank==0xE00)//GOP4: 0x121B00
763 {
764 bank=GOP_REG_GOP4_BK_OFFSET;
765 }
766 else if(bank==0xF00)//GWIN4: 0x121E00
767 {
768 bank=GOP_REG_GOP4_GW_OFFSET;
769 }
770 else if(bank==0x1000) //GOP4_ST
771 {
772 bank=GOP_REG_GOP4_ST_OFFSET;
773 }
774
775 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
776 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
777 break;
778 }
779 case SC1_REG_BASE:
780 if(g_GopChipPro.bXCDirrectBankSupport)
781 { /*Derrick Bank*/
782 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
783 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
784 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
785 }
786 else
787 { /*Sub Bank*/
788 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
789 u16BankAddr = GOP_SC_BANKSEL+0;
790 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
791
792 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
793 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
794 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
795 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
796 }
797 break;
798 case GE_REG_BASE:
799 case CKG_REG_BASE:
800 case MIU0_REG_BASE:
801 case MIU_REG_BASE:
802 {
803 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
804 break;
805 }
806 #ifdef GOP_MIU_GROUP2
807 case (MIU2_REG_BASE & 0xFF00):
808 {
809 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
810 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
811 break;
812 }
813 #endif
814 default:
815 {
816 //Gop lib current do not support this HW ip base
817 MS_ASSERT(0);
818 break;
819 }
820
821 }
822 }
823
824
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)825 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
826 {
827 MS_U32 bank;
828 MS_U32 direct_addr;
829
830 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
831
832 //* Gop driver should access another HW IP register
833 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
834 switch (u32addr & 0xFF00)
835 {
836 case GOP_REG_BASE:
837 {
838 bank = (u32addr & 0xFF0000) >> 8;
839 if(bank==0xE00)//GOP4: 0x121B00
840 {
841 bank=GOP_REG_GOP4_BK_OFFSET;
842 }
843 else if(bank==0xF00)//GWIN4: 0x121E00
844 {
845 bank=GOP_REG_GOP4_GW_OFFSET;
846 }
847 else if(bank==0x1000) //GOP4_ST
848 {
849 bank=GOP_REG_GOP4_ST_OFFSET;
850 }
851
852 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
853 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
854 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
855 break;
856 }
857
858 case GE_REG_BASE:
859 case SC1_REG_BASE:
860 case CKG_REG_BASE:
861 {
862 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
863 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
864 break;
865 }
866
867 default:
868 {
869 //Gop lib current do not support this HW ip base
870 MS_ASSERT(0);
871 break;
872 }
873
874 }
875 }
876
877 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
878
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)879 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
880 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
881 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
882 {
883 MS_U8 i=0;
884 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",u8Index, u8A, u8R, u8G, u8B));
885
886 /* Don't care high byte */
887 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
888
889 for(i =(GOP_WordUnit-1);i>4;i--)
890 {
891 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
892 }
893 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
894 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
895 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
896 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
897 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
898 *pREGMAP_Offset += GOP_WordUnit;
899
900 MsOS_FlushMemory(); //make sure cpu write data to dram
901
902 }
903
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)904 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
905 {
906 MS_U16 bpp=0;
907
908 switch ( fbFmt )
909 {
910 case E_DRV_GOP_COLOR_RGB555_BLINK :
911 case E_DRV_GOP_COLOR_RGB565 :
912 case E_DRV_GOP_COLOR_ARGB1555:
913 case E_DRV_GOP_COLOR_RGBA5551:
914 case E_DRV_GOP_COLOR_ARGB4444 :
915 case E_DRV_GOP_COLOR_RGBA4444 :
916 case E_DRV_GOP_COLOR_RGB555YUV422:
917 case E_DRV_GOP_COLOR_YUV422:
918 case E_DRV_GOP_COLOR_2266:
919 bpp = 16;
920 break;
921 case E_DRV_GOP_COLOR_ARGB8888 :
922 case E_DRV_GOP_COLOR_ABGR8888 :
923 bpp = 32;
924 break;
925
926 case E_DRV_GOP_COLOR_I8 :
927 bpp = 8;
928 break;
929
930 default :
931 //print err
932 MS_ASSERT(0);
933 bpp = 0xFFFF;
934 break;
935 }
936 return bpp;
937
938 }
939
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)940 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
941 {
942 MS_U16 regval;
943 /*For compatibility
944 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
945 MS_U8 u8coef_cpt = u8coef;
946
947 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
948 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
949 {
950 switch(u8coef)
951 {
952 case 0x0 :
953 u8coef_cpt = u8coef<<2;
954 break;
955 case 0x3f :
956 u8coef_cpt = ((u8coef<<2)|0x3);
957 break;
958 default:
959 u8coef_cpt = ((u8coef<<2)|0x1);
960 break;
961 }
962 }
963
964 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
965 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
966 {
967 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
968 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
969 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
970 }
971 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
972 else
973 {
974 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
975 {
976 regval = (MS_U16)(bEnable?(1<<14):0);
977 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
978 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
979 }
980 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
981 {
982 regval = (MS_U16)(bEnable?(1<<14):0);
983 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
984 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
985 }
986 else
987 {
988 regval = (MS_U16)(bEnable?(1<<14):0);
989 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
990 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
991 }
992 }
993 }
994
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)995 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
996 {
997 pGOPHalLocal->va_mmio_base = addr;
998 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)999 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1000 {
1001 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1002 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1003 {
1004 }
1005
1006
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1007 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1008 {
1009 /*A5 GOP dst type:
1010 1: IP (Main)
1011 0: IP (Sub)
1012 2: OP
1013 3: MVOP
1014 4: MVOP (Sub)
1015 6: FRC
1016 11: InsideFRC
1017 */
1018 MS_U8 i=0, Cnt=0;
1019 MS_U16 u16RegVal;
1020 MS_U32 u32BankOffSet;
1021 DRV_GOPDstType pGopDst;
1022 MS_BOOL bEnable;
1023 MS_U16 u16HSyncMask=GOP_BIT14;
1024
1025 if( GopNum >= MAX_GOP_SUPPORT)
1026 {
1027 return GOP_INVALID_PARAMETERS;
1028 }
1029
1030 switch (eDstType)
1031 {
1032 case E_DRV_GOP_DST_IP0:
1033 u16RegVal = 0x0;
1034 bEnable = FALSE;
1035 u16HSyncMask=0;
1036 break;
1037
1038 case E_DRV_GOP_DST_IP0_SUB:
1039 u16RegVal = 0x1;
1040 bEnable = FALSE;
1041 u16HSyncMask=0;
1042 break;
1043
1044 case E_DRV_GOP_DST_OP0:
1045 u16RegVal = 0x2;
1046 bEnable = FALSE;
1047 u16HSyncMask=GOP_BIT14;
1048 break;
1049
1050 case E_DRV_GOP_DST_VOP:
1051 u16RegVal = 0x3;
1052 bEnable = FALSE;
1053 u16HSyncMask=GOP_BIT14;
1054 break;
1055
1056 case E_DRV_GOP_DST_VOP_SUB:
1057 u16RegVal = 0x4;
1058 bEnable = FALSE;
1059 u16HSyncMask=GOP_BIT14;
1060 break;
1061
1062 case E_DRV_GOP_DST_FRC:
1063 u16RegVal = 0x6;
1064 bEnable = TRUE;
1065 u16HSyncMask=GOP_BIT14;
1066 break;
1067
1068 case E_DRV_GOP_DST_VE:
1069 u16RegVal = 0x7;
1070 bEnable = TRUE;
1071 u16HSyncMask=GOP_BIT14;
1072 break;
1073
1074 case E_DRV_GOP_DST_MOD:
1075 //GOP destination --> SC OP
1076 u16RegVal = 0x2;
1077 bEnable = TRUE;
1078 u16HSyncMask=GOP_BIT14;
1079 break;
1080
1081 case E_DRV_GOP_DST_IP1:
1082 u16RegVal = 0x8;
1083 bEnable = TRUE;
1084 break;
1085
1086 default:
1087 return GOP_FUN_NOT_SUPPORTED;
1088 }
1089 if(bOnlyCheck == FALSE)
1090 {
1091 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1092 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1093 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
1094
1095 //for Monaco, IP need set Vsync inverse in IP
1096 if (eDstType == E_DRV_GOP_DST_IP0)
1097 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)GOP_BIT1, GOP_BIT1);
1098 else
1099 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
1100 //For Bypass
1101 for(i=0; i<MAX_GOP_SUPPORT ;i++)
1102 {
1103 HAL_GOP_GetGOPDst(pGOPHalLocal, i, &pGopDst);
1104 if(pGopDst == E_DRV_GOP_DST_FRC)
1105 {
1106 Cnt++;
1107 }
1108 }
1109
1110 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1111 }
1112 return GOP_SUCCESS;
1113 }
1114
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1115 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1116 {
1117 return GOP_FUN_NOT_SUPPORTED;
1118 }
1119
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1120 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1121 {
1122 return GOP_FUN_NOT_SUPPORTED;
1123 }
1124
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1125 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1126 {
1127 /*T8
1128 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1129 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1130 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1131 */
1132 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1133 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1134 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
1135 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1136 return GOP_SUCCESS;
1137 }
1138
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1139 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1140 {
1141 MS_U16 u16GopMux=0;
1142 switch(eGopMux)
1143 {
1144 case E_GOP_MUX0:
1145 case E_GOP_MUX1:
1146 case E_GOP_MUX2:
1147 case E_GOP_MUX3:
1148 case E_GOP_MUX4:
1149 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1150 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1151 break;
1152 case E_GOP_IP0_MUX:
1153 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1154 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1155 break;
1156 case E_GOP_IP0_SUB_MUX:
1157 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1158 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1159 break;
1160 case E_GOP_VOP0_MUX:
1161 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1162 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1163 break;
1164 case E_GOP_VOP0_SUB_MUX:
1165 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1166 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1167 break;
1168 case E_GOP_Mix_MUX0:
1169 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1170 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1171 break;
1172 case E_GOP_Mix_MUX1:
1173 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1174 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1175 break;
1176 case E_GOP_VE0_MUX:
1177 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1178 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1179 break;
1180 case E_GOP_VE1_MUX:
1181 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1182 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1183 break;
1184 case E_GOP_DIP_MUX:
1185 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1186 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1187 break;
1188 case E_GOP_FRC_MUX0:
1189 case E_GOP_FRC_MUX1:
1190 case E_GOP_FRC_MUX2:
1191 case E_GOP_FRC_MUX3:
1192 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1193 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1194 break;
1195 case E_GOP_BYPASS_MUX0:
1196 break;
1197 default:
1198 printf("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1199 break;
1200 }
1201 }
1202
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1203 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1204 {
1205 MS_U16 u16Ret[4]={0};
1206
1207 switch(eGopMux)
1208 {
1209 case E_GOP_MUX0:
1210 case E_GOP_MUX1:
1211 case E_GOP_MUX2:
1212 case E_GOP_MUX3:
1213 case E_GOP_MUX4:
1214 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1215 break;
1216 case E_GOP_IP0_MUX:
1217 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1218 break;
1219 case E_GOP_IP1_MUX:
1220 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_SUB_MUX_SHIFT, GOP_IP_SUB_MUX_MASK);
1221 break;
1222 case E_GOP_VOP0_MUX:
1223 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1224 break;
1225 case E_GOP_VOP1_MUX:
1226 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1227 break;
1228 case E_GOP_Mix_MUX0:
1229 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1230 break;
1231 case E_GOP_Mix_MUX1:
1232 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1233 break;
1234 case E_GOP_VE0_MUX:
1235 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1236 break;
1237 case E_GOP_VE1_MUX:
1238 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1239 break;
1240 case E_GOP_DIP_MUX:
1241 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1242 break;
1243 case E_GOP_FRC_MUX0:
1244 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1245 break;
1246 case E_GOP_FRC_MUX1:
1247 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1248 break;
1249 case E_GOP_FRC_MUX2:
1250 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1251 break;
1252 case E_GOP_FRC_MUX3:
1253 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1254 break;
1255 case E_GOP_BYPASS_MUX0:
1256 //Check MUX is using? Checking from priority high to low
1257 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1258 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1259 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1260 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1261
1262 //Checking if un-use
1263 if((u16Ret[0] & GOP_BIT0) ==0)
1264 {
1265 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1266 }
1267 else if((u16Ret[1] & GOP_BIT0) ==0)
1268 {
1269 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1270 }
1271 else if((u16Ret[2] & GOP_BIT0) ==0)
1272 {
1273 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1274 }
1275 else if((u16Ret[3] & GOP_BIT0) ==0)
1276 {
1277 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1278 }
1279 else
1280 {
1281 printf("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1282 }
1283 break;
1284 break;
1285 default:
1286 printf("[%s]ERROR mux setting\n",__FUNCTION__);
1287 break;
1288 }
1289 }
1290
1291 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_GWIN_SetMUX_ThroughCmdq(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * p_cmdq_struct,MS_U32 * p_number,MS_U8 u8GOPNum)1292 void HAL_GOP_GWIN_SetMUX_ThroughCmdq(GOP_CTX_HAL_LOCAL*pGOPHalLocal,
1293 CAF_Struct *p_cmdq_struct, MS_U32 *p_number, MS_U8 u8GOPNum)
1294 {
1295 Gop_MuxSel eGopMux = E_GOP_MUX0;
1296 MS_U32 pipe_delay;
1297 MS_BOOL osd_alpha;
1298 MS_U16 gop_idx = 0;
1299 MS_U32 u32BankOffSet = 0;
1300 MS_U16 op_mux_val = 0x0;
1301 MS_BOOL bScMode1En = FALSE;
1302 MS_U16 u16scMode1Reg = 0x0;
1303
1304 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &op_mux_val);
1305 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &u16scMode1Reg);
1306
1307 for(gop_idx = 0; gop_idx<MAX_GOP_SUPPORT; gop_idx++)
1308 {
1309 MS_U16 mask = 0xFFFF;
1310 MS_U16 u16val = 0x0;
1311
1312 eGopMux = u16GopMuxChanged[gop_idx];
1313
1314 if (eGopMux == E_GOP_MUX_INVAILD)
1315 {
1316 continue;
1317 }
1318
1319 switch(eGopMux)
1320 {
1321 case E_GOP_MUX0:
1322 case E_GOP_MUX1:
1323 case E_GOP_MUX2:
1324 case E_GOP_MUX3:
1325 case E_GOP_MUX4:
1326 mask = GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux);
1327 u16val = gop_idx <<(GOP_MUX_SHIFT*eGopMux);
1328
1329 op_mux_val &= ~mask;
1330 u16val &= mask;
1331 op_mux_val |= u16val;
1332
1333 HAL_GOP_GetGOPAlphaMode1(pGOPHalLocal, gop_idx, &bScMode1En);
1334 if (E_GOP_MUX0 == eGopMux) {
1335 mask = (0x30);
1336 u16val = (TRUE == bScMode1En) ? (0x10) : (~0x10);
1337 } else if (E_GOP_MUX1 == eGopMux) {
1338 mask = (0x3000);
1339 u16val = (TRUE == bScMode1En) ? (0x1000) : (~0x1000);
1340 } else if (E_GOP_MUX2 == eGopMux) {
1341 mask = (0xC0);
1342 u16val = (TRUE == bScMode1En) ? (0x40) : (~0x40);
1343 } else if (E_GOP_MUX3 == eGopMux) {
1344 mask = (0x300);
1345 u16val = (TRUE == bScMode1En) ? (0x100) : (~0x100);
1346 } else if (E_GOP_MUX4 == eGopMux) {
1347 mask = (0xC000);
1348 u16val = (TRUE == bScMode1En) ? (0x4000) : (~0x4000);
1349 }
1350
1351 u16scMode1Reg &= ~mask;
1352 u16val &= mask;
1353 u16scMode1Reg |= u16val;
1354 break;
1355
1356 default:
1357 printf("[%s] Only support OP mux switch now, ERROR mux setting\n",__FUNCTION__);
1358 break;
1359 }
1360 }
1361 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,p_cmdq_struct,p_number, GOP_MUX, op_mux_val, 0xFFFF);//current GOP force write en
1362 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,p_cmdq_struct,p_number, GOP_SC_GOPENMODE1, u16scMode1Reg, 0xFFFF);//current GOP force write en
1363
1364
1365 for(gop_idx = 0; gop_idx<MAX_GOP_SUPPORT; gop_idx++)
1366 {
1367 MS_U16 u16BnkWrVal;
1368 MS_U16 u16GopReg0Val;
1369 eGopMux = u16GopMuxChanged[gop_idx];
1370 pipe_delay = u32GopPipeDelay[gop_idx];
1371 osd_alpha = bGopUseOsdAlpha[gop_idx];
1372
1373 u16GopMuxChanged[gop_idx] = E_GOP_MUX_INVAILD;
1374 u32GopPipeDelay[gop_idx] = 0;
1375
1376 if (eGopMux == E_GOP_MUX_INVAILD)
1377 {
1378 continue;
1379 }
1380
1381 _GetBnkOfstByGop(gop_idx, &u32BankOffSet);
1382 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,p_cmdq_struct,p_number, u32BankOffSet+GOP_4G_HS_PIPE, pipe_delay, 0xFFFF);
1383
1384 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, &u16GopReg0Val);
1385 if (bGopUseOsdAlpha[gop_idx] == TRUE) {
1386 u16GopReg0Val |= GOP_BIT15;
1387 } else {
1388 u16GopReg0Val &= (~GOP_BIT15);
1389 }
1390 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,p_cmdq_struct,p_number, u32BankOffSet+GOP_4G_CTRL0, u16GopReg0Val, 0xFFFF);
1391
1392 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR, &u16BnkWrVal);
1393 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,p_cmdq_struct,p_number,u32BankOffSet+GOP_4G_BANK_FWR,(u16BnkWrVal|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
1394 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,p_cmdq_struct,p_number,u32BankOffSet+GOP_4G_BANK_FWR,(u16BnkWrVal&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
1395 }
1396 }
1397 #endif
1398
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1399 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1400 {
1401 /* GOP OP Path enable to SC Setting
1402 A5: GOP OP Path blending with SC sequence
1403 mux1-->mux0-->mux2-->mux3
1404 */
1405 MS_U16 muxValue=0, regval=0;
1406
1407 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1408 MS_U16 u164K2KMuxValue=0;
1409
1410 if(gopNum >= MAX_GOP_SUPPORT)
1411 {
1412 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1413 return GOP_FAIL;
1414 }
1415
1416 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1417 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1418
1419 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1420 {
1421 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1422 }
1423
1424 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1425 {
1426 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1427 }
1428
1429 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1430 {
1431 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1432 }
1433
1434 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1435 {
1436 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1437 }
1438
1439 if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1440 {
1441 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1442 }
1443
1444 /*For FRC mux switch*/
1445 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1446 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1447 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1448 {
1449 /* Switch FRC blending */
1450 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1451 }
1452
1453 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1454 {
1455 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1456 }
1457
1458 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1459 {
1460 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1461 }
1462
1463 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1464 {
1465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1466 }
1467
1468 return GOP_SUCCESS;
1469 }
1470
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1471 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1472 {
1473 MS_U32 u32pBankOffSet=0;
1474 MS_U16 u16Regval;
1475
1476 if(g_GopChipPro.b2Pto1PSupport)
1477 {
1478 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1479 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1480 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |0x0800):(u16Regval & ~0x0800), 0x0800);
1481 }
1482 return GOP_SUCCESS;
1483 }
1484
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1485 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1486 {
1487 /* GOP OP Path enable to SC Setting
1488 A5: GOP OP Path blending with SC sequence
1489 mux1-->mux0-->mux2-->mux3
1490 */
1491 MS_U16 muxValue=0, regval=0;
1492
1493 if(gopNum >= MAX_GOP_SUPPORT)
1494 {
1495 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1496 return FALSE;
1497 }
1498
1499 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1500 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1501 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1502 {
1503 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1504 }
1505 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1506 {
1507 //printf("");
1508 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1509 }
1510 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1511 {
1512 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1513 }
1514 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1515 {
1516 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1517 }
1518 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1519 {
1520 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1521 }
1522 else
1523 {
1524 return GOP_FAIL;
1525 }
1526 return GOP_SUCCESS;
1527 }
1528
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1529 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1530 {
1531 MS_U16 muxValue=0, regval=0;
1532
1533 if(gopNum >= MAX_GOP_SUPPORT)
1534 {
1535 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1536 return FALSE;
1537 }
1538
1539 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1540 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1541 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1542 {
1543 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
1544 }
1545 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1546 {
1547 *pbEnable = (regval & GOP_BIT12) == GOP_BIT12;
1548 }
1549 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1550 {
1551 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
1552 }
1553 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1554 {
1555 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
1556 }
1557 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1558 {
1559 *pbEnable = (regval & GOP_BIT14) == GOP_BIT14;
1560 }
1561 else
1562 {
1563 return GOP_FAIL;
1564 }
1565 return GOP_SUCCESS;
1566 }
1567
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1568 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1569 {
1570 /*T8
1571 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1572 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1573 */
1574 MS_U16 Mux3Gop, muxValue=0, i;
1575 MS_U16 MuxShift;
1576
1577 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1578
1579 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1580 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1581 {
1582 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1583 {
1584 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1585
1586 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1587 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1588 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1589 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1590 break;
1591
1592 }
1593
1594 }
1595 return GOP_SUCCESS;
1596 }
1597
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1598 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1599 {
1600 /*T8 GOP dst type:
1601 0: IP (Main)
1602 1: IP (Sub)
1603 2: OP
1604 3: MVOP
1605 */
1606
1607 /* Monaco clkgen setting */
1608 /******************
1609 0: odclk
1610 1: idclk_f2 (ipm)
1611 2: idclk_f1 (ips)
1612 3: ocmixer
1613 4: ve
1614 5 : mvop main
1615 6 : mvop sub
1616 ******************/
1617 if(gopNum >= MAX_GOP_SUPPORT)
1618 {
1619 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1620 MS_ASSERT(0);
1621 return GOP_INVALID_PARAMETERS;
1622 }
1623
1624 switch(eDstType)
1625 {
1626 case E_DRV_GOP_DST_IP0:
1627
1628 if (gopNum==E_GOP1)
1629 {
1630 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1631 }
1632 else if (gopNum ==E_GOP2)
1633 {
1634 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1635 }
1636 else if (gopNum ==E_GOP3)
1637 {
1638 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1639 }
1640 else if (gopNum ==E_GOP4)
1641 {
1642 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1643 }
1644 else if (gopNum==E_GOP0)
1645 {
1646 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1647 }
1648 else
1649 {
1650 MS_ASSERT(0);
1651 return GOP_INVALID_PARAMETERS;
1652 }
1653 break;
1654
1655 case E_DRV_GOP_DST_IP0_SUB:
1656 if (gopNum==E_GOP1)
1657 {
1658 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1659 }
1660 else if (gopNum==E_GOP2)
1661 {
1662 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1663 }
1664 else if (gopNum==E_GOP3)
1665 {
1666 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG3_MASK);
1667 }
1668 else if (gopNum ==E_GOP4)
1669 {
1670 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK1, CKG_GOPG4_MASK);
1671 }
1672 else if (gopNum==E_GOP0)
1673 {
1674 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1675 }
1676 else
1677 {
1678 MS_ASSERT(0);
1679 return GOP_INVALID_PARAMETERS;
1680 }
1681 break;
1682
1683
1684 case E_DRV_GOP_DST_OP0:
1685 if (gopNum==E_GOP1)
1686 {
1687 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1688 }
1689 else if (gopNum==E_GOP2)
1690 {
1691 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1692 }
1693 else if (gopNum==E_GOP3)
1694 {
1695 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
1696 }
1697 else if (gopNum ==E_GOP4)
1698 {
1699 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
1700 }
1701 else if (gopNum==E_GOP0)
1702 {
1703 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1704 }
1705 else
1706 {
1707 MS_ASSERT(0);
1708 return GOP_INVALID_PARAMETERS;
1709 }
1710 break;
1711 case E_DRV_GOP_DST_DIP:
1712 if (gopNum==E_GOP1)
1713 {
1714 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_FCLK, CKG_GOPG1_MASK);
1715 }
1716 else if (gopNum==E_GOP2)
1717 {
1718 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_FCLK, CKG_GOPG2_MASK);
1719 }
1720 else if (gopNum==E_GOP3)
1721 {
1722 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_FCLK, CKG_GOPG3_MASK);
1723 }
1724 else if (gopNum ==E_GOP4)
1725 {
1726 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_FCLK, CKG_GOPG4_MASK);
1727 }
1728 else if (gopNum==E_GOP0)
1729 {
1730 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_FCLK, CKG_GOPG0_MASK);
1731 }
1732 else
1733 {
1734 MS_ASSERT(0);
1735 return GOP_INVALID_PARAMETERS;
1736 }
1737
1738 break;
1739
1740 case E_DRV_GOP_DST_VOP:
1741 if (gopNum==E_GOP1)
1742 {
1743 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1744 }
1745 else if (gopNum ==E_GOP2)
1746 {
1747 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1748 }
1749 else if (gopNum ==E_GOP3)
1750 {
1751 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1752 }
1753 else if (gopNum ==E_GOP4)
1754 {
1755 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1756 }
1757 else if (gopNum==E_GOP0)
1758 {
1759 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1760 }
1761 else
1762 {
1763 MS_ASSERT(0);
1764 return GOP_INVALID_PARAMETERS;
1765 }
1766
1767 break;
1768 case E_DRV_GOP_DST_FRC:
1769 if (gopNum==E_GOP1)
1770 {
1771 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
1772 }
1773 else if (gopNum==E_GOP0)
1774 {
1775 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
1776 }
1777 else if (gopNum==E_GOP2)
1778 {
1779 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
1780 }
1781 else if (gopNum==E_GOP3)
1782 {
1783 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
1784 }
1785 else if (gopNum ==E_GOP4)
1786 {
1787 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
1788 }
1789 else
1790 {
1791 MS_ASSERT(0);
1792 return GOP_INVALID_PARAMETERS;
1793 }
1794
1795 break;
1796
1797 case E_DRV_GOP_DST_MIXER2VE:
1798 //HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_VECLK, CKG_GOPMIXER_MASK);
1799
1800 if(gopNum == 0)
1801 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
1802 else if(gopNum == 1)
1803 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
1804 else if(gopNum == 2)
1805 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
1806 else if(gopNum == 3)
1807 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
1808 else if(gopNum == 4)
1809 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
1810
1811 break;
1812
1813 case E_DRV_GOP_DST_VE:
1814 if(gopNum == 0)
1815 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
1816 else if(gopNum == 1)
1817 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
1818 else if(gopNum == 2)
1819 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
1820 else if(gopNum == 3)
1821 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
1822 else if(gopNum == 4)
1823 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
1824
1825 break;
1826
1827 case E_DRV_GOP_DST_IP1:
1828 if (gopNum==E_GOP1)
1829 {
1830 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1831 }
1832 else if (gopNum==E_GOP2)
1833 {
1834 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG1_IDCLK1, CKG_GOPG2_MASK);
1835 }
1836 else if (gopNum==E_GOP0)
1837 {
1838 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG0_MASK);
1839 }
1840 else
1841 {
1842 MS_ASSERT(0);
1843 return GOP_INVALID_PARAMETERS;
1844 }
1845 break;
1846
1847 default:
1848 MS_ASSERT(0);
1849 return GOP_ENUM_NOT_SUPPORTED;
1850 }
1851 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1852 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1853
1854 return GOP_SUCCESS;
1855 }
1856
1857
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1858 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1859 {
1860 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1861 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1862 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1863 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1864 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1865 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1866 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1867 else
1868 return GOP_INVALID_PARAMETERS;
1869
1870 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1871 return GOP_SUCCESS;
1872 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1873 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1874 {
1875 if (bEnable)
1876 {
1877 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1878 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1879 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1880 }
1881 else
1882 {
1883 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1884 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1885 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1886 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1887 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1888 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1889 }
1890
1891 return GOP_SUCCESS;
1892 }
1893
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1894 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1895 {
1896 return GOP_FUN_NOT_SUPPORTED;
1897 }
1898
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)1899 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
1900 {
1901 return GOP_FUN_NOT_SUPPORTED;
1902 }
1903
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)1904 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
1905 {
1906 return GOP_FUN_NOT_SUPPORTED;
1907 }
1908
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)1909 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
1910 {
1911 MS_U32 u32GopIdx;
1912
1913 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
1914 pGOPHalLocal->pHALShared = pHALShared;
1915
1916 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
1917 {
1918 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
1919 }
1920 pGOPHalLocal->pGopChipPro = &pHALShared->gopChipProperty;
1921 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
1922 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1923 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1924 {
1925 }
1926
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)1927 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
1928 {
1929 MS_U8 u8Miu=0xff;
1930 MS_U16 u16RegVal_L=0;
1931 #ifdef GOP_MIU_GROUP2
1932 MS_U16 u16RegVal_H=0;
1933 #endif
1934
1935 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal_L);
1936 #ifdef GOP_MIU_GROUP2
1937 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
1938 #endif
1939 if (gwinid<MAX_GOP0_GWIN) //gop0
1940 {
1941 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
1942 #ifdef GOP_MIU_GROUP2
1943 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
1944 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
1945 #else
1946 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
1947 #endif
1948 }
1949 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
1950 {
1951 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
1952 #ifdef GOP_MIU_GROUP2
1953 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
1954 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
1955 #else
1956 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
1957 #endif
1958 }
1959 else if (gwinid==GOP2_GwinIdBase) //gop2
1960 {
1961 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
1962 #ifdef GOP_MIU_GROUP2
1963 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
1964 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
1965 #else
1966 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
1967 #endif
1968 }
1969 else if (gwinid==GOP3_GwinIdBase) //gop3
1970 {
1971 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
1972 #ifdef GOP_MIU_GROUP2
1973 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
1974 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
1975 #else
1976 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
1977 #endif
1978 }
1979 else if (gwinid==GOP4_GwinIdBase) //gop4
1980 {
1981 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
1982 #ifdef GOP_MIU_GROUP2
1983 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
1984 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
1985 #else
1986 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
1987 #endif
1988 }
1989 else
1990 {
1991 return GOP_FAIL;
1992 }
1993
1994 if (u8Miu <= 2)
1995 {
1996 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
1997 }
1998 else
1999 {
2000 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2001 return GOP_FAIL;
2002 }
2003 return GOP_SUCCESS;
2004 }
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2005 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2006 {
2007 MS_U8 u8Miu=0xff;
2008 MS_U16 u16RegVal_L=0;
2009 MS_U32 u32BnkOfst=0xFFFF;
2010 #ifdef GOP_MIU_GROUP2
2011 MS_U16 u16RegVal_H=0;
2012 #endif
2013
2014 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2015 {
2016 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2017 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2018 u8Miu= u16RegVal_L& (GOP_BIT0|GOP_BIT1);
2019 }
2020 else
2021 {
2022 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal_L);
2023
2024 #ifdef GOP_MIU_GROUP2
2025 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2026 #endif
2027 switch (gopnum)
2028 {
2029 case 0:
2030 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2031 #ifdef GOP_MIU_GROUP2
2032 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2033 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2034 #else
2035 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2036 #endif
2037 break;
2038 case 1:
2039 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2040 #ifdef GOP_MIU_GROUP2
2041 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2042 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2043 #else
2044 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2045 #endif
2046 break;
2047
2048 case 2:
2049 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2050 #ifdef GOP_MIU_GROUP2
2051 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2052 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2053 #else
2054 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2055 #endif
2056 break;
2057
2058 case 3:
2059 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2060 #ifdef GOP_MIU_GROUP2
2061 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2062 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2063 #else
2064 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2065 #endif
2066 break;
2067 case 4:
2068 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
2069 #ifdef GOP_MIU_GROUP2
2070 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
2071 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
2072 #else
2073 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
2074 #endif
2075 break;
2076 default:
2077 return 0xff;
2078 break;
2079 }
2080
2081 if(u8Miu > MAX_GOP_MIUSEL )
2082 {
2083 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2084 return 0xff;
2085 }
2086
2087 }
2088 return u8Miu;
2089 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2090 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2091 {
2092 MS_U16 u16Regval;
2093 MS_U32 u32pBankOffSet=0;
2094 GOP_Result ret;
2095
2096 if(u8gopNum >= MAX_GOP_SUPPORT)
2097 {
2098 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8gopNum);
2099 *pGopDst = E_DRV_GOP_DST_INVALID;
2100 return GOP_FAIL;
2101 }
2102
2103 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2104 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2105
2106 switch (u16Regval&GOP_DST_MASK)
2107 {
2108 case 0:
2109 *pGopDst = E_DRV_GOP_DST_IP0;
2110 ret = GOP_SUCCESS;
2111 break;
2112 case 1:
2113 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
2114 ret = GOP_SUCCESS;
2115 break;
2116 case 2:
2117 *pGopDst = E_DRV_GOP_DST_OP0;
2118 ret = GOP_SUCCESS;
2119 break;
2120 case 3:
2121 *pGopDst = E_DRV_GOP_DST_VOP;
2122 ret = GOP_SUCCESS;
2123 break;
2124 case 4:
2125 *pGopDst = E_DRV_GOP_DST_VOP_SUB;
2126 ret = GOP_SUCCESS;
2127 break;
2128 case 6:
2129 *pGopDst = E_DRV_GOP_DST_FRC;
2130 ret = GOP_SUCCESS;
2131 break;
2132 case 11:
2133 *pGopDst = E_DRV_GOP_DST_BYPASS;
2134 ret = GOP_SUCCESS;
2135 break;
2136 case 8:
2137 *pGopDst = E_DRV_GOP_DST_IP1;
2138 ret = GOP_SUCCESS;
2139 break;
2140 default:
2141 *pGopDst = E_DRV_GOP_DST_INVALID;
2142 ret = GOP_FAIL;
2143 break;
2144 }
2145
2146 return ret;
2147
2148 }
2149
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2150 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2151 {
2152 MS_U16 muxValue=0;
2153 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2154
2155 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2156
2157 switch(ipSelGop)
2158 {
2159 case MS_DRV_IP0_SEL_GOP0:
2160 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2161 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2162 u16RegVal |= GOP_BIT12;//mux0
2163 else
2164 u16RegVal |= GOP_BIT13;//mux1
2165 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2166 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2167 break;
2168
2169 case MS_DRV_IP0_SEL_GOP1:
2170 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2171 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2172 u16RegVal |= GOP_BIT12;//mux0
2173 else
2174 u16RegVal |= GOP_BIT13;//mux1
2175 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2176 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2177 break;
2178 case MS_DRV_IP0_SEL_GOP2:
2179 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2180 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2181 u16RegVal |= GOP_BIT12;//mux0
2182 else
2183 u16RegVal |= GOP_BIT13;//mux1
2184 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2185 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2186 break;
2187
2188 case MS_DRV_NIP_SEL_GOP0:
2189 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2190 {
2191 u16RegVal = ~GOP_BIT12;//mux0
2192 u16RegMsk = GOP_BIT12;
2193 }
2194 else
2195 {
2196 u16RegVal = ~GOP_BIT13;//mux1
2197 u16RegMsk = GOP_BIT13;
2198 }
2199 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2200 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2201 break;
2202
2203 case MS_DRV_NIP_SEL_GOP1:
2204 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2205 {
2206 u16RegVal = ~GOP_BIT12;//mux0
2207 u16RegMsk = GOP_BIT12;
2208 }
2209 else
2210 {
2211 u16RegVal = ~GOP_BIT13;//mux1
2212 u16RegMsk = GOP_BIT13;
2213 }
2214 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2215 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2216
2217 break;
2218 case MS_DRV_NIP_SEL_GOP2:
2219 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2220 {
2221 u16RegVal = ~GOP_BIT12;//mux0
2222 u16RegMsk = GOP_BIT12;
2223 }
2224 else
2225 {
2226 u16RegVal = ~GOP_BIT13;//mux1
2227 u16RegMsk = GOP_BIT13;
2228 }
2229 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2230 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2231
2232 break;
2233 case MS_DRV_MVOP_SEL:
2234 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2235 u16RegVal |= GOP_BIT12; //mux0
2236 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2237 break;
2238 case MS_DRV_IP1_SEL:
2239 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, 0, GOP_BIT11);
2240 u16RegMsk = 0;
2241 break;
2242 default:
2243 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
2244 break;
2245 }
2246 if(0 != u16RegMsk)
2247 {
2248 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2249 }
2250 }
2251
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2252 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2253 {
2254 return GOP_FUN_NOT_SUPPORTED;
2255 }
2256
2257
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2258 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2259 {
2260 return GOP_FUN_NOT_SUPPORTED;
2261 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2262 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2263 {
2264 return GOP_FUN_NOT_SUPPORTED;
2265 }
2266
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2267 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2268 {
2269 return GOP_FUN_NOT_SUPPORTED;
2270 }
2271
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2272 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2273 {
2274 return GOP_FUN_NOT_SUPPORTED;
2275 }
2276
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2277 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2278 {
2279 return GOP_FUN_NOT_SUPPORTED;
2280 }
2281
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2282 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2283 {
2284 return GOP_FUN_NOT_SUPPORTED;
2285 }
2286
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2287 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2288 {
2289 return GOP_FUN_NOT_SUPPORTED;
2290 }
2291
2292
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2293 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2294 {
2295 MS_U32 u32BankOffSet =0;
2296
2297 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2298
2299 if (bEn)
2300 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2301 else
2302 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2303
2304 return GOP_SUCCESS;
2305 }
2306
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2307 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2308 {
2309 MS_U32 u32BankOffSet =0;
2310
2311 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2312
2313 if (bEn)
2314 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2315 else
2316 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2317
2318 return GOP_SUCCESS;
2319 }
2320
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2321 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2322 {
2323 MS_U16 u16Val =0x0;
2324 if (u8win < GOP1_GwinIdBase)
2325 {
2326 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2327 *pEnable = (MS_BOOL)(u16Val>>15);
2328 }
2329 else if (u8win < GOP2_GwinIdBase)
2330 {
2331 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2332 *pEnable = (MS_BOOL)(u16Val>>15);
2333 }
2334 else if (u8win < GOP3_GwinIdBase)
2335 {
2336 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2337 *pEnable = (MS_BOOL)(u16Val>>15);
2338 }
2339 else if (u8win < GOP4_GwinIdBase)
2340 {
2341 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2342 *pEnable = (MS_BOOL)(u16Val>>15);
2343 }
2344 else if (u8win < GOP5_GwinIdBase)
2345 {
2346 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2347 *pEnable = (MS_BOOL)(u16Val>>15);
2348 }
2349 else
2350 {
2351 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2352 return GOP_INVALID_PARAMETERS;
2353 }
2354
2355 return GOP_SUCCESS;
2356 }
2357
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2358 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2359 {
2360 MS_U16 u16Val = bEnable << 15;
2361 if (u8win < GOP1_GwinIdBase)
2362 {
2363 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2364 }
2365 else if (u8win < GOP2_GwinIdBase)
2366 {
2367 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2368 }
2369 else if (u8win < GOP3_GwinIdBase)
2370 {
2371 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2372 }
2373 else if (u8win < GOP4_GwinIdBase)
2374 {
2375 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2376 }
2377 else if (u8win < GOP5_GwinIdBase)
2378 {
2379 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2380 }
2381 else
2382 {
2383 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2384 return GOP_INVALID_PARAMETERS;
2385 }
2386 return GOP_SUCCESS;
2387 }
2388
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2389 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2390 {
2391 MS_U16 u16Reg = 0;
2392 MS_U32 u32WordBase = 0;
2393 MS_U32 u32BankOffSet=0;
2394
2395 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2396
2397 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2398
2399 if(u16Reg & GOP_BIT7)
2400 {
2401 u32WordBase = 1;
2402 }
2403 else
2404 {
2405 u32WordBase = GOP_WordUnit;
2406 }
2407
2408 u32SubAddr /= u32WordBase;
2409
2410 if(u8GOP == E_GOP2)
2411 {
2412 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2413 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2414 }
2415 else if(u8GOP == E_GOP3)
2416 {
2417 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2418 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2419
2420 }
2421 else if(u8GOP == E_GOP4)
2422 {
2423 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2424 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2425 }
2426 else if(u8GOP == E_GOP1)
2427 {
2428 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2429 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2430 }
2431 else //gop0
2432 {
2433 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2434 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2435 }
2436
2437 return GOP_SUCCESS;
2438
2439 }
2440
2441 //------------------------------------------------------------------------------
2442 /// Set VE output with OSD
2443 /// @return none
2444 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2445 GOP_Result HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2446 {
2447 #ifndef MSOS_TYPE_LINUX_KERNEL
2448 MS_U32 u32Reg = GOP_VE_TVS_OSD_EN;
2449 MS_U16 u16Val = BIT(2)|BIT(3);
2450
2451 if( EN_OSD_0 == eOSD)
2452 {
2453 u32Reg = GOP_VE_TVS_OSD_EN;
2454 }
2455 else if( EN_OSD_1 == eOSD)
2456 {
2457 u32Reg = GOP_VE_TVS_OSD1_EN;
2458 }
2459
2460 if(bEnable) // enable OSD
2461 {
2462 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, ~u16Val, u16Val);
2463 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(5), BIT(5));
2464 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(1), BIT(1));
2465 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(0), BIT(0));
2466 }
2467 else // disable OSD
2468 {
2469 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, 0x0, BIT(0));
2470 }
2471 #endif
2472 return GOP_SUCCESS;
2473 }
2474
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2475 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2476 {
2477 MS_U16 regval = 0x0;
2478
2479 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2480 // there are only 2 mux, the 3rd gop will be set to 2nd mux(osd1).
2481 if((gopNum != (regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8)>>6)) && (gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9)))
2482 {
2483 // if have to overwrite one, overwriting INIT VALUE is better.
2484 if (VE_MUX_INIT_VALUE == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2485 {
2486 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6), (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2487 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2488 }
2489 else
2490 {
2491 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2492 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2493 }
2494 }
2495 else if(gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9))
2496 {
2497 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2498 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2499 }
2500 else
2501 {
2502 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6) , (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2503 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2504 }
2505 return GOP_SUCCESS;
2506
2507 }
2508
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2509 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2510 {
2511 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2512 MS_U16 u16MVOPMirrorCfg = 0;
2513 MS_U16 u16ScalerMirrorCfg = 0;
2514
2515 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2516 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2517 if(bHorizontal) // Horizontal
2518 {
2519 if(u16MVOPMirrorCfg & GOP_BIT1)
2520 {
2521 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2522 }
2523 else if(u16ScalerMirrorCfg & GOP_BIT12)
2524 {
2525 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2526 }
2527 }
2528 else //vertical
2529 {
2530 if(u16MVOPMirrorCfg & GOP_BIT0)
2531 {
2532 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2533 }
2534 else if(u16ScalerMirrorCfg & GOP_BIT13)
2535 {
2536 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2537 }
2538 }
2539 return enMirrorType;
2540 }
2541
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2542 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2543 {
2544 MS_U32 u32BankOffSet =0;
2545
2546 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2547 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2548 return GOP_SUCCESS;
2549 }
2550
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2551 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2552 {
2553 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2554 MS_U16 u16Val=0;
2555 MS_U16 u16Mux[MAX_GOP_MUX];
2556
2557 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2558 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2559 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2560 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2561 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2562 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2563
2564 switch(u8GOP)
2565 {
2566 case E_GOP0:
2567 case E_GOP1:
2568 case E_GOP2:
2569 case E_GOP3:
2570 case E_GOP4:
2571 for(i=0; i<MAX_GOP_MUX; i++)
2572 {
2573 if(u8GOP == u16Mux[i])
2574 {
2575 eGopMux = i;
2576 if(eGopMux == 4)
2577 {
2578 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2579 }
2580 else
2581 {
2582 FRCMuxOffset = 12 + eGopMux;
2583 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2584 }
2585 }
2586 }
2587 break;
2588 default:
2589 return GOP_FAIL;
2590 break;
2591 }
2592
2593 return GOP_SUCCESS;
2594 }
2595
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2596 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2597 {
2598 return GOP_FUN_NOT_SUPPORTED;
2599 }
2600
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2601 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2602 {
2603 return GOP_FUN_NOT_SUPPORTED;
2604 }
2605
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2606 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2607 {
2608 return GOP_FUN_NOT_SUPPORTED;
2609 }
2610
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2611 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2612 {
2613 return GOP_FUN_NOT_SUPPORTED;
2614 }
2615
2616 /********************************************************************************/
2617 ///Test Pattern
2618 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)2619 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
2620 {
2621 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
2622 {
2623 return GOP_SUCCESS;
2624 }
2625 else
2626 {
2627 return GOP_FAIL;
2628 }
2629
2630 }
2631
2632
2633 /********************************************************************************/
2634 ///GOP Scaling down (internal)
2635 /********************************************************************************/
2636
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2637 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
2638 {
2639 MS_U16 u16MG_mask=0;
2640 MS_U16 u16Val=0;
2641 MS_U16 u16LB_mask=0;
2642 MS_U16 u16enable=0;
2643
2644 if(u8GOP==0)
2645 {
2646 u16MG_mask=CKG_GOPG0_MG_MASK;
2647 u16Val=GOP_BIT2;
2648 u16LB_mask=CKG_LB_SRAM1_MASK;
2649 u16enable=GOP_BIT2;
2650 }
2651 else if(u8GOP==2)
2652 {
2653 u16MG_mask=CKG_GOPG2_MG_MASK;
2654 u16Val=GOP_BIT6;
2655 u16LB_mask=CKG_LB_SRAM2_MASK;
2656 u16enable=GOP_BIT6;
2657 }
2658 else
2659 {
2660 printf("[%s] Error message GOP not support scaling down!!",__FUNCTION__);
2661 return GOP_FAIL;
2662 }
2663 if(bEn==TRUE)
2664 {
2665 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, u16Val, u16MG_mask);
2666 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, u16enable, u16LB_mask);
2667 }
2668 else
2669 {
2670 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, u16MG_mask);
2671 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, u16LB_mask);
2672 }
2673 return TRUE;
2674 }
2675
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2676 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2677 {
2678 MS_U32 ratio;
2679 MS_U32 u32BankOffSet=0xFFFF;
2680 MS_U16 u16VScalReg;
2681
2682 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2683 if(bEnable ==TRUE)
2684 {
2685 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, &u16VScalReg);
2686 if( u16VScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2687 {
2688 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2689 printf("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2690 }
2691 //Set scaling down ratio
2692 ratio = (dst * 0x100000) / src;
2693 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, ratio);
2694 }
2695 else
2696 {
2697 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, 0);
2698 }
2699
2700 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
2701 {
2702 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
2703 }
2704 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, bEnable , GOP_BIT0);
2705 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_H_OUTPUTSIZE, dst, GOP_REG_WORD_MASK);
2706
2707 return GOP_SUCCESS;
2708
2709 }
2710
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2711 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2712 {
2713 MS_U32 ratio =0;
2714 MS_U32 u32BankOffSet=0xFFFF;
2715 MS_U16 u16HScalReg;
2716
2717 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2718 if(bEnable ==TRUE)
2719 {
2720 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, &u16HScalReg);
2721 if( u16HScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2722 {
2723 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2724 printf("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2725 }
2726 ratio = (dst * 0x100000) / src;
2727 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, ratio);
2728 }
2729 else
2730 {
2731 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, 0);
2732 }
2733
2734 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
2735 {
2736 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
2737 }
2738 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, (bEnable<<4) , GOP_BIT4);
2739 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SVM_VEND, dst, GOP_REG_WORD_MASK);
2740
2741 return GOP_SUCCESS;
2742
2743 }
2744
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)2745 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
2746 {
2747 MS_U32 u32BankOffSet=0;
2748
2749 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2750 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
2751 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
2752 return GOP_SUCCESS;
2753 }
2754
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)2755 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
2756 {
2757 MS_U32 u32BankOffSet=0;
2758 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
2759
2760 if (u32GopIdx < MAX_GOP_SUPPORT)
2761 {
2762 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
2763 }
2764 else
2765 {
2766 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
2767 *u16Val = 0;
2768 }
2769 return GOP_SUCCESS;
2770 }
2771
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)2772 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
2773 {
2774 MS_U32 u32BankOffSet=0;
2775 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
2776
2777 if (u32GopIdx < MAX_GOP_SUPPORT)
2778 {
2779 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
2780 }
2781 else
2782 {
2783 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
2784 }
2785 return GOP_SUCCESS;
2786 }
2787
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)2788 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
2789 {
2790 switch(u32PowerState)
2791 {
2792 case E_POWER_SUSPEND:
2793 {
2794 //CLK
2795 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
2796 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
2797 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
2798 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
2799 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
2800 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
2801
2802 //SRAM
2803 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
2804 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
2805 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
2806
2807 //XC
2808 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
2809 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
2810 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
2811 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
2812 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
2813 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
2814 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
2815 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
2816 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
2817 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
2818 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
2819 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
2820 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
2821 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[13]));
2822 }
2823 break;
2824 case E_POWER_RESUME:
2825 {
2826 //CLK
2827 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
2828 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
2829 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
2830 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
2831 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
2832 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
2833
2834 //SRAM
2835 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
2836 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
2837 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
2838
2839 //XC
2840 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
2841 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
2842 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
2843 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
2844 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
2845 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
2846 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
2847 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
2848 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
2849 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
2850 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
2851 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
2852 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
2853 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[13], GOP_BIT11);
2854 }
2855 break;
2856 default:
2857 break;
2858 }
2859 return GOP_SUCCESS;
2860 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)2861 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
2862 {
2863 return GOP_FUN_NOT_SUPPORTED;
2864 }
2865
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)2866 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
2867 {
2868 return GOP_FUN_NOT_SUPPORTED;
2869 }
2870
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)2871 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
2872 {
2873 return GOP_FUN_NOT_SUPPORTED;
2874 }
2875
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)2876 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
2877 {
2878 return GOP_FUN_NOT_SUPPORTED;
2879 }
2880
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)2881 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
2882 {
2883 MS_U32 u32BankOffSet=0xFFFF;
2884 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2885
2886 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
2887 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
2888 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
2889
2890 return GOP_SUCCESS;
2891 }
2892
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)2893 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
2894 {
2895 MS_U32 u32BankOffSet=0xFFFF;
2896 MS_U16 mask_shift=0xFF;
2897
2898 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2899 switch(u8GOP)
2900 {
2901 case E_GOP0:
2902 mask_shift = GOP_MIU_CLIENT_GOP0;
2903 break;
2904 case E_GOP1:
2905 mask_shift = GOP_MIU_CLIENT_GOP1;
2906 break;
2907 case E_GOP2:
2908 mask_shift = GOP_MIU_CLIENT_GOP2;
2909 break;
2910 case E_GOP3:
2911 mask_shift = GOP_MIU_CLIENT_GOP3;
2912 break;
2913 case E_GOP4:
2914 mask_shift = GOP_MIU_CLIENT_GOP4;
2915 break;
2916 case E_GOP5:
2917 mask_shift = GOP_MIU_CLIENT_GOP5;
2918 break;
2919 case E_GOP_Dwin:
2920 mask_shift = GOP_MIU_CLIENT_DWIN;
2921 break;
2922 default:
2923 mask_shift = 0xFF;
2924 MS_CRITICAL_MSG(printf("ERROR gop miu client\n"));
2925 break;
2926 }
2927
2928 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, miusel<<mask_shift, 1<<mask_shift );
2929 #ifdef GOP_MIU_GROUP2
2930 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
2931 #endif
2932
2933 return GOP_SUCCESS;
2934 }
2935
HAL_GOP_OC_SetMODEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bMODEn)2936 GOP_Result HAL_GOP_OC_SetMODEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bMODEn)
2937 {
2938 MS_U16 u16RegModVal;
2939
2940 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MOD, (bMODEn? GOP_BIT0:0) , GOP_BIT0);
2941
2942 return GOP_SUCCESS;
2943 }
2944
2945 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)2946 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
2947 {
2948 MS_U16 u16xcSubbank=0;
2949 MS_U32 bank;
2950 MS_U32 direct_addr;
2951 MS_U16 u16tmp=0;
2952
2953 if(mask != 0xffff)
2954 {
2955 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
2956 u16tmp &= ~mask;
2957 u16val &= mask;
2958 u16val |= u16tmp;
2959 }
2960
2961 switch (u32addr & 0xFF00)
2962 {
2963 case GOP_REG_BASE:
2964 {
2965 bank = (u32addr & 0xFF0000) >> 8;
2966
2967 if(bank==0xE00)//GOP4: 0x121B00
2968 {
2969 bank=GOP_REG_GOP4_BK_OFFSET;
2970 }
2971 else if(bank==0xF00)//GWIN4: 0x121E00
2972 {
2973 bank=GOP_REG_GOP4_GW_OFFSET;
2974 }
2975 else if(bank==0x1000) //GOP4_ST
2976 {
2977 bank=GOP_REG_GOP4_ST_OFFSET;
2978 }
2979
2980 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
2981
2982 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
2983 cmdq_struct[(*number)].destionation_value = u16val;
2984 cmdq_struct[(*number)].mask = 0xFFFF; // ((~mask)&0xFFFF);
2985 cmdq_struct[(*number)].operation = 0x57;
2986 (*number)++;
2987 break;
2988 }
2989 case SC1_REG_BASE:
2990 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
2991 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
2992
2993 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
2994 cmdq_struct[(*number)].destionation_value = u16val;
2995 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
2996 cmdq_struct[(*number)].operation = 0x57;
2997 (*number)++;
2998 break;
2999 case GE_REG_BASE:
3000 case CKG_REG_BASE:
3001 case MIU_REG_BASE:
3002 {
3003 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3004 cmdq_struct[(*number)].destionation_value = u16val;
3005 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3006 cmdq_struct[(*number)].operation = 0x57;
3007 (*number)++;
3008 break;
3009 }
3010 #ifdef GOP_MIU_GROUP2
3011 case (MIU2_REG_BASE & 0xFF00):
3012 {
3013 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3014
3015 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3016 cmdq_struct[(*number)].destionation_value = u16val;
3017 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3018 cmdq_struct[(*number)].operation = 0x57;
3019 (*number)++;
3020 break;
3021 }
3022 #endif
3023 default:
3024 {
3025 //Gop lib current do not support this HW ip base
3026 MS_ASSERT(0);
3027 break;
3028 }
3029
3030 }
3031 return GOP_SUCCESS;
3032 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3033 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3034 {
3035 MS_U32 u32BankOffSet;
3036 MS_U16 u16RegVal1 = 0;
3037 MS_BOOL bCheckValidGop = FALSE;
3038 MS_U8 u8CheckTimeCnt = 0;
3039 MS_U8 u8CurrentCmdGop = 0;
3040
3041 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3042 {
3043 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3044 {
3045 u8CurrentCmdGop = 0;
3046 }
3047 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3048 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3049 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3050 {
3051 bCheckValidGop = FALSE;
3052 }
3053 else
3054 {
3055 bCheckValidGop = TRUE;
3056 break;
3057 }
3058
3059 // if current gop not init, use next gop instead, check order 0->2->1->3
3060 switch (u8CurrentCmdGop)
3061 {
3062 case 0:
3063 u8CurrentCmdGop = 2;
3064 break;
3065 case 1:
3066 u8CurrentCmdGop = 0;
3067 break;
3068 case 2:
3069 u8CurrentCmdGop = 3;
3070 break;
3071 case 3:
3072 u8CurrentCmdGop = 1;
3073 break;
3074 default:
3075 u8CurrentCmdGop = 0;
3076 break;
3077 }
3078 u8CheckTimeCnt++;
3079 }
3080 if (!bCheckValidGop)
3081 {
3082 printf("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3083 }
3084
3085 *u32GopIdx = u8CurrentCmdGop;
3086 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3087 (*number)++;
3088 return GOP_SUCCESS;
3089 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3090 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3091 {
3092 CH_Struct ch_fire;
3093 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3094 MS_U16 u16ret = 0,u16ret1 = 0;
3095
3096
3097
3098 _GetBnkOfstByGop(0, &u32BankOffSet);
3099 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3100 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3101 #if 0 //for Debug
3102 int i = 0;
3103 for(i=0;i<(*number);i++)
3104 {
3105 printf("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3106 }
3107 #endif
3108 ch_fire.Command_Number = *number;
3109 ch_fire.Pointer_To_CAFArray = target;
3110 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3111 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3112 {
3113 Receive_Return_Value = 0;
3114 MDrv_CMDQ_Printf_Crash_Command();
3115 }
3116
3117 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3118 MsOS_DelayTask(1);
3119 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3120 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3121
3122 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3123 timer1 = MsOS_GetSystemTime();
3124 timer2 = MsOS_GetSystemTime();
3125 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3126 {
3127 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3128 MsOS_DelayTask(1);
3129 timer2 = MsOS_GetSystemTime();
3130 }
3131 if(u16ret1 != (u16ret+1)){
3132 printf("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3133 MDrv_CMDQ_Printf_Crash_Command();
3134 }
3135 return GOP_SUCCESS;
3136 }
3137
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3138 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3139 {
3140 CAF_Struct fire_struct[24];
3141 MS_U32 u32BankOffSet;
3142 MS_U32 number = 0;
3143 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3144 MS_U32 fireGOP;
3145 MS_BOOL bSettingMiuClient = FALSE;
3146 _GetBnkOfstByGop(gop, &u32BankOffSet);
3147
3148 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal1);
3149 #ifdef GOP_MIU_GROUP2
3150 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3151 #endif
3152 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3153 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3154
3155 switch(gop)
3156 {
3157 case E_GOP0:
3158 {
3159 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3160 break;
3161 }
3162 case E_GOP1:
3163 {
3164 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3165 break;
3166 }
3167 case E_GOP2:
3168 {
3169 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3170 break;
3171 }
3172 case E_GOP3:
3173 {
3174 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3175 break;
3176 }
3177 case E_GOP4:
3178 {
3179 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3180 break;
3181 }
3182 default:
3183 {
3184 MS_ASSERT(0);
3185 break;
3186 }
3187 }
3188 if(bMIUSelect[gop] == TRUE)
3189 {
3190 if(u16MIUSelect[gop] == 0)
3191 {
3192 u16RegVal1 &= ~(1<<u16MiuClient);
3193 u16RegVal3 &= ~(1<<u16MiuClient);
3194 }
3195 else if(u16MIUSelect[gop] == 1)
3196 {
3197 u16RegVal1 |= (1<<u16MiuClient);
3198 u16RegVal3 &= ~(1<<u16MiuClient);
3199 }
3200 else if(u16MIUSelect[gop] == 2)
3201 {
3202 u16RegVal1 &= ~(1<<u16MiuClient);
3203 u16RegVal3 |= (1<<u16MiuClient);
3204 }
3205 else if(u16MIUSelect[gop] == 3)
3206 {
3207 u16RegVal1 |= (1<<u16MiuClient);
3208 u16RegVal3 |= (1<<u16MiuClient);
3209 }
3210 bMIUSelect[gop] = FALSE;
3211 bSettingMiuClient = TRUE;
3212 }
3213 HAL_GOP_GWIN_SetMUX_ThroughCmdq(pGOPHalLocal, fire_struct, &number, gop);
3214 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3215 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3216 if (bSettingMiuClient == TRUE)
3217 {
3218 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_SC_MIU_SEL,u16RegVal1,0xFFFF);
3219 #ifdef GOP_MIU_GROUP2
3220 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3221 #endif
3222 }
3223
3224 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3225 return GOP_SUCCESS;
3226 }
3227
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)3228 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3229 {
3230 CAF_Struct fire_struct[24];
3231 MS_U32 u32BankOffSet;
3232 MS_U32 number = 0;
3233 MS_U8 gop;
3234 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3235 MS_U32 fireGOP;
3236 MS_BOOL bSettingMiuClient = FALSE;
3237
3238 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal1);
3239 #ifdef GOP_MIU_GROUP2
3240 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3241 #endif
3242 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3243
3244 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3245 {
3246 switch(gop)
3247 {
3248 case E_GOP0:
3249 {
3250 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3251 break;
3252 }
3253 case E_GOP1:
3254 {
3255 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3256 break;
3257 }
3258 case E_GOP2:
3259 {
3260 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3261 break;
3262 }
3263 case E_GOP3:
3264 {
3265 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3266 break;
3267 }
3268 case E_GOP4:
3269 {
3270 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3271 break;
3272 }
3273 default:
3274 {
3275 continue;
3276 }
3277 }
3278 if( ( u16GopMask & (1<<gop) ) )
3279 {
3280 _GetBnkOfstByGop(gop, &u32BankOffSet);
3281 if(bMIUSelect[gop] == TRUE)
3282 {
3283 if(u16MIUSelect[gop] == 0)
3284 {
3285 u16RegVal1 &= ~(1<<u16MiuClient);
3286 u16RegVal3 &= ~(1<<u16MiuClient);
3287 }
3288 else if(u16MIUSelect[gop] == 1)
3289 {
3290 u16RegVal1 |= (1<<u16MiuClient);
3291 u16RegVal3 &= ~(1<<u16MiuClient);
3292 }
3293 else if(u16MIUSelect[gop] == 2)
3294 {
3295 u16RegVal1 &= ~(1<<u16MiuClient);
3296 u16RegVal3 |= (1<<u16MiuClient);
3297 }
3298 else if(u16MIUSelect[gop] == 3)
3299 {
3300 u16RegVal1 |= (1<<u16MiuClient);
3301 u16RegVal3 |= (1<<u16MiuClient);
3302 }
3303 bMIUSelect[gop] = FALSE;
3304 bSettingMiuClient = TRUE;
3305 }
3306 HAL_GOP_GWIN_SetMUX_ThroughCmdq(pGOPHalLocal, fire_struct, &number, gop);
3307 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3308 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3309 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3310 }
3311 }
3312 if (bSettingMiuClient == TRUE)
3313 {
3314 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_SC_MIU_SEL,u16RegVal1,0xFFFF);
3315 #ifdef GOP_MIU_GROUP2
3316 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3317 #endif
3318 }
3319 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3320 return GOP_SUCCESS;
3321 }
3322 #endif
3323