1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108 #define HAL_GOP_DEBUGINFO(x) //x
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 //------------------------------------------------------------------------------
120 // Local Var
121 //------------------------------------------------------------------------------
122 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
123 {
124 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
125 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
126 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
127 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
128 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
129 };
130 #ifdef GOP_CMDQ_ENABLE
131 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
132 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
133
134 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
135 extern MS_BOOL bAFBCMIUSelect[MAX_GOP_SUPPORT];
136 #endif
137 GOP_CHIP_PROPERTY g_GopChipPro =
138 {
139 .bSetHSyncInverse = TRUE,
140 .bGop1GPalette = TRUE,
141 .bSetHPipeOfst = FALSE,
142 .bNeedCheckMVOP = FALSE,
143 .bNeedSetMUX1ToIP0 = FALSE,
144 .bNeedSetMUX3ToIP0 = FALSE,
145 .bNewMux = TRUE,
146 .bNewPalette = TRUE,
147 .bNewBwReg = TRUE,
148 .bGop2VStretch = TRUE,
149 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
150 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
151 .bhastilemode = TRUE,
152 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
153 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
154 .bGOPWithVscale = {TRUE, TRUE, TRUE, FALSE, FALSE}, //setting GOP with/without Vscale
155
156 .bDWINSupport = FALSE,
157 .DwinVer = 0x1,
158 .bTstPatternAlpha = TRUE,
159 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
160 .bFRCSupport = FALSE, /*OC path*/
161 .bGOPMixerToVE= TRUE, /*Mixer to VE path*/
162 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
163 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
164 .bScalingDownSupport= FALSE,
165 .b2Pto1PSupport= TRUE,
166 .bTLBSupport= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE},
167 .GOP_TestPattern_Vaild= E_GOP0,
168 .bInternalMIUSelect= {TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
169 .bAFBC_Support= {TRUE, FALSE, TRUE, FALSE, FALSE, FALSE},
170
171 #ifdef ENABLE_GOP_T3DPATCH
172 #ifdef GOP_ZORDER_PD_PATCH
173 .GOP_PD = 0x20,
174 #else
175 .GOP_PD = 0x30,
176 #endif
177 #else
178 .GOP_PD = 0x179,
179 #endif
180 .GOP_HDR_OP_PD = 0x0,
181 .GOP_IP_PD = 0x00,
182 .GOP_MVOP_PD = 0x69,
183 .GOP_VE_PD = 0x89,
184 .GOP_MIXER_PD = 0x0,
185 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
186 .GOP_VE_V_Offset = 0x0,
187 .GOP_OP1_PD = 0x16F,
188
189 .GOP_MUX_Delta = 0x4,
190 .GOP_Mux_Offset = {0x0, 0x1, 0x2, 0x3, 0x3},
191 .GOP_Zorder_Mux_Offset = {0x3, 0x3, 0x3, 0x3, 0x3},
192 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX4},
193 .GOP_Mux_FRC_offset= 0x13,
194
195 .WordUnit = GOP_WordUnit,
196 .TotalGwinNum = GOP_TotalGwinNum,
197 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
198 .enGOP3DType = E_DRV_3D_DUP_FULL,
199 .bOpInterlace = FALSE,
200 .bAFBC_Merge_GOP_Trig = FALSE,
201 .bAFBCMIUSelDoubleBuffer = FALSE,
202 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, TRUE, TRUE, FALSE},
203 .bGOPAutoClkGating = TRUE,
204 };
205
206
207 //------------------------------------------------------------------------------
208 // Global Functions
209 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)210 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
211 {
212 GOP_TYPE->GOP0 = E_GOP0;
213 GOP_TYPE->GOP1 = E_GOP1;
214 GOP_TYPE->GOP2 = E_GOP2;
215 GOP_TYPE->GOP3 = E_GOP3;
216 GOP_TYPE->GOP4 = E_GOP4;
217 GOP_TYPE->GOP5 = E_GOP5;
218 GOP_TYPE->DWIN = E_GOP_Dwin;
219 GOP_TYPE->MIXER = E_GOP_MIXER;
220 }
221
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)222 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
223 {
224 MS_U32 u32BankOffSet = 0;
225
226 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
227
228 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
229 {
230 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
231 }
232 else
233 {
234 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
235 }
236
237 return GOP_SUCCESS;
238 }
239
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)240 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
241 {
242 MS_U32 u32BankOffSet =0;
243 MS_U32 u32BitMask,Regval;
244
245 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
246
247 switch(pinpon_mode)
248 {
249 default:
250 case E_DRV_GOP_PINPON_G3D:
251 Regval = bEn << 5;
252 u32BitMask = GOP_BIT5;
253 break;
254 case E_DRV_GOP_PINPON_DWIN:
255 Regval = bEn << 6;
256 u32BitMask = GOP_BIT6;
257 break;
258 case E_DRV_GOP_PINPON_DIP:
259 Regval = bEn << 7;
260 u32BitMask = GOP_BIT7;
261 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
262 break;
263 case E_DRV_GOP_PINPON_DWIN0:
264 Regval = bEn << 7;
265 u32BitMask = GOP_BIT7;
266 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
267 break;
268 case E_DRV_GOP_PINPON_DWIN1:
269 Regval = bEn << 7;
270 u32BitMask = GOP_BIT7;
271 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
272 break;
273 break;
274 }
275
276 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
277 return GOP_SUCCESS;
278 }
279
280
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)281 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
282 {
283 if(gop >= MAX_GOP_SUPPORT)
284 {
285 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
286 return FALSE;
287 }
288
289 if (gop==E_GOP0)
290 *pBnkOfst = GOP_4G_OFST<<16;
291 else if (gop==E_GOP1)
292 *pBnkOfst = GOP_2G_OFST<<16;
293 else if (gop==E_GOP2)
294 *pBnkOfst = GOP_1G_OFST<<16;
295 else if (gop==E_GOP3)
296 *pBnkOfst = GOP_1GX_OFST<<16;
297 #if (MAX_GOP_SUPPORT>4)
298 else if (gop==E_GOP4)
299 *pBnkOfst = GOP_1GS0_OFST<<16;
300 else if (gop==E_GOP_MIXER)
301 *pBnkOfst = 0xD<<16;
302 else
303 return FALSE;
304 #endif
305
306 return TRUE;
307 }
308
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)309 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
310 {
311 MS_U16 u16Mask0 = 0;
312 MS_U16 u16Mask1 = 0;
313 if (u16GopMask&GOP_BIT0)
314 {
315 u16Mask0 |= GOP_BIT12;
316 }
317 if (u16GopMask&GOP_BIT1)
318 {
319 u16Mask0 |= GOP_BIT13;
320 }
321 if (u16GopMask&GOP_BIT2)
322 {
323 u16Mask0 |= GOP_BIT14;
324 }
325 if (u16GopMask&GOP_BIT3)
326 {
327 u16Mask0 |= GOP_BIT15;
328 }
329 if (u16GopMask&GOP_BIT4)
330 {
331 u16Mask1 |= GOP_BIT4;
332 }
333 if (u16Mask0 != 0)
334 {
335 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
336 }
337 if (u16Mask1 != 0)
338 {
339 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
340 }
341
342 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
343 {
344 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
345 }
346 return GOP_SUCCESS;
347 }
348
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)349 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
350 {
351 if(gop >= MAX_GOP_SUPPORT)
352 {
353 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
354 return GOP_FAIL;
355 }
356
357 switch(gop)
358 {
359 case E_GOP0:
360 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
361 break;
362 case E_GOP1:
363 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
364 break;
365 case E_GOP2:
366 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
367 break;
368 case E_GOP3:
369 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
370 break;
371 #if (MAX_GOP_SUPPORT>4)
372 case E_GOP4:
373 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
374 break;
375 #endif
376 default:
377 break;
378 }
379 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
380 {
381 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
382 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
383 }
384 return GOP_SUCCESS;
385 }
386
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)387 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
388 {
389 MS_U16 u16GopAck = 0,reg_val =0;
390
391 if(gop >= MAX_GOP_SUPPORT)
392 {
393 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
394 return FALSE;
395 }
396
397 switch(gop)
398 {
399 case E_GOP0:
400 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
401 if(reg_val&GOP_BIT12)
402 u16GopAck = FALSE;
403 else
404 u16GopAck = TRUE;
405 break;
406 case E_GOP1:
407 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
408 if(reg_val&GOP_BIT13)
409 u16GopAck = FALSE;
410 else
411 u16GopAck = TRUE;
412 break;
413 case E_GOP2:
414 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
415 if(reg_val&GOP_BIT14)
416 u16GopAck = FALSE;
417 else
418 u16GopAck = TRUE;
419 break;
420 case E_GOP3:
421 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
422 if(reg_val&GOP_BIT15)
423 u16GopAck = FALSE;
424 else
425 u16GopAck = TRUE;
426 break;
427 #if (MAX_GOP_SUPPORT>4)
428 case E_GOP4:
429 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
430 if(reg_val&GOP_BIT4)
431 u16GopAck = FALSE;
432 else
433 u16GopAck = TRUE;
434 break;
435 #endif
436 default:
437 break;
438 }
439 return u16GopAck;
440 }
441
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)442 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
443 {
444 return GOP_FUN_NOT_SUPPORTED;
445 }
446
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)447 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
448 {
449 MS_U32 u32bankoff = 0;
450 MS_U16 mask_shift=0xFF;
451 MS_U16 u16RegVal=0xFF;
452 MS_U8 u8MIUSel=0xF;
453 MS_U8 u8Core=0;
454
455 if(u8GOPNum >= MAX_GOP_SUPPORT)
456 {
457 return;
458 }
459
460 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
461 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
462
463 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDCF0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32"
464
465 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
466 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
467 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT8|GOP_BIT9, GOP_BIT8|GOP_BIT9);
468
469 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
470
471 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
472 {
473 if(u8GOPNum == 0)
474 {
475 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT13|GOP_BIT14);
476 }
477 else
478 {
479 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT14);
480 }
481 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
482
483 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK);
484 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, GOP_BIT2);
485 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, GOP_BIT8|GOP_BIT10|GOP_BIT12, (GOP_BIT8|GOP_BIT9)|(GOP_BIT10|GOP_BIT11)|(GOP_BIT12|GOP_BIT13));
486 }
487
488 /* enable GOP clock */
489 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
490 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
491
492 switch(u8GOPNum)
493 {
494 case E_GOP0:
495 mask_shift = GOP_MIU_CLIENT_GOP0;
496 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
497 break;
498 case E_GOP1:
499 mask_shift = GOP_MIU_CLIENT_GOP1;
500 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
501 break;
502 case E_GOP2:
503 mask_shift = GOP_MIU_CLIENT_GOP2;
504 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
505 break;
506 case E_GOP3:
507 mask_shift = GOP_MIU_CLIENT_GOP3;
508 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
509 break;
510 #if (MAX_GOP_SUPPORT>4)
511 case E_GOP4:
512 mask_shift = GOP_MIU_CLIENT_GOP4;
513 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, 0, CKG_GOPG4_DISABLE_CLK_MASK); /* GOP 4 */
514 break;
515 case E_GOP5:
516 mask_shift = GOP_MIU_CLIENT_GOP5;
517 break;
518 case E_GOP_Dwin:
519 mask_shift = GOP_MIU_CLIENT_DWIN;
520 break;
521 #endif
522 default:
523 mask_shift = 0xFF;
524 break;
525 }
526 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
527 {
528 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
529 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
530 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
531 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
532 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
533 }
534
535
536 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
537 {
538 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
539 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
540 #ifdef GOP_MIU_GROUP2
541 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
542 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
543 #endif
544 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
545 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
546 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
547 {
548 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
549 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
550 }
551 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
552 }
553
554 //OC_RM_alpha
555 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
556 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
557 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
558
559 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
560 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
561 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP,GOP_IP_SUB_MUX_MASK, GOP_IP_SUB_MUX_MASK); //default mask sub IP
562 }
563
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)564 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
565 {
566 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
567 }
568
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)569 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
570 {
571 switch(u8GopNum)
572 {
573 case E_GOP0:
574 return (MS_U8)MAX_GOP0_GWIN;
575 break;
576 case E_GOP1:
577 return (MS_U8)MAX_GOP1_GWIN;
578 break;
579 case E_GOP2:
580 return (MS_U8)MAX_GOP2_GWIN;
581 break;
582 case E_GOP3:
583 return (MS_U8)MAX_GOP3_GWIN;
584 break;
585 case E_GOP4:
586 return (MS_U8)MAX_GOP4_GWIN;
587 break;
588 default:
589 MS_ASSERT(0);
590 return 0xFF;
591 break;
592 }
593 }
594
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)595 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
596 {
597 MS_U8 u8GWinId = 0;
598
599 //Adjust GWIN ID by different Chip
600 if(u8Gop >= MAX_GOP_SUPPORT)
601 {
602 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8Gop);
603 MS_ASSERT(0);
604 return 0xFF;
605 }
606
607 switch(u8Gop)
608 {
609 case E_GOP0:
610 u8GWinId = GOP0_GwinIdBase + u8Idx;
611 break;
612 case E_GOP1:
613 u8GWinId = GOP1_GwinIdBase + u8Idx;
614 break;
615 case E_GOP2:
616 u8GWinId = GOP2_GwinIdBase + u8Idx;
617 break;
618 case E_GOP3:
619 u8GWinId = GOP3_GwinIdBase + u8Idx;
620 break;
621 #if (MAX_GOP_SUPPORT>4)
622 case E_GOP4:
623 u8GWinId = GOP4_GwinIdBase + u8Idx;
624 break;
625 #endif
626 default:
627 break;
628 }
629 return u8GWinId;
630
631 }
632
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)633 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
634 {
635 if(u8GOPNum >= MAX_GOP_SUPPORT)
636 {
637 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
638 MS_ASSERT(0);
639 return 0xFF;
640 }
641
642 switch(u8GOPNum)
643 {
644 case E_GOP0: // GOP4G
645 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
646 return GOP_SUCCESS;
647 case E_GOP1: // GOP2G
648 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
649 return GOP_SUCCESS;
650 case E_GOP2: // GOP1G
651 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
652 return GOP_SUCCESS;
653 case E_GOP3: // GOP1GX
654 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
655 return GOP_SUCCESS;
656 #if (MAX_GOP_SUPPORT>4)
657 case E_GOP4: // GOP1GS
658 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
659 return GOP_SUCCESS;
660 #endif
661 default:
662 MS_ASSERT(0);
663 return GOP_FAIL;
664 }
665 }
666
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)667 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
668 {
669 MS_U16 u16Bank;
670 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
671 u16Bank &= ~BMASK(3:0);
672 u16Bank |= (u8bank&BMASK(3:0));
673 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
674 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
675 u16Bank &= ~GOP_BIT4;
676 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
677 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
678 }
679
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)680 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
681 {
682 MS_U16 u16GetBank=0;
683 #if (MAX_GOP_SUPPORT>4)
684 MS_U16 u16BankMask=0;
685
686 if(MAX_GOP_SUPPORT ==5)
687 {
688 u16BankMask = GOP_BANK_MASK | GOP_BIT4;
689 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
690 return (u16GetBank&u16BankMask);
691 }
692 else
693 #endif
694 {
695 u16GetBank = (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
696 return (u16GetBank&GOP_BANK_MASK);
697 }
698 }
699
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)700 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
701 {
702 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
703 MS_U32 bank;
704 MS_U32 direct_addr;
705
706 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
707
708 //* Gop driver should access another HW IP register
709 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
710 switch (u32addr & 0xFF00)
711 {
712 case GOP_REG_BASE:
713 {
714 bank = (u32addr & 0xFF0000) >> 8;
715 #if 0 //for GOP4
716 if(bank==0xE00)//GOP4: 0x121B00
717 {
718 bank=GOP_REG_GOP4_BK_OFFSET;
719 }
720 else if(bank==0xF00)//GWIN4: 0x121E00
721 {
722 bank=GOP_REG_GOP4_GW_OFFSET;
723 }
724 else if(bank==0x1000)//GOP4_ST
725 {
726 bank=GOP_REG_GOP4_ST_OFFSET;
727 }
728 #endif
729 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
730 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
731 break;
732 }
733 case SC1_REG_BASE:
734 {
735 if(g_GopChipPro.bXCDirrectBankSupport)
736 {
737 u16xcSubbank = (u32addr & 0xFF0000)>>8;
738 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
739 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
740 }
741 else
742 {
743 u16xcSubbank = (u32addr & 0xFF0000)>>16;
744 u16BankAddr = GOP_SC_BANKSEL+0;
745 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
746
747 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
748 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
749 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
750 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
751 }
752 break;
753 }
754 case GE_REG_BASE:
755 case CKG_REG_BASE:
756 case MIU0_REG_BASE:
757 case MIU_REG_BASE:
758 case MVOP_REG_BASE:
759 case VE_REG_BASE:
760 {
761 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
762 break;
763 }
764 #ifdef GOP_MIU_GROUP2
765 case (MIU2_REG_BASE & 0xFF00):
766 {
767 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
768 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
769
770 break;
771 }
772 #endif
773 default:
774 {
775 //Gop lib current do not support this HW ip base
776 MS_ASSERT(0);
777 *pu16ret =0;
778 break;
779 }
780 }
781 }
782
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)783 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
784 {
785 MS_U16 u16tmp=0;
786 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
787 MS_U32 bank;
788 MS_U32 direct_addr;
789
790 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u32addr, u16val));
791
792 if(mask!=0xffff)
793 {
794 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
795 u16tmp &= ~mask;
796 u16val &= mask;
797 u16val |= u16tmp;
798 }
799
800 //* Gop driver should access another HW IP register
801 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
802 switch (u32addr & 0xFF00)
803 {
804 case GOP_REG_BASE:
805 {
806 bank = (u32addr & 0xFF0000) >> 8;
807 #if 0 //for GOP4
808 if(bank==0xE00)//GOP4: 0x121B00
809 {
810 bank=GOP_REG_GOP4_BK_OFFSET;
811 }
812 else if(bank==0xF00)//GWIN4: 0x121E00
813 {
814 bank=GOP_REG_GOP4_GW_OFFSET;
815 }
816 else if(bank==0x1000) //GOP4_ST
817 {
818 bank=GOP_REG_GOP4_ST_OFFSET;
819 }
820 #endif
821 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
822 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
823 break;
824 }
825 case SC1_REG_BASE:
826 if(g_GopChipPro.bXCDirrectBankSupport)
827 { /*Derrick Bank*/
828 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
829 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
830 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
831 }
832 else
833 { /*Sub Bank*/
834 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
835 u16BankAddr = GOP_SC_BANKSEL+0;
836 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
837
838 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
839 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
840 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
841 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
842 }
843 break;
844 case GE_REG_BASE:
845 case CKG_REG_BASE:
846 case MIU0_REG_BASE:
847 case MIU_REG_BASE:
848 case VE_REG_BASE:
849 {
850 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
851 break;
852 }
853 #ifdef GOP_MIU_GROUP2
854 case (MIU2_REG_BASE & 0xFF00):
855 {
856 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
857 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
858 break;
859 }
860 #endif
861 default:
862 {
863 //Gop lib current do not support this HW ip base
864 MS_ASSERT(0);
865 break;
866 }
867
868 }
869 }
870
871
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)872 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
873 {
874 MS_U32 bank;
875 MS_U32 direct_addr;
876
877 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
878
879 //* Gop driver should access another HW IP register
880 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
881 switch (u32addr & 0xFF00)
882 {
883 case GOP_REG_BASE:
884 {
885 bank = (u32addr & 0xFF0000) >> 8;
886 #if 0 //for GOP4
887 if(bank==0xE00)//GOP4: 0x121B00
888 {
889 bank=GOP_REG_GOP4_BK_OFFSET;
890 }
891 else if(bank==0xF00)//GWIN4: 0x121E00
892 {
893 bank=GOP_REG_GOP4_GW_OFFSET;
894 }
895 else if(bank==0x1000) //GOP4_ST
896 {
897 bank=GOP_REG_GOP4_ST_OFFSET;
898 }
899 #endif
900 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
901 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
902 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
903 break;
904 }
905
906 case GE_REG_BASE:
907 case SC1_REG_BASE:
908 case CKG_REG_BASE:
909 {
910 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
911 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
912 break;
913 }
914
915 default:
916 {
917 //Gop lib current do not support this HW ip base
918 MS_ASSERT(0);
919 break;
920 }
921
922 }
923 }
924
925 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
926
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)927 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
928 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
929 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
930 {
931 MS_U8 i=0;
932 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",u8Index, u8A, u8R, u8G, u8B));
933
934 /* Don't care high byte */
935 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
936
937 for(i =(GOP_WordUnit-1);i>4;i--)
938 {
939 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
940 }
941 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
942 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
943 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
944 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
945 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
946 *pREGMAP_Offset += GOP_WordUnit;
947
948 MsOS_FlushMemory(); //make sure cpu write data to dram
949
950 }
951
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)952 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
953 {
954 MS_U16 bpp=0;
955
956 switch ( fbFmt )
957 {
958 case E_DRV_GOP_COLOR_RGB555_BLINK :
959 case E_DRV_GOP_COLOR_RGB565 :
960 case E_DRV_GOP_COLOR_ARGB1555:
961 case E_DRV_GOP_COLOR_RGBA5551:
962 case E_DRV_GOP_COLOR_ARGB4444 :
963 case E_DRV_GOP_COLOR_RGBA4444 :
964 case E_DRV_GOP_COLOR_RGB555YUV422:
965 case E_DRV_GOP_COLOR_YUV422:
966 case E_DRV_GOP_COLOR_2266:
967 bpp = 16;
968 break;
969 case E_DRV_GOP_COLOR_ARGB8888 :
970 case E_DRV_GOP_COLOR_ABGR8888 :
971 bpp = 32;
972 break;
973
974 case E_DRV_GOP_COLOR_I8 :
975 bpp = 8;
976 break;
977
978 default :
979 //print err
980 MS_ASSERT(0);
981 bpp = 0xFFFF;
982 break;
983 }
984 return bpp;
985
986 }
987
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)988 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
989 {
990 MS_U16 regval;
991 /*For compatibility
992 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
993 MS_U8 u8coef_cpt = u8coef;
994
995 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
996 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
997 {
998 switch(u8coef)
999 {
1000 case 0x0 :
1001 u8coef_cpt = u8coef<<2;
1002 break;
1003 case 0x3f :
1004 u8coef_cpt = ((u8coef<<2)|0x3);
1005 break;
1006 default:
1007 u8coef_cpt = ((u8coef<<2)|0x1);
1008 break;
1009 }
1010 }
1011
1012 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1013 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1014 {
1015 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1016 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1017 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1018 }
1019 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1020 else
1021 {
1022 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1023 {
1024 regval = (MS_U16)(bEnable?(1<<14):0);
1025 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1026 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1027 }
1028 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1029 {
1030 regval = (MS_U16)(bEnable?(1<<14):0);
1031 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1032 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1033 }
1034 else
1035 {
1036 regval = (MS_U16)(bEnable?(1<<14):0);
1037 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1038 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1039 }
1040 }
1041 }
1042
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1043 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1044 {
1045 pGOPHalLocal->va_mmio_base = addr;
1046 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1047 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1048 {
1049 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1050 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1051 {
1052 }
1053
1054
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1055 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1056 {
1057 /*A5 GOP dst type:
1058 1: IP (Main)
1059 0: IP (Sub)
1060 2: OP
1061 3: MVOP
1062 4: MVOP (Sub)
1063 6: FRC
1064 11: InsideFRC
1065 */
1066 MS_U16 u16RegVal;
1067 MS_U32 u32BankOffSet;
1068 MS_BOOL bEnable=FALSE;
1069 MS_U16 u16HSyncMask=GOP_BIT14;
1070
1071 if( GopNum >= MAX_GOP_SUPPORT)
1072 {
1073 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,GopNum);
1074 return GOP_INVALID_PARAMETERS;
1075 }
1076
1077 switch (eDstType)
1078 {
1079 case E_DRV_GOP_DST_IP0:
1080 u16RegVal = 0x0;
1081 bEnable = FALSE;
1082 u16HSyncMask=0;
1083 break;
1084
1085 case E_DRV_GOP_DST_IP0_SUB:
1086 u16RegVal = 0x1;
1087 bEnable = FALSE;
1088 u16HSyncMask=0;
1089 break;
1090
1091 case E_DRV_GOP_DST_OP0:
1092 u16RegVal = 0x2;
1093 bEnable = FALSE;
1094 u16HSyncMask=GOP_BIT14;
1095 break;
1096
1097 case E_DRV_GOP_DST_VOP:
1098 u16RegVal = 0x3;
1099 bEnable = FALSE;
1100 u16HSyncMask=GOP_BIT14;
1101 break;
1102
1103 case E_DRV_GOP_DST_VOP_SUB:
1104 u16RegVal = 0x4;
1105 bEnable = FALSE;
1106 u16HSyncMask=GOP_BIT14;
1107 break;
1108
1109 case E_DRV_GOP_DST_FRC:
1110 u16RegVal = 0x6;
1111 bEnable = TRUE;
1112 u16HSyncMask=GOP_BIT14;
1113 break;
1114
1115 case E_DRV_GOP_DST_DIP:
1116 u16RegVal = 0x8;
1117 bEnable = TRUE;
1118 u16HSyncMask=GOP_BIT14;
1119 break;
1120 case E_DRV_GOP_DST_VE:
1121 case E_DRV_GOP_DST_OP1:
1122 u16RegVal = 0x6;
1123 bEnable = TRUE;
1124 u16HSyncMask=GOP_BIT14;
1125 break;
1126 case E_DRV_GOP_DST_IP1:
1127 u16RegVal = 0x5;
1128 bEnable = TRUE;
1129 break;
1130
1131 default:
1132 return GOP_FUN_NOT_SUPPORTED;
1133 }
1134
1135 if(bOnlyCheck == FALSE)
1136 {
1137 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1138 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1139 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(3:0));
1140
1141 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1142 }
1143 return GOP_SUCCESS;
1144 }
1145
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1146 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1147 {
1148 /*U4 Mixer dst type:
1149 2: OP
1150 3: VE
1151 */
1152 MS_U16 u16Regval = 0;
1153 DRV_MixerDstType eType=E_DRV_MIXER_DST_VE;
1154
1155 switch(eDstType)
1156 {
1157 case E_DRV_GOP_DST_MIXER2VE:
1158 eType = E_DRV_MIXER_DST_VE;
1159 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //Enable pseudo hsync
1160 break;
1161 case E_DRV_GOP_DST_MIXER2OP:
1162 eType = E_DRV_MIXER_DST_OP;
1163 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT7); //Disable pseudo hsync
1164 break;
1165 default:
1166 break;
1167 }
1168
1169 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1170
1171 u16Regval &= (~(GOP_BIT3|GOP_BIT4));
1172 u16Regval |= (eType<<0x3);
1173
1174 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4));
1175 return GOP_SUCCESS;
1176 }
1177
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1178 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1179 {
1180 MS_U16 u16Regval = 0;
1181
1182 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1183
1184 if(((u16Regval&0x18)>>3) == 0x2)
1185 *pGopDst = E_DRV_GOP_DST_MIXER2OP;
1186 else
1187 *pGopDst = E_DRV_GOP_DST_MIXER2VE;
1188
1189 return GOP_SUCCESS;
1190 }
1191
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1192 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1193 {
1194 /*T8
1195 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1196 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1197 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1198 */
1199 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1200 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1201
1202 /*Disable VE OSD enable*/
1203 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_0, 0x4);
1204 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_1, 0x4);
1205
1206 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_VOPNBL, 1<<7, GOP_BIT7);
1207 return GOP_SUCCESS;
1208 }
1209
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1210 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1211 {
1212 MS_U16 u16GopMux=0;
1213 switch(eGopMux)
1214 {
1215 case E_GOP_MUX0:
1216 case E_GOP_MUX1:
1217 case E_GOP_MUX2:
1218 case E_GOP_MUX3:
1219 case E_GOP_MUX4:
1220 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1221 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1222 break;
1223 case E_GOP_IP0_MUX:
1224 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1225 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1226 break;
1227 case E_GOP_IP0_SUB_MUX:
1228 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1229 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1230 break;
1231 case E_GOP_VOP0_MUX:
1232 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1233 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1234 break;
1235 case E_GOP_VOP0_SUB_MUX:
1236 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1237 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1238 break;
1239 case E_GOP_Mix_MUX0:
1240 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1241 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1242 break;
1243 case E_GOP_Mix_MUX1:
1244 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1245 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1246 break;
1247 case E_GOP_VE0_MUX:
1248 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1249 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1250 break;
1251 case E_GOP_VE1_MUX:
1252 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1253 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1254 break;
1255 case E_GOP_DIP_MUX:
1256 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1257 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1258 break;
1259 case E_GOP_FRC_MUX0:
1260 case E_GOP_FRC_MUX1:
1261 case E_GOP_FRC_MUX2:
1262 case E_GOP_FRC_MUX3:
1263 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1264 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1265 break;
1266 case E_GOP_BYPASS_MUX0:
1267 break;
1268 case E_GOP_OP1_MUX:
1269 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_SC1, &u16GopMux);
1270 *u8GOPNum = (u16GopMux& ((BMASK((GOP_MUX_SHIFT-1):0))<<12))>>12;
1271 break;
1272 case E_GOP_IP1_MUX:
1273 case E_GOP_VOP1_MUX:
1274 case E_GOP_GS_MUX:
1275 case E_GOP_DUALRATE_OP_MUX0:
1276 case E_GOP_DUALRATE_OP_MUX1:
1277 case E_GOP_DUALRATE_OP_MUX2:
1278 // to prevent warning log
1279 break;
1280 default:
1281 printf("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1282 break;
1283 }
1284 }
1285
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1286 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1287 {
1288 MS_U16 u16Ret[4]={0};
1289
1290 switch(eGopMux)
1291 {
1292 case E_GOP_MUX0:
1293 case E_GOP_MUX1:
1294 case E_GOP_MUX2:
1295 case E_GOP_MUX3:
1296 case E_GOP_MUX4:
1297 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1298 break;
1299 case E_GOP_OP1_MUX:
1300 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_SC1, u8GOPNum <<12, GOP_REGMUX_MASK<<12);
1301 break;
1302 case E_GOP_IP0_MUX:
1303 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1304 break;
1305 case E_GOP_IP1_MUX:
1306 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << 0, BMASK(2:0));
1307 break;
1308 case E_GOP_VOP0_MUX:
1309 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1310 break;
1311 case E_GOP_VOP1_MUX:
1312 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1313 break;
1314 case E_GOP_Mix_MUX0:
1315 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1316 break;
1317 case E_GOP_Mix_MUX1:
1318 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1319 break;
1320 case E_GOP_VE0_MUX:
1321 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1322 break;
1323 case E_GOP_VE1_MUX:
1324 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1325 break;
1326 case E_GOP_DIP_MUX:
1327 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1328 break;
1329 case E_GOP_FRC_MUX0:
1330 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1331 break;
1332 case E_GOP_FRC_MUX1:
1333 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1334 break;
1335 case E_GOP_FRC_MUX2:
1336 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1337 break;
1338 case E_GOP_FRC_MUX3:
1339 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1340 break;
1341 case E_GOP_BYPASS_MUX0:
1342 //Check MUX is using? Checking from priority high to low
1343 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1344 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1345 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1346 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1347
1348 //Checking if un-use
1349 if((u16Ret[0] & GOP_BIT0) ==0)
1350 {
1351 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1352 }
1353 else if((u16Ret[1] & GOP_BIT0) ==0)
1354 {
1355 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1356 }
1357 else if((u16Ret[2] & GOP_BIT0) ==0)
1358 {
1359 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1360 }
1361 else if((u16Ret[3] & GOP_BIT0) ==0)
1362 {
1363 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1364 }
1365 else
1366 {
1367 printf("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1368 }
1369 break;
1370 break;
1371 default:
1372 printf("[%s]ERROR mux setting\n",__FUNCTION__);
1373 break;
1374 }
1375 }
1376
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1377 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1378 {
1379 /* GOP OP Path enable to SC Setting
1380 A5: GOP OP Path blending with SC sequence
1381 mux1-->mux0-->mux2-->mux3
1382 */
1383 MS_BOOL bOSDBEnable=TRUE;
1384 MS_U16 muxValue=0, mux4Value=0, regval=0;
1385
1386 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1387 MS_U16 u164K2KMuxValue=0;
1388
1389 if(gopNum >= MAX_GOP_SUPPORT)
1390 {
1391 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1392 return GOP_FAIL;
1393 }
1394
1395 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1396 if(bOSDBEnable)
1397 {
1398 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, 0x0, GOP_REG_HW_MASK);
1399
1400 }else
1401 {
1402 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1403 }
1404
1405 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1406 {
1407 if(bOSDBEnable)
1408 {
1409 if(bEnable)
1410 {
1411 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1412 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3);
1413 }else{
1414 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3);
1415 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1416 }
1417 }
1418 else
1419 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1420 }
1421
1422 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1423 {
1424 if(bOSDBEnable)
1425 {
1426 if(bEnable)
1427 {
1428 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1429 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT11, GOP_BIT11);
1430 }else{
1431 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT11);
1432 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1433 }
1434 }
1435 else
1436 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1437 }
1438
1439 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1440 {
1441 if(bOSDBEnable)
1442 {
1443 if(bEnable)
1444 {
1445 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1446 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3);
1447 }else{
1448 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3);
1449 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1450 }
1451 }
1452 else
1453 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1454 }
1455
1456 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1457 {
1458 if(bOSDBEnable)
1459 {
1460 if(bEnable)
1461 {
1462 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1463 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT11, GOP_BIT11);
1464 }else{
1465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT11);
1466 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1467 }
1468 }
1469 else
1470 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1471 }
1472
1473
1474 if(MAX_GOP_SUPPORT ==5)
1475 {
1476 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &mux4Value);
1477 if (gopNum== ((mux4Value & GOP_MUX4_MASK)>> GOP_MUX4_SHIFT)) //enable mux4
1478 {
1479 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1480 }
1481 }
1482
1483 /*For FRC mux switch*/
1484 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1485 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1486 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1487 {
1488 /* Switch FRC blending */
1489 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1490 }
1491
1492 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1493 {
1494 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1495 }
1496
1497 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1498 {
1499 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1500 }
1501
1502 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1503 {
1504 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1505 }
1506
1507 return GOP_SUCCESS;
1508 }
1509
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1510 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1511 {
1512 MS_U32 u32pBankOffSet=0;
1513 MS_U16 u16Regval;
1514
1515 if(g_GopChipPro.b2Pto1PSupport)
1516 {
1517 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1518 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1519 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |GOP_BIT11):(u16Regval & ~GOP_BIT11), GOP_BIT11);
1520 }
1521 return GOP_SUCCESS;
1522 }
1523
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1524 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1525 {
1526 /* GOP OP Path enable to SC Setting
1527 A5: GOP OP Path blending with SC sequence
1528 mux1-->mux0-->mux2-->mux3
1529 */
1530 MS_U16 muxValue=0;
1531
1532 if(gopNum >= MAX_GOP_SUPPORT)
1533 {
1534 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1535 return FALSE;
1536 }
1537
1538 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1539 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1540 {
1541 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, bEnable?(GOP_BIT5):(~GOP_BIT5), GOP_BIT5);
1542 }
1543 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1544 {
1545 //printf("");
1546 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, bEnable?(GOP_BIT13):(~GOP_BIT13), GOP_BIT13);
1547 }
1548 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1549 {
1550 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, bEnable?(GOP_BIT5):(~GOP_BIT5), GOP_BIT5);
1551 }
1552 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1553 {
1554 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, bEnable?(GOP_BIT13):(~GOP_BIT13), GOP_BIT13);
1555 }
1556 else
1557 {
1558 return GOP_FAIL;
1559 }
1560 return GOP_SUCCESS;
1561 }
1562
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1563 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1564 {
1565 MS_U16 muxValue=0;
1566 MS_U16 regval37=0;
1567 MS_U16 regval38=0;
1568
1569 if(gopNum >= MAX_GOP_SUPPORT)
1570 {
1571 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1572 return FALSE;
1573 }
1574
1575 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1576 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, ®val37);
1577 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, ®val38);
1578 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1579 {
1580 *pbEnable = (regval37& GOP_BIT5) == GOP_BIT5;
1581 }
1582 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1583 {
1584 *pbEnable = (regval37 & GOP_BIT13) == GOP_BIT13;
1585 }
1586 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1587 {
1588 *pbEnable = (regval38 & GOP_BIT5) == GOP_BIT5;
1589 }
1590 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1591 {
1592 *pbEnable = (regval38 & GOP_BIT13) == GOP_BIT13;
1593 }
1594 else
1595 {
1596 return GOP_FAIL;
1597 }
1598 return GOP_SUCCESS;
1599 }
1600
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1601 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1602 {
1603 /*T8
1604 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1605 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1606 */
1607 MS_U16 Mux3Gop, muxValue=0, i;
1608 MS_U16 MuxShift;
1609
1610 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1611
1612 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1613 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1614 {
1615 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1616 {
1617 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1618
1619 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1620 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1621 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1622 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1623 break;
1624
1625 }
1626
1627 }
1628 return GOP_SUCCESS;
1629 }
1630
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1631 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1632 {
1633 /*T8 GOP dst type:
1634 0: IP (Main)
1635 1: IP (Sub)
1636 2: OP
1637 3: MVOP
1638 */
1639
1640 if(gopNum >= MAX_GOP_SUPPORT)
1641 {
1642 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1643 MS_ASSERT(0);
1644 return GOP_INVALID_PARAMETERS;
1645 }
1646 /* Monaco clkgen setting */
1647 /******************
1648 0: odclk
1649 1: idclk_f2 (ipm)
1650 2: idclk_f1 (ips)
1651 3: ocmixer
1652 4: ve
1653 5 : mvop main
1654 6 : mvop sub
1655 ******************/
1656
1657 switch(eDstType)
1658 {
1659 case E_DRV_GOP_DST_IP0:
1660
1661 if (gopNum==E_GOP1)
1662 {
1663 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1664 }
1665 else if (gopNum ==E_GOP2)
1666 {
1667 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1668 }
1669 else if (gopNum ==E_GOP3)
1670 {
1671 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1672 }
1673 #if (MAX_GOP_SUPPORT>4)
1674 else if (gopNum ==E_GOP4)
1675 {
1676 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1677 }
1678 #endif
1679 else if (gopNum==E_GOP0)
1680 {
1681 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1682 }
1683 else
1684 {
1685 MS_ASSERT(0);
1686 return GOP_INVALID_PARAMETERS;
1687 }
1688 break;
1689
1690 case E_DRV_GOP_DST_IP0_SUB:
1691 if (gopNum==E_GOP1)
1692 {
1693 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1694 }
1695 else if (gopNum==E_GOP2)
1696 {
1697 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG1_IDCLK2, CKG_GOPG2_MASK);
1698 }
1699 else if (gopNum==E_GOP3)
1700 {
1701 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG1_IDCLK2, CKG_GOPG3_MASK);
1702 }
1703 #if (MAX_GOP_SUPPORT>4)
1704 else if (gopNum ==E_GOP4)
1705 {
1706 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG1_IDCLK2, CKG_GOPG4_MASK);
1707 }
1708 #endif
1709 else if (gopNum==E_GOP0)
1710 {
1711 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG0_MASK);
1712 }
1713 else
1714 {
1715 MS_ASSERT(0);
1716 return GOP_INVALID_PARAMETERS;
1717 }
1718 break;
1719
1720 case E_DRV_GOP_DST_IP1:
1721 if (gopNum==E_GOP1)
1722 {
1723 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1724 }
1725 else if (gopNum==E_GOP2)
1726 {
1727 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG1_IDCLK1, CKG_GOPG2_MASK);
1728 }
1729 else if (gopNum==E_GOP3)
1730 {
1731 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG1_IDCLK1, CKG_GOPG3_MASK);
1732 }
1733 #if (MAX_GOP_SUPPORT>4)
1734 else if (gopNum ==E_GOP4)
1735 {
1736 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG1_IDCLK1, CKG_GOPG4_MASK);
1737 }
1738 #endif
1739 else if (gopNum==E_GOP0)
1740 {
1741 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG0_MASK);
1742 }
1743 else
1744 {
1745 MS_ASSERT(0);
1746 return GOP_INVALID_PARAMETERS;
1747 }
1748 break;
1749 case E_DRV_GOP_DST_MIXER2VE:
1750 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_VECLK, CKG_GOPMIXER_MASK);
1751
1752 if(gopNum == 0)
1753 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
1754 else if(gopNum == 1)
1755 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
1756 else if(gopNum == 2)
1757 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
1758 else if(gopNum == 3)
1759 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
1760 break;
1761
1762 case E_DRV_GOP_DST_OP0:
1763 if (gopNum==E_GOP1)
1764 {
1765 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1766 }
1767 else if (gopNum==E_GOP2)
1768 {
1769 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1770 }
1771 else if (gopNum==E_GOP3)
1772 {
1773 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
1774 }
1775 #if (MAX_GOP_SUPPORT>4)
1776 else if (gopNum ==E_GOP4)
1777 {
1778 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
1779 }
1780 #endif
1781 else if (gopNum==E_GOP0)
1782 {
1783 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1784 }
1785 else
1786 {
1787 MS_ASSERT(0);
1788 return GOP_INVALID_PARAMETERS;
1789 }
1790
1791 break;
1792
1793 case E_DRV_GOP_DST_DIP:
1794 if (gopNum==E_GOP1)
1795 {
1796 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
1797 }
1798 else if (gopNum==E_GOP2)
1799 {
1800 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
1801 }
1802 else if (gopNum==E_GOP3)
1803 {
1804 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
1805 }
1806 #if (MAX_GOP_SUPPORT>4)
1807 else if (gopNum ==E_GOP4)
1808 {
1809 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
1810 }
1811 #endif
1812 else if (gopNum==E_GOP0)
1813 {
1814 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
1815 }
1816 else
1817 {
1818 MS_ASSERT(0);
1819 return GOP_INVALID_PARAMETERS;
1820 }
1821
1822 break;
1823 case E_DRV_GOP_DST_VOP:
1824 if (gopNum==E_GOP1)
1825 {
1826 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MVOP, CKG_GOPG1_MASK);
1827 }
1828 else if (gopNum==E_GOP2)
1829 {
1830 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_MVOP, CKG_GOPG2_MASK);
1831 }
1832 else if (gopNum==E_GOP3)
1833 {
1834 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_MVOP, CKG_GOPG3_MASK);
1835 }
1836 #if (MAX_GOP_SUPPORT>4)
1837 else if (gopNum ==E_GOP4)
1838 {
1839 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MVOP, CKG_GOPG4_MASK);
1840 }
1841 #endif
1842 else if (gopNum==E_GOP0)
1843 {
1844 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MVOP, CKG_GOPG0_MASK);
1845 }
1846 else
1847 {
1848 MS_ASSERT(0);
1849 return GOP_INVALID_PARAMETERS;
1850 }
1851
1852 break;
1853 case E_DRV_GOP_DST_FRC:
1854 if (gopNum==E_GOP1)
1855 {
1856 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
1857 }
1858 else if (gopNum==E_GOP0)
1859 {
1860 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
1861 }
1862 else if (gopNum ==E_GOP2)
1863 {
1864 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
1865 }
1866 else if (gopNum ==E_GOP3)
1867 {
1868 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
1869 }
1870 #if (MAX_GOP_SUPPORT>4)
1871 else if (gopNum ==E_GOP4)
1872 {
1873 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
1874 }
1875 #endif
1876 else
1877 {
1878 MS_ASSERT(0);
1879 return GOP_INVALID_PARAMETERS;
1880 }
1881
1882 break;
1883 case E_DRV_GOP_DST_BYPASS:
1884 if (gopNum==E_GOP0)
1885 {
1886 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_BYPASS_FRCCLK, CKG_GOPG0_MASK);
1887 }
1888 else if (gopNum==E_GOP1)
1889 {
1890 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_BYPASS_FRCCLK, CKG_GOPG1_MASK);
1891 }
1892 else if (gopNum==E_GOP2)
1893 {
1894 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_BYPASS_FRCCLK, CKG_GOPG2_MASK);
1895 }
1896 else if (gopNum==E_GOP3)
1897 {
1898 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_BYPASS_FRCCLK, CKG_GOPG3_MASK);
1899 }
1900 #if (MAX_GOP_SUPPORT>4)
1901 else if (gopNum ==E_GOP4)
1902 {
1903 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_BYPASS_FRCCLK, CKG_GOPG4_MASK);
1904 }
1905 #endif
1906 else
1907 {
1908 MS_ASSERT(0);
1909 return GOP_INVALID_PARAMETERS;
1910 }
1911 break;
1912 case E_DRV_GOP_DST_MIXER2OP:
1913 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_ODCLK, CKG_GOPMIXER_MASK);
1914 break;
1915 case E_DRV_GOP_DST_OP1:
1916 if (gopNum==E_GOP1)
1917 {
1918 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OD1CLK, CKG_GOPG1_MASK);
1919 }
1920 else if (gopNum==E_GOP2)
1921 {
1922 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OD1CLK, CKG_GOPG2_MASK);
1923 }
1924 else if (gopNum==E_GOP3)
1925 {
1926 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OD1CLK, CKG_GOPG3_MASK);
1927 }
1928 #if (MAX_GOP_SUPPORT>4)
1929 else if (gopNum ==E_GOP4)
1930 {
1931 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OD1CLK, CKG_GOPG4_MASK);
1932 }
1933 #endif
1934 else if (gopNum==E_GOP0)
1935 {
1936 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OD1CLK, CKG_GOPG0_MASK);
1937 }
1938 else
1939 {
1940 MS_ASSERT(0);
1941 return GOP_INVALID_PARAMETERS;
1942 }
1943 break;
1944
1945 default:
1946 MS_ASSERT(0);
1947 return GOP_ENUM_NOT_SUPPORTED;
1948 }
1949 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1950 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1951
1952 return GOP_SUCCESS;
1953 }
1954
1955
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1956 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1957 {
1958 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1959 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1960 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1961 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1962 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1963 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1964 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1965 else
1966 return GOP_INVALID_PARAMETERS;
1967
1968 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1969 return GOP_SUCCESS;
1970 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1971 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1972 {
1973 if (bEnable)
1974 {
1975 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1976 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1977 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1978 }
1979 else
1980 {
1981 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1982 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1983 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1984 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1985 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1986 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1987 }
1988
1989 return GOP_SUCCESS;
1990 }
1991
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1992 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1993 {
1994 DRV_GOPDstType MixerDstType;
1995 MS_U16 regval = 0;
1996 MS_U8 u8MUXGOPNum = 0;
1997 int i = 0;
1998
1999 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2000 #if 0 //TO DO: To disable mixer mux
2001 MS_U16 u16val;
2002 if( regval & 0x0001) //MIXER GOP0 enable -> enable GOP1
2003 {
2004 u16val = (bEnable? TRUE: FALSE);
2005 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
2006 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2007 }
2008 else //enable GOP0
2009 {
2010 u16val = (bEnable? TRUE: FALSE);
2011 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
2012 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2013 }
2014 #else
2015 if((regval&(GOP_BIT0|GOP_BIT1)) == (GOP_BIT0|GOP_BIT1))
2016 {
2017 if((gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10)) && (gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12)))
2018 {
2019 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2020 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2021 }
2022 }
2023 else if(regval&GOP_BIT0)
2024 {
2025 if(gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2026 {
2027 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
2028 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2029 }
2030 }
2031 else if(regval&GOP_BIT1) //gop1Enable
2032 {
2033 if(gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2034 {
2035 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
2036 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2037 }
2038 }
2039 else //no one enable
2040 {
2041 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2042 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2043 }
2044 #endif
2045
2046 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //disable pseudo hsync
2047
2048 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2049
2050 HAL_GOP_GetMixerDst(pGOPHalLocal,&MixerDstType);
2051 if(MixerDstType == E_DRV_GOP_DST_MIXER2OP)
2052 {
2053 for (i=0; i<MAX_GOP_MUX - 1; i++) //mux3 not supported to OP
2054 {
2055 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &u8MUXGOPNum, (Gop_MuxSel)i);
2056 if (0x4==u8MUXGOPNum)
2057 {
2058 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, TRUE);
2059 }
2060 else
2061 {
2062 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, FALSE);
2063 }
2064 }
2065 }
2066 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_EN_VFIL, GOP_MIXER_EN_VFIL_MASK);
2067 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_VS_FLD_ON, GOP_MIXER_VS_FLD_ON_MASK);
2068 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_REG_DUMMY, GOP_BIT0, GOP_BIT0);
2069 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15); //Enable Mixer
2070
2071 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2072 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2073
2074
2075 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2076
2077 #if 0 /* PAL System*/
2078 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2079 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2080 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_HSTART_OFST, GOP_REG_WORD_MASK);
2081 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_VSTART_OFST, GOP_REG_WORD_MASK);
2082 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, 0x330, GOP_REG_WORD_MASK);
2083 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, 0x25D, GOP_REG_WORD_MASK);
2084 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2085 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_HS_DELAY, GOP_REG_WORD_MASK);
2086 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, GOP_MIXER_PD, GOP_REG_WORD_MASK);
2087 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2088 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2089 #endif
2090 return GOP_SUCCESS;
2091
2092 }
2093
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)2094 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
2095 {
2096 MS_U16 u16val;
2097
2098 if (muxNum >= MAX_MIXER_MUX)
2099 {
2100 MS_CRITICAL_MSG(printf("\n[%s] not support mux%d in this chip version!!",__FUNCTION__, muxNum));
2101 return GOP_FAIL;
2102 }
2103
2104 if(muxNum==MIXER_MUX0Id) //Set GOP to mux0
2105 {
2106 u16val = (bEnable? TRUE: FALSE);
2107 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
2108 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2109 }
2110 else //Set GOP to mux1
2111 {
2112 u16val = (bEnable? TRUE: FALSE);
2113 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
2114 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2115 }
2116 return GOP_SUCCESS;
2117
2118 }
2119
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2120 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
2121 {
2122 MS_U32 u32bankoffset = 0;
2123 DRV_GOPDstType gopDstType = E_DRV_GOP_DST_IP0;
2124 MS_U16 regval = 0x0;
2125
2126 HAL_GOP_GetGOPDst(pGOPHalLocal, u8GOP, &gopDstType);
2127
2128 if(gopDstType == E_DRV_GOP_DST_MIXER2VE)
2129 {
2130
2131 _GetBnkOfstByGop(u8GOP, &u32bankoffset);
2132
2133 if(bEn)
2134 {
2135
2136 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT2, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2137 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)~GOP_BIT15, GOP_BIT15);
2138
2139 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2140
2141 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2142 {
2143 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2144 }
2145 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2146 {
2147 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD1_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2148 }
2149 else
2150 {
2151 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2152 return GOP_FAIL;
2153 }
2154 }
2155 else
2156 {
2157 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2158 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2159
2160 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2161
2162 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2163 {
2164 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2165 }
2166 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2167 {
2168 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD1_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2169 }
2170 else
2171 {
2172 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2173 return GOP_FAIL;
2174 }
2175 }
2176 }
2177 else
2178 {
2179 printf("[%s][%d]GOP not on Mixer2VE path\n",__FUNCTION__,__LINE__);
2180 return GOP_FAIL;
2181 }
2182
2183 return GOP_SUCCESS;
2184
2185 }
2186
HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2187 GOP_Result HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2188 {
2189 MS_U16 bankTemp = 0;
2190 MS_U16 u16val = 0;
2191
2192 u16val = (bEnable? TRUE: FALSE);
2193 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2194 switch (muxNum) //Enable OP new alpha mode
2195 {
2196 case 0:
2197 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2198 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<1), GOP_BIT1);
2199 break;
2200 case 1:
2201 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2202 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<6), GOP_BIT6);
2203 break;
2204 case 2:
2205 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2206 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<8), GOP_BIT8);
2207 break;
2208 default:
2209 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2210 break;
2211 }
2212 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2213 return GOP_SUCCESS;
2214 }
2215
HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2216 GOP_Result HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2217 {
2218 MS_U16 bankTemp = 0;
2219 MS_U16 u16val = 0;
2220
2221 u16val = (bEnable? TRUE: FALSE);
2222 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2223 switch (muxNum) //Enable OP per pixel new alpha mode
2224 {
2225 case 0:
2226 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2227 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<3), GOP_BIT3);
2228 break;
2229 case 1:
2230 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2231 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<14), GOP_BIT14);
2232 break;
2233 case 2:
2234 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2235 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<15), GOP_BIT15);
2236 break;
2237 default:
2238 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2239 break;
2240 }
2241 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2242 return GOP_SUCCESS;
2243 }
2244
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2245 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2246 {
2247 MS_U32 u32GopIdx;
2248
2249 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2250 pGOPHalLocal->pHALShared = pHALShared;
2251
2252 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2253 {
2254 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2255 }
2256 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
2257 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2258 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2259 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2260 {
2261 }
2262
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2263 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2264 {
2265 MS_U8 u8Miu=0xff;
2266 MS_U16 u16RegVal_L=0;
2267 #ifdef GOP_MIU_GROUP2
2268 MS_U16 u16RegVal_H=0;
2269 #endif
2270
2271 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2272 #ifdef GOP_MIU_GROUP2
2273 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2274 #endif
2275 if (gwinid<MAX_GOP0_GWIN) //gop0
2276 {
2277 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2278 #ifdef GOP_MIU_GROUP2
2279 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2280 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2281 #else
2282 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2283 #endif
2284 }
2285 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
2286 {
2287 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2288 #ifdef GOP_MIU_GROUP2
2289 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2290 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2291 #else
2292 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2293 #endif
2294 }
2295 else if (gwinid==GOP2_GwinIdBase) //gop2
2296 {
2297 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2298 #ifdef GOP_MIU_GROUP2
2299 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2300 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2301 #else
2302 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2303 #endif
2304 }
2305 else if (gwinid==GOP3_GwinIdBase) //gop3
2306 {
2307 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2308 #ifdef GOP_MIU_GROUP2
2309 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2310 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2311 #else
2312 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2313 #endif
2314 }
2315 else if (gwinid==GOP4_GwinIdBase)//gop4
2316 {
2317 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
2318 #ifdef GOP_MIU_GROUP2
2319 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
2320 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
2321 #else
2322 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
2323 #endif
2324 }
2325 else
2326 {
2327 return GOP_FAIL;
2328 }
2329
2330 if (u8Miu <= 2)
2331 {
2332 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2333 }
2334 else
2335 {
2336 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2337 return GOP_FAIL;
2338 }
2339 return GOP_SUCCESS;
2340 }
2341
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2342 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2343 {
2344 MS_U8 u8Miu=0xff;
2345 MS_U16 u16RegVal_L=0;
2346 MS_U32 u32BnkOfst=0xFFFF;
2347 #ifdef GOP_MIU_GROUP2
2348 MS_U16 u16RegVal_H=0;
2349 #endif
2350
2351 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2352 {
2353 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2354 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2355
2356 u8Miu= (u16RegVal_L& (GOP_BIT2|GOP_BIT3)) >>2;
2357 }
2358 else
2359 {
2360 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2361
2362 #ifdef GOP_MIU_GROUP2
2363 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2364 #endif
2365 switch (gopnum)
2366 {
2367 case 0:
2368 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2369 #ifdef GOP_MIU_GROUP2
2370 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2371 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2372 #else
2373 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2374 #endif
2375 break;
2376 case 1:
2377 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2378 #ifdef GOP_MIU_GROUP2
2379 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2380 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2381 #else
2382 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2383 #endif
2384 break;
2385
2386 case 2:
2387 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2388 #ifdef GOP_MIU_GROUP2
2389 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2390 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2391 #else
2392 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2393 #endif
2394 break;
2395
2396 case 3:
2397 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2398 #ifdef GOP_MIU_GROUP2
2399 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2400 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2401 #else
2402 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2403 #endif
2404 break;
2405 case 4:
2406 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
2407 #ifdef GOP_MIU_GROUP2
2408 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
2409 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
2410 #else
2411 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
2412 #endif
2413 break;
2414 default:
2415 return 0xff;
2416 break;
2417 }
2418
2419 if(u8Miu > MAX_GOP_MIUSEL )
2420 {
2421 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2422 return 0xff;
2423 }
2424
2425 }
2426 return u8Miu;
2427 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2428 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2429 {
2430 MS_U16 u16Regval;
2431 MS_U32 u32pBankOffSet=0;
2432 GOP_Result ret;
2433
2434 if(u8gopNum >= MAX_GOP_SUPPORT)
2435 {
2436 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8gopNum);
2437 *pGopDst = E_DRV_GOP_DST_INVALID;
2438 return GOP_FAIL;
2439 }
2440
2441 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2442 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2443
2444 switch (u16Regval&GOP_DST_MASK)
2445 {
2446 case 0:
2447 *pGopDst = E_DRV_GOP_DST_IP0;
2448 ret = GOP_SUCCESS;
2449 break;
2450 case 1:
2451 HAL_GOP_GetMixerDst(pGOPHalLocal,pGopDst);
2452 ret = GOP_SUCCESS;
2453 break;
2454 case 2:
2455 *pGopDst = E_DRV_GOP_DST_OP0;
2456 ret = GOP_SUCCESS;
2457 break;
2458 case 3:
2459 *pGopDst = E_DRV_GOP_DST_VOP;
2460 ret = GOP_SUCCESS;
2461 break;
2462 case 4:
2463 *pGopDst = E_DRV_GOP_DST_VOP_SUB;
2464 ret = GOP_SUCCESS;
2465 break;
2466 case 6:
2467 *pGopDst = E_DRV_GOP_DST_OP1;
2468 ret = GOP_SUCCESS;
2469 break;
2470 case 11:
2471 *pGopDst = E_DRV_GOP_DST_BYPASS;
2472 ret = GOP_SUCCESS;
2473 break;
2474 case 8:
2475 *pGopDst = E_DRV_GOP_DST_DIP;
2476 ret = GOP_SUCCESS;
2477 break;
2478 default:
2479 *pGopDst = E_DRV_GOP_DST_INVALID;
2480 ret = GOP_FAIL;
2481 break;
2482 }
2483
2484 return ret;
2485
2486 }
2487
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2488 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2489 {
2490 MS_U16 muxValue=0;
2491 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2492 MS_BOOL bSC1_OP=0,bSC1_IP=0;
2493
2494 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2495
2496 switch(ipSelGop)
2497 {
2498 case MS_DRV_IP0_SEL_GOP0:
2499 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2500 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2501 u16RegVal |= GOP_BIT12;//mux0
2502 else
2503 u16RegVal |= GOP_BIT13;//mux1
2504 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2505 bSC1_OP =FALSE;
2506 bSC1_IP =FALSE;
2507 break;
2508
2509 case MS_DRV_IP0_SEL_GOP1:
2510 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2511 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2512 u16RegVal |= GOP_BIT12;//mux0
2513 else
2514 u16RegVal |= GOP_BIT13;//mux1
2515 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2516 bSC1_OP =FALSE;
2517 bSC1_IP =FALSE;
2518 break;
2519 case MS_DRV_IP0_SEL_GOP2:
2520 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2521 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2522 u16RegVal |= GOP_BIT12;//mux0
2523 else
2524 u16RegVal |= GOP_BIT13;//mux1
2525 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2526 bSC1_OP =FALSE;
2527 bSC1_IP =FALSE;
2528 break;
2529
2530 case MS_DRV_NIP_SEL_GOP0:
2531 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2532 {
2533 u16RegVal = ~GOP_BIT12;//mux0
2534 u16RegMsk = GOP_BIT12;
2535 }
2536 else
2537 {
2538 u16RegVal = ~GOP_BIT13;//mux1
2539 u16RegMsk = GOP_BIT13;
2540 }
2541 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2542 bSC1_OP =FALSE;
2543 bSC1_IP =FALSE;
2544 break;
2545
2546 case MS_DRV_NIP_SEL_GOP1:
2547 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2548 {
2549 u16RegVal = ~GOP_BIT12;//mux0
2550 u16RegMsk = GOP_BIT12;
2551 }
2552 else
2553 {
2554 u16RegVal = ~GOP_BIT13;//mux1
2555 u16RegMsk = GOP_BIT13;
2556 }
2557 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2558 bSC1_OP =FALSE;
2559 bSC1_IP =FALSE;
2560 break;
2561 case MS_DRV_NIP_SEL_GOP2:
2562 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2563 {
2564 u16RegVal = ~GOP_BIT12;//mux0
2565 u16RegMsk = GOP_BIT12;
2566 }
2567 else
2568 {
2569 u16RegVal = ~GOP_BIT13;//mux1
2570 u16RegMsk = GOP_BIT13;
2571 }
2572 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2573 bSC1_OP =FALSE;
2574 bSC1_IP =FALSE;
2575 break;
2576 case MS_DRV_MVOP_SEL:
2577 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2578 u16RegVal |= GOP_BIT12; //mux0
2579 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2580 bSC1_OP =FALSE;
2581 bSC1_IP =FALSE;
2582 break;
2583 case MS_DRV_SC1OP_SEL:
2584 bSC1_OP =TRUE;
2585 bSC1_IP =FALSE;
2586 break;
2587 case MS_DRV_IP1_SEL:
2588 bSC1_OP =FALSE;
2589 bSC1_IP =TRUE;
2590 break;
2591 default:
2592 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
2593 break;
2594 }
2595 if(0 != u16RegMsk)
2596 {
2597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2598 }
2599
2600 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bSC1_OP<<14, GOP_BIT14);
2601 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, !bSC1_IP<<11, GOP_BIT11);
2602 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, bSC1_IP<<12, GOP_BIT12);
2603
2604 }
2605
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2606 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2607 {
2608 return GOP_FUN_NOT_SUPPORTED;
2609 }
2610
2611
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2612 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2613 {
2614 return GOP_FUN_NOT_SUPPORTED;
2615 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2616 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2617 {
2618 return GOP_FUN_NOT_SUPPORTED;
2619 }
2620
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2621 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2622 {
2623 return GOP_FUN_NOT_SUPPORTED;
2624 }
2625
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2626 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2627 {
2628 if(u32mode == E_GOP_PAL)
2629 {
2630 /* PAL System*/
2631 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x73;
2632 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0x13;
2633 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, ~GOP_BIT2, GOP_BIT2);
2634 }
2635 else if(u32mode == E_GOP_NTSC)
2636 {
2637 /* NTSC System*/
2638 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x65;
2639 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0xF;
2640 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, GOP_BIT2, GOP_BIT2);
2641 }
2642 return GOP_SUCCESS;
2643 }
2644
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2645 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2646 {
2647
2648 if(u32mode == E_GOP_PAL)
2649 {
2650 /* PAL System*/
2651 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2652 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2653 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2654 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2655 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_PAL_WIDTH, GOP_REG_WORD_MASK);
2656 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_PAL_HEIGHT, GOP_REG_WORD_MASK);
2657 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2658 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_PAL_HS_DELAY, GOP_REG_WORD_MASK);
2659 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2660
2661 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2662 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2663 }
2664 else if(u32mode == E_GOP_NTSC)
2665 {
2666 /* NTSC System*/
2667 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2668 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2669 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_NTSC_HSTART_OFST, GOP_REG_WORD_MASK);
2670 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_NTSC_VSTART_OFST, GOP_REG_WORD_MASK);
2671 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_NTSC_WIDTH, GOP_REG_WORD_MASK);
2672 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_NTSC_HEIGHT, GOP_REG_WORD_MASK);
2673 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_NTSC_HTOTAL, GOP_REG_WORD_MASK);
2674 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_NTSC_HS_DELAY, GOP_REG_WORD_MASK);
2675
2676 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2677
2678 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2679 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2680 }
2681 else if(u32mode == E_GOP_CUSTOM)
2682 {
2683 return GOP_FUN_NOT_SUPPORTED;
2684 /*
2685 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2686 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2687 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, pTM->hstart, GOP_REG_WORD_MASK);
2688 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, pTM->vstart, GOP_REG_WORD_MASK);
2689 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, pTM->hend, GOP_REG_WORD_MASK);
2690 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, pTM->vend, GOP_REG_WORD_MASK);
2691 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, pTM->htotal, GOP_REG_WORD_MASK);
2692 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, pTM->hsyncdelay, GOP_REG_WORD_MASK);
2693
2694 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2695
2696 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //enable pseudo hsync
2697 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2698 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2699 */
2700 }
2701 else if(u32mode == E_GOP_CUSTOM_OP)
2702 {
2703 return GOP_FUN_NOT_SUPPORTED;
2704 }
2705 return GOP_SUCCESS;
2706 }
2707
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2708 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2709 {
2710 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, bEn, GOP_MIXER_EN_VFIL_MASK);
2711 return GOP_SUCCESS;
2712 }
2713
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2714 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2715 {
2716 //fix me need to modify tile_32bpp mode in 64b_bus
2717 if(E_DRV_GOP_TILE_DATA_16BPP == tilemode)
2718 {
2719 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2720 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2721 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2722 ~GOP_BIT7, GOP_BIT7);
2723
2724 }
2725 else if(E_DRV_GOP_TILE_DATA_32BPP == tilemode)
2726 {
2727 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2728 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2729 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2730 ~GOP_BIT7, GOP_BIT7);
2731 }
2732 else
2733 {
2734 return GOP_FUN_NOT_SUPPORTED;
2735 }
2736
2737 return GOP_SUCCESS;
2738
2739 }
2740
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2741 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2742 {
2743 MS_U32 u32BankOffSet =0;
2744
2745 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2746
2747 if (bEn)
2748 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2749 else
2750 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2751
2752 return GOP_SUCCESS;
2753 }
2754
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2755 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2756 {
2757 MS_U32 u32BankOffSet =0;
2758
2759 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2760
2761 if (bEn)
2762 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2763 else
2764 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2765
2766 return GOP_SUCCESS;
2767 }
2768
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2769 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2770 {
2771 MS_U16 u16Val =0x0;
2772 if (u8win < GOP1_GwinIdBase)
2773 {
2774 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2775 *pEnable = (MS_BOOL)(u16Val>>15);
2776 }
2777 else if (u8win < GOP2_GwinIdBase)
2778 {
2779 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2780 *pEnable = (MS_BOOL)(u16Val>>15);
2781 }
2782 else if (u8win < GOP3_GwinIdBase)
2783 {
2784 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2785 *pEnable = (MS_BOOL)(u16Val>>15);
2786 }
2787 else if (u8win < GOP4_GwinIdBase)
2788 {
2789 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2790 *pEnable = (MS_BOOL)(u16Val>>15);
2791 }
2792 else if (u8win < GOP5_GwinIdBase)
2793 {
2794 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2795 *pEnable = (MS_BOOL)(u16Val>>15);
2796 }
2797 else
2798 {
2799 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2800 return GOP_INVALID_PARAMETERS;
2801 }
2802
2803 return GOP_SUCCESS;
2804 }
2805
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2806 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2807 {
2808 MS_U16 u16Val = bEnable << 15;
2809 if (u8win < GOP1_GwinIdBase)
2810 {
2811 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2812 }
2813 else if (u8win < GOP2_GwinIdBase)
2814 {
2815 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2816 }
2817 else if (u8win < GOP3_GwinIdBase)
2818 {
2819 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2820 }
2821 else if (u8win < GOP4_GwinIdBase)
2822 {
2823 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2824 }
2825 else if (u8win < GOP5_GwinIdBase)
2826 {
2827 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2828 }
2829 else
2830 {
2831 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2832 return GOP_INVALID_PARAMETERS;
2833 }
2834 return GOP_SUCCESS;
2835 }
2836
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2837 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2838 {
2839 MS_U16 u16Reg = 0;
2840 MS_U32 u32WordBase = 0;
2841 MS_U32 u32BankOffSet=0;
2842
2843 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2844
2845 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2846
2847 if(u16Reg & GOP_BIT7)
2848 {
2849 u32WordBase = 1;
2850 }
2851 else
2852 {
2853 u32WordBase = GOP_WordUnit;
2854 }
2855
2856 u32SubAddr /= u32WordBase;
2857
2858 if(u8GOP == E_GOP2)
2859 {
2860 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2861 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2862 }
2863 else if(u8GOP == E_GOP3)
2864 {
2865 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2866 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2867
2868 }
2869 else if(u8GOP == E_GOP4)
2870 {
2871 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2872 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2873 }
2874 else if(u8GOP == E_GOP1)
2875 {
2876 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2877 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2878 }
2879 else //gop0
2880 {
2881 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2882 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2883 }
2884
2885 return GOP_SUCCESS;
2886
2887 }
2888
2889 //------------------------------------------------------------------------------
2890 /// Set VE output with OSD
2891 /// @return none
2892 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2893 GOP_Result HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2894 {
2895 if(eOSD == EN_OSD_0)
2896 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bEnable<<14, GOP_BIT14);
2897
2898 if(eOSD == EN_OSD_1)
2899 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bEnable<<15, GOP_BIT15);
2900 return GOP_SUCCESS;
2901 }
2902
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2903 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2904 {
2905 /*
2906 MS_U32 u32BankOffSet=0;
2907 _GetBnkOfstByGop(gopNum, &u32BankOffSet);
2908
2909 //Direct to SC1 OP
2910 HAL_GOP_SetIPSel2SC(pGOPHalLocal, MS_DRV_SC1OP_SEL);
2911 HAL_GOP_SetGOPClk(pGOPHalLocal, gopNum, E_DRV_GOP_DST_OP1);
2912 HAL_GOP_GWIN_SetMUX(pGOPHalLocal,gopNum,E_GOP_OP1_MUX);
2913 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
2914 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2915 */
2916 return GOP_SUCCESS;
2917 }
2918
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2919 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2920 {
2921 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2922 MS_U16 u16MVOPMirrorCfg = 0;
2923 MS_U16 u16ScalerMirrorCfg = 0;
2924
2925 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2926 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2927 if(bHorizontal) // Horizontal
2928 {
2929 if(u16MVOPMirrorCfg & GOP_BIT1)
2930 {
2931 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2932 }
2933 else if(u16ScalerMirrorCfg & GOP_BIT12)
2934 {
2935 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2936 }
2937 }
2938 else //vertical
2939 {
2940 if(u16MVOPMirrorCfg & GOP_BIT0)
2941 {
2942 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2943 }
2944 else if(u16ScalerMirrorCfg & GOP_BIT13)
2945 {
2946 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2947 }
2948 }
2949 return enMirrorType;
2950 }
2951
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2952 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2953 {
2954 MS_U32 u32BankOffSet =0;
2955
2956 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2957 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2958 return GOP_SUCCESS;
2959 }
2960
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2961 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2962 {
2963 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2964 MS_U16 u16Val=0;
2965 MS_U16 u16Mux[MAX_GOP_MUX];
2966
2967 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2968 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2969 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2970 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2971 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2972 #if (MAX_GOP_MUX>4)
2973 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2974 #endif
2975 switch(u8GOP)
2976 {
2977 case E_GOP0:
2978 case E_GOP1:
2979 case E_GOP2:
2980 case E_GOP3:
2981 #if (MAX_GOP_MUX>4)
2982 case E_GOP4:
2983 #endif
2984 for(i=0; i<MAX_GOP_MUX; i++)
2985 {
2986 if(u8GOP == u16Mux[i])
2987 {
2988 eGopMux = i;
2989 #if (MAX_GOP_MUX>4)
2990 if(eGopMux == 4)
2991 {
2992 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2993 }
2994 else
2995 #endif
2996 {
2997 FRCMuxOffset = 12 + eGopMux;
2998 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2999 }
3000 }
3001 }
3002 break;
3003 default:
3004 return GOP_FAIL;
3005 break;
3006 }
3007
3008 return GOP_SUCCESS;
3009 }
3010
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)3011 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
3012 {
3013 return GOP_FUN_NOT_SUPPORTED;
3014 }
3015
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)3016 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
3017 {
3018 return GOP_FUN_NOT_SUPPORTED;
3019 }
3020
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)3021 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
3022 {
3023 return GOP_FUN_NOT_SUPPORTED;
3024 }
3025
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)3026 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
3027 {
3028 MS_U32 u32BankOffSet = 0;
3029 MS_BOOL bInverse = 0xFF;
3030 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
3031
3032 switch (eDstType)
3033 {
3034 case E_DRV_GOP_DST_IP0:
3035 case E_DRV_GOP_DST_IP1:
3036 case E_DRV_GOP_DST_OP1:
3037 bInverse = TRUE;
3038 break;
3039 default:
3040 bInverse = FALSE;
3041 break;
3042 }
3043 if(bInverse == TRUE)
3044 {
3045 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 1<<4, 0x10);
3046 }
3047 else
3048 {
3049 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 0<<4, 0x10);
3050 }
3051 return GOP_SUCCESS;
3052 }
3053
3054 /********************************************************************************/
3055 ///Test Pattern
3056 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)3057 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
3058 {
3059 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
3060 {
3061 return GOP_SUCCESS;
3062 }
3063 else
3064 {
3065 return GOP_FAIL;
3066 }
3067
3068 }
3069
3070
3071 /********************************************************************************/
3072 ///GOP Scaling down (internal)
3073 /********************************************************************************/
3074
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)3075 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
3076 {
3077 MS_U16 u16MG_mask=0;
3078 MS_U16 u16Val=0;
3079 MS_U16 u16LB_mask=0;
3080 MS_U16 u16enable=0;
3081
3082 if(u8GOP==0)
3083 {
3084 u16MG_mask=CKG_GOPG0_MG_MASK;
3085 u16Val=GOP_BIT2;
3086 u16LB_mask=CKG_LB_SRAM1_MASK;
3087 u16enable=GOP_BIT2;
3088 }
3089 else if(u8GOP==2)
3090 {
3091 u16MG_mask=CKG_GOPG2_MG_MASK;
3092 u16Val=GOP_BIT6;
3093 u16LB_mask=CKG_LB_SRAM2_MASK;
3094 u16enable=GOP_BIT6;
3095 }
3096 else
3097 {
3098 printf("[%s] Error message GOP not support scaling down!!",__FUNCTION__);
3099 return GOP_FAIL;
3100 }
3101 if(bEn==TRUE)
3102 {
3103 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, u16Val, u16MG_mask);
3104 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, u16enable, u16LB_mask);
3105 }
3106 else
3107 {
3108 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, u16MG_mask);
3109 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, u16LB_mask);
3110 }
3111 return TRUE;
3112 }
3113
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3114 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3115 {
3116 MS_U32 ratio;
3117 MS_U32 u32BankOffSet=0xFFFF;
3118 MS_U16 u16VScalReg;
3119
3120 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3121 if(bEnable ==TRUE)
3122 {
3123 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, &u16VScalReg);
3124 if( u16VScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
3125 {
3126 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, 0x1000 , GOP_REG_WORD_MASK);
3127 printf("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
3128 }
3129 //Set scaling down ratio
3130 ratio = (dst * 0x100000) / src;
3131 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, ratio);
3132 }
3133 else
3134 {
3135 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, 0);
3136 }
3137
3138 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3139 {
3140 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3141 }
3142 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, bEnable , GOP_BIT0);
3143 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_H_OUTPUTSIZE, dst, GOP_REG_WORD_MASK);
3144
3145 return GOP_SUCCESS;
3146
3147 }
3148
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3149 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3150 {
3151 MS_U32 ratio =0;
3152 MS_U32 u32BankOffSet=0xFFFF;
3153 MS_U16 u16HScalReg;
3154
3155 if(pGOPHalLocal->pGopChipPro->bScalingDownSupport ==FALSE)
3156 {
3157 return GOP_FUN_NOT_SUPPORTED;
3158 }
3159
3160 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3161 if(bEnable ==TRUE)
3162 {
3163 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, &u16HScalReg);
3164 if( u16HScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
3165 {
3166 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, 0x1000 , GOP_REG_WORD_MASK);
3167 printf("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
3168 }
3169 ratio = (dst * 0x100000) / src;
3170 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, ratio);
3171 }
3172 else
3173 {
3174 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, 0);
3175 }
3176
3177 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3178 {
3179 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3180 }
3181 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, (bEnable<<4) , GOP_BIT4);
3182 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SVM_VEND, dst, GOP_REG_WORD_MASK);
3183
3184 return GOP_SUCCESS;
3185
3186 }
3187
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)3188 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
3189 {
3190 MS_U32 u32BankOffSet=0;
3191
3192 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3193 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
3194 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
3195 return GOP_SUCCESS;
3196 }
3197
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)3198 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
3199 {
3200 MS_U32 u32BankOffSet=0;
3201 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3202
3203 if (u32GopIdx < MAX_GOP_SUPPORT)
3204 {
3205 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
3206 }
3207 else
3208 {
3209 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3210 *u16Val = 0;
3211 }
3212 return GOP_SUCCESS;
3213 }
3214
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)3215 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
3216 {
3217 MS_U32 u32BankOffSet=0;
3218 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3219
3220 if (u32GopIdx < MAX_GOP_SUPPORT)
3221 {
3222 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
3223 }
3224 else
3225 {
3226 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3227 }
3228 return GOP_SUCCESS;
3229 }
3230
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)3231 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
3232 {
3233 switch(u32PowerState)
3234 {
3235 case E_POWER_SUSPEND:
3236 {
3237 //CLK
3238 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
3239 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
3240 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
3241 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
3242 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
3243 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
3244
3245 //SRAM
3246 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
3247 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
3248 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
3249
3250 //XC
3251 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
3252 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
3253 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
3254 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
3255 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
3256 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
3257 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
3258 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
3259 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
3260 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
3261 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
3262 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
3263 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
3264 }
3265 break;
3266 case E_POWER_RESUME:
3267 {
3268 //CLK
3269 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
3270 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
3271 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
3272 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
3273 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
3274 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
3275
3276 //SRAM
3277 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
3278 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
3279 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
3280
3281 //XC
3282 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3283 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3284 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3285 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3286 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3287 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3288 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3289 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3290 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3291 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3292 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3293 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3294 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3295 }
3296 break;
3297 default:
3298 break;
3299 }
3300 return GOP_SUCCESS;
3301 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3302 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3303 {
3304 return GOP_FUN_NOT_SUPPORTED;
3305 }
3306
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3307 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3308 {
3309 MS_U32 u32BankOffSet=0xFFFF;
3310
3311 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3312 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3313
3314 return GOP_SUCCESS;
3315 }
3316
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3317 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3318 {
3319 MS_U32 u32BankOffSet=0xFFFF;
3320 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3321
3322 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3323 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3324
3325 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3326 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3327
3328 return GOP_SUCCESS;
3329 }
3330
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3331 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3332 {
3333 MS_U32 u32BankOffSet=0xFFFF;
3334 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3335
3336 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3337 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3338
3339 return GOP_SUCCESS;
3340 }
3341
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3342 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3343 {
3344 MS_U32 u32BankOffSet=0xFFFF;
3345 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3346
3347 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3348 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3349
3350 return GOP_SUCCESS;
3351 }
3352
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3353 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3354 {
3355 GOP_Result ret = GOP_SUCCESS;
3356
3357 switch(u8GOP)
3358 {
3359 case E_GOP0:
3360 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3361 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3362 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VSTR(u8win), vstart, GOP_REG_WORD_MASK);
3363 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VEND(u8win), vend, GOP_REG_WORD_MASK);
3364 break;
3365
3366 case E_GOP1:
3367 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3368 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3369 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VSTR(u8win), vstart, GOP_REG_WORD_MASK); // 1 pixel
3370 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VEND(u8win), vend, GOP_REG_WORD_MASK); // 1 pixel
3371 break;
3372
3373 case E_GOP2:
3374 case E_GOP3:
3375 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HSTR:GOP_1GX_HSTR, hstart, GOP_REG_WORD_MASK); // word pixels
3376 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HEND:GOP_1GX_HEND, hend, GOP_REG_WORD_MASK); // word pixels
3377 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VSTR:GOP_1GX_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3378 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VEND:GOP_1GX_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3379 break;
3380
3381 default:
3382 printf("invalid Gwin number:%d\n",u8win);
3383 break;
3384 }
3385
3386 return ret;
3387 }
3388
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3389 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3390 {
3391 MS_U32 u32BankOffSet=0xFFFF;
3392 MS_U16 mask_shift=0xFF;
3393
3394 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3395
3396 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP] == TRUE)
3397 {
3398 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3399 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3400 }
3401 else
3402 {
3403 switch(u8GOP)
3404 {
3405 case E_GOP0:
3406 mask_shift = GOP_MIU_CLIENT_GOP0;
3407 break;
3408 case E_GOP1:
3409 mask_shift = GOP_MIU_CLIENT_GOP1;
3410 break;
3411 case E_GOP2:
3412 mask_shift = GOP_MIU_CLIENT_GOP2;
3413 break;
3414 case E_GOP3:
3415 mask_shift = GOP_MIU_CLIENT_GOP3;
3416 break;
3417 case E_GOP4:
3418 mask_shift = GOP_MIU_CLIENT_GOP4;
3419 break;
3420 case E_GOP5:
3421 mask_shift = GOP_MIU_CLIENT_GOP5;
3422 break;
3423 case E_GOP_Dwin:
3424 mask_shift = GOP_MIU_CLIENT_DWIN;
3425 break;
3426 default:
3427 mask_shift = 0xFF;
3428 MS_CRITICAL_MSG(printf("ERROR gop miu client\n"));
3429 break;
3430 }
3431
3432 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3433 #ifdef GOP_MIU_GROUP2
3434 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3435 #endif
3436 }
3437
3438 return GOP_SUCCESS;
3439 }
3440
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3441 GOP_Result Hal_SetCropWindow(
3442 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3443 MS_U8 u8GOP,
3444 EN_GOP_CROP_CTL crop_mode
3445 )
3446 {
3447 return GOP_SUCCESS;
3448 }
3449
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)3450 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
3451 {
3452 MS_U16 reg_val = 0;
3453
3454 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_USR_INTERLACE, ®_val);
3455 if(reg_val & BIT(1))
3456 *bInterlace = TRUE;
3457 else
3458 *bInterlace = FALSE;
3459 return GOP_SUCCESS;
3460 }
3461
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)3462 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
3463 {
3464 *pbHDREnable= FALSE;
3465 return GOP_FUN_NOT_SUPPORTED;
3466 }
3467
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3468 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3469 {
3470 if(u8GOP==0)
3471 {
3472 *u8Core=0;
3473 }
3474 else
3475 {
3476 *u8Core=1;
3477 }
3478 return GOP_SUCCESS;
3479 }
3480
3481 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3482 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3483 {
3484 MS_U16 u16xcSubbank=0;
3485 MS_U32 bank;
3486 MS_U32 direct_addr;
3487
3488 switch (u32addr & 0xFF00)
3489 {
3490 case GOP_REG_BASE:
3491 {
3492 bank = (u32addr & 0xFF0000) >> 8;
3493 #if 0 //for GOP4
3494 if(bank==0xE00)//GOP4: 0x121B00
3495 {
3496 bank=GOP_REG_GOP4_BK_OFFSET;
3497 }
3498 else if(bank==0xF00)//GWIN4: 0x121E00
3499 {
3500 bank=GOP_REG_GOP4_GW_OFFSET;
3501 }
3502 else if(bank==0x1000) //GOP4_ST
3503 {
3504 bank=GOP_REG_GOP4_ST_OFFSET;
3505 }
3506 #endif
3507 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3508
3509 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3510 cmdq_struct[(*number)].destionation_value = u16val;
3511 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3512 cmdq_struct[(*number)].operation = 0x57;
3513 (*number)++;
3514 break;
3515 }
3516 case SC1_REG_BASE:
3517 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3518 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3519
3520 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3521 cmdq_struct[(*number)].destionation_value = u16val;
3522 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3523 cmdq_struct[(*number)].operation = 0x57;
3524 (*number)++;
3525 break;
3526 case GE_REG_BASE:
3527 case CKG_REG_BASE:
3528 case MIU_REG_BASE:
3529 {
3530 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3531 cmdq_struct[(*number)].destionation_value = u16val;
3532 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3533 cmdq_struct[(*number)].operation = 0x57;
3534 (*number)++;
3535 break;
3536 }
3537 #ifdef GOP_MIU_GROUP2
3538 case (MIU2_REG_BASE & 0xFF00):
3539 {
3540 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3541
3542 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3543 cmdq_struct[(*number)].destionation_value = u16val;
3544 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3545 cmdq_struct[(*number)].operation = 0x57;
3546 (*number)++;
3547 break;
3548 }
3549 #endif
3550 default:
3551 {
3552 //Gop lib current do not support this HW ip base
3553 MS_ASSERT(0);
3554 break;
3555 }
3556
3557 }
3558 return GOP_SUCCESS;
3559 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3560 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3561 {
3562 MS_U32 u32BankOffSet=0xFFFF;
3563 MS_U16 u16RegVal1 = 0;
3564 MS_BOOL bCheckValidGop = FALSE;
3565 MS_U8 u8CheckTimeCnt = 0;
3566 MS_U8 u8CurrentCmdGop = 0;
3567
3568 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3569 {
3570 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3571 {
3572 u8CurrentCmdGop = 0;
3573 }
3574 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3575 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3576 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3577 {
3578 bCheckValidGop = FALSE;
3579 }
3580 else
3581 {
3582 bCheckValidGop = TRUE;
3583 break;
3584 }
3585
3586 // if current gop not init, use next gop instead, check order 0->2->1->3
3587 switch (u8CurrentCmdGop)
3588 {
3589 case 0:
3590 u8CurrentCmdGop = 2;
3591 break;
3592 case 1:
3593 u8CurrentCmdGop = 0;
3594 break;
3595 case 2:
3596 u8CurrentCmdGop = 3;
3597 break;
3598 case 3:
3599 u8CurrentCmdGop = 1;
3600 break;
3601 default:
3602 u8CurrentCmdGop = 0;
3603 break;
3604 }
3605 u8CheckTimeCnt++;
3606 }
3607 if (!bCheckValidGop)
3608 {
3609 printf("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3610 }
3611
3612 *u32GopIdx = u8CurrentCmdGop;
3613 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3614 (*number)++;
3615 return GOP_SUCCESS;
3616 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3617 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3618 {
3619 CH_Struct ch_fire;
3620 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3621 MS_U16 u16ret = 0,u16ret1 = 0;
3622 int i = 0;
3623
3624
3625 _GetBnkOfstByGop(0, &u32BankOffSet);
3626 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3627 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3628 #if 0 //for Debug
3629 for(i=0;i<(*number);i++)
3630 {
3631 printf("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3632 }
3633 #endif
3634 ch_fire.Command_Number = *number;
3635 ch_fire.Pointer_To_CAFArray = target;
3636 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3637 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3638 {
3639 Receive_Return_Value = 0;
3640 MDrv_CMDQ_Printf_Crash_Command();
3641 }
3642
3643 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3644 MsOS_DelayTask(1);
3645 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3646 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3647
3648 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3649 timer1 = MsOS_GetSystemTime();
3650 timer2 = MsOS_GetSystemTime();
3651 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3652 {
3653 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3654 MsOS_DelayTask(1);
3655 timer2 = MsOS_GetSystemTime();
3656 }
3657 if(u16ret1 != (u16ret+1))
3658 {
3659 printf("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3660 MDrv_CMDQ_Printf_Crash_Command();
3661 }
3662 return GOP_SUCCESS;
3663 }
3664
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3665 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3666 {
3667 CAF_Struct fire_struct[24];
3668 MS_U32 u32BankOffSet;
3669 MS_U32 number = 0;
3670 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3671 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3672 MS_U32 fireGOP=0;
3673
3674 _GetBnkOfstByGop(gop, &u32BankOffSet);
3675
3676 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3677 #ifdef GOP_MIU_GROUP2
3678 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3679 #endif
3680 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3681 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3682
3683 switch(gop)
3684 {
3685 case E_GOP0:
3686 {
3687 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3688 break;
3689 }
3690 case E_GOP1:
3691 {
3692 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3693 break;
3694 }
3695 case E_GOP2:
3696 {
3697 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3698 break;
3699 }
3700 case E_GOP3:
3701 {
3702 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3703 break;
3704 }
3705 case E_GOP4:
3706 {
3707 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3708 break;
3709 }
3710 default:
3711 {
3712 MS_ASSERT(0);
3713 break;
3714 }
3715 }
3716 if(bMIUSelect[gop] == TRUE)
3717 {
3718 if(u16MIUSelect[gop] == 0)
3719 {
3720 u16RegVal1 &= ~(1<<u16MiuClient);
3721 u16RegVal3 &= ~(1<<u16MiuClient);
3722 }
3723 else if(u16MIUSelect[gop] == 1)
3724 {
3725 u16RegVal1 |= (1<<u16MiuClient);
3726 u16RegVal3 &= ~(1<<u16MiuClient);
3727 }
3728 else if(u16MIUSelect[gop] == 2)
3729 {
3730 u16RegVal1 &= ~(1<<u16MiuClient);
3731 u16RegVal3 |= (1<<u16MiuClient);
3732 }
3733 else if(u16MIUSelect[gop] == 3)
3734 {
3735 u16RegVal1 |= (1<<u16MiuClient);
3736 u16RegVal3 |= (1<<u16MiuClient);
3737 }
3738 bMIUSelect[gop] = FALSE;
3739 }
3740
3741 if(bAFBCMIUSelect[gop] == TRUE)
3742 {
3743 bAFBCMIUSelect[gop] = FALSE;
3744 }
3745 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3746 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3747 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3748
3749 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
3750 {
3751 if(bAFBCMIUSelect[gop] == TRUE)
3752 {
3753 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3754 bAFBCMIUSelect[gop] = FALSE;
3755 }
3756 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3757 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
3758 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
3759 }
3760 #ifdef GOP_MIU_GROUP2
3761 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3762 #endif
3763
3764 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3765 return GOP_SUCCESS;
3766 }
3767
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)3768 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3769 {
3770 CAF_Struct fire_struct[24];
3771 MS_U32 u32BankOffSet=0;
3772 MS_U32 number = 0;
3773 MS_U8 gop=0;
3774 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3775 MS_U16 u16RegMiu=0,u16RegCoreEna=0;
3776 MS_U8 u8Core=0;
3777 MS_U32 fireGOP=0;
3778 MS_BOOL bCoreTrig[AFBC_CORE_COUNT];
3779 MS_BOOL bCoreMiu[AFBC_CORE_COUNT];
3780 MS_U8 i=0;
3781
3782 for(i=0;i<AFBC_CORE_COUNT;i++)
3783 {
3784 bCoreTrig[i]=FALSE;
3785 }
3786
3787
3788 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3789 #ifdef GOP_MIU_GROUP2
3790 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3791 #endif
3792 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3793
3794 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3795 {
3796 switch(gop)
3797 {
3798 case E_GOP0:
3799 {
3800 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3801 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP0, &u8Core);
3802 bCoreTrig[u8Core]=TRUE;
3803 break;
3804 }
3805 case E_GOP1:
3806 {
3807 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3808 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP1, &u8Core);
3809 bCoreTrig[u8Core]=TRUE;
3810 break;
3811 }
3812 case E_GOP2:
3813 {
3814 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3815 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP2, &u8Core);
3816 bCoreTrig[u8Core]=TRUE;
3817 break;
3818 }
3819 case E_GOP3:
3820 {
3821 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3822 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP3, &u8Core);
3823 bCoreTrig[u8Core]=TRUE;
3824 break;
3825 }
3826 case E_GOP4:
3827 {
3828 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3829 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP4, &u8Core);
3830 bCoreTrig[u8Core]=TRUE;
3831 break;
3832 }
3833 default:
3834 {
3835 continue;
3836 }
3837 }
3838 if( ( u16GopMask & (1<<gop) ) )
3839 {
3840 _GetBnkOfstByGop(gop, &u32BankOffSet);
3841 if(bMIUSelect[gop] == TRUE)
3842 {
3843 if(u16MIUSelect[gop] == 0)
3844 {
3845 u16RegVal1 &= ~(1<<u16MiuClient);
3846 u16RegVal3 &= ~(1<<u16MiuClient);
3847 }
3848 else if(u16MIUSelect[gop] == 1)
3849 {
3850 u16RegVal1 |= (1<<u16MiuClient);
3851 u16RegVal3 &= ~(1<<u16MiuClient);
3852 }
3853 else if(u16MIUSelect[gop] == 2)
3854 {
3855 u16RegVal1 &= ~(1<<u16MiuClient);
3856 u16RegVal3 |= (1<<u16MiuClient);
3857 }
3858 else if(u16MIUSelect[gop] == 3)
3859 {
3860 u16RegVal1 |= (1<<u16MiuClient);
3861 u16RegVal3 |= (1<<u16MiuClient);
3862 }
3863 bMIUSelect[gop] = FALSE;
3864 }
3865 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3866 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3867 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3868 }
3869
3870 if(bAFBCMIUSelect[gop] == TRUE)
3871 {
3872 HAL_GOP_AFBC_GetCore(pGOPHalLocal, gop, &u8Core);
3873 bCoreMiu[gop]=TRUE;
3874 bAFBCMIUSelect[gop] = FALSE;
3875 }
3876 }
3877
3878 for(i=0;i<AFBC_CORE_COUNT;i++)
3879 {
3880 if(g_GopChipPro.bAFBC_Merge_GOP_Trig == FALSE)
3881 {
3882 if(bCoreTrig[i]==TRUE)
3883 {
3884 if((g_GopChipPro.bAFBCMIUSelDoubleBuffer == FALSE)&&(bCoreMiu[i]==TRUE))
3885 {
3886 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3887 }
3888 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
3889 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
3890 }
3891 }
3892 }
3893
3894 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3895 #ifdef GOP_MIU_GROUP2
3896 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3897 #endif
3898 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3899 return GOP_SUCCESS;
3900 }
3901 #endif
3902