1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108 #define HAL_GOP_DEBUGINFO(x) //x
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 //Kastor have 5 GOP(s):GOP0 GOP1 GOP2 GOP3 GOP5
120 //The last gop num is 4 for API,but 5 needs to be set for register
121 //So we need to do a conversion.
122 #define GOPNUM_SW_MAX_ID (4UL)
123 #define GOPNUM_HW_MAX_ID (5UL)
124 #define GOPNUM_TRANSFORM(num) (((num) == GOPNUM_SW_MAX_ID) ? GOPNUM_HW_MAX_ID : (num))
125 #define GOPNUM_TRANSFORM_INVERSE(num) (((num) == GOPNUM_HW_MAX_ID) ? GOPNUM_SW_MAX_ID : (num))
126
127
128 //------------------------------------------------------------------------------
129 // Local Var
130 //------------------------------------------------------------------------------
131 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
132 {
133 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
134 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
135 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
136 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
137 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
138 };
139 #ifdef GOP_CMDQ_ENABLE
140 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
141 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
142
143 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
144 extern MS_BOOL bAFBCMIUSelect[MAX_GOP_SUPPORT];
145 #endif
146 GOP_CHIP_PROPERTY g_GopChipPro =
147 {
148 .bSetHSyncInverse = FALSE,
149 .bGop1GPalette = TRUE,
150 .bSetHPipeOfst = FALSE,
151 .bNeedCheckMVOP = FALSE,
152 .bNeedSetMUX1ToIP0 = FALSE,
153 .bNeedSetMUX3ToIP0 = FALSE,
154 .bNewMux = TRUE,
155 .bNewPalette = TRUE,
156 .bNewBwReg = TRUE,
157 .bGop2VStretch = TRUE,
158 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
159 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
160 .bhastilemode = TRUE,
161 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
162 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
163 .bGOPWithVscale = {TRUE, TRUE, TRUE, FALSE, FALSE}, //setting GOP with/without Vscale
164
165 .bDWINSupport = FALSE,
166 .DwinVer = 0x1,
167 .bTstPatternAlpha = TRUE,
168 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
169 .bFRCSupport = FALSE, /*OC path*/
170 .bGOPMixerToVE= TRUE, /*Mixer to VE path*/
171 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
172 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
173 .bScalingDownSupport= FALSE,
174 .b2Pto1PSupport= TRUE,
175 .bTLBSupport= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE},
176 .GOP_TestPattern_Vaild= E_GOP0,
177 .bInternalMIUSelect= {TRUE, TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
178 .bAFBC_Support= {FALSE, FALSE, FALSE, FALSE, FALSE},
179
180 #ifdef ENABLE_GOP_T3DPATCH
181 .GOP_PD = -0x42,
182 #else
183 .GOP_PD = 0xDB,
184 #endif
185 .GOP_HDR_OP_PD = -0x8A,
186 .GOP_IP_PD = 0x00,
187 .GOP_MVOP_PD = 0x69,
188 .GOP_VE_PD = 0xB9,
189 .GOP_MIXER_PD = 0x0,
190 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
191 .GOP_VE_V_Offset = 0x0,
192 .GOP_OP1_PD = 0xA2,
193
194 .GOP_MUX_Delta = 0x4,
195 .GOP_Mux_Offset = {0x0, 0x1, 0x2, 0x3, 0x4},
196 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX4},
197 .GOP_Mux_FRC_offset= 0x13,
198
199 .WordUnit = GOP_WordUnit,
200 .TotalGwinNum = GOP_TotalGwinNum,
201 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
202 .enGOP3DType = E_DRV_3D_DUP_FULL,
203 .bOpInterlace = FALSE,
204 .bAFBC_Merge_GOP_Trig = FALSE,
205 .bAFBCMIUSelDoubleBuffer = FALSE,
206 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, TRUE, FALSE, FALSE},
207 .bOPHandShakeModeSupport = FALSE,
208 .bIgnoreIP1HPD = TRUE,
209 .bOPMuxDoubleBuffer = FALSE,
210 .bGOPAutoClkGating = TRUE,
211 };
212
213
214 //------------------------------------------------------------------------------
215 // Global Functions
216 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)217 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
218 {
219 GOP_TYPE->GOP0 = E_GOP0;
220 GOP_TYPE->GOP1 = E_GOP1;
221 GOP_TYPE->GOP2 = E_GOP2;
222 GOP_TYPE->GOP3 = E_GOP3;
223 GOP_TYPE->GOP4 = E_GOP4;
224 GOP_TYPE->GOP5 = E_GOP5;
225 GOP_TYPE->DWIN = E_GOP_Dwin;
226 GOP_TYPE->MIXER = E_GOP_MIXER;
227 }
228
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)229 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
230 {
231 MS_U32 u32BankOffSet = 0;
232
233 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
234
235 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
236 {
237 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
238 }
239 else
240 {
241 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
242 }
243
244 return GOP_SUCCESS;
245 }
246
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)247 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
248 {
249 MS_U32 u32BankOffSet =0;
250 MS_U32 u32BitMask,Regval;
251
252 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
253
254 switch(pinpon_mode)
255 {
256 default:
257 case E_DRV_GOP_PINPON_G3D:
258 Regval = bEn << 5;
259 u32BitMask = GOP_BIT5;
260 break;
261 case E_DRV_GOP_PINPON_DWIN:
262 Regval = bEn << 6;
263 u32BitMask = GOP_BIT6;
264 break;
265 case E_DRV_GOP_PINPON_DIP:
266 Regval = bEn << 7;
267 u32BitMask = GOP_BIT7;
268 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
269 break;
270 case E_DRV_GOP_PINPON_DWIN0:
271 Regval = bEn << 7;
272 u32BitMask = GOP_BIT7;
273 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
274 break;
275 case E_DRV_GOP_PINPON_DWIN1:
276 Regval = bEn << 7;
277 u32BitMask = GOP_BIT7;
278 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
279 break;
280 break;
281 }
282
283 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
284 return GOP_SUCCESS;
285 }
286
287
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)288 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
289 {
290 if(gop >= MAX_GOP_SUPPORT)
291 {
292 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
293 return FALSE;
294 }
295
296 if (gop==E_GOP0)
297 *pBnkOfst = GOP_4G_OFST<<16;
298 else if (gop==E_GOP1)
299 *pBnkOfst = GOP_2G_OFST<<16;
300 else if (gop==E_GOP2)
301 *pBnkOfst = GOP_1G_OFST<<16;
302 else if (gop==E_GOP3)
303 *pBnkOfst = GOP_1GX_OFST<<16;
304 else if (gop==E_GOP4)
305 *pBnkOfst = GOP_1GS0_OFST<<16;
306 else
307 return FALSE;
308
309 return TRUE;
310 }
311
_GetGwinOffsetInGOP(MS_U8 u8GwinId)312 MS_U8 _GetGwinOffsetInGOP(MS_U8 u8GwinId)
313 {
314 if(u8GwinId >= GOP4_GwinIdBase)
315 return (u8GwinId - GOP4_GwinIdBase);
316 else if(u8GwinId >= GOP3_GwinIdBase)
317 return (u8GwinId - GOP3_GwinIdBase);
318 else if( u8GwinId >= GOP2_GwinIdBase)
319 return (u8GwinId - GOP2_GwinIdBase);
320 else if (u8GwinId >= GOP1_GwinIdBase)
321 return (u8GwinId - GOP1_GwinIdBase);
322 else
323 return u8GwinId;
324 }
325
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)326 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
327 {
328 MS_U16 u16Mask0 = 0;
329 MS_U16 u16Mask1 = 0;
330 if (u16GopMask&GOP_BIT0)
331 {
332 u16Mask0 |= GOP_BIT12;
333 }
334 if (u16GopMask&GOP_BIT1)
335 {
336 u16Mask0 |= GOP_BIT13;
337 }
338 if (u16GopMask&GOP_BIT2)
339 {
340 u16Mask0 |= GOP_BIT14;
341 }
342 if (u16GopMask&GOP_BIT3)
343 {
344 u16Mask0 |= GOP_BIT15;
345 }
346 if (u16GopMask&GOP_BIT4)
347 {
348 u16Mask1 |= GOP_BIT2;
349 }
350 if (u16Mask0 != 0)
351 {
352 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
353 }
354 if (u16Mask1 != 0)
355 {
356 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
357 }
358
359 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
360 {
361 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
362 }
363 return GOP_SUCCESS;
364 }
365
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)366 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
367 {
368 if(gop >= MAX_GOP_SUPPORT)
369 {
370 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
371 return GOP_FAIL;
372 }
373
374 switch(gop)
375 {
376 case E_GOP0:
377 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
378 break;
379 case E_GOP1:
380 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
381 break;
382 case E_GOP2:
383 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
384 break;
385 case E_GOP3:
386 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
387 break;
388 case E_GOP4:
389 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT2 , GOP_BIT2);
390 break;
391 default:
392 printf("[%s][%d] Unsurrport GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
393 break;
394 }
395 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
396 {
397 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
398 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
399 }
400 return GOP_SUCCESS;
401 }
402
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)403 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
404 {
405 MS_U16 u16GopAck = 0,reg_val =0;
406
407 if(gop >= MAX_GOP_SUPPORT)
408 {
409 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
410 return FALSE;
411 }
412
413 switch(gop)
414 {
415 case E_GOP0:
416 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
417 if(reg_val&GOP_BIT12)
418 u16GopAck = FALSE;
419 else
420 u16GopAck = TRUE;
421 break;
422 case E_GOP1:
423 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
424 if(reg_val&GOP_BIT13)
425 u16GopAck = FALSE;
426 else
427 u16GopAck = TRUE;
428 break;
429 case E_GOP2:
430 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
431 if(reg_val&GOP_BIT14)
432 u16GopAck = FALSE;
433 else
434 u16GopAck = TRUE;
435 break;
436 case E_GOP3:
437 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
438 if(reg_val&GOP_BIT15)
439 u16GopAck = FALSE;
440 else
441 u16GopAck = TRUE;
442 break;
443 case E_GOP4:
444 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
445 if(reg_val&GOP_BIT2)
446 u16GopAck = FALSE;
447 else
448 u16GopAck = TRUE;
449 break;
450 default:
451 printf("[%s][%d] Unsurrport GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
452 break;
453 }
454 return u16GopAck;
455 }
456
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)457 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
458 {
459 return GOP_FUN_NOT_SUPPORTED;
460 }
461
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)462 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
463 {
464 MS_U32 u32bankoff = 0;
465 MS_U16 mask_shift=0xFF;
466 MS_U16 u16RegVal=0xFF;
467 MS_U8 u8MIUSel=0xF;
468 MS_U8 u8Core=0;
469
470 if(u8GOPNum >= MAX_GOP_SUPPORT)
471 {
472 return;
473 }
474
475 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
476 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
477
478 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, GOP_BIT15|GOP_BIT14, GOP_BIT15|GOP_BIT14);
479 if(u8GOPNum==E_GOP3)
480 {
481 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, GOP3_FIFO_THRESHOLD, GOP_REG_LW_MASK ); //set DMA FIFO threshold to 3/4 FIFO length
482 }
483 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
484 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
485 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT8|GOP_BIT9, GOP_BIT8|GOP_BIT9);
486
487 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
488
489 // H121 filter
490 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT0); // HD alpha Enable
491 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT1); // HD data Enable
492 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT2, GOP_BIT2); // SD data Enable
493 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable
494 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0x2000, 0x3F00); // Ratio between [H121] and [Bypass mode]
495
496 //Set handshake mode
497 if(g_GopChipPro.bOPHandShakeModeSupport)
498 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BANK_FWR, GOP_BIT10, GOP_BIT10);
499 else
500 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BANK_FWR, 0, GOP_BIT10);
501
502 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
503 {
504 if(u8GOPNum == 0)
505 {
506 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT13|GOP_BIT14);
507 }
508 else
509 {
510 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT14);
511 }
512 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
513 }
514
515 /* enable GOP clock */
516 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
517 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
518
519 switch(u8GOPNum)
520 {
521 case E_GOP0:
522 mask_shift = GOP_MIU_CLIENT_GOP0;
523 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
524 break;
525 case E_GOP1:
526 mask_shift = GOP_MIU_CLIENT_GOP1;
527 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
528 break;
529 case E_GOP2:
530 mask_shift = GOP_MIU_CLIENT_GOP2;
531 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
532 break;
533 case E_GOP3:
534 mask_shift = GOP_MIU_CLIENT_GOP3;
535 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
536 break;
537 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
538 mask_shift = GOP_MIU_CLIENT_GOP5;
539 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, 0, CKG_GOPG5_DISABLE_CLK_MASK); /* GOP 5 */
540 break;
541 default:
542 mask_shift = 0xFF;
543 break;
544 }
545 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
546 {
547 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
548 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
549 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
550 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
551 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
552 }
553
554
555 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
556 {
557 if(u8GOPNum ==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
558 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal);
559 else
560 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
561 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
562 #ifdef GOP_MIU_GROUP2
563 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
564 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
565 #endif
566 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
567 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
568 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
569 {
570 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
571 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
572 }
573
574 if(u8GOPNum ==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
575 HAL_GOP_Write16Reg(pGOPHalLocal, GOP5_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
576 else
577 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
578 }
579
580 //OC_RM_alpha
581 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
582 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
583 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
584
585 // set VIP/VOP timing select, always select VOP should be OK.
586 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_VIP_VOP_TIMING_SEL, GOP_BIT10, GOP_BIT10);
587
588 // Enable OP Mux double buff
589 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
590 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_OP_MUX_DBF, GOP_BIT15 , GOP_BIT15);
591 else
592 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_OP_MUX_DBF, 0 , GOP_BIT15);
593
594 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
595 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
596 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP,GOP_IP_SUB_MUX_MASK, GOP_IP_SUB_MUX_MASK); //default mask sub IP
597 }
598
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)599 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
600 {
601 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
602 }
603
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)604 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
605 {
606 switch(u8GopNum)
607 {
608 case E_GOP0:
609 return (MS_U8)MAX_GOP0_GWIN;
610 break;
611 case E_GOP1:
612 return (MS_U8)MAX_GOP1_GWIN;
613 break;
614 case E_GOP2:
615 return (MS_U8)MAX_GOP2_GWIN;
616 break;
617 case E_GOP3:
618 return (MS_U8)MAX_GOP3_GWIN;
619 break;
620 case E_GOP4:
621 return (MS_U8)MAX_GOP4_GWIN;
622 break;
623 default:
624 MS_ASSERT(0);
625 return 0xFF;
626 break;
627 }
628 }
629
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)630 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
631 {
632 MS_U8 u8GWinId = 0;
633
634 //Adjust GWIN ID by different Chip
635 if(u8Gop >= MAX_GOP_SUPPORT)
636 {
637 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8Gop);
638 MS_ASSERT(0);
639 return 0xFF;
640 }
641
642 switch(u8Gop)
643 {
644 case E_GOP0:
645 u8GWinId = GOP0_GwinIdBase + u8Idx;
646 break;
647 case E_GOP1:
648 u8GWinId = GOP1_GwinIdBase + u8Idx;
649 break;
650 case E_GOP2:
651 u8GWinId = GOP2_GwinIdBase + u8Idx;
652 break;
653 case E_GOP3:
654 u8GWinId = GOP3_GwinIdBase + u8Idx;
655 break;
656 #if (MAX_GOP_SUPPORT>4)
657 case E_GOP4:
658 u8GWinId = GOP4_GwinIdBase + u8Idx;
659 break;
660 #endif
661 default:
662 break;
663 }
664 return u8GWinId;
665
666 }
667
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)668 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
669 {
670 if(u8GOPNum >= MAX_GOP_SUPPORT)
671 {
672 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
673 MS_ASSERT(0);
674 return 0xFF;
675 }
676
677 switch(u8GOPNum)
678 {
679 case E_GOP0: // GOP4G
680 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
681 return GOP_SUCCESS;
682 case E_GOP1: // GOP2G
683 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
684 return GOP_SUCCESS;
685 case E_GOP2: // GOP1G
686 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
687 return GOP_SUCCESS;
688 case E_GOP3: // GOP1GX
689 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
690 return GOP_SUCCESS;
691 #if (MAX_GOP_SUPPORT>4)
692 case E_GOP4: // GOP1GS
693 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
694 return GOP_SUCCESS;
695 #endif
696 default:
697 MS_ASSERT(0);
698 return GOP_FAIL;
699 }
700 }
701
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)702 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
703 {
704 MS_U16 u16Bank;
705 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
706 u16Bank &= ~BMASK(3:0);
707 u16Bank |= (u8bank&BMASK(3:0));
708 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
709
710 #if(MAX_GOP_SUPPORT>4)
711 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
712 u16Bank &= ~GOP_BIT8;
713 if(u8bank&GOP_BIT4); // reg_gop_bnk_4
714 u16Bank |= GOP_BIT8;
715 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
716 #endif
717 }
718
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)719 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
720 {
721 MS_U16 u16GetBank=0;
722 u16GetBank = (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
723
724 #if (MAX_GOP_SUPPORT>4)
725 if(GOP_READ2BYTE(GOP_BAK_SEL_EX)&GOP_BIT8) //reg_gop_bnk_4
726 return GOP_BIT4|(u16GetBank&GOP_BANK_MASK);
727 #endif
728 return (u16GetBank&GOP_BANK_MASK);
729
730 }
731
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)732 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
733 {
734 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
735 MS_U32 bank;
736 MS_U32 direct_addr;
737
738 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
739
740 //* Gop driver should access another HW IP register
741 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
742 switch (u32addr & 0xFF00)
743 {
744 case GOP_REG_BASE:
745 {
746 bank = (u32addr & 0xFF0000) >> 8;
747 #if 0 //for GOP4
748 if(bank==0xE00)//GOP4: 0x121B00
749 {
750 bank=GOP_REG_GOP4_BK_OFFSET;
751 }
752 else if(bank==0xF00)//GWIN4: 0x121E00
753 {
754 bank=GOP_REG_GOP4_GW_OFFSET;
755 }
756 else if(bank==0x1000)//GOP4_ST
757 {
758 bank=GOP_REG_GOP4_ST_OFFSET;
759 }
760 #endif
761 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
762 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
763 break;
764 }
765 case SC1_REG_BASE:
766 {
767 if(g_GopChipPro.bXCDirrectBankSupport)
768 {
769 u16xcSubbank = (u32addr & 0xFF0000)>>8;
770 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
771 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
772 }
773 else
774 {
775 u16xcSubbank = (u32addr & 0xFF0000)>>16;
776 u16BankAddr = GOP_SC_BANKSEL+0;
777 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
778
779 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
780 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
781 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
782 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
783 }
784 break;
785 }
786 case GE_REG_BASE:
787 case CKG_REG_BASE:
788 case MIU0_REG_BASE:
789 case MIU_REG_BASE:
790 case MVOP_REG_BASE:
791 case VE_REG_BASE:
792 {
793 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
794 break;
795 }
796 #ifdef GOP_MIU_GROUP2
797 case (MIU2_REG_BASE & 0xFF00):
798 {
799 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
800 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
801
802 break;
803 }
804 #endif
805 default:
806 {
807 //Gop lib current do not support this HW ip base
808 MS_ASSERT(0);
809 *pu16ret =0;
810 break;
811 }
812 }
813 }
814
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)815 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
816 {
817 MS_U16 u16tmp=0;
818 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
819 MS_U32 bank;
820 MS_U32 direct_addr;
821
822 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u32addr, u16val));
823
824 if(mask!=0xffff)
825 {
826 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
827 u16tmp &= ~mask;
828 u16val &= mask;
829 u16val |= u16tmp;
830 }
831
832 //* Gop driver should access another HW IP register
833 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
834 switch (u32addr & 0xFF00)
835 {
836 case GOP_REG_BASE:
837 {
838 bank = (u32addr & 0xFF0000) >> 8;
839 #if 0 //for GOP4
840 if(bank==0xE00)//GOP4: 0x121B00
841 {
842 bank=GOP_REG_GOP4_BK_OFFSET;
843 }
844 else if(bank==0xF00)//GWIN4: 0x121E00
845 {
846 bank=GOP_REG_GOP4_GW_OFFSET;
847 }
848 else if(bank==0x1000) //GOP4_ST
849 {
850 bank=GOP_REG_GOP4_ST_OFFSET;
851 }
852 #endif
853 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
854 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
855 break;
856 }
857 case SC1_REG_BASE:
858 if(g_GopChipPro.bXCDirrectBankSupport)
859 { /*Derrick Bank*/
860 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
861 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
862 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
863 }
864 else
865 { /*Sub Bank*/
866 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
867 u16BankAddr = GOP_SC_BANKSEL+0;
868 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
869
870 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
871 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
872 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
873 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
874 }
875 break;
876 case GE_REG_BASE:
877 case CKG_REG_BASE:
878 case MIU0_REG_BASE:
879 case MIU_REG_BASE:
880 case VE_REG_BASE:
881 {
882 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
883 break;
884 }
885 #ifdef GOP_MIU_GROUP2
886 case (MIU2_REG_BASE & 0xFF00):
887 {
888 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
889 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
890 break;
891 }
892 #endif
893 default:
894 {
895 //Gop lib current do not support this HW ip base
896 MS_ASSERT(0);
897 break;
898 }
899
900 }
901 }
902
903
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)904 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
905 {
906 MS_U32 bank;
907 MS_U32 direct_addr;
908
909 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
910
911 //* Gop driver should access another HW IP register
912 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
913 switch (u32addr & 0xFF00)
914 {
915 case GOP_REG_BASE:
916 {
917 bank = (u32addr & 0xFF0000) >> 8;
918 #if 0 //for GOP4
919 if(bank==0xE00)//GOP4: 0x121B00
920 {
921 bank=GOP_REG_GOP4_BK_OFFSET;
922 }
923 else if(bank==0xF00)//GWIN4: 0x121E00
924 {
925 bank=GOP_REG_GOP4_GW_OFFSET;
926 }
927 else if(bank==0x1000) //GOP4_ST
928 {
929 bank=GOP_REG_GOP4_ST_OFFSET;
930 }
931 #endif
932 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
933 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
934 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
935 break;
936 }
937
938 case GE_REG_BASE:
939 case SC1_REG_BASE:
940 case CKG_REG_BASE:
941 {
942 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
943 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
944 break;
945 }
946
947 default:
948 {
949 //Gop lib current do not support this HW ip base
950 MS_ASSERT(0);
951 break;
952 }
953
954 }
955 }
956
957 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
958
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)959 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
960 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
961 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
962 {
963 MS_U8 i=0;
964 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",u8Index, u8A, u8R, u8G, u8B));
965
966 /* Don't care high byte */
967 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
968
969 for(i =(GOP_WordUnit-1);i>4;i--)
970 {
971 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
972 }
973 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
974 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
975 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
976 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
977 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
978 *pREGMAP_Offset += GOP_WordUnit;
979
980 MsOS_FlushMemory(); //make sure cpu write data to dram
981
982 }
983
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)984 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
985 {
986 MS_U16 bpp=0;
987
988 switch ( fbFmt )
989 {
990 case E_DRV_GOP_COLOR_RGB555_BLINK :
991 case E_DRV_GOP_COLOR_RGB565 :
992 case E_DRV_GOP_COLOR_ARGB1555:
993 case E_DRV_GOP_COLOR_RGBA5551:
994 case E_DRV_GOP_COLOR_ARGB4444 :
995 case E_DRV_GOP_COLOR_RGBA4444 :
996 case E_DRV_GOP_COLOR_RGB555YUV422:
997 case E_DRV_GOP_COLOR_YUV422:
998 case E_DRV_GOP_COLOR_2266:
999 bpp = 16;
1000 break;
1001 case E_DRV_GOP_COLOR_ARGB8888 :
1002 case E_DRV_GOP_COLOR_ABGR8888 :
1003 bpp = 32;
1004 break;
1005
1006 case E_DRV_GOP_COLOR_I8 :
1007 bpp = 8;
1008 break;
1009
1010 default :
1011 //print err
1012 MS_ASSERT(0);
1013 bpp = 0xFFFF;
1014 break;
1015 }
1016 return bpp;
1017
1018 }
1019
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)1020 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
1021 {
1022 MS_U16 regval;
1023 /*For compatibility
1024 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
1025 MS_U8 u8coef_cpt = u8coef;
1026
1027 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
1028 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
1029 {
1030 switch(u8coef)
1031 {
1032 case 0x0 :
1033 u8coef_cpt = u8coef<<2;
1034 break;
1035 case 0x3f :
1036 u8coef_cpt = ((u8coef<<2)|0x3);
1037 break;
1038 default:
1039 u8coef_cpt = ((u8coef<<2)|0x1);
1040 break;
1041 }
1042 }
1043
1044 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1045 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1046 {
1047 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1048 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1049 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1050 }
1051 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1052 else
1053 {
1054 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1055 {
1056 regval = (MS_U16)(bEnable?(1<<14):0);
1057 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1058 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1059 }
1060 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1061 {
1062 regval = (MS_U16)(bEnable?(1<<14):0);
1063 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1064 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1065 }
1066 else
1067 {
1068 regval = (MS_U16)(bEnable?(1<<14):0);
1069 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1070 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1071 }
1072 }
1073 }
1074
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1075 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1076 {
1077 pGOPHalLocal->va_mmio_base = addr;
1078 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1079 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1080 {
1081 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1082 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1083 {
1084 }
1085
1086
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1087 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1088 {
1089 /*A5 GOP dst type:
1090 1: IP (Main)
1091 0: IP (Sub)
1092 2: OP
1093 3: MVOP
1094 4: MVOP (Sub)
1095 6: FRC
1096 11: InsideFRC
1097 */
1098 MS_U16 u16RegVal;
1099 MS_U32 u32BankOffSet;
1100 MS_BOOL bEnable=FALSE;
1101 MS_U16 u16HSyncMask=GOP_BIT14;
1102
1103 if( GopNum >= MAX_GOP_SUPPORT)
1104 {
1105 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,GopNum);
1106 return GOP_INVALID_PARAMETERS;
1107 }
1108
1109 switch (eDstType)
1110 {
1111 case E_DRV_GOP_DST_IP0:
1112 if( (GopNum == E_GOP0) || (GopNum == E_GOP1) )
1113 {
1114 u16RegVal = 0x0;
1115 bEnable = FALSE;
1116 u16HSyncMask=0;
1117 }else{
1118 return GOP_FUN_NOT_SUPPORTED;
1119 }
1120 break;
1121
1122 case E_DRV_GOP_DST_IP0_SUB:
1123 if( (GopNum == E_GOP0) || (GopNum == E_GOP1) )
1124 {
1125 u16RegVal = 0x1;
1126 bEnable = FALSE;
1127 u16HSyncMask=0;
1128 }else{
1129 return GOP_FUN_NOT_SUPPORTED;
1130 }
1131 break;
1132
1133 case E_DRV_GOP_DST_OP0:
1134 u16RegVal = 0x2;
1135 bEnable = FALSE;
1136 u16HSyncMask=GOP_BIT14;
1137 break;
1138
1139 case E_DRV_GOP_DST_IP1:
1140 u16RegVal = 0x5;
1141 bEnable = TRUE;
1142 break;
1143
1144 case E_DRV_GOP_DST_OP1:
1145 u16RegVal = 0x6;
1146 bEnable = TRUE;
1147 u16HSyncMask=GOP_BIT14;
1148 break;
1149
1150 case E_DRV_GOP_DST_VE:
1151 u16RegVal = 0x7;
1152 bEnable = TRUE;
1153 u16HSyncMask=GOP_BIT14;
1154 break;
1155
1156 case E_DRV_GOP_DST_DIP:
1157 u16RegVal = 0x8;
1158 bEnable = TRUE;
1159 u16HSyncMask=GOP_BIT14;
1160 break;
1161
1162 default:
1163 return GOP_FUN_NOT_SUPPORTED;
1164 }
1165
1166 if(bOnlyCheck == FALSE)
1167 {
1168 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1169 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1170 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(3:0));
1171
1172 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1173 }
1174 return GOP_SUCCESS;
1175 }
1176
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1177 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1178 {
1179 /*U4 Mixer dst type:
1180 2: OP
1181 3: VE
1182 */
1183 MS_U16 u16Regval = 0;
1184 DRV_MixerDstType eType=E_DRV_MIXER_DST_VE;
1185
1186 switch(eDstType)
1187 {
1188 case E_DRV_GOP_DST_MIXER2VE:
1189 eType = E_DRV_MIXER_DST_VE;
1190 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //Enable pseudo hsync
1191 break;
1192 case E_DRV_GOP_DST_MIXER2OP:
1193 eType = E_DRV_MIXER_DST_OP;
1194 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT7); //Disable pseudo hsync
1195 break;
1196 default:
1197 break;
1198 }
1199
1200 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1201
1202 u16Regval &= (~(GOP_BIT3|GOP_BIT4));
1203 u16Regval |= (eType<<0x3);
1204
1205 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4));
1206 return GOP_SUCCESS;
1207 }
1208
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1209 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1210 {
1211 MS_U16 u16Regval = 0;
1212
1213 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1214
1215 if(((u16Regval&0x18)>>3) == 0x2)
1216 *pGopDst = E_DRV_GOP_DST_MIXER2OP;
1217 else
1218 *pGopDst = E_DRV_GOP_DST_MIXER2VE;
1219
1220 return GOP_SUCCESS;
1221 }
1222
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1223 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1224 {
1225 /*T8
1226 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1227 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1228 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1229 */
1230 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=5;
1231 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1232
1233 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1234 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT14 , GOP_BIT14); //SC_0 Mux trigger
1235
1236 /*Disable VE OSD enable*/
1237 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_0, 0x4);
1238 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_1, 0x4);
1239
1240 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_VOPNBL, 1<<7, GOP_BIT7);
1241 return GOP_SUCCESS;
1242 }
1243
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1244 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1245 {
1246 MS_U16 u16GopMux=0;
1247 switch(eGopMux)
1248 {
1249 case E_GOP_MUX0:
1250 case E_GOP_MUX1:
1251 case E_GOP_MUX2:
1252 case E_GOP_MUX3:
1253 case E_GOP_MUX4:
1254 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1255 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1256 break;
1257 case E_GOP_IP0_MUX:
1258 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1259 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1260 break;
1261 case E_GOP_IP0_SUB_MUX:
1262 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1263 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1264 break;
1265 case E_GOP_VOP0_MUX:
1266 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1267 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1268 break;
1269 case E_GOP_VOP0_SUB_MUX:
1270 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1271 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1272 break;
1273 case E_GOP_Mix_MUX0:
1274 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1275 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1276 break;
1277 case E_GOP_Mix_MUX1:
1278 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1279 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1280 break;
1281 case E_GOP_VE0_MUX:
1282 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1283 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1284 break;
1285 case E_GOP_VE1_MUX:
1286 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1287 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1288 break;
1289 case E_GOP_DIP_MUX:
1290 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1291 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1292 break;
1293 case E_GOP_FRC_MUX0:
1294 case E_GOP_FRC_MUX1:
1295 case E_GOP_FRC_MUX2:
1296 case E_GOP_FRC_MUX3:
1297 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1298 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1299 break;
1300 case E_GOP_BYPASS_MUX0:
1301 break;
1302 case E_GOP_OP1_MUX:
1303 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_SC1, &u16GopMux);
1304 *u8GOPNum = (u16GopMux& ((BMASK((GOP_MUX_SHIFT-1):0))<<12))>>12;
1305 break;
1306 case E_GOP_IP1_MUX:
1307 case E_GOP_VOP1_MUX:
1308 case E_GOP_GS_MUX:
1309 case E_GOP_DUALRATE_OP_MUX0:
1310 case E_GOP_DUALRATE_OP_MUX1:
1311 case E_GOP_DUALRATE_OP_MUX2:
1312 // to prevent warning log
1313 break;
1314 default:
1315 printf("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1316 break;
1317 }
1318 //Transform GOPNum for app user
1319 *u8GOPNum = GOPNUM_TRANSFORM_INVERSE(*u8GOPNum);
1320 }
1321
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1322 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1323 {
1324 MS_U16 u16Ret[4]={0};
1325 u8GOPNum = GOPNUM_TRANSFORM(u8GOPNum);
1326
1327 switch(eGopMux)
1328 {
1329 case E_GOP_MUX0:
1330 case E_GOP_MUX1:
1331 case E_GOP_MUX2:
1332 case E_GOP_MUX3:
1333 case E_GOP_MUX4:
1334 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1335 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1336 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT14 , GOP_BIT14); //SC_0 Mux trigger
1337 break;
1338 case E_GOP_OP1_MUX:
1339 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_SC1, u8GOPNum <<12, GOP_REGMUX_MASK<<12);
1340 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1341 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT13 , GOP_BIT13); //SC_1 Mux trigger
1342 break;
1343 case E_GOP_IP0_MUX:
1344 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1345 break;
1346 case E_GOP_IP1_MUX:
1347 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << 0, BMASK(2:0));
1348 break;
1349 case E_GOP_VOP0_MUX:
1350 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1351 break;
1352 case E_GOP_VOP1_MUX:
1353 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1354 break;
1355 case E_GOP_Mix_MUX0:
1356 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1357 break;
1358 case E_GOP_Mix_MUX1:
1359 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1360 break;
1361 case E_GOP_VE0_MUX:
1362 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1363 break;
1364 case E_GOP_VE1_MUX:
1365 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1366 break;
1367 case E_GOP_DIP_MUX:
1368 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1369 break;
1370 case E_GOP_FRC_MUX0:
1371 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1372 break;
1373 case E_GOP_FRC_MUX1:
1374 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1375 break;
1376 case E_GOP_FRC_MUX2:
1377 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1378 break;
1379 case E_GOP_FRC_MUX3:
1380 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1381 break;
1382 case E_GOP_BYPASS_MUX0:
1383 //Check MUX is using? Checking from priority high to low
1384 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1385 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1386 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1387 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1388
1389 //Checking if un-use
1390 if((u16Ret[0] & GOP_BIT0) ==0)
1391 {
1392 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1393 }
1394 else if((u16Ret[1] & GOP_BIT0) ==0)
1395 {
1396 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1397 }
1398 else if((u16Ret[2] & GOP_BIT0) ==0)
1399 {
1400 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1401 }
1402 else if((u16Ret[3] & GOP_BIT0) ==0)
1403 {
1404 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1405 }
1406 else
1407 {
1408 printf("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1409 }
1410 break;
1411 break;
1412 default:
1413 printf("[%s]ERROR mux setting\n",__FUNCTION__);
1414 break;
1415 }
1416 }
1417
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1418 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1419 {
1420 /* GOP OP Path enable to SC Setting
1421 A5: GOP OP Path blending with SC sequence
1422 mux1-->mux0-->mux2-->mux3
1423 */
1424 MS_BOOL bOSDBEnable=TRUE;
1425 MS_U16 muxValue=0, mux4Value=0, regval=0;
1426
1427 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1428 MS_U16 u164K2KMuxValue=0;
1429 MS_U8 u8GopNumTemp = 0;//save the gop num after convert
1430
1431 if(gopNum >= MAX_GOP_SUPPORT)
1432 {
1433 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1434 return GOP_FAIL;
1435 }
1436 u8GopNumTemp = GOPNUM_TRANSFORM(gopNum);
1437 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1438 if(bOSDBEnable)
1439 {
1440 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, 0x0, GOP_REG_HW_MASK);
1441
1442 }else
1443 {
1444 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1445 }
1446
1447 if (u8GopNumTemp == (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1448 {
1449 if(bOSDBEnable)
1450 {
1451 if(bEnable)
1452 {
1453 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1454 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3);
1455 }else{
1456 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3);
1457 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1458 }
1459 }
1460 else
1461 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1462 }
1463
1464 if (u8GopNumTemp == ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1465 {
1466 if(bOSDBEnable)
1467 {
1468 if(bEnable)
1469 {
1470 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1471 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT11, GOP_BIT11);
1472 }else{
1473 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT11);
1474 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1475 }
1476 }
1477 else
1478 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1479 }
1480
1481 if (u8GopNumTemp == ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1482 {
1483 if(bOSDBEnable)
1484 {
1485 if(bEnable)
1486 {
1487 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1488 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3);
1489 }else{
1490 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3);
1491 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1492 }
1493 }
1494 else
1495 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1496 }
1497
1498 if (u8GopNumTemp == ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1499 {
1500 if(bOSDBEnable)
1501 {
1502 if(bEnable)
1503 {
1504 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1505 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT11, GOP_BIT11);
1506 }else{
1507 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT11);
1508 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1509 }
1510 }
1511 else
1512 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1513 }
1514
1515 if (u8GopNumTemp == ((muxValue & GOP_MUX4_MASK)>>(GOP_MUX_SHIFT*4))) //enable mux4
1516 {
1517 if(bOSDBEnable)
1518 {
1519 if(bEnable)
1520 {
1521 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_EX, GOP_BIT3, GOP_BIT3);
1522 }else{
1523 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_EX, 0, GOP_BIT3);
1524 }
1525 }
1526 else
1527 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1528 }
1529
1530 if(MAX_GOP_SUPPORT ==5)
1531 {
1532 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &mux4Value);
1533 if (u8GopNumTemp == ((mux4Value & GOP_MUX4_MASK)>> GOP_MUX4_SHIFT)) //enable mux4
1534 {
1535 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1536 }
1537 }
1538
1539 /*For FRC mux switch*/
1540 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1541 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1542 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1543 {
1544 /* Switch FRC blending */
1545 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1546 }
1547
1548 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1549 {
1550 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1551 }
1552
1553 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1554 {
1555 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1556 }
1557
1558 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1559 {
1560 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1561 }
1562
1563 return GOP_SUCCESS;
1564 }
1565
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1566 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1567 {
1568 MS_U32 u32pBankOffSet=0;
1569 MS_U16 u16Regval;
1570
1571 if(g_GopChipPro.b2Pto1PSupport)
1572 {
1573 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1574 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1575 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |GOP_BIT11):(u16Regval & ~GOP_BIT11), GOP_BIT11);
1576 }
1577 return GOP_SUCCESS;
1578 }
1579
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1580 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1581 {
1582 /* GOP OP Path enable to SC Setting
1583 A5: GOP OP Path blending with SC sequence
1584 mux1-->mux0-->mux2-->mux3
1585 */
1586 MS_U16 muxValue=0, regval=0;
1587
1588 if(gopNum >= MAX_GOP_SUPPORT)
1589 {
1590 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1591 return FALSE;
1592 }
1593
1594 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1595 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1596 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1597 {
1598 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1599 }
1600 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1601 {
1602 //printf("");
1603 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1604 }
1605 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1606 {
1607 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1608 }
1609 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1610 {
1611 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1612 }
1613 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1614 {
1615 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1616 }
1617 else
1618 {
1619 return GOP_FAIL;
1620 }
1621 return GOP_SUCCESS;
1622 }
1623
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1624 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1625 {
1626 MS_U16 muxValue=0;
1627 MS_U16 regval37=0;
1628 MS_U16 regval38=0;
1629
1630 if(gopNum >= MAX_GOP_SUPPORT)
1631 {
1632 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1633 return FALSE;
1634 }
1635
1636 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1637 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, ®val37);
1638 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, ®val38);
1639 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1640 {
1641 *pbEnable = (regval37& GOP_BIT5) == GOP_BIT5;
1642 }
1643 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1644 {
1645 *pbEnable = (regval37 & GOP_BIT13) == GOP_BIT13;
1646 }
1647 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1648 {
1649 *pbEnable = (regval38 & GOP_BIT5) == GOP_BIT5;
1650 }
1651 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1652 {
1653 *pbEnable = (regval38 & GOP_BIT13) == GOP_BIT13;
1654 }
1655 else
1656 {
1657 return GOP_FAIL;
1658 }
1659 return GOP_SUCCESS;
1660 }
1661
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1662 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1663 {
1664 /*T8
1665 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1666 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1667 */
1668 MS_U16 Mux3Gop, muxValue=0, i;
1669 MS_U16 MuxShift;
1670
1671 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1672
1673 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1674 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1675 {
1676 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1677 {
1678 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1679
1680 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1681 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1682 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1683 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1684
1685 if(g_GopChipPro.bOPMuxDoubleBuffer == TRUE)
1686 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT14 , GOP_BIT14); //SC_0 Mux trigger
1687
1688 break;
1689
1690 }
1691
1692 }
1693 return GOP_SUCCESS;
1694 }
1695
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1696 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1697 {
1698 /*T8 GOP dst type:
1699 0: IP (Main)
1700 1: IP (Sub)
1701 2: OP
1702 3: MVOP
1703 */
1704
1705 if(gopNum >= MAX_GOP_SUPPORT)
1706 {
1707 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1708 MS_ASSERT(0);
1709 return GOP_INVALID_PARAMETERS;
1710 }
1711 /* Monaco clkgen setting */
1712 /******************
1713 0: odclk
1714 1: idclk_f2 (ipm)
1715 2: idclk_f1 (ips)
1716 3: ocmixer
1717 4: ve
1718 5 : mvop main
1719 6 : mvop sub
1720 ******************/
1721
1722 switch(eDstType)
1723 {
1724 case E_DRV_GOP_DST_IP0:
1725 if (gopNum==E_GOP0)
1726 {
1727 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1728 }
1729 else if (gopNum==E_GOP1)
1730 {
1731 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1732 }
1733 else
1734 {
1735 MS_ASSERT(0);
1736 return GOP_INVALID_PARAMETERS;
1737 }
1738 break;
1739
1740 case E_DRV_GOP_DST_IP0_SUB:
1741 if (gopNum==E_GOP0)
1742 {
1743 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1744 }
1745 else if (gopNum==E_GOP1)
1746 {
1747 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1748 }
1749 else
1750 {
1751 MS_ASSERT(0);
1752 return GOP_INVALID_PARAMETERS;
1753 }
1754 break;
1755
1756 case E_DRV_GOP_DST_OP0:
1757 if (gopNum==E_GOP0)
1758 {
1759 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1760 }
1761 else if (gopNum==E_GOP1)
1762 {
1763 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1764 }
1765 else if (gopNum==E_GOP2)
1766 {
1767 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1768 }else if (gopNum==E_GOP3)
1769 {
1770 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
1771 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1772 {
1773 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_ODCLK, CKG_GOPG5_MASK);
1774 }else
1775 {
1776 MS_ASSERT(0);
1777 return GOP_INVALID_PARAMETERS;
1778 }
1779 break;
1780
1781 case E_DRV_GOP_DST_IP1:
1782 if (gopNum==E_GOP0)
1783 {
1784 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
1785 }
1786 else if (gopNum==E_GOP1)
1787 {
1788 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1789 }
1790 else if (gopNum==E_GOP2)
1791 {
1792 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
1793 }else if (gopNum==E_GOP3)
1794 {
1795 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG3_MASK);
1796 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1797 {
1798 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_IDCLK1, CKG_GOPG5_MASK);
1799 }else
1800 {
1801 MS_ASSERT(0);
1802 return GOP_INVALID_PARAMETERS;
1803 }
1804 break;
1805
1806 case E_DRV_GOP_DST_OP1:
1807 if (gopNum==E_GOP0)
1808 {
1809 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OD1CLK, CKG_GOPG0_MASK);
1810 }
1811 else if (gopNum==E_GOP1)
1812 {
1813 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OD1CLK, CKG_GOPG1_MASK);
1814 }
1815 else if (gopNum==E_GOP2)
1816 {
1817 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OD1CLK, CKG_GOPG2_MASK);
1818 }else if (gopNum==E_GOP3)
1819 {
1820 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OD1CLK, CKG_GOPG3_MASK);
1821 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1822 {
1823 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_OD1CLK, CKG_GOPG5_MASK);
1824 }else
1825 {
1826 MS_ASSERT(0);
1827 return GOP_INVALID_PARAMETERS;
1828 }
1829 break;
1830
1831 case E_DRV_GOP_DST_DIP:
1832 if (gopNum==E_GOP0)
1833 {
1834 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DIP, CKG_GOPG0_MASK);
1835 }
1836 else if (gopNum==E_GOP1)
1837 {
1838 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DIP, CKG_GOPG1_MASK);
1839 }
1840 else if (gopNum==E_GOP2)
1841 {
1842 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DIP, CKG_GOPG2_MASK);
1843 }else if (gopNum==E_GOP3)
1844 {
1845 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_DIP, CKG_GOPG3_MASK);
1846 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1847 {
1848 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_DIP, CKG_GOPG5_MASK);
1849 }else
1850 {
1851 MS_ASSERT(0);
1852 return GOP_INVALID_PARAMETERS;
1853 }
1854 break;
1855
1856 case E_DRV_GOP_DST_VE:
1857 if (gopNum==E_GOP0)
1858 {
1859 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OD1CLK, CKG_GOPG0_MASK);
1860 }
1861 else if (gopNum==E_GOP1)
1862 {
1863 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OD1CLK, CKG_GOPG1_MASK);
1864 }
1865 else if (gopNum==E_GOP2)
1866 {
1867 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OD1CLK, CKG_GOPG2_MASK);
1868 }else if (gopNum==E_GOP3)
1869 {
1870 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OD1CLK, CKG_GOPG3_MASK);
1871 }else if (gopNum==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
1872 {
1873 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, CKG_GOPG5_OD1CLK, CKG_GOPG5_MASK);
1874 }else
1875 {
1876 MS_ASSERT(0);
1877 return GOP_INVALID_PARAMETERS;
1878 }
1879 break;
1880
1881 default:
1882 MS_ASSERT(0);
1883 return GOP_ENUM_NOT_SUPPORTED;
1884 }
1885
1886 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1887 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1888
1889 return GOP_SUCCESS;
1890 }
1891
1892
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1893 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1894 {
1895 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1896 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1897 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1898 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1899 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1900 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1901 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1902 else
1903 return GOP_INVALID_PARAMETERS;
1904
1905 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1906 return GOP_SUCCESS;
1907 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1908 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1909 {
1910 if (bEnable)
1911 {
1912 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1913 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1914 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1915 }
1916 else
1917 {
1918 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1919 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1920 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1921 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPDCLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1922 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1923 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1924 }
1925
1926 return GOP_SUCCESS;
1927 }
1928
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1929 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1930 {
1931 DRV_GOPDstType MixerDstType;
1932 MS_U16 regval = 0;
1933 MS_U8 u8MUXGOPNum = 0;
1934 int i = 0;
1935
1936 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
1937 #if 0 //TO DO: To disable mixer mux
1938 MS_U16 u16val;
1939 if( regval & 0x0001) //MIXER GOP0 enable -> enable GOP1
1940 {
1941 u16val = (bEnable? TRUE: FALSE);
1942 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
1943 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1944 }
1945 else //enable GOP0
1946 {
1947 u16val = (bEnable? TRUE: FALSE);
1948 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
1949 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1950 }
1951 #else
1952 if((regval&(GOP_BIT0|GOP_BIT1)) == (GOP_BIT0|GOP_BIT1))
1953 {
1954 if((gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10)) && (gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12)))
1955 {
1956 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1957 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1958 }
1959 }
1960 else if(regval&GOP_BIT0)
1961 {
1962 if(gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10))
1963 {
1964 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
1965 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1966 }
1967 }
1968 else if(regval&GOP_BIT1) //gop1Enable
1969 {
1970 if(gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12))
1971 {
1972 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
1973 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1974 }
1975 }
1976 else //no one enable
1977 {
1978 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1979 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1980 }
1981 #endif
1982
1983 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //disable pseudo hsync
1984
1985 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
1986
1987 HAL_GOP_GetMixerDst(pGOPHalLocal,&MixerDstType);
1988 if(MixerDstType == E_DRV_GOP_DST_MIXER2OP)
1989 {
1990 for (i=0; i<MAX_GOP_MUX - 1; i++) //mux3 not supported to OP
1991 {
1992 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &u8MUXGOPNum, (Gop_MuxSel)i);
1993 if (0x4==u8MUXGOPNum)
1994 {
1995 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, TRUE);
1996 }
1997 else
1998 {
1999 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, FALSE);
2000 }
2001 }
2002 }
2003 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_EN_VFIL, GOP_MIXER_EN_VFIL_MASK);
2004 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_VS_FLD_ON, GOP_MIXER_VS_FLD_ON_MASK);
2005 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_REG_DUMMY, GOP_BIT0, GOP_BIT0);
2006 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15); //Enable Mixer
2007
2008 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2009 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2010
2011
2012 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2013
2014 #if 0 /* PAL System*/
2015 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2016 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2017 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_HSTART_OFST, GOP_REG_WORD_MASK);
2018 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_VSTART_OFST, GOP_REG_WORD_MASK);
2019 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, 0x330, GOP_REG_WORD_MASK);
2020 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, 0x25D, GOP_REG_WORD_MASK);
2021 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2022 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_HS_DELAY, GOP_REG_WORD_MASK);
2023 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, GOP_MIXER_PD, GOP_REG_WORD_MASK);
2024 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2025 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2026 #endif
2027 return GOP_SUCCESS;
2028
2029 }
2030
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)2031 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
2032 {
2033 MS_U16 u16val;
2034
2035 if (muxNum >= MAX_MIXER_MUX)
2036 {
2037 MS_CRITICAL_MSG(printf("\n[%s] not support mux%d in this chip version!!",__FUNCTION__, muxNum));
2038 return GOP_FAIL;
2039 }
2040
2041 if(muxNum==MIXER_MUX0Id) //Set GOP to mux0
2042 {
2043 u16val = (bEnable? TRUE: FALSE);
2044 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
2045 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2046 }
2047 else //Set GOP to mux1
2048 {
2049 u16val = (bEnable? TRUE: FALSE);
2050 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
2051 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2052 }
2053 return GOP_SUCCESS;
2054
2055 }
2056
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2057 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
2058 {
2059 MS_U32 u32bankoffset = 0;
2060 DRV_GOPDstType gopDstType = E_DRV_GOP_DST_IP0;
2061 MS_U16 regval = 0x0;
2062
2063 HAL_GOP_GetGOPDst(pGOPHalLocal, u8GOP, &gopDstType);
2064
2065 if(gopDstType == E_DRV_GOP_DST_MIXER2VE)
2066 {
2067
2068 _GetBnkOfstByGop(u8GOP, &u32bankoffset);
2069
2070 if(bEn)
2071 {
2072
2073 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT2, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2074 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)~GOP_BIT15, GOP_BIT15);
2075
2076 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2077
2078 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2079 {
2080 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2081 }
2082 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2083 {
2084 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2085 }
2086 else
2087 {
2088 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2089 return GOP_FAIL;
2090 }
2091 }
2092 else
2093 {
2094 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2095 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2096
2097 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2098
2099 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2100 {
2101 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2102 }
2103 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2104 {
2105 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2106 }
2107 else
2108 {
2109 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2110 return GOP_FAIL;
2111 }
2112 }
2113 }
2114 else
2115 {
2116 printf("[%s][%d]GOP not on Mixer2VE path\n",__FUNCTION__,__LINE__);
2117 return GOP_FAIL;
2118 }
2119
2120 return GOP_SUCCESS;
2121
2122 }
2123
HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2124 GOP_Result HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2125 {
2126 MS_U16 bankTemp = 0;
2127 MS_U16 u16val = 0;
2128
2129 u16val = (bEnable? TRUE: FALSE);
2130 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2131 switch (muxNum) //Enable OP new alpha mode
2132 {
2133 case 0:
2134 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2135 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<1), GOP_BIT1);
2136 break;
2137 case 1:
2138 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2139 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<6), GOP_BIT6);
2140 break;
2141 case 2:
2142 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2143 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<8), GOP_BIT8);
2144 break;
2145 default:
2146 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2147 break;
2148 }
2149 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2150 return GOP_SUCCESS;
2151 }
2152
HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2153 GOP_Result HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2154 {
2155 MS_U16 bankTemp = 0;
2156 MS_U16 u16val = 0;
2157
2158 u16val = (bEnable? TRUE: FALSE);
2159 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2160 switch (muxNum) //Enable OP per pixel new alpha mode
2161 {
2162 case 0:
2163 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2164 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<3), GOP_BIT3);
2165 break;
2166 case 1:
2167 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2168 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<14), GOP_BIT14);
2169 break;
2170 case 2:
2171 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2172 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<15), GOP_BIT15);
2173 break;
2174 default:
2175 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2176 break;
2177 }
2178 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2179 return GOP_SUCCESS;
2180 }
2181
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2182 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2183 {
2184 MS_U32 u32GopIdx;
2185
2186 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2187 pGOPHalLocal->pHALShared = pHALShared;
2188
2189 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2190 {
2191 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2192 }
2193 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
2194 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2195 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2196 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2197 {
2198 }
2199
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2200 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2201 {
2202 MS_U8 u8Miu=0xff;
2203 MS_U16 u16RegVal_L=0;
2204 #ifdef GOP_MIU_GROUP2
2205 MS_U16 u16RegVal_H=0;
2206 #endif
2207
2208 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2209 #ifdef GOP_MIU_GROUP2
2210 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2211 #endif
2212 if (gwinid<MAX_GOP0_GWIN) //gop0
2213 {
2214 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2215 #ifdef GOP_MIU_GROUP2
2216 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2217 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2218 #else
2219 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2220 #endif
2221 }
2222 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
2223 {
2224 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2225 #ifdef GOP_MIU_GROUP2
2226 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2227 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2228 #else
2229 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2230 #endif
2231 }
2232 else if (gwinid==GOP2_GwinIdBase) //gop2
2233 {
2234 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2235 #ifdef GOP_MIU_GROUP2
2236 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2237 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2238 #else
2239 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2240 #endif
2241 }
2242 else if (gwinid==GOP3_GwinIdBase) //gop3
2243 {
2244 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2245 #ifdef GOP_MIU_GROUP2
2246 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2247 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2248 #else
2249 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2250 #endif
2251 }
2252 else if (gwinid==GOP5_GwinIdBase) //gop5
2253 {
2254 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal_L);
2255 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP5);
2256 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP5);
2257 }
2258 else
2259 {
2260 return GOP_FAIL;
2261 }
2262
2263 if (u8Miu <= 2)
2264 {
2265 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2266 }
2267 else
2268 {
2269 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2270 return GOP_FAIL;
2271 }
2272 return GOP_SUCCESS;
2273 }
2274
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2275 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2276 {
2277 MS_U8 u8Miu=0xff;
2278 MS_U16 u16RegVal_L=0;
2279 MS_U32 u32BnkOfst=0xFFFF;
2280 #ifdef GOP_MIU_GROUP2
2281 MS_U16 u16RegVal_H=0;
2282 #endif
2283
2284 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2285 {
2286 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2287 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2288
2289 u8Miu= (u16RegVal_L& (GOP_BIT2|GOP_BIT3)) >>2;
2290 }
2291 else
2292 {
2293 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2294 #ifdef GOP_MIU_GROUP2
2295 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2296 #endif
2297 switch (gopnum)
2298 {
2299 case 0:
2300 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2301 #ifdef GOP_MIU_GROUP2
2302 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2303 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2304 #else
2305 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2306 #endif
2307 break;
2308 case 1:
2309 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2310 #ifdef GOP_MIU_GROUP2
2311 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2312 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2313 #else
2314 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2315 #endif
2316 break;
2317
2318 case 2:
2319 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2320 #ifdef GOP_MIU_GROUP2
2321 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2322 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2323 #else
2324 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2325 #endif
2326 break;
2327
2328 case 3:
2329 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2330 #ifdef GOP_MIU_GROUP2
2331 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2332 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2333 #else
2334 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2335 #endif
2336 break;
2337 case 4: //GOP5
2338 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal_L);
2339 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP5);
2340
2341 default:
2342 return 0xff;
2343 break;
2344 }
2345
2346 if(u8Miu > MAX_GOP_MIUSEL )
2347 {
2348 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2349 return 0xff;
2350 }
2351
2352 }
2353 return u8Miu;
2354 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2355 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2356 {
2357 MS_U16 u16Regval;
2358 MS_U32 u32pBankOffSet=0;
2359 GOP_Result ret;
2360
2361 if(u8gopNum >= MAX_GOP_SUPPORT)
2362 {
2363 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8gopNum);
2364 *pGopDst = E_DRV_GOP_DST_INVALID;
2365 return GOP_FAIL;
2366 }
2367
2368 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2369 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2370
2371 switch (u16Regval&GOP_DST_MASK)
2372 {
2373 case 0:
2374 *pGopDst = E_DRV_GOP_DST_IP0;
2375 ret = GOP_SUCCESS;
2376 break;
2377 case 1:
2378 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
2379 ret = GOP_SUCCESS;
2380 break;
2381 case 2:
2382 *pGopDst = E_DRV_GOP_DST_OP0;
2383 ret = GOP_SUCCESS;
2384 break;
2385 case 5:
2386 *pGopDst = E_DRV_GOP_DST_IP1;
2387 ret = GOP_SUCCESS;
2388 break;
2389 case 6:
2390 *pGopDst = E_DRV_GOP_DST_OP1;
2391 ret = GOP_SUCCESS;
2392 break;
2393 case 7:
2394 *pGopDst = E_DRV_GOP_DST_VE;
2395 ret = GOP_SUCCESS;
2396 break;
2397 case 8:
2398 *pGopDst = E_DRV_GOP_DST_DIP;
2399 ret = GOP_SUCCESS;
2400 break;
2401 default:
2402 *pGopDst = E_DRV_GOP_DST_INVALID;
2403 ret = GOP_FAIL;
2404 break;
2405 }
2406
2407 return ret;
2408
2409 }
2410
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2411 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2412 {
2413 MS_U16 muxValue=0;
2414 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2415 MS_BOOL bSC1_OP=0,bSC1_IP=0;
2416
2417 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2418
2419 switch(ipSelGop)
2420 {
2421 case MS_DRV_IP0_SEL_GOP0:
2422 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2423 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2424 u16RegVal |= GOP_BIT12;//mux0
2425 else
2426 u16RegVal |= GOP_BIT13;//mux1
2427 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2428 bSC1_OP =FALSE;
2429 bSC1_IP =FALSE;
2430 break;
2431
2432 case MS_DRV_IP0_SEL_GOP1:
2433 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2434 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2435 u16RegVal |= GOP_BIT12;//mux0
2436 else
2437 u16RegVal |= GOP_BIT13;//mux1
2438 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2439 bSC1_OP =FALSE;
2440 bSC1_IP =FALSE;
2441 break;
2442 case MS_DRV_IP0_SEL_GOP2:
2443 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2444 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2445 u16RegVal |= GOP_BIT12;//mux0
2446 else
2447 u16RegVal |= GOP_BIT13;//mux1
2448 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2449 bSC1_OP =FALSE;
2450 bSC1_IP =FALSE;
2451 break;
2452
2453 case MS_DRV_NIP_SEL_GOP0:
2454 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2455 {
2456 u16RegVal = ~GOP_BIT12;//mux0
2457 u16RegMsk = GOP_BIT12;
2458 }
2459 else
2460 {
2461 u16RegVal = ~GOP_BIT13;//mux1
2462 u16RegMsk = GOP_BIT13;
2463 }
2464 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2465 bSC1_OP =FALSE;
2466 bSC1_IP =FALSE;
2467 break;
2468
2469 case MS_DRV_NIP_SEL_GOP1:
2470 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2471 {
2472 u16RegVal = ~GOP_BIT12;//mux0
2473 u16RegMsk = GOP_BIT12;
2474 }
2475 else
2476 {
2477 u16RegVal = ~GOP_BIT13;//mux1
2478 u16RegMsk = GOP_BIT13;
2479 }
2480 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2481 bSC1_OP =FALSE;
2482 bSC1_IP =FALSE;
2483 break;
2484 case MS_DRV_NIP_SEL_GOP2:
2485 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2486 {
2487 u16RegVal = ~GOP_BIT12;//mux0
2488 u16RegMsk = GOP_BIT12;
2489 }
2490 else
2491 {
2492 u16RegVal = ~GOP_BIT13;//mux1
2493 u16RegMsk = GOP_BIT13;
2494 }
2495 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2496 bSC1_OP =FALSE;
2497 bSC1_IP =FALSE;
2498 break;
2499 case MS_DRV_MVOP_SEL:
2500 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2501 u16RegVal |= GOP_BIT12; //mux0
2502 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2503 bSC1_OP =FALSE;
2504 bSC1_IP =FALSE;
2505 break;
2506 case MS_DRV_SC1OP_SEL:
2507 bSC1_OP =TRUE;
2508 bSC1_IP =FALSE;
2509 break;
2510 case MS_DRV_IP1_SEL:
2511 bSC1_OP =FALSE;
2512 bSC1_IP =TRUE;
2513 break;
2514 default:
2515 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
2516 break;
2517 }
2518 if(0 != u16RegMsk)
2519 {
2520 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2521 }
2522
2523 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bSC1_OP<<14, GOP_BIT14);
2524 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, !bSC1_IP<<11, GOP_BIT11);
2525 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, bSC1_IP<<12, GOP_BIT12);
2526
2527 }
2528
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2529 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2530 {
2531 return GOP_FUN_NOT_SUPPORTED;
2532 }
2533
2534
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2535 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2536 {
2537 return GOP_FUN_NOT_SUPPORTED;
2538 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2539 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2540 {
2541 return GOP_FUN_NOT_SUPPORTED;
2542 }
2543
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2544 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2545 {
2546 return GOP_FUN_NOT_SUPPORTED;
2547 }
2548
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2549 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2550 {
2551 if(u32mode == E_GOP_PAL)
2552 {
2553 /* PAL System*/
2554 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0xB9;
2555 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0x13;
2556 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, ~GOP_BIT2, GOP_BIT2);
2557 }
2558 else if(u32mode == E_GOP_NTSC)
2559 {
2560 /* NTSC System*/
2561 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0xA3;
2562 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0xF;
2563 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, GOP_BIT2, GOP_BIT2);
2564 }
2565 return GOP_SUCCESS;
2566 }
2567
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2568 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2569 {
2570
2571 if(u32mode == E_GOP_PAL)
2572 {
2573 /* PAL System*/
2574 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2575 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2576 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2577 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2578 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_PAL_WIDTH, GOP_REG_WORD_MASK);
2579 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_PAL_HEIGHT, GOP_REG_WORD_MASK);
2580 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2581 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_PAL_HS_DELAY, GOP_REG_WORD_MASK);
2582 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2583
2584 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2585 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2586 }
2587 else if(u32mode == E_GOP_NTSC)
2588 {
2589 /* NTSC System*/
2590 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2591 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2592 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_NTSC_HSTART_OFST, GOP_REG_WORD_MASK);
2593 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_NTSC_VSTART_OFST, GOP_REG_WORD_MASK);
2594 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_NTSC_WIDTH, GOP_REG_WORD_MASK);
2595 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_NTSC_HEIGHT, GOP_REG_WORD_MASK);
2596 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_NTSC_HTOTAL, GOP_REG_WORD_MASK);
2597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_NTSC_HS_DELAY, GOP_REG_WORD_MASK);
2598
2599 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2600
2601 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2602 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2603 }
2604 else if(u32mode == E_GOP_CUSTOM)
2605 {
2606 return GOP_FUN_NOT_SUPPORTED;
2607 /*
2608 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2609 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2610 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, pTM->hstart, GOP_REG_WORD_MASK);
2611 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, pTM->vstart, GOP_REG_WORD_MASK);
2612 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, pTM->hend, GOP_REG_WORD_MASK);
2613 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, pTM->vend, GOP_REG_WORD_MASK);
2614 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, pTM->htotal, GOP_REG_WORD_MASK);
2615 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, pTM->hsyncdelay, GOP_REG_WORD_MASK);
2616
2617 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2618
2619 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //enable pseudo hsync
2620 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2621 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2622 */
2623 }
2624 else if(u32mode == E_GOP_CUSTOM_OP)
2625 {
2626 return GOP_FUN_NOT_SUPPORTED;
2627 }
2628 return GOP_SUCCESS;
2629 }
2630
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2631 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2632 {
2633 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, bEn, GOP_MIXER_EN_VFIL_MASK);
2634 return GOP_SUCCESS;
2635 }
2636
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2637 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2638 {
2639 //fix me need to modify tile_32bpp mode in 64b_bus
2640 if(E_DRV_GOP_TILE_DATA_16BPP == tilemode)
2641 {
2642 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2643 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2644 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2645 ~GOP_BIT7, GOP_BIT7);
2646
2647 }
2648 else if(E_DRV_GOP_TILE_DATA_32BPP == tilemode)
2649 {
2650 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2651 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2652 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2653 ~GOP_BIT7, GOP_BIT7);
2654 }
2655 else
2656 {
2657 return GOP_FUN_NOT_SUPPORTED;
2658 }
2659
2660 return GOP_SUCCESS;
2661
2662 }
2663
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2664 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2665 {
2666 MS_U32 u32BankOffSet =0;
2667
2668 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2669
2670 if (bEn)
2671 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2672 else
2673 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2674
2675 return GOP_SUCCESS;
2676 }
2677
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2678 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2679 {
2680 MS_U32 u32BankOffSet =0;
2681
2682 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2683
2684 if (bEn)
2685 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2686 else
2687 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2688
2689 return GOP_SUCCESS;
2690 }
2691
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2692 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2693 {
2694 MS_U16 u16Val =0x0;
2695 if (u8win < GOP1_GwinIdBase)
2696 {
2697 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2698 *pEnable = (MS_BOOL)(u16Val>>15);
2699 }
2700 else if (u8win < GOP2_GwinIdBase)
2701 {
2702 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2703 *pEnable = (MS_BOOL)(u16Val>>15);
2704 }
2705 else if (u8win < GOP3_GwinIdBase)
2706 {
2707 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2708 *pEnable = (MS_BOOL)(u16Val>>15);
2709 }
2710 else if (u8win < GOP4_GwinIdBase)
2711 {
2712 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2713 *pEnable = (MS_BOOL)(u16Val>>15);
2714 }
2715 else if (u8win < GOP5_GwinIdBase)
2716 {
2717 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2718 *pEnable = (MS_BOOL)(u16Val>>15);
2719 }
2720 else
2721 {
2722 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2723 return GOP_INVALID_PARAMETERS;
2724 }
2725
2726 return GOP_SUCCESS;
2727 }
2728
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2729 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2730 {
2731 MS_U16 u16Val = bEnable << 15;
2732 if (u8win < GOP1_GwinIdBase)
2733 {
2734 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2735 }
2736 else if (u8win < GOP2_GwinIdBase)
2737 {
2738 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2739 }
2740 else if (u8win < GOP3_GwinIdBase)
2741 {
2742 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2743 }
2744 else if (u8win < GOP4_GwinIdBase)
2745 {
2746 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2747 }
2748 else if (u8win < GOP5_GwinIdBase)
2749 {
2750 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2751 }
2752 else
2753 {
2754 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2755 return GOP_INVALID_PARAMETERS;
2756 }
2757 return GOP_SUCCESS;
2758 }
2759
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2760 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2761 {
2762 MS_U16 u16Reg = 0;
2763 MS_U32 u32WordBase = 0;
2764 MS_U32 u32BankOffSet=0;
2765
2766 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2767
2768 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2769
2770 if(u16Reg & GOP_BIT7)
2771 {
2772 u32WordBase = 1;
2773 }
2774 else
2775 {
2776 u32WordBase = GOP_WordUnit;
2777 }
2778
2779 u32SubAddr /= u32WordBase;
2780
2781 if(u8GOP == E_GOP2)
2782 {
2783 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2784 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2785 }
2786 else if(u8GOP == E_GOP3)
2787 {
2788 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2789 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2790
2791 }
2792 else if(u8GOP == E_GOP4)
2793 {
2794 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2795 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2796 }
2797 else if(u8GOP == E_GOP1)
2798 {
2799 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2800 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2801 }
2802 else //gop0
2803 {
2804 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2805 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2806 }
2807
2808 return GOP_SUCCESS;
2809
2810 }
2811
2812 //------------------------------------------------------------------------------
2813 /// Set VE output with OSD
2814 /// @return none
2815 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2816 GOP_Result HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2817 {
2818 if(bEnable) // enable OSD
2819 {
2820 if(eOSD == EN_OSD_0)
2821 {
2822 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN, BIT(0), BIT(0));
2823 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN_ALPHA_INV, (bEnable? BIT(7): ~(BIT(7))), BIT(7));
2824 }
2825 else if(eOSD == EN_OSD_1)
2826 {
2827 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, BIT(0), BIT(0));
2828 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, (bEnable? BIT(5): ~(BIT(5))), BIT(5));
2829 }
2830 }
2831 else // disable OSD
2832 {
2833 if(eOSD == EN_OSD_0)
2834 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD_EN, 0x0, BIT(0));
2835 else
2836 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_TVS_OSD1_EN, 0x0, BIT(0));
2837 }
2838
2839 return GOP_SUCCESS;
2840 }
2841
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2842 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2843 {
2844 MS_U16 regval = 0x0;
2845
2846 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2847 // there are only 2 mux, the 3rd gop will be set to 2nd mux(osd1).
2848 if((gopNum != ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8)>>6))) && (gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9)))
2849 {
2850 // if have to overwrite one, overwriting INIT VALUE is better.
2851 if (VE_MUX_INIT_VALUE == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2852 {
2853 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6), GOP_BIT6|GOP_BIT7|GOP_BIT8);
2854 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_0, gopNum);
2855 }
2856 else
2857 {
2858 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2859 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_1, gopNum);
2860 }
2861 }
2862 else if(gopNum != ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2863 {
2864 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2865 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_1, gopNum);
2866 }
2867 else
2868 {
2869 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6) , GOP_BIT6|GOP_BIT7|GOP_BIT8);
2870 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal,bEn, EN_OSD_0, gopNum);
2871 }
2872 /*
2873 MS_U32 u32BankOffSet=0;
2874 _GetBnkOfstByGop(gopNum, &u32BankOffSet);
2875
2876 //Direct to SC1 OP
2877 HAL_GOP_SetIPSel2SC(pGOPHalLocal, MS_DRV_SC1OP_SEL);
2878 HAL_GOP_SetGOPClk(pGOPHalLocal, gopNum, E_DRV_GOP_DST_OP1);
2879 HAL_GOP_GWIN_SetMUX(pGOPHalLocal,gopNum,E_GOP_OP1_MUX);
2880 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
2881 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2882 */
2883 return GOP_SUCCESS;
2884 }
2885
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2886 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2887 {
2888 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2889 MS_U16 u16MVOPMirrorCfg = 0;
2890 MS_U16 u16ScalerMirrorCfg = 0;
2891
2892 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2893 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2894 if(bHorizontal) // Horizontal
2895 {
2896 if(u16MVOPMirrorCfg & GOP_BIT1)
2897 {
2898 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2899 }
2900 else if(u16ScalerMirrorCfg & GOP_BIT12)
2901 {
2902 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2903 }
2904 }
2905 else //vertical
2906 {
2907 if(u16MVOPMirrorCfg & GOP_BIT0)
2908 {
2909 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2910 }
2911 else if(u16ScalerMirrorCfg & GOP_BIT13)
2912 {
2913 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2914 }
2915 }
2916 return enMirrorType;
2917 }
2918
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2919 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2920 {
2921 MS_U32 u32BankOffSet =0;
2922
2923 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2924 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2925 return GOP_SUCCESS;
2926 }
2927
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2928 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2929 {
2930 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2931 MS_U16 u16Val=0;
2932 MS_U16 u16Mux[MAX_GOP_MUX];
2933
2934 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2935 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2936 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2937 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2938 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2939 #if (MAX_GOP_MUX>4)
2940 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2941 #endif
2942 switch(u8GOP)
2943 {
2944 case E_GOP0:
2945 case E_GOP1:
2946 case E_GOP2:
2947 case E_GOP3:
2948 #if (MAX_GOP_MUX>4)
2949 case E_GOP4:
2950 #endif
2951 for(i=0; i<MAX_GOP_MUX; i++)
2952 {
2953 if(u8GOP == u16Mux[i])
2954 {
2955 eGopMux = i;
2956 #if (MAX_GOP_MUX>4)
2957 if(eGopMux == 4)
2958 {
2959 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2960 }
2961 else
2962 #endif
2963 {
2964 FRCMuxOffset = 12 + eGopMux;
2965 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2966 }
2967 }
2968 }
2969 break;
2970 default:
2971 return GOP_FAIL;
2972 break;
2973 }
2974
2975 return GOP_SUCCESS;
2976 }
2977
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2978 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2979 {
2980 return GOP_FUN_NOT_SUPPORTED;
2981 }
2982
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2983 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2984 {
2985 return GOP_FUN_NOT_SUPPORTED;
2986 }
2987
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2988 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2989 {
2990 return GOP_FUN_NOT_SUPPORTED;
2991 }
2992
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2993 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2994 {
2995 MS_U32 u32BankOffSet = 0;
2996 MS_BOOL bInverse = 0xFF;
2997 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
2998
2999 switch (eDstType)
3000 {
3001 case E_DRV_GOP_DST_IP0:
3002 case E_DRV_GOP_DST_IP1:
3003 case E_DRV_GOP_DST_OP1:
3004 case E_DRV_GOP_DST_VE:
3005 bInverse = TRUE;
3006 break;
3007 default:
3008 bInverse = FALSE;
3009 break;
3010 }
3011 if(bInverse == TRUE)
3012 {
3013 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 1<<4, 0x10);
3014 }
3015 else
3016 {
3017 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 0<<4, 0x10);
3018 }
3019 return GOP_SUCCESS;
3020 }
3021
3022 /********************************************************************************/
3023 ///Test Pattern
3024 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)3025 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
3026 {
3027 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
3028 {
3029 return GOP_SUCCESS;
3030 }
3031 else
3032 {
3033 return GOP_FAIL;
3034 }
3035
3036 }
3037
3038
3039 /********************************************************************************/
3040 ///GOP Scaling down (internal)
3041 /********************************************************************************/
3042
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)3043 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
3044 {
3045 return GOP_FUN_NOT_SUPPORTED;
3046 }
3047
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3048 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3049 {
3050 return GOP_FUN_NOT_SUPPORTED;
3051 }
3052
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3053 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3054 {
3055 return GOP_FUN_NOT_SUPPORTED;
3056 }
3057
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)3058 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
3059 {
3060 MS_U32 u32BankOffSet=0;
3061
3062 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3063 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
3064 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
3065 return GOP_SUCCESS;
3066 }
3067
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)3068 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
3069 {
3070 MS_U32 u32BankOffSet=0;
3071 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3072
3073 if (u32GopIdx < MAX_GOP_SUPPORT)
3074 {
3075 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
3076 }
3077 else
3078 {
3079 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3080 *u16Val = 0;
3081 }
3082 return GOP_SUCCESS;
3083 }
3084
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)3085 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
3086 {
3087 MS_U32 u32BankOffSet=0;
3088 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3089
3090 if (u32GopIdx < MAX_GOP_SUPPORT)
3091 {
3092 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
3093 }
3094 else
3095 {
3096 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3097 }
3098 return GOP_SUCCESS;
3099 }
3100
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)3101 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
3102 {
3103 switch(u32PowerState)
3104 {
3105 case E_POWER_SUSPEND:
3106 {
3107 //CLK
3108 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
3109 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
3110 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
3111 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP5CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
3112 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
3113 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
3114
3115 //XC
3116 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
3117 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
3118 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
3119 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
3120 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
3121 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
3122 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
3123 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
3124 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
3125 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
3126 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
3127 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
3128 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
3129 }
3130 break;
3131 case E_POWER_RESUME:
3132 {
3133 //CLK
3134 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
3135 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
3136 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
3137 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP5CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
3138 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
3139 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
3140
3141 //XC
3142 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3143 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3144 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3145 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3146 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3147 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3148 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3149 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3150 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3151 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3152 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3153 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3154 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3155 }
3156 break;
3157 default:
3158 break;
3159 }
3160 return GOP_SUCCESS;
3161 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3162 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3163 {
3164 return GOP_FUN_NOT_SUPPORTED;
3165 }
3166
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3167 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3168 {
3169 MS_U32 u32BankOffSet=0xFFFF;
3170
3171 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3172 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3173
3174 return GOP_SUCCESS;
3175 }
3176
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3177 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3178 {
3179 MS_U32 u32BankOffSet=0xFFFF;
3180 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3181
3182 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3183 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3184
3185 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3186 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3187
3188 return GOP_SUCCESS;
3189 }
3190
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3191 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3192 {
3193 MS_U32 u32BankOffSet=0xFFFF;
3194 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3195
3196 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3197 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3198
3199 return GOP_SUCCESS;
3200 }
3201
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3202 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3203 {
3204 MS_U32 u32BankOffSet=0xFFFF;
3205 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3206
3207 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3208 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3209
3210 return GOP_SUCCESS;
3211 }
3212
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3213 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3214 {
3215 GOP_Result ret = GOP_SUCCESS;
3216 MS_U32 u32BankOffSet=0xFFFF;
3217 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3218 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_HSTR(_GetGwinOffsetInGOP(u8win)), hstart, GOP_REG_WORD_MASK);
3219 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_HEND(_GetGwinOffsetInGOP(u8win)), hend, GOP_REG_WORD_MASK);
3220 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_VSTR(_GetGwinOffsetInGOP(u8win)), vstart, GOP_REG_WORD_MASK);
3221 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_VEND(_GetGwinOffsetInGOP(u8win)), vend, GOP_REG_WORD_MASK);
3222
3223
3224 return ret;
3225 }
3226
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3227 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3228 {
3229 MS_U32 u32BankOffSet=0xFFFF;
3230 MS_U16 mask_shift=0xFF;
3231
3232 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3233
3234 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP] == TRUE)
3235 {
3236 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3237 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3238 }
3239 else
3240 {
3241 switch(u8GOP)
3242 {
3243 case E_GOP0:
3244 mask_shift = GOP_MIU_CLIENT_GOP0;
3245 break;
3246 case E_GOP1:
3247 mask_shift = GOP_MIU_CLIENT_GOP1;
3248 break;
3249 case E_GOP2:
3250 mask_shift = GOP_MIU_CLIENT_GOP2;
3251 break;
3252 case E_GOP3:
3253 mask_shift = GOP_MIU_CLIENT_GOP3;
3254 break;
3255 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3256 mask_shift = GOP_MIU_CLIENT_GOP5;
3257 break;
3258 default:
3259 mask_shift = 0xFF;
3260 MS_CRITICAL_MSG(printf("ERROR gop miu client\n"));
3261 break;
3262 }
3263 if(u8GOP==E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3264 HAL_GOP_Write16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3265 else
3266 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3267 #ifdef GOP_MIU_GROUP2
3268 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3269 #endif
3270 }
3271
3272 return GOP_SUCCESS;
3273 }
3274
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3275 GOP_Result Hal_SetCropWindow(
3276 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3277 MS_U8 u8GOP,
3278 EN_GOP_CROP_CTL crop_mode
3279 )
3280 {
3281 return GOP_SUCCESS;
3282 }
3283
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)3284 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
3285 {
3286 MS_U16 reg_val = 0;
3287
3288 // Note: Kastor XC use hand-shake mode, this register is differ to Kano's
3289 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_USR_INTERLACE, ®_val);
3290 if(reg_val & BIT(1))
3291 *bInterlace = TRUE;
3292 else
3293 *bInterlace = FALSE;
3294 return GOP_SUCCESS;
3295 }
3296
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)3297 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
3298 {
3299 MS_U16 u16regval=0,u16GopMux;
3300 MS_U8 u8mux=0,u8mux_sel=0;
3301
3302 for (u8mux=0; u8mux<MAX_GOP_MUX; u8mux++)
3303 {
3304 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
3305 u8mux_sel = (u16GopMux >> (u8mux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
3306 if (u8mux_sel==GOP_MIXER_MUX)
3307 {
3308 switch(u8mux)
3309 {
3310 case E_GOP_MUX0:
3311 {
3312 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, &u16regval);
3313 if(u16regval&GOP_BIT3)
3314 {
3315 *pbHDREnable = TRUE;
3316 return GOP_SUCCESS;
3317 }
3318 break;
3319 }
3320 case E_GOP_MUX1:
3321 {
3322 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, &u16regval);
3323 if(u16regval&GOP_BIT11)
3324 {
3325 *pbHDREnable = TRUE;
3326 return GOP_SUCCESS;
3327 }
3328 break;
3329 }
3330 case E_GOP_MUX2:
3331 {
3332 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, &u16regval);
3333 if(u16regval&GOP_BIT3)
3334 {
3335 *pbHDREnable = TRUE;
3336 return GOP_SUCCESS;
3337 }
3338 break;
3339 }
3340 case E_GOP_MUX3:
3341 {
3342 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, &u16regval);
3343 if(u16regval&GOP_BIT11)
3344 {
3345 *pbHDREnable = TRUE;
3346 return GOP_SUCCESS;
3347 }
3348 break;
3349 }
3350 case E_GOP_MUX4:
3351 {
3352 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_EX, &u16regval);
3353 if(u16regval&GOP_BIT3)
3354 {
3355 *pbHDREnable = TRUE;
3356 return GOP_SUCCESS;
3357 }
3358 break;
3359 }
3360 default:
3361 break;
3362
3363 }
3364 }
3365 }
3366
3367 *pbHDREnable = FALSE;
3368
3369 return GOP_SUCCESS;
3370 }
3371
3372
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3373 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3374 {
3375 if(u8GOP==0)
3376 {
3377 *u8Core=0;
3378 }
3379 else
3380 {
3381 *u8Core=1;
3382 }
3383 return GOP_SUCCESS;
3384 }
3385
3386 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3387 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3388 {
3389 MS_U16 u16xcSubbank=0;
3390 MS_U32 bank;
3391 MS_U32 direct_addr;
3392
3393 switch (u32addr & 0xFF00)
3394 {
3395 case GOP_REG_BASE:
3396 {
3397 bank = (u32addr & 0xFF0000) >> 8;
3398 #if 0 //for GOP4
3399 if(bank==0xE00)//GOP4: 0x121B00
3400 {
3401 bank=GOP_REG_GOP4_BK_OFFSET;
3402 }
3403 else if(bank==0xF00)//GWIN4: 0x121E00
3404 {
3405 bank=GOP_REG_GOP4_GW_OFFSET;
3406 }
3407 else if(bank==0x1000) //GOP4_ST
3408 {
3409 bank=GOP_REG_GOP4_ST_OFFSET;
3410 }
3411 #endif
3412 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3413
3414 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3415 cmdq_struct[(*number)].destionation_value = u16val;
3416 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3417 cmdq_struct[(*number)].operation = 0x57;
3418 (*number)++;
3419 break;
3420 }
3421 case SC1_REG_BASE:
3422 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3423 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3424
3425 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3426 cmdq_struct[(*number)].destionation_value = u16val;
3427 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3428 cmdq_struct[(*number)].operation = 0x57;
3429 (*number)++;
3430 break;
3431 case GE_REG_BASE:
3432 case CKG_REG_BASE:
3433 case MIU_REG_BASE:
3434 {
3435 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3436 cmdq_struct[(*number)].destionation_value = u16val;
3437 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3438 cmdq_struct[(*number)].operation = 0x57;
3439 (*number)++;
3440 break;
3441 }
3442 #ifdef GOP_MIU_GROUP2
3443 case (MIU2_REG_BASE & 0xFF00):
3444 {
3445 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3446
3447 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3448 cmdq_struct[(*number)].destionation_value = u16val;
3449 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3450 cmdq_struct[(*number)].operation = 0x57;
3451 (*number)++;
3452 break;
3453 }
3454 #endif
3455 default:
3456 {
3457 //Gop lib current do not support this HW ip base
3458 MS_ASSERT(0);
3459 break;
3460 }
3461
3462 }
3463 return GOP_SUCCESS;
3464 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3465 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3466 {
3467 MS_U32 u32BankOffSet=0xFFFF;
3468 MS_U16 u16RegVal1 = 0;
3469 MS_BOOL bCheckValidGop = FALSE;
3470 MS_U8 u8CheckTimeCnt = 0;
3471 MS_U8 u8CurrentCmdGop = 0;
3472
3473 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3474 {
3475 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3476 {
3477 u8CurrentCmdGop = 0;
3478 }
3479 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3480 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3481 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3482 {
3483 bCheckValidGop = FALSE;
3484 }
3485 else
3486 {
3487 bCheckValidGop = TRUE;
3488 break;
3489 }
3490
3491 // if current gop not init, use next gop instead, check order 0->2->1->3
3492 switch (u8CurrentCmdGop)
3493 {
3494 case 0:
3495 u8CurrentCmdGop = 2;
3496 break;
3497 case 1:
3498 u8CurrentCmdGop = 0;
3499 break;
3500 case 2:
3501 u8CurrentCmdGop = 3;
3502 break;
3503 case 3:
3504 u8CurrentCmdGop = 1;
3505 break;
3506 default:
3507 u8CurrentCmdGop = 0;
3508 break;
3509 }
3510 u8CheckTimeCnt++;
3511 }
3512 if (!bCheckValidGop)
3513 {
3514 printf("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3515 }
3516
3517 *u32GopIdx = u8CurrentCmdGop;
3518 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3519 (*number)++;
3520 return GOP_SUCCESS;
3521 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3522 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3523 {
3524 CH_Struct ch_fire;
3525 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3526 MS_U16 u16ret = 0,u16ret1 = 0;
3527 int i = 0;
3528
3529
3530 _GetBnkOfstByGop(0, &u32BankOffSet);
3531 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3532 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3533 #if 0 //for Debug
3534 for(i=0;i<(*number);i++)
3535 {
3536 printf("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3537 }
3538 #endif
3539 ch_fire.Command_Number = *number;
3540 ch_fire.Pointer_To_CAFArray = target;
3541 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3542 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3543 {
3544 Receive_Return_Value = 0;
3545 MDrv_CMDQ_Printf_Crash_Command();
3546 }
3547
3548 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3549 MsOS_DelayTask(1);
3550 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3551 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3552
3553 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3554 timer1 = MsOS_GetSystemTime();
3555 timer2 = MsOS_GetSystemTime();
3556 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3557 {
3558 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3559 MsOS_DelayTask(1);
3560 timer2 = MsOS_GetSystemTime();
3561 }
3562 if(u16ret1 != (u16ret+1))
3563 {
3564 printf("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3565 MDrv_CMDQ_Printf_Crash_Command();
3566 }
3567 return GOP_SUCCESS;
3568 }
3569
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3570 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3571 {
3572 CAF_Struct fire_struct[24];
3573 MS_U32 u32BankOffSet;
3574 MS_U32 number = 0;
3575 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3576 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3577 MS_U32 fireGOP=0;
3578
3579 _GetBnkOfstByGop(gop, &u32BankOffSet);
3580
3581 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3582 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal1);
3583 else
3584 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3585 #ifdef GOP_MIU_GROUP2
3586 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3587 #endif
3588 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3589 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3590
3591 switch(gop)
3592 {
3593 case E_GOP0:
3594 {
3595 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3596 break;
3597 }
3598 case E_GOP1:
3599 {
3600 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3601 break;
3602 }
3603 case E_GOP2:
3604 {
3605 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3606 break;
3607 }
3608 case E_GOP3:
3609 {
3610 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3611 break;
3612 }
3613 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3614 {
3615 u16MiuClient = GOP_MIU_CLIENT_GOP5;
3616 break;
3617 }
3618 default:
3619 {
3620 MS_ASSERT(0);
3621 break;
3622 }
3623 }
3624 if(bMIUSelect[gop] == TRUE)
3625 {
3626 if(u16MIUSelect[gop] == 0)
3627 {
3628 u16RegVal1 &= ~(1<<u16MiuClient);
3629 u16RegVal3 &= ~(1<<u16MiuClient);
3630 }
3631 else if(u16MIUSelect[gop] == 1)
3632 {
3633 u16RegVal1 |= (1<<u16MiuClient);
3634 u16RegVal3 &= ~(1<<u16MiuClient);
3635 }
3636 else if(u16MIUSelect[gop] == 2)
3637 {
3638 u16RegVal1 &= ~(1<<u16MiuClient);
3639 u16RegVal3 |= (1<<u16MiuClient);
3640 }
3641 else if(u16MIUSelect[gop] == 3)
3642 {
3643 u16RegVal1 |= (1<<u16MiuClient);
3644 u16RegVal3 |= (1<<u16MiuClient);
3645 }
3646 bMIUSelect[gop] = FALSE;
3647 }
3648
3649 if(bAFBCMIUSelect[gop] == TRUE)
3650 {
3651 bAFBCMIUSelect[gop] = FALSE;
3652 }
3653 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3654 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3655 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3656 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP5_MIU_GROUP1,u16RegVal1,0xFFFF);
3657 else
3658 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3659
3660 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
3661 {
3662 if(bAFBCMIUSelect[gop] == TRUE)
3663 {
3664 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3665 bAFBCMIUSelect[gop] = FALSE;
3666 }
3667 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3668 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
3669 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
3670 }
3671 #ifdef GOP_MIU_GROUP2
3672 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3673 #endif
3674
3675 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3676 return GOP_SUCCESS;
3677 }
3678
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)3679 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3680 {
3681 CAF_Struct fire_struct[24];
3682 MS_U32 u32BankOffSet=0;
3683 MS_U32 number = 0;
3684 MS_U8 gop=0;
3685 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3686 MS_U16 u16RegMiu=0,u16RegCoreEna=0;
3687 MS_U8 u8Core=0;
3688 MS_U32 fireGOP=0;
3689 MS_BOOL bCoreTrig[AFBC_CORE_COUNT];
3690 MS_BOOL bCoreMiu[AFBC_CORE_COUNT];
3691 MS_U8 i=0;
3692
3693 for(i=0;i<AFBC_CORE_COUNT;i++)
3694 {
3695 bCoreTrig[i]=FALSE;
3696 }
3697
3698 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3699 HAL_GOP_Read16Reg(pGOPHalLocal, GOP5_MIU_GROUP1, &u16RegVal1);
3700 else
3701 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3702 #ifdef GOP_MIU_GROUP2
3703 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3704 #endif
3705 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3706
3707 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3708 {
3709 switch(gop)
3710 {
3711 case E_GOP0:
3712 {
3713 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3714 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP0, &u8Core);
3715 bCoreTrig[u8Core]=TRUE;
3716 break;
3717 }
3718 case E_GOP1:
3719 {
3720 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3721 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP1, &u8Core);
3722 bCoreTrig[u8Core]=TRUE;
3723 break;
3724 }
3725 case E_GOP2:
3726 {
3727 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3728 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP2, &u8Core);
3729 bCoreTrig[u8Core]=TRUE;
3730 break;
3731 }
3732 case E_GOP3:
3733 {
3734 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3735 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP3, &u8Core);
3736 bCoreTrig[u8Core]=TRUE;
3737 break;
3738 }
3739 case E_GOP4: // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3740 {
3741 u16MiuClient = GOP_MIU_CLIENT_GOP5;
3742 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP4, &u8Core);
3743 bCoreTrig[u8Core]=TRUE;
3744 break;
3745 }
3746 default:
3747 {
3748 continue;
3749 }
3750 }
3751 if( ( u16GopMask & (1<<gop) ) )
3752 {
3753 _GetBnkOfstByGop(gop, &u32BankOffSet);
3754 if(bMIUSelect[gop] == TRUE)
3755 {
3756 if(u16MIUSelect[gop] == 0)
3757 {
3758 u16RegVal1 &= ~(1<<u16MiuClient);
3759 u16RegVal3 &= ~(1<<u16MiuClient);
3760 }
3761 else if(u16MIUSelect[gop] == 1)
3762 {
3763 u16RegVal1 |= (1<<u16MiuClient);
3764 u16RegVal3 &= ~(1<<u16MiuClient);
3765 }
3766 else if(u16MIUSelect[gop] == 2)
3767 {
3768 u16RegVal1 &= ~(1<<u16MiuClient);
3769 u16RegVal3 |= (1<<u16MiuClient);
3770 }
3771 else if(u16MIUSelect[gop] == 3)
3772 {
3773 u16RegVal1 |= (1<<u16MiuClient);
3774 u16RegVal3 |= (1<<u16MiuClient);
3775 }
3776 bMIUSelect[gop] = FALSE;
3777 }
3778 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3779 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3780 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3781 }
3782
3783 if(bAFBCMIUSelect[gop] == TRUE)
3784 {
3785 HAL_GOP_AFBC_GetCore(pGOPHalLocal, gop, &u8Core);
3786 bCoreMiu[gop]=TRUE;
3787 bAFBCMIUSelect[gop] = FALSE;
3788 }
3789 }
3790
3791 for(i=0;i<AFBC_CORE_COUNT;i++)
3792 {
3793 if(g_GopChipPro.bAFBC_Merge_GOP_Trig == FALSE)
3794 {
3795 if(bCoreTrig[i]==TRUE)
3796 {
3797 if((g_GopChipPro.bAFBCMIUSelDoubleBuffer == FALSE)&&(bCoreMiu[i]==TRUE))
3798 {
3799 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3800 }
3801 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
3802 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
3803 }
3804 }
3805 }
3806
3807 if(gop == E_GOP4) // K6 : GOP0~3 and GOP5, NO GOP4. Mapping E_GOP4 to GOP 5 reg
3808 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP5_MIU_GROUP1,u16RegVal1,0xFFFF);
3809 else
3810 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3811 #ifdef GOP_MIU_GROUP2
3812 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3813 #endif
3814 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3815 return GOP_SUCCESS;
3816 }
3817 #endif
3818