1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_GOP_H_ 96 #define _REG_GOP_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 102 103 //------------------------------------------------------------------------------------------------- 104 // Macro and Define 105 //------------------------------------------------------------------------------------------------- 106 //---------------------------------------------------------------------------- 107 // HW IP Reg Base Adr 108 //---------------------------------------------------------------------------- 109 #define GOP_REG_BASE 0x1F00UL 110 #define GE_REG_BASE 0x2800UL 111 #define SC1_REG_BASE 0x2F00UL 112 #define CKG_REG_BASE 0x0B00UL 113 #define MIU0_REG_BASE 0x0600UL 114 #define MIU_REG_BASE 0x1200UL 115 #define MIU2_REG_BASE 0x162000 116 #define MVOP_REG_BASE 0x1400UL 117 #define VE_REG_BASE 0x3B00UL 118 #define SC1_DIRREG_BASE 0x130000UL 119 120 //---------------------------------------------------------------------------- 121 // Scaler Reg 122 //---------------------------------------------------------------------------- 123 #define XC_REG(bk, reg) (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 124 125 #define REG_SC_BK00_00_L XC_REG(0x00, 0x00) 126 #define REG_SC_BK00_05_L XC_REG(0x00, 0x05) 127 #define REG_SC_BK00_06_L XC_REG(0x00, 0x06) 128 #define REG_SC_BK01_02_L XC_REG(0x01, 0x02) 129 #define REG_SC_BK01_05_L XC_REG(0x01, 0x05) 130 #define REG_SC_BK01_21_L XC_REG(0x01, 0x21) 131 #define REG_SC_BK02_5F_L XC_REG(0x02, 0x5F) 132 #define REG_SC_BK0F_2B_L XC_REG(0x0F, 0x2B) 133 #define REG_SC_BK10_23_L XC_REG(0x10, 0x23) 134 #define REG_SC_BK10_5B_L XC_REG(0x10, 0x5B) 135 #define REG_SC_BK12_03_L XC_REG(0x12, 0x03) 136 #define REG_SC_BK2F_27_L XC_REG(0x2F, 0x27) 137 #define REG_SC_BK2F_36_L XC_REG(0x2F, 0x36) 138 #define REG_SC_BK2F_37_L XC_REG(0x2F, 0x37) 139 #define REG_SC_BK2F_38_L XC_REG(0x2F, 0x38) 140 #define REG_SC_BK2F_3A_L XC_REG(0x2F, 0x3A) 141 #define REG_SC_BK2F_3B_L XC_REG(0x2F, 0x3B) 142 #define REG_SC_BK2F_3C_L XC_REG(0x2F, 0x3C) 143 #define REG_SC_BK37_22_L XC_REG(0x37, 0x22) 144 #define REG_SC_BK37_24_L XC_REG(0x37, 0x24) 145 #define REG_SC_BK37_28_L XC_REG(0x37, 0x28) 146 #define REG_SC_BK3D_0D_L XC_REG(0x3D, 0x0D) 147 #define REG_SC_BK40_22_L XC_REG(0x40, 0x22) 148 #define REG_SC_BK40_23_L XC_REG(0x40, 0x23) 149 #define REG_SC_BK40_24_L XC_REG(0x40, 0x24) 150 #define REG_SC_BK40_25_L XC_REG(0x40, 0x25) 151 #define REG_SC_BK7F_10_L XC_REG(0x7F, 0x10) 152 #define REG_SC_BK7F_11_L XC_REG(0x7F, 0x11) 153 154 #define REG_SC1_BK00_05_L XC_REG(0x80+0x00, 0x05) 155 #define REG_SC1_BK00_06_L XC_REG(0x80+0x00, 0x06) 156 #define REG_SC1_BK10_23_L XC_REG(0x80+0x10, 0x23) 157 158 #define GOP_SC_BANKSEL REG_SC_BK00_00_L 159 #define GOP_SC_CHANNELSYNC REG_SC_BK00_05_L 160 #define GOP_SC_GOPEN REG_SC_BK00_06_L 161 #define GOP_SC_IP_SYNC REG_SC_BK01_02_L 162 #define GOP_SC_IP_MAIN_HSTART REG_SC_BK01_05_L 163 #define GOP_SC_IP_MAIN_USR_INTERLACE REG_SC_BK01_21_L 164 #define GOP_SC_IP2GOP_SRCSEL REG_SC_BK02_5F_L 165 #define GOP_SC_OSD_CHECK_ALPHA REG_SC_BK0F_2B_L 166 #define GOP_SC_VOPNBL REG_SC_BK10_23_L 167 #define GOP_SC_ALPHAMODE REG_SC_BK10_5B_L 168 #define GOP_SC_GOPENMODE1 REG_SC_BK10_5B_L 169 #define GOP_SC_MIRRORCFG REG_SC_BK12_03_L 170 #define GOP_SC_BLEND0_GOP_SWITCH REG_SC_BK2F_27_L 171 #define GOP_SC_ZORDER REG_SC_BK2F_36_L 172 #define GOP_SC_VOP2BLENDING_L REG_SC_BK2F_37_L 173 #define GOP_SC_VOP2BLENDING_H REG_SC_BK2F_38_L 174 #define GOP_SC_VOPVTK REG_SC_BK2F_3A_L 175 #define GOP_SC_VOPVTK_L REG_SC_BK2F_3B_L 176 #define GOP_SC_VOPVTK_H REG_SC_BK2F_3C_L 177 #define GOP_SC_OCMIXER REG_SC_BK37_22_L 178 #define GOP_SC_OCMISC REG_SC_BK37_24_L 179 #define GOP_SC_OCALPHA REG_SC_BK37_28_L 180 #define GOP_SC_GOPSC_SRAM_CTRL REG_SC_BK3D_0D_L 181 #define GOP_SC_FRC_LAYER1_L_EN REG_SC_BK40_22_L 182 #define GOP_SC_FRC_LAYER1_R_EN REG_SC_BK40_23_L 183 #define GOP_SC_FRC_LAYER2_L_EN REG_SC_BK40_24_L 184 #define GOP_SC_FRC_LAYER2_R_EN REG_SC_BK40_25_L 185 #define GOP_SC_MIU_SEL REG_SC_BK7F_10_L 186 #define GOP_SC_MIU_IP_SEL REG_SC_BK7F_11_L 187 #define GOP_SC_ZORDER_CTRLER REG_SC_BK2F_36_L 188 189 #define GOP_SC1_CHANNELSYNC REG_SC1_BK00_05_L 190 #define GOP_SC1_GOPEN REG_SC1_BK00_06_L 191 #define GOP_SC1_VOPNBL REG_SC1_BK10_23_L 192 //---------------------------------------------------------------------------- 193 // MVOP Reg 194 //---------------------------------------------------------------------------- 195 #define GOP_MVOP_MIRRORCFG (MVOP_REG_BASE+0x76) 196 197 //---------------------------------------------------------------------------- 198 // VE Reg 199 //---------------------------------------------------------------------------- 200 #define GOP_VE_TVS_CTRL 0x00 201 #define GOP_VE_TVS_OSD_EN 0x55 202 #define GOP_VE_TVS_OSD1_EN 0x60 203 #define GOP_VE_TVE_SWRST 0x07 204 205 //---------------------------------------------------------------------------- 206 // GE Reg 207 //---------------------------------------------------------------------------- 208 #define GOP_GE_FMT_BLT (GE_REG_BASE+(0x01*2)) 209 #define GOP_GE_EN_CMDQ BIT(0) 210 #define GOP_GE_EN_VCMDQ BIT(1) 211 212 #define GOP_GE_VQ_FIFO_STATUS_L (GE_REG_BASE+(0x04*2)) 213 #define GOP_GE_VQ_FIFO_STATUS_H (GE_REG_BASE+(0x05*2)) 214 215 #define GOP_GE_STATUS (GE_REG_BASE+(0x07*2)) 216 #define GOP_GE_BUSY BIT(0) 217 #define GOP_GE_CMDQ1_STATUS BMASK(7:3) 218 #define GOP_GE_CMDQ2_STATUS BMASK(15:11) 219 220 #define GOP_GE_TAG (GE_REG_BASE+(0x2C*2)) 221 222 #define GOP_GE_DBBASE0 (GE_REG_BASE+(0x26*2)) 223 #define GOP_GE_DBBASE1 (GE_REG_BASE+(0x27*2)) 224 #define GOP_GE_DBPIT (GE_REG_BASE+(0x33*2)) 225 #define GOP_GE_FBFMT (GE_REG_BASE+(0x34*2)) 226 #define GOP_GE_SRCW (GE_REG_BASE+(0x6e*2)) 227 #define GOP_GE_SRCH (GE_REG_BASE+(0x6f*2)) 228 229 230 //---------------------------------------------------------------------------- 231 // ChipTop Reg 232 //---------------------------------------------------------------------------- 233 /* GOP0 and GOP1 CLK */ 234 #define GOP_GOPCLK (CKG_REG_BASE+(0x40<<1)) 235 #define CKG_GOPG0_DISABLE_CLK ~(GOP_BIT0) 236 #define CKG_GOPG0_ODCLK (0<<2) 237 #define CKG_GOPG0_OD1CLK (2<<2) 238 #define CKG_GOPG0_IDCLK2 (6 << 2) 239 #define CKG_GOPG0_IDCLK1 (7 << 2) 240 #define CKG_GOPG0_OCC_FRCCLK (3 << 2) 241 #define CKG_GOPG0_MIXERCLK_VE (4 << 2) 242 #define CKG_GOPG0_BYPASS_FRCCLK (5 << 2) 243 #define CKG_GOPG0_FCLK (8 << 2) 244 #define CKG_GOPG0_MVOP (1 << 2) 245 #define CKG_GOPG0_DISABLE_CLK_MASK (GOP_BIT0) 246 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 247 248 #define CKG_GOPG1_DISABLE_CLK ~(GOP_BIT8) 249 #define CKG_GOPG1_ODCLK (0 << 10) 250 #define CKG_GOPG1_OD1CLK (2 << 10) 251 #define CKG_GOPG1_IDCLK2 (6 << 10) 252 #define CKG_GOPG1_IDCLK1 (7 << 10) 253 #define CKG_GOPG1_OCC_FRCCLK (3 << 10) 254 #define CKG_GOPG1_MIXERCLK_VE (4 << 10) 255 #define CKG_GOPG1_BYPASS_FRCCLK (5 << 10) 256 #define CKG_GOPG1_FCLK (8 << 10) 257 #define CKG_GOPG1_MVOP (1 << 10) 258 #define CKG_GOPG1_DISABLE_CLK_MASK (GOP_BIT8) 259 #define CKG_GOPG1_MASK (GOP_BIT13 | GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 260 261 #define CKG_GOPG0_SCALING (CKG_REG_BASE+0x88) 262 #define CKG_GOPG0_MG (CKG_REG_BASE+0xFE) 263 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2) 264 #define CKG_GOPG2_MG_MASK (GOP_BIT7 | GOP_BIT6) 265 266 #define CKG_GOPMIXER_CLK (CKG_REG_BASE+0x82) 267 #define CKG_GOPMIXER_ODCLK (4<<2) 268 #define CKG_GOPMIXER_VECLK (6<<2) 269 #define CKG_GOPMIXER_MASK (GOP_BIT4|GOP_BIT3 | GOP_BIT2) 270 271 /* GOP2 and GOPDWIN CLK */ 272 #define GOP_GOP2CLK (CKG_REG_BASE+(0x42<<1)) 273 #define CKG_GOPG2_DISABLE_CLK ~(GOP_BIT0) 274 #define CKG_GOPG2_ODCLK (0 << 2) 275 #define CKG_GOPG2_OD1CLK (2 << 2) 276 #define CKG_GOPG2_IDCLK2 (6 << 2) 277 #define CKG_GOPG2_IDCLK1 (7 << 2) 278 #define CKG_GOPG2_OCC_FRCCLK (3 << 2) 279 #define CKG_GOPG2_MIXERCLK_VE (4 << 2) 280 #define CKG_GOPG2_BYPASS_FRCCLK (5 << 2) 281 #define CKG_GOPG2_FCLK (8 << 2) 282 #define CKG_GOPG2_MVOP (7 << 2) 283 #define CKG_GOPG2_DISABLE_CLK_MASK (GOP_BIT0) 284 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 285 286 #define CKG_GOPD_CLK_IDCLK2 (0 << 10) 287 #define CKG_GOPD_CLK_ODCLK (1 << 10) 288 #define CKG_GOPD_CLK_DC0CLK (2 << 10) 289 #define CKG_GOPD_CLK_SUBDC0CLK (3 << 10) 290 #define CKG_GOPD_CLK_MIXERCLK_VE (4 << 10) 291 #define CKG_GOPD_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 292 293 294 /* GOP3 CLK*/ 295 #define GOP_GOP3CLK (CKG_REG_BASE+(0x42<<1)) 296 #define CKG_GOPG3_ODCLK (0<<10) 297 #define CKG_GOPG3_OD1CLK (2<<10) 298 #define CKG_GOPG3_IDCLK2 (6 << 10) 299 #define CKG_GOPG3_IDCLK1 (7 << 10) 300 #define CKG_GOPG3_OCC_FRCCLK (3 << 10) 301 #define CKG_GOPG3_MIXERCLK_VE (4 << 10) 302 #define CKG_GOPG3_BYPASS_FRCCLK (5 << 10) 303 #define CKG_GOPG3_FCLK (8 << 10) 304 #define CKG_GOPG3_MVOP (7 << 10) 305 #define CKG_GOPG3_DISABLE_CLK_MASK (GOP_BIT8) 306 #define CKG_GOPG3_MASK (GOP_BIT13 | GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 307 #define CKG_GOPD_DISABLE_CLK ~(GOP_BIT8) 308 309 310 /* GOP4 CLK*/ 311 #define GOP_GOP4CLK (CKG_REG_BASE+(0x7E<<1)) 312 #define CKG_GOPG4_ODCLK (0 << 10) 313 #define CKG_GOPG4_OD1CLK (2 << 10) 314 #define CKG_GOPG4_IDCLK2 (6 << 10) 315 #define CKG_GOPG4_IDCLK1 (7 << 10) 316 #define CKG_GOPG4_OCC_FRCCLK (3 << 10) 317 #define CKG_GOPG4_MIXERCLK_VE (4 << 10) 318 #define CKG_GOPG4_BYPASS_FRCCLK (5 << 10) 319 #define CKG_GOPG4_FCLK (8 << 10) 320 #define CKG_GOPG4_MVOP (7 << 10) 321 #define CKG_GOPG4_DISABLE_CLK_MASK (GOP_BIT8) 322 #define CKG_GOPG4_MASK (GOP_BIT13 |GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 323 324 325 /* SRAM CLK */ 326 #define GOP_SRAMCLK (CKG_REG_BASE+(0x43<<1)) 327 #define CKG_SRAM0_DISABLE_CLK (GOP_BIT0) 328 #define CKG_SRAM1_DISABLE_CLK (GOP_BIT2) 329 #define CKG_SRAM0_MASK (GOP_BIT0|GOP_BIT1) 330 #define CKG_SRAM1_MASK (GOP_BIT2|GOP_BIT3) 331 332 /* LINE BUFFER SRAM CLK */ 333 #define GOP_LB_SRAMCLK (CKG_REG_BASE+(0x45<<1)) 334 #define CKG_LB_SRAM1_DISABLE_CLK (GOP_BIT0) /*GOP1*/ 335 #define CKG_LB_SRAM2_DISABLE_CLK (GOP_BIT4) /*GOP2*/ 336 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3) 337 #define CKG_LB_SRAM2_MASK (GOP_BIT6|GOP_BIT7) 338 339 /*AFBC CLK*/ 340 #define GOP_AFBCCLK (CKG_REG_BASE+(0x5F<<1)) 341 #define CKG_AFBCCLK_DISABLE_CLK (GOP_BIT0) 342 #define CKG_AFBCCLK_216 (0 << 2) 343 #define CKG_AFBCCLK_432 (1 << 2) 344 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3) 345 346 //---------------------------------------------------------------------------- 347 // MIU Reg 348 //---------------------------------------------------------------------------- 349 #define GOP_CLIENT_REG 0x7D 350 #define GOP_MIU_GROUP (MIU0_REG_BASE+(GOP_CLIENT_REG*2)) 351 #define GOP_MIU_GROUP1 (MIU_REG_BASE+(GOP_CLIENT_REG*2)) 352 353 /*Define each gop miu clint bit*/ 354 #define GOP_MIU_CLIENT_DWIN 0xFF 355 #define GOP_MIU_CLIENT_GOP0 0x0 356 #define GOP_MIU_CLIENT_GOP1 0x1 357 #define GOP_MIU_CLIENT_GOP2 0x2 358 #define GOP_MIU_CLIENT_GOP3 0x3 359 #define GOP_MIU_CLIENT_GOP4 0x4 360 #define GOP_MIU_CLIENT_GOP5 0xff 361 362 //---------------------------------------------------------------------------- 363 // GOP Reg 364 //---------------------------------------------------------------------------- 365 #define GOP_REG(bk, reg) (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 366 #define __GOP_REG(reg) (GOP_REG_BASE+(reg) * 2) 367 #define GOP_REG_DIRECT_BASE (0x120200) 368 #define GOP_REG_GOP4_BK_OFFSET 0x1900 369 #define GOP_REG_GOP4_GW_OFFSET 0x1C00 370 #define GOP_REG_GOP4_ST_OFFSET 0x1D00 371 372 #define GOP_REG_VAL(x) (1<<x) 373 374 //MUX Setting 375 #define GOP_MUX_SHIFT 0x3 376 #define GOP_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 377 #define GOP_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 378 #define GOP_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 379 #define GOP_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 380 #define GOP_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 381 #define GOP_MUX4_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*4)) 382 #define GOP_MUX4_SHIFT 1<<14 383 384 //Priority Setting 385 #define GOP_REGPRI_MASK BMASK(1:0) 386 #define GWIN0_PRI_SHIFT 0 387 #define GWIN0_PRI_MASK (GOP_REGPRI_MASK<<GWIN0_PRI_SHIFT) 388 #define GWIN1_PRI_SHIFT 4 389 #define GWIN1_PRI_MASK (GOP_REGPRI_MASK<<GWIN1_PRI_SHIFT) 390 #define GWIN2_PRI_SHIFT 8 391 #define GWIN2_PRI_MASK (GOP_REGPRI_MASK<<GWIN2_PRI_SHIFT) 392 #define GWIN3_PRI_SHIFT 12 393 #define GWIN3_PRI_MASK (GOP_REGPRI_MASK<<GWIN3_PRI_SHIFT) 394 395 //IP and VOP MUX Setting 396 #define GOP_IP_MAIN_MUX_SHIFT 0 397 #define GOP_IP_MAIN_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_MAIN_MUX_SHIFT 398 #define GOP_IP_SUB_MUX_SHIFT 3 399 #define GOP_IP_SUB_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_SUB_MUX_SHIFT 400 #define GOP_IP_VOP0_MUX_SHIFT 6 401 #define GOP_IP_VOP0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP0_MUX_SHIFT 402 #define GOP_IP_VOP1_MUX_SHIFT 9 403 #define GOP_IP_VOP1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP1_MUX_SHIFT 404 405 406 //IP and VOP MUX Setting 407 #define GOP_Mix_MUX0_SHIFT 0 408 #define GOP_Mix_MUX0_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX0_SHIFT 409 #define GOP_Mix_MUX1_SHIFT 3 410 #define GOP_Mix_MUX1_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX1_SHIFT 411 #define GOP_VE0_MUX_SHIFT 6 412 #define GOP_VE0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE0_MUX_SHIFT 413 #define GOP_VE1_MUX_SHIFT 9 414 #define GOP_VE1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE1_MUX_SHIFT 415 416 417 //4k2k FRC MUX Setting 418 #define GOP_FRC_MUX_SHIFT 0x3 419 #define GOP_FRC_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 420 #define GOP_FRC_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 421 #define GOP_FRC_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 422 #define GOP_FRC_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 423 #define GOP_FRC_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 424 425 // for gwin color format mask 426 #define GOP_REG_COLORTYPE_MASK BMASK(4:0) 427 #define GOP_REG_COLORTYPE_SHIFT 4 428 429 //DIP Setting 430 #define GOP_DIP_MUX_SHIFT 12 431 #define GOP_DIP_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_DIP_MUX_SHIFT 432 433 #define GOP_BANK_OFFSET 0x3 434 #define GOP_4G_OFST 0x0 435 #define GOP_2G_OFST (0x1*GOP_BANK_OFFSET) 436 #define GOP_1G_OFST (0x2*GOP_BANK_OFFSET) 437 #define GOP_1GX_OFST (0x3*GOP_BANK_OFFSET) 438 #define GOP_DW_OFST (0x4*GOP_BANK_OFFSET) 439 #define GOP_AFBC_OFST 0xE 440 #define GOP_MIXER_OFST 0xD 441 #define GOP_1GS0_OFST 0xE 442 #define GOP_1GS1_OFST 0x11 443 444 #define GOP_OFFSET_WR 8 445 #define GOP_VAL_WR GOP_REG_VAL(GOP_OFFSET_WR) 446 #define GOP_OFFSET_FWR 9 447 #define GOP_VAL_FWR GOP_REG_VAL(GOP_OFFSET_FWR) 448 #define GOP_OFFSET_FCLR 11 449 #define GOP_VAL_FCL GOP_REG_VAL(GOP_OFFSET_FCLR) 450 #define GOP4G_OFFSET_WR_ACK 12 451 #define GOP4G_VAL_WR_ACK GOP_REG_VAL(GOP4G_OFFSET_WR_ACK) 452 #define GOP2G_OFFSET_WR_ACK 13 453 #define GOP2G_VAL_WR_ACK GOP_REG_VAL(GOP2G_OFFSET_WR_ACK) 454 #define GOPD_OFFSET_WR_ACK 14 455 #define GOPD_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 456 #define GOP1G_OFFSET_WR_ACK 15 457 #define GOP1G_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 458 #define GOP_VAL_ACK(x) GOP_REG_VAL(GOP4G_OFFSET_WR_ACK+x) 459 460 #define GOP_4G_CTRL0 GOP_REG(GOP_4G_OFST, 0x00) 461 #define GOP_4G_CTRL1 GOP_REG(GOP_4G_OFST, 0x01) 462 #define GOP_4G_RATE GOP_REG(GOP_4G_OFST, 0x02) 463 #define GOP_4G_PALDATA_L GOP_REG(GOP_4G_OFST, 0x03) 464 #define GOP_4G_PALDATA_H GOP_REG(GOP_4G_OFST, 0x04) 465 #define GOP_4G_PALCTRL GOP_REG(GOP_4G_OFST, 0x05) 466 #define GOP_4G_REGDMA_END GOP_REG(GOP_4G_OFST, 0x06) 467 #define GOP_4G_REGDMA_STR GOP_REG(GOP_4G_OFST, 0x07) 468 #define GOP_4G_INT GOP_REG(GOP_4G_OFST, 0x08) 469 #define GOP_4G_HWSTATE GOP_REG(GOP_4G_OFST, 0x09) 470 #define GOP_4G_SVM_HSTR GOP_REG(GOP_4G_OFST, 0x0a) 471 #define GOP_4G_SVM_HEND GOP_REG(GOP_4G_OFST, 0x0b) 472 #define GOP_4G_SVM_VSTR GOP_REG(GOP_4G_OFST, 0x0c) 473 #define GOP_4G_SVM_VEND GOP_REG(GOP_4G_OFST, 0x0d) 474 #define GOP_4G_RDMA_HT GOP_REG(GOP_4G_OFST, 0x0e) 475 #define GOP_4G_HS_PIPE GOP_REG(GOP_4G_OFST, 0x0f) 476 #define GOP_4G_SLOW GOP_REG(GOP_4G_OFST, 0x10) 477 #define GOP_4G_BRI GOP_REG(GOP_4G_OFST, 0x11) 478 #define GOP_4G_CON GOP_REG(GOP_4G_OFST, 0x12) 479 #define GOP_4G_BW GOP_REG(GOP_4G_OFST, 0x19) 480 #define GOP_4G_H121 GOP_REG(GOP_4G_OFST, 0x1B) 481 #define GOP_4G_NEW_BW GOP_REG(GOP_4G_OFST, 0x1C) 482 #define GOP_4G_SRAM_BORROW GOP_REG(GOP_4G_OFST, 0x1D) 483 #define GOP_4G_3D_MIDDLE GOP_REG(GOP_4G_OFST, 0x1E) 484 #define GOP_4G_MIU_SEL GOP_REG(GOP_4G_OFST, 0x1F) 485 #define GOP_4G_PRI0 GOP_REG(GOP_4G_OFST, 0x20) 486 #define GOP_4G_BOT_HS GOP_REG(GOP_4G_OFST, 0x23) 487 #define GOP_4G_TRSCLR_L GOP_REG(GOP_4G_OFST, 0x24) 488 #define GOP_4G_TRSCLR_H GOP_REG(GOP_4G_OFST, 0x25) 489 #define GOP_4G_TRSCLR_TUV_L GOP_REG(GOP_4G_OFST, 0x26) 490 #define GOP_4G_TRSCLR_TUV_H GOP_REG(GOP_4G_OFST, 0x27) 491 #define GOP_4G_YUV_SWAP GOP_REG(GOP_4G_OFST, 0x28) 492 #define GOP_4G_STRCH_HSZ GOP_REG(GOP_4G_OFST, 0x30) 493 #define GOP_4G_STRCH_VSZ GOP_REG(GOP_4G_OFST, 0x31) 494 #define GOP_4G_STRCH_HSTR GOP_REG(GOP_4G_OFST, 0x32) 495 #define GOP_4G_STRCH_VSTR GOP_REG(GOP_4G_OFST, 0x34) 496 #define GOP_4G_HSTRCH GOP_REG(GOP_4G_OFST, 0x35) 497 #define GOP_4G_VSTRCH GOP_REG(GOP_4G_OFST, 0x36) 498 #define GOP_4G_HSTRCH_INI GOP_REG(GOP_4G_OFST, 0x38) 499 #define GOP_4G_VSTRCH_INI GOP_REG(GOP_4G_OFST, 0x39) 500 #define GOP_4G_HVSTRCHMD GOP_REG(GOP_4G_OFST, 0x3a) 501 #define GOP_4G_OLDADDR GOP_REG(GOP_4G_OFST, 0x3b) 502 #define GOP_4G_MULTI_ALPHA GOP_REG(GOP_4G_OFST, 0x3c) 503 #define GOP_4G_TWO_LINEBUFFER GOP_4G_MULTI_ALPHA 504 #define GOP_4G_HW_USAGE GOP_REG(GOP_4G_OFST, 0x40) 505 #define GOP_4G_BANK_FWR GOP_REG(GOP_4G_OFST, 0x50) 506 #define GOP_4G_BANK_HVAILDSIZE GOP_REG(GOP_4G_OFST, 0x52) 507 #define GOP_4G_BANK_VVAILDSIZE GOP_REG(GOP_4G_OFST, 0x53) 508 #define GOP_4G_SCALING_H_OUTPUTSIZE GOP_REG(GOP_4G_OFST, 0x56) 509 #define GOP_4G_SCALING_HRATIO_L GOP_REG(GOP_4G_OFST, 0x59) //GOP scaling down ratio dst / out * 2^20 510 #define GOP_4G_SCALING_HRATIO_H GOP_REG(GOP_4G_OFST, 0x5A) 511 #define GOP_4G_SCALING_CFG GOP_REG(GOP_4G_OFST, 0x5B) 512 #define GOP_4G_SCALING_VRATIO_L GOP_REG(GOP_4G_OFST, 0x5C) //GOP scaling down ratio dst / out * 2^20 513 #define GOP_4G_SCALING_VRATIO_H GOP_REG(GOP_4G_OFST, 0x5D) 514 515 516 #define GOP_4G_RBLK0_VOFFL GOP_REG(GOP_4G_OFST, 0x60) 517 #define GOP_4G_RBLK0_VOFFH GOP_REG(GOP_4G_OFST, 0x61) 518 #define GOP_4G_RBLK1_VOFFL GOP_REG(GOP_4G_OFST, 0x62) 519 #define GOP_4G_RBLK1_VOFFH GOP_REG(GOP_4G_OFST, 0x63) 520 #define GOP_4G_RBLK2_VOFFL GOP_REG(GOP_4G_OFST, 0x64) 521 #define GOP_4G_RBLK2_VOFFH GOP_REG(GOP_4G_OFST, 0x65) 522 #define GOP_4G_RBLK3_VOFFL GOP_REG(GOP_4G_OFST, 0x66) 523 #define GOP_4G_RBLK3_VOFFH GOP_REG(GOP_4G_OFST, 0x67) 524 #define GOP_4G_GOP_INTERNAL_ZORDER GOP_REG(GOP_4G_OFST, 0x6A) 525 #define GOP_4G_GOP_INTERNAL_ZORDER_TRIG GOP_REG(GOP_4G_OFST, 0x6B) 526 #define GOP_4G_RBLK0_HOFF GOP_REG(GOP_4G_OFST, 0x70) 527 #define GOP_4G_RBLK1_HOFF GOP_REG(GOP_4G_OFST, 0x71) 528 #define GOP_4G_RBLK2_HOFF GOP_REG(GOP_4G_OFST, 0x72) 529 #define GOP_4G_RBLK3_HOFF GOP_REG(GOP_4G_OFST, 0x73) 530 #define GOP_4G_REGDMA_EN GOP_REG(GOP_4G_OFST, 0x78) 531 #define GOP_MUX_IPVOP __GOP_REG(0x77) 532 #define GOP_MUX_SC1 __GOP_REG(0x7A) 533 #define GOP_MUX4_MIX_VE __GOP_REG(0x7B) 534 #define GOP_BAK_SEL_EX __GOP_REG(0x7C) 535 #define GOP_MUX_4K2K __GOP_REG(0x7D) 536 #define GOP_MUX __GOP_REG(0x7e) 537 #define GOP_BAK_SEL __GOP_REG(0x7f) 538 539 #define GOP_4G_GWIN0_CTRL(id) GOP_REG(GOP_4G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP0_GWIN))) 540 #define GOP_4G_DRAM_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP0_GWIN))) 541 #define GOP_4G_DRAM_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP0_GWIN))) 542 #define GOP_4G_DEL_PIXEL(id) GOP_REG(GOP_4G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 543 #define GOP_4G_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP0_GWIN))) 544 #define GOP_4G_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP0_GWIN))) 545 #define GOP_4G_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP0_GWIN))) 546 #define GOP_4G_GWIN_MIDDLE(id) GOP_REG(GOP_4G_OFST+1, 0x07 + (0x20*((id)%MAX_GOP0_GWIN))) 547 #define GOP_4G_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP0_GWIN))) 548 #define GOP_4G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_4G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP0_GWIN))) 549 #define GOP_4G_GWIN_ALPHA01(id) GOP_REG(GOP_4G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP0_GWIN))) 550 #define GOP_4G_DRAM_VSTR_L(id) GOP_REG(GOP_4G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP0_GWIN))) 551 #define GOP_4G_DRAM_VSTR_H(id) GOP_REG(GOP_4G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP0_GWIN))) 552 #define GOP_4G_DRAM_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x0E + (0x20*((id)%MAX_GOP0_GWIN))) 553 #define GOP_4G_DRAM_RBLK_SIZE_L(id) GOP_REG(GOP_4G_OFST+1, 0x10 + (0x20*((id)%MAX_GOP0_GWIN))) 554 #define GOP_4G_DRAM_RBLK_SIZE_H(id) GOP_REG(GOP_4G_OFST+1, 0x11 + (0x20*((id)%MAX_GOP0_GWIN))) 555 #define GOP_4G_DRAM_RLEN_L(id) GOP_REG(GOP_4G_OFST+1, 0x12 + (0x20*((id)%MAX_GOP0_GWIN))) 556 #define GOP_4G_DRAM_RLEN_H(id) GOP_REG(GOP_4G_OFST+1, 0x13 + (0x20*((id)%MAX_GOP0_GWIN))) 557 #define GOP_4G_DRAM_HVSTOP_L(id) GOP_REG(GOP_4G_OFST+1, 0x14 + (0x20*((id)%MAX_GOP0_GWIN))) 558 #define GOP_4G_DRAM_HVSTOP_H(id) GOP_REG(GOP_4G_OFST+1, 0x15 + (0x20*((id)%MAX_GOP0_GWIN))) 559 #define GOP_4G_DRAM_FADE(id) GOP_REG(GOP_4G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP0_GWIN))) 560 #define GOP_4G_BG_CLR(id) GOP_REG(GOP_4G_OFST+1, 0x18 + (0x20*((id)%MAX_GOP0_GWIN))) 561 #define GOP_4G_BG_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x19 + (0x20*((id)%MAX_GOP0_GWIN))) 562 #define GOP_4G_BG_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x1a + (0x20*((id)%MAX_GOP0_GWIN))) 563 #define GOP_4G_BG_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x1C + (0x20*((id)%MAX_GOP0_GWIN))) 564 #define GOP_4G_BG_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x1D + (0x20*((id)%MAX_GOP0_GWIN))) 565 #define GOP_4G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP0_GWIN))) 566 #define GOP_4G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP0_GWIN))) 567 568 569 #define GOP_2G_CTRL0 GOP_REG(GOP_2G_OFST, 0x00) 570 #define GOP_2G_CTRL1 GOP_REG(GOP_2G_OFST, 0x01) 571 #define GOP_2G_RATE GOP_REG(GOP_2G_OFST, 0x02) 572 #define GOP_2G_PALDATA_L GOP_REG(GOP_2G_OFST, 0x03) 573 #define GOP_2G_PALDATA_H GOP_REG(GOP_2G_OFST, 0x04) 574 #define GOP_2G_PALCTRL GOP_REG(GOP_2G_OFST, 0x05) 575 #define GOP_2G_REGDMA_END GOP_REG(GOP_2G_OFST, 0x06) 576 #define GOP_2G_REGDMA_STR GOP_REG(GOP_2G_OFST, 0x07) 577 #define GOP_2G_INT GOP_REG(GOP_2G_OFST, 0x08) 578 #define GOP_2G_HWSTATE GOP_REG(GOP_2G_OFST, 0x09) 579 #define GOP_2G_RDMA_HT GOP_REG(GOP_2G_OFST, 0x0e) 580 #define GOP_2G_HS_PIPE GOP_REG(GOP_2G_OFST, 0x0f) 581 #define GOP_2G_SLOW GOP_REG(GOP_2G_OFST, 0x10) 582 #define GOP_2G_BRI GOP_REG(GOP_2G_OFST, 0x11) 583 #define GOP_2G_CON GOP_REG(GOP_2G_OFST, 0x12) 584 #define GOP_2G_BW GOP_REG(GOP_2G_OFST, 0x19) 585 #define GOP_2G_H121 GOP_REG(GOP_2G_OFST, 0x1B) 586 #define GOP_2G_3D_MIDDLE GOP_REG(GOP_2G_OFST, 0x1E) 587 #define GOP_2G_PRI0 GOP_REG(GOP_2G_OFST, 0x20) 588 #define GOP_2G_TRSCLR_L GOP_REG(GOP_2G_OFST, 0x24) 589 #define GOP_2G_TRSCLR_H GOP_REG(GOP_2G_OFST, 0x25) 590 #define GOP_2G_STRCH_HSZ GOP_REG(GOP_2G_OFST, 0x30) 591 #define GOP_2G_STRCH_VSZ GOP_REG(GOP_2G_OFST, 0x31) 592 #define GOP_2G_STRCH_HSTR GOP_REG(GOP_2G_OFST, 0x32) 593 #define GOP_2G_STRCH_VSTR GOP_REG(GOP_2G_OFST, 0x34) 594 #define GOP_2G_HSTRCH GOP_REG(GOP_2G_OFST, 0x35) 595 #define GOP_2G_VSTRCH GOP_REG(GOP_2G_OFST, 0x36) 596 #define GOP_2G_HSTRCH_INI GOP_REG(GOP_2G_OFST, 0x38) 597 #define GOP_2G_VSTRCH_INI GOP_REG(GOP_2G_OFST, 0x39) 598 #define GOP_2G_HVStrch_MD GOP_REG(GOP_2G_OFST, 0x3a) 599 #define GOP_2G_OLDADDR GOP_REG(GOP_2G_OFST, 0x3b) 600 #define GOP_2G_MULTI_ALPHA GOP_REG(GOP_2G_OFST, 0x3c) 601 #define GOP_2G_REGDMA_EN GOP_REG(GOP_2G_OFST, 0x78) 602 603 604 #define GOP_2G_GWIN0_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 605 #define GOP_2G_GWIN_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 606 #define GOP_2G_DRAM_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP1_GWIN))) 607 #define GOP_2G_DRAM_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP1_GWIN))) 608 #define GOP_2G_DEL_PIXEL(id) GOP_REG(GOP_2G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 609 #define GOP_2G_HSTR(id) GOP_REG(GOP_2G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP1_GWIN))) 610 #define GOP_2G_HEND(id) GOP_REG(GOP_2G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP1_GWIN))) 611 #define GOP_2G_VSTR(id) GOP_REG(GOP_2G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP1_GWIN))) 612 #define GOP_2G_VEND(id) GOP_REG(GOP_2G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP1_GWIN))) 613 #define GOP_2G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_2G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP1_GWIN))) 614 #define GOP_2G_GWIN_ALPHA01(id) GOP_REG(GOP_2G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP1_GWIN))) 615 #define GOP_2G_DRAM_VSTR_L(id) GOP_REG(GOP_2G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP1_GWIN))) 616 #define GOP_2G_DRAM_VSTR_H(id) GOP_REG(GOP_2G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP1_GWIN))) 617 #define GOP_2G_DRAM_FADE(id) GOP_REG(GOP_2G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP1_GWIN))) 618 #define GOP_2G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP1_GWIN))) 619 #define GOP_2G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP1_GWIN))) 620 621 // DWIN reg 622 #define GOP_DW_CTL0_EN GOP_REG(GOP_DW_OFST, 0x00) 623 #define GOP_DWIN_EN (0x00) 624 #define GOP_DWIN_EN_VAL GOP_REG_VAL(GOP_DWIN_EN) 625 #define GOP_DWIN_SHOT (0x07) 626 #define GOP_DWIN_SHOT_VAL GOP_REG_VAL(GOP_DWIN_SHOT) 627 628 #define GOP_DW_LSTR_WBE GOP_REG(GOP_DW_OFST, 0x01) 629 #define GOP_DW_INT_MASK GOP_REG(GOP_DW_OFST, 0x02) 630 #define GOP_DW_DEBUG GOP_REG(GOP_DW_OFST, 0x03) 631 #define GOP_DW_ALPHA GOP_REG(GOP_DW_OFST, 0x04) 632 #define GOP_DW_BW GOP_REG(GOP_DW_OFST, 0x05) 633 #define GOP_DW_VSTR GOP_REG(GOP_DW_OFST, 0x10) 634 #define GOP_DW_HSTR GOP_REG(GOP_DW_OFST, 0x11) 635 #define GOP_DW_VEND GOP_REG(GOP_DW_OFST, 0x12) 636 #define GOP_DW_HEND GOP_REG(GOP_DW_OFST, 0x13) 637 #define GOP_DW_HSIZE GOP_REG(GOP_DW_OFST, 0x14) 638 #define GOP_DW_JMPLEN GOP_REG(GOP_DW_OFST, 0x15) 639 #define GOP_DW_DSTR_L GOP_REG(GOP_DW_OFST, 0x16) 640 #define GOP_DW_DSTR_H GOP_REG(GOP_DW_OFST, 0x17) 641 #define GOP_DW_UB_L GOP_REG(GOP_DW_OFST, 0x18) 642 #define GOP_DW_UB_H GOP_REG(GOP_DW_OFST, 0x19) 643 644 #define GOP_DW_PON_DSTR_L GOP_REG(GOP_DW_OFST, 0x1a) 645 #define GOP_DW_PON_DSTR_H GOP_REG(GOP_DW_OFST, 0x1b) 646 #define GOP_DW_PON_UB_L GOP_REG(GOP_DW_OFST, 0x1c) 647 #define GOP_DW_PON_UB_H GOP_REG(GOP_DW_OFST, 0x1d) 648 #define GOP_DW_FRAME_CTRL GOP_REG(GOP_DW_OFST, 0x30) 649 650 #define GOP_VE_DATA_MUX GOP_REG(GOP_MIXER_OFST, 0x30) 651 652 #define GOP_1G_CTRL0 GOP_REG(GOP_1G_OFST, 0x00) 653 #define GOP_1G_CTRL1 GOP_REG(GOP_1G_OFST, 0x01) 654 #define GOP_1G_RATE GOP_REG(GOP_1G_OFST, 0x02) 655 #define GOP_1G_PALDATA_L GOP_REG(GOP_1G_OFST, 0x03) 656 #define GOP_1G_PALDATA_H GOP_REG(GOP_1G_OFST, 0x04) 657 #define GOP_1G_PALCTRL GOP_REG(GOP_1G_OFST, 0x05) 658 #define GOP_1G_REGDMA_END GOP_REG(GOP_1G_OFST, 0x06) 659 #define GOP_1G_REGDMA_STR GOP_REG(GOP_1G_OFST, 0x07) 660 #define GOP_1G_INT GOP_REG(GOP_1G_OFST, 0x08) 661 #define GOP_1G_HWSTATE GOP_REG(GOP_1G_OFST, 0x09) 662 #define GOP_1G_RDMA_HT GOP_REG(GOP_1G_OFST, 0x0e) 663 #define GOP_1G_HS_PIPE GOP_REG(GOP_1G_OFST, 0x0f) 664 #define GOP_1G_BRI GOP_REG(GOP_1G_OFST, 0x11) 665 #define GOP_1G_CON GOP_REG(GOP_1G_OFST, 0x12) 666 #define GOP_1G_BW GOP_REG(GOP_1G_OFST, 0x19) 667 #define GOP_1G_H121 GOP_REG(GOP_1G_OFST, 0x1B) 668 #define GOP_1G_3D_MIDDLE GOP_REG(GOP_1G_OFST, 0x1E) 669 #define GOP_1G_TRSCLR_L GOP_REG(GOP_1G_OFST, 0x24) 670 #define GOP_1G_TRSCLR_H GOP_REG(GOP_1G_OFST, 0x25) 671 #define GOP_1G_STRCH_HSZ GOP_REG(GOP_1G_OFST, 0x30) 672 #define GOP_1G_STRCH_VSZ GOP_REG(GOP_1G_OFST, 0x31) 673 #define GOP_1G_STRCH_HSTR GOP_REG(GOP_1G_OFST, 0x32) 674 #define GOP_1G_STRCH_VSTR GOP_REG(GOP_1G_OFST, 0x34) 675 #define GOP_1G_HSTRCH GOP_REG(GOP_1G_OFST, 0x35) 676 #define GOP_1G_HSTRCH_INI GOP_REG(GOP_1G_OFST, 0x38) 677 #define GOP_1G_VSTRCH_INI GOP_REG(GOP_1G_OFST, 0x39) 678 #define GOP_1G_HStrch_MD GOP_REG(GOP_1G_OFST, 0x3a) 679 #define GOP_1G_OLDADDR GOP_REG(GOP_1G_OFST, 0x3b) 680 #define GOP_1G_MULTI_ALPHA GOP_REG(GOP_1G_OFST, 0x3c) 681 682 #define GOP_1G_GWIN0_CTRL GOP_REG(GOP_1G_OFST+1, 0x0) 683 #define GOP_1G_DRAM_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1) 684 #define GOP_1G_DRAM_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x2) 685 #define GOP_1G_DEL_PIXEL GOP_REG(GOP_1G_OFST+1, 0x3) 686 #define GOP_1G_HSTR GOP_REG(GOP_1G_OFST+1, 0x4) 687 #define GOP_1G_HEND GOP_REG(GOP_1G_OFST+1, 0x5) 688 #define GOP_1G_VSTR GOP_REG(GOP_1G_OFST+1, 0x6) 689 #define GOP_1G_VEND GOP_REG(GOP_1G_OFST+1, 0x8) 690 #define GOP_1G_DRAM_RBLK_HSIZE GOP_REG(GOP_1G_OFST+1, 0x9) 691 #define GOP_1G_GWIN_ALPHA01 GOP_REG(GOP_1G_OFST+1, 0xA) 692 #define GOP_1G_DRAM_VSTR_L GOP_REG(GOP_1G_OFST+1, 0x0C) 693 #define GOP_1G_DRAM_VSTR_H GOP_REG(GOP_1G_OFST+1, 0x0D) 694 #define GOP_1G_DRAM_FADE GOP_REG(GOP_1G_OFST+1, 0x16) 695 #define GOP_1G_3DOSD_SUB_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1E) 696 #define GOP_1G_3DOSD_SUB_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x1F) 697 698 #define GOP_1GX_CTRL0 GOP_REG(GOP_1GX_OFST, 0x00) 699 #define GOP_1GX_CTRL1 GOP_REG(GOP_1GX_OFST, 0x01) 700 #define GOP_1GX_RATE GOP_REG(GOP_1GX_OFST, 0x02) 701 #define GOP_1GX_PALDATA_L GOP_REG(GOP_1GX_OFST, 0x03) 702 #define GOP_1GX_PALDATA_H GOP_REG(GOP_1GX_OFST, 0x04) 703 #define GOP_1GX_PALCTRL GOP_REG(GOP_1GX_OFST, 0x05) 704 #define GOP_1GX_REGDMA_END GOP_REG(GOP_1GX_OFST, 0x06) 705 #define GOP_1GX_REGDMA_STR GOP_REG(GOP_1GX_OFST, 0x07) 706 #define GOP_1GX_INT GOP_REG(GOP_1GX_OFST, 0x08) 707 #define GOP_1GX_HWSTATE GOP_REG(GOP_1GX_OFST, 0x09) 708 #define GOP_1GX_RDMA_HT GOP_REG(GOP_1GX_OFST, 0x0e) 709 #define GOP_1GX_HS_PIPE GOP_REG(GOP_1GX_OFST, 0x0f) 710 #define GOP_1GX_BRI GOP_REG(GOP_1GX_OFST, 0x11) 711 #define GOP_1GX_CON GOP_REG(GOP_1GX_OFST, 0x12) 712 #define GOP_1GX_BW GOP_REG(GOP_1GX_OFST, 0x19) 713 #define GOP_1GX_H121 GOP_REG(GOP_1GX_OFST, 0x1B) 714 #define GOP_1GX_3D_MIDDLE GOP_REG(GOP_1GX_OFST, 0x1E) 715 #define GOP_1GX_TRSCLR_L GOP_REG(GOP_1GX_OFST, 0x24) 716 #define GOP_1GX_TRSCLR_H GOP_REG(GOP_1GX_OFST, 0x25) 717 #define GOP_1GX_STRCH_HSZ GOP_REG(GOP_1GX_OFST, 0x30) 718 #define GOP_1GX_STRCH_VSZ GOP_REG(GOP_1GX_OFST, 0x31) 719 #define GOP_1GX_STRCH_HSTR GOP_REG(GOP_1GX_OFST, 0x32) 720 #define GOP_1GX_STRCH_VSTR GOP_REG(GOP_1GX_OFST, 0x34) 721 #define GOP_1GX_HSTRCH GOP_REG(GOP_1GX_OFST, 0x35) 722 #define GOP_1GX_HSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x38) 723 #define GOP_1GX_VSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x39) 724 #define GOP_1GX_HStrch_MD GOP_REG(GOP_1GX_OFST, 0x3a) 725 #define GOP_1GX_OLDADDR GOP_REG(GOP_1GX_OFST, 0x3b) 726 #define GOP_1GX_MULTI_ALPHA GOP_REG(GOP_1GX_OFST, 0x3c) 727 728 #define GOP_1GX_GWIN0_CTRL GOP_REG(GOP_1GX_OFST+1, 0x00) 729 #define GOP_1GX_DRAM_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x01) 730 #define GOP_1GX_DRAM_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x02) 731 #define GOP_1GX_DEL_PIXEL GOP_REG(GOP_1GX_OFST+1, 0x03) 732 #define GOP_1GX_HSTR GOP_REG(GOP_1GX_OFST+1, 0x04) 733 #define GOP_1GX_HEND GOP_REG(GOP_1GX_OFST+1, 0x05) 734 #define GOP_1GX_VSTR GOP_REG(GOP_1GX_OFST+1, 0x06) 735 #define GOP_1GX_VEND GOP_REG(GOP_1GX_OFST+1, 0x08) 736 #define GOP_1GX_DRAM_RBLK_HSIZE GOP_REG(GOP_1GX_OFST+1, 0x09) 737 #define GOP_1GX_GWIN_ALPHA01 GOP_REG(GOP_1GX_OFST+1, 0x0A) 738 #define GOP_1GX_DRAM_VSTR_L GOP_REG(GOP_1GX_OFST+1, 0x0C) 739 #define GOP_1GX_DRAM_VSTR_H GOP_REG(GOP_1GX_OFST+1, 0x0D) 740 #define GOP_1GX_DRAM_FADE GOP_REG(GOP_1GX_OFST+1, 0x16) 741 #define GOP_1GX_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x1E) 742 #define GOP_1GX_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x1F) 743 744 #define GOP_MIXER_CTRL GOP_REG(GOP_MIXER_OFST, 0x0) 745 746 #define GOP_MIXER_EN_GOP_MIX0 (1<<0) 747 #define GOP_MIXER_EN_GOP_MIX1 (1<<1) 748 #define GOP_MIXER_GOP_MIX_MODE (1<<2) 749 #define GOP_MIXER_HS_POL (1<<5) 750 #define GOP_MIXER_VS_POL (1<<6) 751 #define GOP_MIXER_EN_FLD_FREERUN_MD (1<<7) 752 #define GOP_MIXER_INV_FIELD_VEOSD (1<<8) 753 #define GOP_MIXER_ABL_POL (1<<9) 754 #define GOP_MIXER_EN_MIX (1<<15) 755 756 757 #define GOP_MIXER_FHST GOP_REG(GOP_MIXER_OFST, 0x1) 758 #define GOP_MIXER_FVST GOP_REG(GOP_MIXER_OFST, 0x2) 759 #define GOP_MIXER_FHEND GOP_REG(GOP_MIXER_OFST, 0x3) 760 #define GOP_MIXER_FVEND GOP_REG(GOP_MIXER_OFST, 0x4) 761 #define GOP_MIXER_HTT GOP_REG(GOP_MIXER_OFST, 0x5) 762 #define GOP_MIXER_HS_DELAY GOP_REG(GOP_MIXER_OFST, 0x6) 763 #define GOP_MIXER_FLD_DELAY_LINE GOP_REG(GOP_MIXER_OFST, 0x7) 764 #define GOP_MIXER_FLD_DE_ADJUST GOP_REG(GOP_MIXER_OFST, 0x8) 765 #define GOP_MIXER_C_FIL_COEF0COEF1 GOP_REG(GOP_MIXER_OFST, 0x9) 766 #define GOP_MIXER_C_FIL_COEF2COEF3 GOP_REG(GOP_MIXER_OFST, 0xa) 767 #define GOP_MIXER_VFIL_RATIO GOP_REG(GOP_MIXER_OFST, 0xb) 768 #define GOP_MIXER_MIX_DUMMY GOP_REG(GOP_MIXER_OFST, 0xc) 769 #define GOP_MIXER_DEBUG_H GOP_REG(GOP_MIXER_OFST, 0xd) 770 #define GOP_MIXER_DEBUG_V GOP_REG(GOP_MIXER_OFST, 0xe) 771 #define GOP_MIXER_DEBUG_PIXEL_L GOP_REG(GOP_MIXER_OFST, 0xf) 772 #define GOP_MIXER_DEBUG_PIXEL_H GOP_REG(GOP_MIXER_OFST, 0x10) 773 #define GOP_MIXER_VE GOP_REG(GOP_MIXER_OFST, 0x11) 774 #define GOP_MIXER_FULL_WIN_DE GOP_REG(GOP_MIXER_OFST, 0x20) 775 #define GOP_VE_DATA_MUX GOP_REG(GOP_MIXER_OFST, 0x30) 776 777 #define GOP_MIXER_EN_VFIL (1<<0) 778 #define GOP_MIXER_EN_VFIL_MASK GOP_BIT0 779 #define GOP_MIXER_VS_FLD_ON (1<<7) 780 #define GOP_MIXER_VS_FLD_ON_MASK GOP_BIT7 781 #define GOP_MIXER_REG_DUMMY GOP_REG(GOP_MIXER_OFST, 0x20) 782 783 #define GOP_1GS0_CTRL0 GOP_REG(GOP_1GS0_OFST, 0x00) 784 #define GOP_1GS0_CTRL1 GOP_REG(GOP_1GS0_OFST, 0x01) 785 #define GOP_1GS0_RATE GOP_REG(GOP_1GS0_OFST, 0x02) 786 #define GOP_1GS0_PALDATA_L GOP_REG(GOP_1GS0_OFST, 0x03) 787 #define GOP_1GS0_PALDATA_H GOP_REG(GOP_1GS0_OFST, 0x04) 788 #define GOP_1GS0_PALCTRL GOP_REG(GOP_1GS0_OFST, 0x05) 789 #define GOP_1GS0_REGDMA_END GOP_REG(GOP_1GS0_OFST, 0x06) 790 #define GOP_1GS0_REGDMA_STR GOP_REG(GOP_1GS0_OFST, 0x07) 791 #define GOP_1GS0_INT GOP_REG(GOP_1GS0_OFST, 0x08) 792 #define GOP_1GS0_HWSTATE GOP_REG(GOP_1GS0_OFST, 0x09) 793 #define GOP_1GS0_RDMA_HT GOP_REG(GOP_1GS0_OFST, 0x0e) 794 #define GOP_1GS0_HS_PIPE GOP_REG(GOP_1GS0_OFST, 0x0f) 795 #define GOP_1GS0_BRI GOP_REG(GOP_1GS0_OFST, 0x11) 796 #define GOP_1GS0_CON GOP_REG(GOP_1GS0_OFST, 0x12) 797 #define GOP_1GS0_BW GOP_REG(GOP_1GS0_OFST, 0x19) 798 #define GOP_1GS0_TRSCLR_L GOP_REG(GOP_1GS0_OFST, 0x24) 799 #define GOP_1GS0_TRSCLR_H GOP_REG(GOP_1GS0_OFST, 0x25) 800 #define GOP_1GS0_STRCH_HSZ GOP_REG(GOP_1GS0_OFST, 0x30) 801 #define GOP_1GS0_STRCH_VSZ GOP_REG(GOP_1GS0_OFST, 0x31) 802 #define GOP_1GS0_STRCH_HSTR GOP_REG(GOP_1GS0_OFST, 0x32) 803 #define GOP_1GS0_STRCH_VSTR GOP_REG(GOP_1GS0_OFST, 0x34) 804 #define GOP_1GS0_HSTRCH GOP_REG(GOP_1GS0_OFST, 0x35) 805 #define GOP_1GS0_HSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x38) 806 #define GOP_1GS0_VSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x39) 807 #define GOP_1GS0_HVStrch_MD GOP_REG(GOP_1GS0_OFST, 0x3a) 808 #define GOP_1GS0_OLDADDR GOP_REG(GOP_1GS0_OFST, 0x3b) 809 #define GOP_1GS0_MULTI_ALPHA GOP_REG(GOP_1GS0_OFST, 0x3c) 810 811 #define GOP_1GS0_GWIN0_CTRL GOP_REG(GOP_1GS0_OFST+1, 0x00) 812 #define GOP_1GS0_DRAM_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x01) 813 #define GOP_1GS0_DRAM_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x02) 814 #define GOP_1GS0_DEL_PIXEL GOP_REG(GOP_1GS0_OFST+1, 0x03) 815 #define GOP_1GS0_HSTR GOP_REG(GOP_1GS0_OFST+1, 0x04) 816 #define GOP_1GS0_HEND GOP_REG(GOP_1GS0_OFST+1, 0x05) 817 #define GOP_1GS0_VSTR GOP_REG(GOP_1GS0_OFST+1, 0x06) 818 #define GOP_1GS0_VEND GOP_REG(GOP_1GS0_OFST+1, 0x08) 819 #define GOP_1GS0_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS0_OFST+1, 0x09) 820 #define GOP_1GS0_GWIN_ALPHA01 GOP_REG(GOP_1GS0_OFST+1, 0x0A) 821 #define GOP_1GS0_DRAM_VSTR_L GOP_REG(GOP_1GS0_OFST+1, 0x0C) 822 #define GOP_1GS0_DRAM_VSTR_H GOP_REG(GOP_1GS0_OFST+1, 0x0D) 823 #define GOP_1GS0_DRAM_FADE GOP_REG(GOP_1GS0_OFST+1, 0x16) 824 #define GOP_1GS0_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x1E) 825 #define GOP_1GS0_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x1F) 826 827 #define GOP_1GS1_CTRL0 GOP_REG(GOP_1GS1_OFST, 0x00) 828 #define GOP_1GS1_CTRL1 GOP_REG(GOP_1GS1_OFST, 0x01) 829 #define GOP_1GS1_RATE GOP_REG(GOP_1GS1_OFST, 0x02) 830 #define GOP_1GS1_PALDATA_L GOP_REG(GOP_1GS1_OFST, 0x03) 831 #define GOP_1GS1_PALDATA_H GOP_REG(GOP_1GS1_OFST, 0x04) 832 #define GOP_1GS1_PALCTRL GOP_REG(GOP_1GS1_OFST, 0x05) 833 #define GOP_1GS1_REGDMA_END GOP_REG(GOP_1GS1_OFST, 0x06) 834 #define GOP_1GS1_REGDMA_STR GOP_REG(GOP_1GS1_OFST, 0x07) 835 #define GOP_1GS1_INT GOP_REG(GOP_1GS1_OFST, 0x08) 836 #define GOP_1GS1_HWSTATE GOP_REG(GOP_1GS1_OFST, 0x09) 837 #define GOP_1GS1_RDMA_HT GOP_REG(GOP_1GS1_OFST, 0x0e) 838 #define GOP_1GS1_HS_PIPE GOP_REG(GOP_1GS1_OFST, 0x0f) 839 #define GOP_1GS1_BRI GOP_REG(GOP_1GS1_OFST, 0x11) 840 #define GOP_1GS1_CON GOP_REG(GOP_1GS1_OFST, 0x12) 841 #define GOP_1GS1_BW GOP_REG(GOP_1GS1_OFST, 0x19) 842 #define GOP_1GS1_TRSCLR_L GOP_REG(GOP_1GS1_OFST, 0x24) 843 #define GOP_1GS1_TRSCLR_H GOP_REG(GOP_1GS1_OFST, 0x25) 844 #define GOP_1GS1_STRCH_HSZ GOP_REG(GOP_1GS1_OFST, 0x30) 845 #define GOP_1GS1_STRCH_VSZ GOP_REG(GOP_1GS1_OFST, 0x31) 846 #define GOP_1GS1_STRCH_HSTR GOP_REG(GOP_1GS1_OFST, 0x32) 847 #define GOP_1GS1_STRCH_VSTR GOP_REG(GOP_1GS1_OFST, 0x34) 848 #define GOP_1GS1_HSTRCH GOP_REG(GOP_1GS1_OFST, 0x35) 849 #define GOP_1GS1_HSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x38) 850 #define GOP_1GS1_VSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x39) 851 #define GOP_1GS1_HVStrch_MD GOP_REG(GOP_1GS1_OFST, 0x3a) 852 #define GOP_1GS1_OLDADDR GOP_REG(GOP_1GS1_OFST, 0x3b) 853 #define GOP_1GS1_MULTI_ALPHA GOP_REG(GOP_1GS1_OFST, 0x3c) 854 855 #define GOP_1GS1_GWIN0_CTRL GOP_REG(GOP_1GS1_OFST+1, 0x00) 856 #define GOP_1GS1_DRAM_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x01) 857 #define GOP_1GS1_DRAM_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x02) 858 #define GOP_1GS1_DEL_PIXEL GOP_REG(GOP_1GS1_OFST+1, 0x03) 859 #define GOP_1GS1_HSTR GOP_REG(GOP_1GS1_OFST+1, 0x04) 860 #define GOP_1GS1_HEND GOP_REG(GOP_1GS1_OFST+1, 0x05) 861 #define GOP_1GS1_VSTR GOP_REG(GOP_1GS1_OFST+1, 0x06) 862 #define GOP_1GS1_VEND GOP_REG(GOP_1GS1_OFST+1, 0x08) 863 #define GOP_1GS1_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS1_OFST+1, 0x09) 864 #define GOP_1GS1_GWIN_ALPHA01 GOP_REG(GOP_1GS1_OFST+1, 0x0A) 865 #define GOP_1GS1_DRAM_VSTR_L GOP_REG(GOP_1GS1_OFST+1, 0x0C) 866 #define GOP_1GS1_DRAM_VSTR_H GOP_REG(GOP_1GS1_OFST+1, 0x0D) 867 #define GOP_1GS1_DRAM_FADE GOP_REG(GOP_1GS1_OFST+1, 0x16) 868 #define GOP_1GS1_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x1E) 869 #define GOP_1GS1_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x1F) 870 //------------------------------------------------------------------------------------------------- 871 // Type and Structure 872 //------------------------------------------------------------------------------------------------- 873 874 //---------------------------------------------------------------------------- 875 // GOP Test Pattern Reg 876 //---------------------------------------------------------------------------- 877 #define REG_TSTCLR_EN GOP_REG(GOP_4G_OFST, 0x00) 878 #define REG_TSTCLR_ALPHA_EN GOP_REG(GOP_4G_OFST+2, 0x00) 879 #define REG_TLB_TAG_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x2C) 880 #define REG_TLB_TAG_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x2D) 881 #define REG_TLB_TAG_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x2E) 882 #define REG_TLB_TAG_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x2F) 883 #define REG_TSTCLR_ALPHA GOP_REG(GOP_4G_OFST+2, 0x40) 884 #define REG_R_STC GOP_REG(GOP_4G_OFST+2, 0x41) 885 #define REG_G_STC GOP_REG(GOP_4G_OFST+2, 0x48) 886 #define REG_B_STC GOP_REG(GOP_4G_OFST+2, 0x49) 887 #define REG_TSTCLR_HDUP GOP_REG(GOP_4G_OFST+2, 0x01) 888 #define REG_TSTCLR_VDUP GOP_REG(GOP_4G_OFST+2, 0x01) 889 #define REG_HR_INC GOP_REG(GOP_4G_OFST+2, 0x42) 890 #define REG_HR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x42) 891 #define REG_HG_INC GOP_REG(GOP_4G_OFST+2, 0x43) 892 #define REG_HG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x43) 893 #define REG_HB_INC GOP_REG(GOP_4G_OFST+2, 0x44) 894 #define REG_HB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x44) 895 #define REG_HR_STEP GOP_REG(GOP_4G_OFST+2, 0x4A) 896 #define REG_HG_STEP GOP_REG(GOP_4G_OFST+2, 0x4B) 897 #define REG_HB_STEP GOP_REG(GOP_4G_OFST+2, 0x4C) 898 #define REG_VR_INC GOP_REG(GOP_4G_OFST+2, 0x45) 899 #define REG_VR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x45) 900 #define REG_VG_INC GOP_REG(GOP_4G_OFST+2, 0x46) 901 #define REG_VG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x46) 902 #define REG_VB_INC GOP_REG(GOP_4G_OFST+2, 0x47) 903 #define REG_VB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x47) 904 #define REG_VR_STEP GOP_REG(GOP_4G_OFST+2, 0x4D) 905 #define REG_VG_STEP GOP_REG(GOP_4G_OFST+2, 0x4E) 906 #define REG_VB_STEP GOP_REG(GOP_4G_OFST+2, 0x4F) 907 #define REG_TLB_BASE_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x58) 908 #define REG_TLB_BASE_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x59) 909 #define REG_TLB_BASE_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x5A) 910 #define REG_TLB_BASE_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x5B) 911 912 #define MASK_TSTCLR_EN GOP_BIT6 913 #define MASK_TSTCLR_ALPHA_EN GOP_BIT1 914 #define MASK_TSTCLR_ALPHA BMASK(11:8)|BMASK(3:0) 915 #define MASK_RGB_STC_VALID BMASK(7:0) 916 #define MASK_R_STC BMASK(11:8)|BMASK(3:0) 917 #define MASK_G_STC BMASK(11:8)|BMASK(3:0) 918 #define MASK_B_STC BMASK(11:8)|BMASK(3:0) 919 #define MASK_INI_TSTCLR_EN GOP_BIT0 920 #define MASK_TSTCLR_HDUP BMASK(3:2) 921 #define MASK_TSTCLR_VDUP BMASK(1:0) 922 #define MASK_HR_INC BMASK(10:8)|BMASK(3:0) 923 #define MASK_HR_INC_SIGNZ GOP_BIT11 924 #define MASK_HG_INC BMASK(10:8)|BMASK(3:0) 925 #define MASK_HG_INC_SIGNZ GOP_BIT11 926 #define MASK_HB_INC BMASK(10:8)|BMASK(3:0) 927 #define MASK_HB_INC_SIGNZ GOP_BIT11 928 #define MASK_HR_STEP BMASK(11:8)|BMASK(3:0) 929 #define MASK_HG_STEP BMASK(11:8)|BMASK(3:0) 930 #define MASK_HB_STEP BMASK(11:8)|BMASK(3:0) 931 #define MASK_VR_INC BMASK(10:8)|BMASK(3:0) 932 #define MASK_VR_INC_SIGNZ GOP_BIT11 933 #define MASK_VG_INC BMASK(10:8)|BMASK(3:0) 934 #define MASK_VG_INC_SIGNZ GOP_BIT11 935 #define MASK_VB_INC BMASK(10:8)|BMASK(3:0) 936 #define MASK_VB_INC_SIGNZ GOP_BIT11 937 #define MASK_VR_STEP BMASK(11:8)|BMASK(3:0) 938 #define MASK_VG_STEP BMASK(11:8)|BMASK(3:0) 939 #define MASK_VB_STEP BMASK(11:8)|BMASK(3:0) 940 941 #define SHIFT_TSTCLR_EN 6 942 #define SHIFT_TSTCLR_ALPHA_EN 1 943 #define SHIFT_TSTCLR_ALPHA 8 944 #define SHIFT_R_STC 0 945 #define SHIFT_G_STC 0 946 #define SHIFT_B_STC 0 947 #define SHIFT_INI_TSTCLR_EN 0 948 #define SHIFT_TSTCLR_HDUP 2 949 #define SHIFT_TSTCLR_VDUP 0 950 #define SHIFT_HR_INC 0 951 #define SHIFT_HR_INC_SIGNZ 11 952 #define SHIFT_HG_INC 0 953 #define SHIFT_HG_INC_SIGNZ 11 954 #define SHIFT_HB_INC 0 955 #define SHIFT_HB_INC_SIGNZ 11 956 #define SHIFT_HR_STEP 0 957 #define SHIFT_HG_STEP 0 958 #define SHIFT_HB_STEP 0 959 #define SHIFT_VR_INC 0 960 #define SHIFT_VR_INC_SIGNZ 11 961 #define SHIFT_VG_INC 0 962 #define SHIFT_VG_INC_SIGNZ 11 963 #define SHIFT_VB_INC 0 964 #define SHIFT_VB_INC_SIGNZ 11 965 #define SHIFT_VR_STEP 0 966 #define SHIFT_VG_STEP 0 967 #define SHIFT_VB_STEP 0 968 969 970 //---------------------------------------------------------------------------- 971 // GOP AFBC Reg 972 //---------------------------------------------------------------------------- 973 #define REG_AFBC_CORE_EN(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x00+(0x20*id)) 974 #define REG_AFBC_ADDR_L(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x01+(0x20*id)) 975 #define REG_AFBC_ADDR_H(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x02+(0x20*id)) 976 #define REG_AFBC_FMT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0C+(0x20*id)) 977 #define REG_AFBC_WIDTH(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0A+(0x20*id)) 978 #define REG_AFBC_HEIGHT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0B+(0x20*id)) 979 #define REG_AFBC_RESP(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0F+(0x20*id)) 980 #define REG_AFBC_MIU GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x43) 981 #define REG_AFBC_DEBUG(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x44+(0x20*id)) 982 #define REG_AFBC_READCNT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x4C+(0x20*id)) 983 #define REG_AFBC_TRIGGER GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x50) 984 985 #endif // _REG_GOP_H_ 986