1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108 #define HAL_GOP_DEBUGINFO(x) //x
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 //------------------------------------------------------------------------------
120 // Local Var
121 //------------------------------------------------------------------------------
122 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
123 {
124 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
125 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
126 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
127 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
128 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
129 };
130 #ifdef GOP_CMDQ_ENABLE
131 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
132 extern MS_U8 bMIUSelect[MAX_GOP_SUPPORT];
133
134 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
135 extern MS_U8 bAFBCMIUSelect[MAX_GOP_SUPPORT];
136 #endif
137 GOP_CHIP_PROPERTY g_GopChipPro =
138 {
139 .bSetHSyncInverse = TRUE,
140 .bGop1GPalette = TRUE,
141 .bSetHPipeOfst = FALSE,
142 .bNeedCheckMVOP = FALSE,
143 .bNeedSetMUX1ToIP0 = FALSE,
144 .bNeedSetMUX3ToIP0 = FALSE,
145 .bNewMux = TRUE,
146 .bNewPalette = TRUE,
147 .bNewBwReg = TRUE,
148 .bGop2VStretch = TRUE,
149 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
150 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
151 .bhastilemode = TRUE,
152 .bInitNotEnableGOPToSC = FALSE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
153 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
154 .bGOPWithVscale = {TRUE, TRUE, TRUE, FALSE, FALSE}, //setting GOP with/without Vscale
155
156 .bDWINSupport = FALSE,
157 .DwinVer = 0x1,
158 .bTstPatternAlpha = TRUE,
159 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
160 .bFRCSupport = FALSE, /*OC path*/
161 .bGOPMixerToVE= TRUE, /*Mixer to VE path*/
162 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
163 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
164 .bScalingDownSupport= FALSE,
165 .b2Pto1PSupport= TRUE,
166 .bTLBSupport= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE},
167 .GOP_TestPattern_Vaild= E_GOP0,
168 .bInternalMIUSelect= {TRUE, TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
169 .bAFBC_Support= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE},
170
171 #ifdef ENABLE_GOP_T3DPATCH
172 .GOP_PD = 0x2A,
173 #else
174 .GOP_PD = 0x179,
175 #endif
176 .GOP_HDR_OP_PD = 0x0,
177 .GOP_IP_PD = 0x00,
178 .GOP_MVOP_PD = 0x69,
179 .GOP_VE_PD = 0x89,
180 .GOP_MIXER_PD = 0x0,
181 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
182 .GOP_VE_V_Offset = 0x0,
183 .GOP_OP1_PD = 0x109,
184
185 .GOP_MUX_Delta = 0x4,
186 .GOP_Mux_Offset = {0x0, 0x1, 0x2, 0x3, 0x3},
187 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX1, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX4},
188 .GOP_Mux_FRC_offset= 0x13,
189
190 .WordUnit = GOP_WordUnit,
191 .TotalGwinNum = GOP_TotalGwinNum,
192 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
193 .enGOP3DType = E_DRV_3D_DUP_FULL,
194 .bOpInterlace = FALSE,
195 .bAFBC_Merge_GOP_Trig = FALSE,
196 .bAFBCMIUSelDoubleBuffer = FALSE,
197 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE},
198 .bGOPAutoClkGating = FALSE,
199 };
200
201
202 //------------------------------------------------------------------------------
203 // Global Functions
204 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)205 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
206 {
207 GOP_TYPE->GOP0 = E_GOP0;
208 GOP_TYPE->GOP1 = E_GOP1;
209 GOP_TYPE->GOP2 = E_GOP2;
210 GOP_TYPE->GOP3 = E_GOP3;
211 GOP_TYPE->GOP4 = E_GOP4;
212 GOP_TYPE->GOP5 = E_GOP5;
213 GOP_TYPE->DWIN = E_GOP_Dwin;
214 GOP_TYPE->MIXER = E_GOP_MIXER;
215 }
216
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)217 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
218 {
219 MS_U32 u32BankOffSet = 0;
220
221 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
222
223 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
224 {
225 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
226 }
227 else
228 {
229 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
230 }
231
232 return GOP_SUCCESS;
233 }
234
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)235 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
236 {
237 MS_U32 u32BankOffSet =0;
238 MS_U32 u32BitMask,Regval;
239
240 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
241
242 switch(pinpon_mode)
243 {
244 default:
245 case E_DRV_GOP_PINPON_G3D:
246 Regval = bEn << 5;
247 u32BitMask = GOP_BIT5;
248 break;
249 case E_DRV_GOP_PINPON_DWIN:
250 Regval = bEn << 6;
251 u32BitMask = GOP_BIT6;
252 break;
253 case E_DRV_GOP_PINPON_DIP:
254 Regval = bEn << 7;
255 u32BitMask = GOP_BIT7;
256 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
257 break;
258 case E_DRV_GOP_PINPON_DWIN0:
259 Regval = bEn << 7;
260 u32BitMask = GOP_BIT7;
261 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
262 break;
263 case E_DRV_GOP_PINPON_DWIN1:
264 Regval = bEn << 7;
265 u32BitMask = GOP_BIT7;
266 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
267 break;
268 break;
269 }
270
271 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
272 return GOP_SUCCESS;
273 }
274
275
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)276 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
277 {
278 if(gop >= MAX_GOP_SUPPORT)
279 {
280 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
281 return FALSE;
282 }
283
284 if (gop==E_GOP0)
285 *pBnkOfst = GOP_4G_OFST<<16;
286 else if (gop==E_GOP1)
287 *pBnkOfst = GOP_2G_OFST<<16;
288 else if (gop==E_GOP2)
289 *pBnkOfst = GOP_1G_OFST<<16;
290 else if (gop==E_GOP3)
291 *pBnkOfst = GOP_1GX_OFST<<16;
292 else if (gop==E_GOP4)
293 *pBnkOfst = GOP_1GS0_OFST<<16;
294 else if (gop==E_GOP_MIXER)
295 *pBnkOfst = 0xD<<16;
296 else
297 return FALSE;
298
299 return TRUE;
300 }
301
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)302 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
303 {
304 MS_U16 u16Mask0 = 0;
305 MS_U16 u16Mask1 = 0;
306 MS_U8 u8Core=0;
307 MS_BOOL bCoreTrig[AFBC_CORE_COUNT];
308 MS_U8 i=0;
309
310 for(i=0;i<AFBC_CORE_COUNT;i++)
311 {
312 bCoreTrig[i]=FALSE;
313 }
314 if (u16GopMask&GOP_BIT0)
315 {
316 u16Mask0 |= GOP_BIT12;
317 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP0, &u8Core);
318 bCoreTrig[u8Core]=TRUE;
319 }
320 if (u16GopMask&GOP_BIT1)
321 {
322 u16Mask0 |= GOP_BIT13;
323 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP1, &u8Core);
324 bCoreTrig[u8Core]=TRUE;
325 }
326 if (u16GopMask&GOP_BIT2)
327 {
328 u16Mask0 |= GOP_BIT14;
329 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP2, &u8Core);
330 bCoreTrig[u8Core]=TRUE;
331 }
332 if (u16GopMask&GOP_BIT3)
333 {
334 u16Mask0 |= GOP_BIT15;
335 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP2, &u8Core);
336 bCoreTrig[u8Core]=TRUE;
337 }
338 if (u16GopMask&GOP_BIT4)
339 {
340 u16Mask1 |= GOP_BIT4;
341 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP4, &u8Core);
342 bCoreTrig[u8Core]=TRUE;
343 }
344 if (u16Mask0 != 0)
345 {
346 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
347 }
348 if (u16Mask1 != 0)
349 {
350 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
351 }
352
353 for(i=0;i<AFBC_CORE_COUNT;i++)
354 {
355 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
356 {
357 if(bCoreTrig[i]==TRUE)
358 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
359 }
360 }
361
362 return GOP_SUCCESS;
363 }
364
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)365 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
366 {
367 if(gop >= MAX_GOP_SUPPORT)
368 {
369 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
370 return GOP_FAIL;
371 }
372
373 switch(gop)
374 {
375 case E_GOP0:
376 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
377 break;
378 case E_GOP1:
379 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
380 break;
381 case E_GOP2:
382 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
383 break;
384 case E_GOP3:
385 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
386 break;
387 case E_GOP4:
388 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
389 break;
390 default:
391 break;
392 }
393 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
394 {
395 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
396 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
397 }
398 return GOP_SUCCESS;
399 }
400
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)401 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
402 {
403 MS_U16 u16GopAck = 0,reg_val =0;
404
405 if(gop >= MAX_GOP_SUPPORT)
406 {
407 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gop);
408 return FALSE;
409 }
410
411 switch(gop)
412 {
413 case E_GOP0:
414 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
415 if(reg_val&GOP_BIT12)
416 u16GopAck = FALSE;
417 else
418 u16GopAck = TRUE;
419 break;
420 case E_GOP1:
421 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
422 if(reg_val&GOP_BIT13)
423 u16GopAck = FALSE;
424 else
425 u16GopAck = TRUE;
426 break;
427 case E_GOP2:
428 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
429 if(reg_val&GOP_BIT14)
430 u16GopAck = FALSE;
431 else
432 u16GopAck = TRUE;
433 break;
434 case E_GOP3:
435 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
436 if(reg_val&GOP_BIT15)
437 u16GopAck = FALSE;
438 else
439 u16GopAck = TRUE;
440 break;
441 case E_GOP4:
442 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
443 if(reg_val&GOP_BIT4)
444 u16GopAck = FALSE;
445 else
446 u16GopAck = TRUE;
447 break;
448 default:
449 break;
450 }
451 return u16GopAck;
452 }
453
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)454 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
455 {
456 return GOP_FUN_NOT_SUPPORTED;
457 }
458
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)459 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
460 {
461 MS_U32 u32bankoff = 0;
462 MS_U16 mask_shift=0xFF;
463 MS_U16 u16RegVal=0xFF;
464 MS_U8 u8MIUSel=0xF;
465 MS_U8 u8Core=0;
466
467 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
468 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
469
470 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDCF0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32"
471
472 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
473 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
474 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT8|GOP_BIT9, GOP_BIT8|GOP_BIT9);
475
476 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
477
478 // H121 filter
479 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT0); // HD alpha Enable
480 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0, GOP_BIT1); // HD data Enable
481 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT2, GOP_BIT2); // SD data Enable
482 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, GOP_BIT3, GOP_BIT3); // SD data Enable
483 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_H121, 0x2000, 0x3F00); // Ratio between [H121] and [Bypass mode]
484
485 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
486 {
487 if(u8GOPNum == 0)
488 {
489 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT13|GOP_BIT14);
490 }
491 else
492 {
493 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_SRAM_BORROW, 0, GOP_BIT14);
494 }
495 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
496
497 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK);
498 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, GOP_BIT2);
499 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, GOP_BIT8|GOP_BIT10|GOP_BIT12, (GOP_BIT8|GOP_BIT9)|(GOP_BIT10|GOP_BIT11)|(GOP_BIT12|GOP_BIT13));
500 }
501
502 /* enable GOP clock */
503 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
504 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
505
506 switch(u8GOPNum)
507 {
508 case E_GOP0:
509 mask_shift = GOP_MIU_CLIENT_GOP0;
510 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
511 break;
512 case E_GOP1:
513 mask_shift = GOP_MIU_CLIENT_GOP1;
514 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
515 break;
516 case E_GOP2:
517 mask_shift = GOP_MIU_CLIENT_GOP2;
518 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
519 break;
520 case E_GOP3:
521 mask_shift = GOP_MIU_CLIENT_GOP3;
522 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
523 break;
524 case E_GOP4:
525 mask_shift = GOP_MIU_CLIENT_GOP4;
526 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, 0, CKG_GOPG4_DISABLE_CLK_MASK); /* GOP 4 */
527 break;
528 case E_GOP5:
529 mask_shift = GOP_MIU_CLIENT_GOP5;
530 break;
531 case E_GOP_Dwin:
532 mask_shift = GOP_MIU_CLIENT_DWIN;
533 break;
534 default:
535 mask_shift = 0xFF;
536 break;
537 }
538 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
539 {
540 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
541 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
542 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
543 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
544 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
545 }
546
547
548 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
549 {
550 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
551 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
552 #ifdef GOP_MIU_GROUP2
553 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
554 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
555 #endif
556 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
557 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
558 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<4, GOP_BIT4|GOP_BIT5 );//GWIN Palette MIU Select
559 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Set Control MIU select by GOP itself, XC part
560 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
561 {
562 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
563 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
564 }
565 }
566
567 //OC_RM_alpha
568 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
569 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
570 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
571
572 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
573 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT7|GOP_BIT15, GOP_BIT7|GOP_BIT15);//Per Pixel New alpha mode
574 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP,GOP_IP_SUB_MUX_MASK, GOP_IP_SUB_MUX_MASK); //default mask sub IP
575
576 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GOP_INTERNAL_ZORDER_TRIG, GOP_BIT13, GOP_BIT13); // enable double buffe
577 }
578
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)579 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
580 {
581 *pGOPHalLocal->pGopChipPro = g_GopChipPro;
582 }
583
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)584 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
585 {
586 switch(u8GopNum)
587 {
588 case E_GOP0:
589 return (MS_U8)MAX_GOP0_GWIN;
590 break;
591 case E_GOP1:
592 return (MS_U8)MAX_GOP1_GWIN;
593 break;
594 case E_GOP2:
595 return (MS_U8)MAX_GOP2_GWIN;
596 break;
597 case E_GOP3:
598 return (MS_U8)MAX_GOP3_GWIN;
599 break;
600 case E_GOP4:
601 return (MS_U8)MAX_GOP4_GWIN;
602 break;
603 default:
604 MS_ASSERT(0);
605 return 0xFF;
606 break;
607 }
608 }
609
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)610 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
611 {
612 MS_U8 u8GWinId = 0;
613
614 //Adjust GWIN ID by different Chip
615 if(u8Gop >= MAX_GOP_SUPPORT)
616 {
617 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8Gop);
618 MS_ASSERT(0);
619 return 0xFF;
620 }
621
622 switch(u8Gop)
623 {
624 case E_GOP0:
625 u8GWinId = GOP0_GwinIdBase + u8Idx;
626 break;
627 case E_GOP1:
628 u8GWinId = GOP1_GwinIdBase + u8Idx;
629 break;
630 case E_GOP2:
631 u8GWinId = GOP2_GwinIdBase + u8Idx;
632 break;
633 case E_GOP3:
634 u8GWinId = GOP3_GwinIdBase + u8Idx;
635 break;
636 case E_GOP4:
637 u8GWinId = GOP4_GwinIdBase + u8Idx;
638 break;
639 default:
640 break;
641 }
642 return u8GWinId;
643
644 }
645
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)646 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
647 {
648 if(u8GOPNum >= MAX_GOP_SUPPORT)
649 {
650 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOPNum);
651 MS_ASSERT(0);
652 return 0xFF;
653 }
654
655 switch(u8GOPNum)
656 {
657 case E_GOP0: // GOP4G
658 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
659 return GOP_SUCCESS;
660 case E_GOP1: // GOP2G
661 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
662 return GOP_SUCCESS;
663 case E_GOP2: // GOP1G
664 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
665 return GOP_SUCCESS;
666 case E_GOP3: // GOP1GX
667 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
668 return GOP_SUCCESS;
669 case E_GOP4: // GOP1GS
670 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
671 return GOP_SUCCESS;
672 default:
673 MS_ASSERT(0);
674 return GOP_FAIL;
675 }
676 }
677
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)678 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
679 {
680 MS_U16 u16Bank;
681 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
682 u16Bank &= ~BMASK(3:0);
683 u16Bank |= (u8bank&BMASK(3:0));
684 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
685 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
686 u16Bank &= ~GOP_BIT4;
687 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
688 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
689 }
690
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)691 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
692 {
693 MS_U16 u16GetBank;
694 MS_U16 u16BankMask=0;
695
696 if(MAX_GOP_SUPPORT ==5)
697 {
698 u16BankMask = GOP_BANK_MASK | GOP_BIT4;
699 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
700 return (u16GetBank&u16BankMask);
701 }
702 else
703 {
704 u16GetBank = (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
705 return (u16GetBank&GOP_BANK_MASK);
706 }
707 }
708
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)709 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
710 {
711 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
712 MS_U32 bank;
713 MS_U32 direct_addr;
714
715 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Read16Reg[%x]\n", u32addr));
716
717 //* Gop driver should access another HW IP register
718 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
719 switch (u32addr & 0xFF00)
720 {
721 case GOP_REG_BASE:
722 {
723 bank = (u32addr & 0xFF0000) >> 8;
724 #if 0 //for GOP4
725 if(bank==0xE00)//GOP4: 0x121B00
726 {
727 bank=GOP_REG_GOP4_BK_OFFSET;
728 }
729 else if(bank==0xF00)//GWIN4: 0x121E00
730 {
731 bank=GOP_REG_GOP4_GW_OFFSET;
732 }
733 else if(bank==0x1000)//GOP4_ST
734 {
735 bank=GOP_REG_GOP4_ST_OFFSET;
736 }
737 #endif
738 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
739 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
740 break;
741 }
742 case SC1_REG_BASE:
743 {
744 if(g_GopChipPro.bXCDirrectBankSupport)
745 {
746 u16xcSubbank = (u32addr & 0xFF0000)>>8;
747 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
748 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
749 }
750 else
751 {
752 u16xcSubbank = (u32addr & 0xFF0000)>>16;
753 u16BankAddr = GOP_SC_BANKSEL+0;
754 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
755
756 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
757 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
758 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
759 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
760 }
761 break;
762 }
763 case GE_REG_BASE:
764 case CKG_REG_BASE:
765 case MIU0_REG_BASE:
766 case MIU_REG_BASE:
767 case MVOP_REG_BASE:
768 case VE_REG_BASE:
769 {
770 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
771 break;
772 }
773 #ifdef GOP_MIU_GROUP2
774 case (MIU2_REG_BASE & 0xFF00):
775 {
776 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
777 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
778
779 break;
780 }
781 #endif
782 default:
783 {
784 //Gop lib current do not support this HW ip base
785 MS_ASSERT(0);
786 *pu16ret =0;
787 break;
788 }
789 }
790 }
791
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)792 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
793 {
794 MS_U16 u16tmp=0;
795 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
796 MS_U32 bank;
797 MS_U32 direct_addr;
798
799 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write16Reg[%04x] = %04x\n", u32addr, u16val));
800
801 if(mask!=0xffff)
802 {
803 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
804 u16tmp &= ~mask;
805 u16val &= mask;
806 u16val |= u16tmp;
807 }
808
809 //* Gop driver should access another HW IP register
810 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
811 switch (u32addr & 0xFF00)
812 {
813 case GOP_REG_BASE:
814 {
815 bank = (u32addr & 0xFF0000) >> 8;
816 #if 0 //for GOP4
817 if(bank==0xE00)//GOP4: 0x121B00
818 {
819 bank=GOP_REG_GOP4_BK_OFFSET;
820 }
821 else if(bank==0xF00)//GWIN4: 0x121E00
822 {
823 bank=GOP_REG_GOP4_GW_OFFSET;
824 }
825 else if(bank==0x1000) //GOP4_ST
826 {
827 bank=GOP_REG_GOP4_ST_OFFSET;
828 }
829 #endif
830 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
831 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
832 break;
833 }
834 case SC1_REG_BASE:
835 if(g_GopChipPro.bXCDirrectBankSupport)
836 { /*Derrick Bank*/
837 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
838 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
839 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
840 }
841 else
842 { /*Sub Bank*/
843 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
844 u16BankAddr = GOP_SC_BANKSEL+0;
845 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
846
847 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
848 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
849 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
850 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
851 }
852 break;
853 case GE_REG_BASE:
854 case CKG_REG_BASE:
855 case MIU0_REG_BASE:
856 case MIU_REG_BASE:
857 case VE_REG_BASE:
858 {
859 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
860 break;
861 }
862 #ifdef GOP_MIU_GROUP2
863 case (MIU2_REG_BASE & 0xFF00):
864 {
865 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
866 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
867 break;
868 }
869 #endif
870 default:
871 {
872 //Gop lib current do not support this HW ip base
873 MS_ASSERT(0);
874 break;
875 }
876
877 }
878 }
879
880
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)881 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
882 {
883 MS_U32 bank;
884 MS_U32 direct_addr;
885
886 HAL_GOP_DEBUGINFO(printf("HAL_GOP_Write32Reg[%bx] = %lx\n", u32addr, u32val));
887
888 //* Gop driver should access another HW IP register
889 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
890 switch (u32addr & 0xFF00)
891 {
892 case GOP_REG_BASE:
893 {
894 bank = (u32addr & 0xFF0000) >> 8;
895 #if 0 //for GOP4
896 if(bank==0xE00)//GOP4: 0x121B00
897 {
898 bank=GOP_REG_GOP4_BK_OFFSET;
899 }
900 else if(bank==0xF00)//GWIN4: 0x121E00
901 {
902 bank=GOP_REG_GOP4_GW_OFFSET;
903 }
904 else if(bank==0x1000) //GOP4_ST
905 {
906 bank=GOP_REG_GOP4_ST_OFFSET;
907 }
908 #endif
909 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
910 GOP_WRITE2BYTE((direct_addr&0xFFFFF), (u32val&0xFFFF));
911 GOP_WRITE2BYTE((direct_addr&0xFFFFF)+2, (u32val&0xFFFF0000)>>16);
912 break;
913 }
914
915 case GE_REG_BASE:
916 case SC1_REG_BASE:
917 case CKG_REG_BASE:
918 {
919 GOP_WRITE2BYTE((u32addr&0xFFFF), (u32val&0xFFFF));
920 GOP_WRITE2BYTE((u32addr&0xFFFF)+2, (u32val&0xFFFF0000)>>16);
921 break;
922 }
923
924 default:
925 {
926 //Gop lib current do not support this HW ip base
927 MS_ASSERT(0);
928 break;
929 }
930
931 }
932 }
933
934 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
935
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)936 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
937 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
938 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
939 {
940 MS_U8 i=0;
941 HAL_GOP_DEBUGINFO(printf("GOP_Write32Pal : i= %02bx, ARGB = %02bx,%02bx,%02bx,%02bx\n",u8Index, u8A, u8R, u8G, u8B));
942
943 /* Don't care high byte */
944 MS_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
945
946 for(i =(GOP_WordUnit-1);i>4;i--)
947 {
948 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
949 }
950 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
951 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
952 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
953 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
954 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
955 *pREGMAP_Offset += GOP_WordUnit;
956
957 MsOS_FlushMemory(); //make sure cpu write data to dram
958
959 }
960
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)961 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
962 {
963 MS_U16 bpp=0;
964
965 switch ( fbFmt )
966 {
967 case E_DRV_GOP_COLOR_RGB555_BLINK :
968 case E_DRV_GOP_COLOR_RGB565 :
969 case E_DRV_GOP_COLOR_ARGB1555:
970 case E_DRV_GOP_COLOR_RGBA5551:
971 case E_DRV_GOP_COLOR_ARGB4444 :
972 case E_DRV_GOP_COLOR_RGBA4444 :
973 case E_DRV_GOP_COLOR_RGB555YUV422:
974 case E_DRV_GOP_COLOR_YUV422:
975 case E_DRV_GOP_COLOR_2266:
976 bpp = 16;
977 break;
978 case E_DRV_GOP_COLOR_ARGB8888 :
979 case E_DRV_GOP_COLOR_ABGR8888 :
980 bpp = 32;
981 break;
982
983 case E_DRV_GOP_COLOR_I8 :
984 bpp = 8;
985 break;
986
987 default :
988 //print err
989 MS_ASSERT(0);
990 bpp = 0xFFFF;
991 break;
992 }
993 return bpp;
994
995 }
996
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)997 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
998 {
999 MS_U16 regval;
1000 /*For compatibility
1001 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
1002 MS_U8 u8coef_cpt = u8coef;
1003
1004 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
1005 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
1006 {
1007 switch(u8coef)
1008 {
1009 case 0x0 :
1010 u8coef_cpt = u8coef<<2;
1011 break;
1012 case 0x3f :
1013 u8coef_cpt = ((u8coef<<2)|0x3);
1014 break;
1015 default:
1016 u8coef_cpt = ((u8coef<<2)|0x1);
1017 break;
1018 }
1019 }
1020
1021 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1022 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1023 {
1024 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1025 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1026 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1027 }
1028 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1029 else
1030 {
1031 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1032 {
1033 regval = (MS_U16)(bEnable?(1<<14):0);
1034 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1035 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1036 }
1037 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1038 {
1039 regval = (MS_U16)(bEnable?(1<<14):0);
1040 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1041 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1042 }
1043 else
1044 {
1045 regval = (MS_U16)(bEnable?(1<<14):0);
1046 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1047 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1048 }
1049 }
1050 }
1051
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1052 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1053 {
1054 pGOPHalLocal->va_mmio_base = addr;
1055 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1056 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1057 {
1058 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1059 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1060 {
1061 }
1062
1063
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1064 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1065 {
1066 /*A5 GOP dst type:
1067 1: IP (Main)
1068 0: IP (Sub)
1069 2: OP
1070 3: MVOP
1071 4: MVOP (Sub)
1072 6: FRC
1073 11: InsideFRC
1074 */
1075 MS_U16 u16RegVal;
1076 MS_U32 u32BankOffSet;
1077 MS_BOOL bEnable=FALSE;
1078 MS_U16 u16HSyncMask=GOP_BIT14;
1079
1080 if( GopNum >= MAX_GOP_SUPPORT)
1081 {
1082 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,GopNum);
1083 return GOP_INVALID_PARAMETERS;
1084 }
1085
1086 switch (eDstType)
1087 {
1088 case E_DRV_GOP_DST_IP0:
1089 u16RegVal = 0x0;
1090 bEnable = FALSE;
1091 u16HSyncMask=0;
1092 break;
1093
1094 case E_DRV_GOP_DST_OP0:
1095 u16RegVal = 0x2;
1096 bEnable = FALSE;
1097 u16HSyncMask=GOP_BIT14;
1098 break;
1099
1100 case E_DRV_GOP_DST_IP1:
1101 u16RegVal = 0x5;
1102 bEnable = TRUE;
1103 u16HSyncMask=GOP_BIT14;
1104 break;
1105
1106 case E_DRV_GOP_DST_OP1:
1107 u16RegVal = 0x6;
1108 bEnable = TRUE;
1109 u16HSyncMask=GOP_BIT14;
1110 break;
1111
1112 case E_DRV_GOP_DST_VE:
1113 u16RegVal = 0x7;
1114 bEnable = TRUE;
1115 u16HSyncMask=GOP_BIT14;
1116 break;
1117
1118 case E_DRV_GOP_DST_DIP:
1119 u16RegVal = 0x8;
1120 bEnable = TRUE;
1121 u16HSyncMask=GOP_BIT14;
1122 break;
1123
1124 default:
1125 printf("[%s][%d] Not Define DST = %d !!!\n", __FUNCTION__, __LINE__ , eDstType);
1126 return GOP_FUN_NOT_SUPPORTED;
1127 }
1128
1129 if(bOnlyCheck == FALSE)
1130 {
1131 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1132 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1133 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(3:0));
1134
1135 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1136 }
1137 return GOP_SUCCESS;
1138 }
1139
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1140 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1141 {
1142 /*U4 Mixer dst type:
1143 2: OP
1144 3: VE
1145 */
1146 MS_U16 u16Regval = 0;
1147 DRV_MixerDstType eType=E_DRV_MIXER_DST_VE;
1148
1149 switch(eDstType)
1150 {
1151 case E_DRV_GOP_DST_MIXER2VE:
1152 eType = E_DRV_MIXER_DST_VE;
1153 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //Enable pseudo hsync
1154 break;
1155 case E_DRV_GOP_DST_MIXER2OP:
1156 eType = E_DRV_MIXER_DST_OP;
1157 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT7); //Disable pseudo hsync
1158 break;
1159 default:
1160 break;
1161 }
1162
1163 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1164
1165 u16Regval &= (~(GOP_BIT3|GOP_BIT4));
1166 u16Regval |= (eType<<0x3);
1167
1168 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16Regval, (GOP_BIT3|GOP_BIT4));
1169 return GOP_SUCCESS;
1170 }
1171
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1172 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1173 {
1174 MS_U16 u16Regval = 0;
1175
1176 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, &u16Regval);
1177
1178 if(((u16Regval&0x18)>>3) == 0x2)
1179 *pGopDst = E_DRV_GOP_DST_MIXER2OP;
1180 else
1181 *pGopDst = E_DRV_GOP_DST_MIXER2VE;
1182
1183 return GOP_SUCCESS;
1184 }
1185
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1186 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1187 {
1188 /*T8
1189 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1190 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1191 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1192 */
1193 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1194 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1195
1196 /*Disable VE OSD enable*/
1197 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_0, 0x4);
1198 HAL_GOP_VE_SetOSDEnable(pGOPHalLocal, FALSE, EN_OSD_1, 0x4);
1199
1200 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_VOPNBL, 1<<7, GOP_BIT7);
1201 return GOP_SUCCESS;
1202 }
1203
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1204 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1205 {
1206 MS_U16 u16GopMux=0;
1207 switch(eGopMux)
1208 {
1209 case E_GOP_MUX0:
1210 case E_GOP_MUX1:
1211 case E_GOP_MUX2:
1212 case E_GOP_MUX3:
1213 case E_GOP_MUX4:
1214 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1215 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1216 break;
1217 case E_GOP_IP0_MUX:
1218 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1219 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1220 break;
1221 case E_GOP_IP0_SUB_MUX:
1222 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1223 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1224 break;
1225 case E_GOP_VOP0_MUX:
1226 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1227 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1228 break;
1229 case E_GOP_VOP0_SUB_MUX:
1230 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1231 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1232 break;
1233 case E_GOP_Mix_MUX0:
1234 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1235 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1236 break;
1237 case E_GOP_Mix_MUX1:
1238 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1239 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1240 break;
1241 case E_GOP_VE0_MUX:
1242 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1243 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1244 break;
1245 case E_GOP_VE1_MUX:
1246 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1247 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1248 break;
1249 case E_GOP_DIP_MUX:
1250 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1251 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1252 break;
1253 case E_GOP_FRC_MUX0:
1254 case E_GOP_FRC_MUX1:
1255 case E_GOP_FRC_MUX2:
1256 case E_GOP_FRC_MUX3:
1257 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1258 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1259 break;
1260 case E_GOP_BYPASS_MUX0:
1261 break;
1262 case E_GOP_OP1_MUX:
1263 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_SC1, &u16GopMux);
1264 *u8GOPNum = (u16GopMux& ((BMASK((GOP_MUX_SHIFT-1):0))<<12))>>12;
1265 break;
1266 default:
1267 printf("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1268 break;
1269 }
1270 }
1271
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1272 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1273 {
1274 MS_U16 u16Ret[4]={0};
1275
1276 switch(eGopMux)
1277 {
1278 case E_GOP_MUX0:
1279 case E_GOP_MUX1:
1280 case E_GOP_MUX2:
1281 case E_GOP_MUX3:
1282 case E_GOP_MUX4:
1283 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1284 break;
1285 case E_GOP_OP1_MUX:
1286 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_SC1, u8GOPNum <<12, GOP_REGMUX_MASK<<12);
1287 break;
1288 case E_GOP_IP0_MUX:
1289 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1290 break;
1291 case E_GOP_IP1_MUX:
1292 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << 0, BMASK(2:0));
1293 break;
1294 case E_GOP_VOP0_MUX:
1295 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1296 break;
1297 case E_GOP_VOP1_MUX:
1298 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1299 break;
1300 case E_GOP_Mix_MUX0:
1301 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1302 break;
1303 case E_GOP_Mix_MUX1:
1304 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1305 break;
1306 case E_GOP_VE0_MUX:
1307 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1308 break;
1309 case E_GOP_VE1_MUX:
1310 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1311 break;
1312 case E_GOP_DIP_MUX:
1313 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1314 break;
1315 case E_GOP_FRC_MUX0:
1316 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1317 break;
1318 case E_GOP_FRC_MUX1:
1319 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1320 break;
1321 case E_GOP_FRC_MUX2:
1322 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1323 break;
1324 case E_GOP_FRC_MUX3:
1325 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1326 break;
1327 case E_GOP_BYPASS_MUX0:
1328 //Check MUX is using? Checking from priority high to low
1329 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1330 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1331 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1332 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1333
1334 //Checking if un-use
1335 if((u16Ret[0] & GOP_BIT0) ==0)
1336 {
1337 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1338 }
1339 else if((u16Ret[1] & GOP_BIT0) ==0)
1340 {
1341 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1342 }
1343 else if((u16Ret[2] & GOP_BIT0) ==0)
1344 {
1345 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1346 }
1347 else if((u16Ret[3] & GOP_BIT0) ==0)
1348 {
1349 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1350 }
1351 else
1352 {
1353 printf("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1354 }
1355 break;
1356 break;
1357 default:
1358 printf("[%s]ERROR mux setting\n",__FUNCTION__);
1359 break;
1360 }
1361 }
1362
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1363 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1364 {
1365 /* GOP OP Path enable to SC Setting
1366 A5: GOP OP Path blending with SC sequence
1367 mux1-->mux0-->mux2-->mux3
1368 */
1369 MS_BOOL bOSDBEnable=TRUE;
1370 MS_U16 muxValue=0, mux4Value=0, regval=0;
1371
1372 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1373 MS_U16 u164K2KMuxValue=0;
1374
1375 if(gopNum >= MAX_GOP_SUPPORT)
1376 {
1377 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1378 return GOP_FAIL;
1379 }
1380
1381 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1382 if(bOSDBEnable)
1383 {
1384 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, 0x0, GOP_REG_HW_MASK);
1385
1386 }else
1387 {
1388 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1389 }
1390
1391 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1392 {
1393 if(bOSDBEnable)
1394 {
1395 if(bEnable)
1396 {
1397 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1398 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT3, GOP_BIT3);
1399 }else{
1400 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT3);
1401 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0<<1, GOP_BIT1|GOP_BIT2);
1402 }
1403 }
1404 else
1405 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1406 }
1407
1408 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1409 {
1410 if(bOSDBEnable)
1411 {
1412 if(bEnable)
1413 {
1414 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1415 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, GOP_BIT11, GOP_BIT11);
1416 }else{
1417 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 0, GOP_BIT11);
1418 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, 1<<9, GOP_BIT9|GOP_BIT10);
1419 }
1420 }
1421 else
1422 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1423 }
1424
1425 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1426 {
1427 if(bOSDBEnable)
1428 {
1429 if(bEnable)
1430 {
1431 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1432 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT3, GOP_BIT3);
1433 }else{
1434 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT3);
1435 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 2<<1, GOP_BIT1|GOP_BIT2);
1436 }
1437 }
1438 else
1439 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1440 }
1441
1442 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1443 {
1444 if(bOSDBEnable)
1445 {
1446 if(bEnable)
1447 {
1448 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1449 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, GOP_BIT11, GOP_BIT11);
1450 }else{
1451 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 0, GOP_BIT11);
1452 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, 3<<9, GOP_BIT9|GOP_BIT10);
1453 }
1454 }
1455 else
1456 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1457 }
1458
1459
1460 if(MAX_GOP_SUPPORT ==5)
1461 {
1462 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &mux4Value);
1463 if (gopNum== ((mux4Value & GOP_MUX4_MASK)>> GOP_MUX4_SHIFT)) //enable mux4
1464 {
1465 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1466 }
1467 }
1468
1469 /*For FRC mux switch*/
1470 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1471 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1472 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1473 {
1474 /* Switch FRC blending */
1475 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1476 }
1477
1478 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1479 {
1480 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1481 }
1482
1483 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1484 {
1485 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1486 }
1487
1488 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1489 {
1490 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1491 }
1492
1493 return GOP_SUCCESS;
1494 }
1495
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1496 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1497 {
1498 MS_U32 u32pBankOffSet=0;
1499 MS_U16 u16Regval;
1500
1501 if(g_GopChipPro.b2Pto1PSupport)
1502 {
1503 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1504 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1505 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |GOP_BIT11):(u16Regval & ~GOP_BIT11), GOP_BIT11);
1506 }
1507 return GOP_SUCCESS;
1508 }
1509
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1510 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1511 {
1512 /* GOP OP Path enable to SC Setting
1513 A5: GOP OP Path blending with SC sequence
1514 mux1-->mux0-->mux2-->mux3
1515 */
1516 MS_U16 muxValue=0, regval=0;
1517
1518 if(gopNum >= MAX_GOP_SUPPORT)
1519 {
1520 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1521 return FALSE;
1522 }
1523
1524 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1525 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1526 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1527 {
1528 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1529 }
1530 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1531 {
1532 //printf("");
1533 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1534 }
1535 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1536 {
1537 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1538 }
1539 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1540 {
1541 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1542 }
1543 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1544 {
1545 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1546 }
1547 else
1548 {
1549 return GOP_FAIL;
1550 }
1551 return GOP_SUCCESS;
1552 }
1553
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1554 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1555 {
1556 MS_U16 muxValue=0;
1557 MS_U16 regval37=0;
1558 MS_U16 regval38=0;
1559
1560 if(gopNum >= MAX_GOP_SUPPORT)
1561 {
1562 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum );
1563 return FALSE;
1564 }
1565
1566 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1567 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_L, ®val37);
1568 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOP2BLENDING_H, ®val38);
1569 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1570 {
1571 *pbEnable = (regval37& GOP_BIT5) == GOP_BIT5;
1572 }
1573 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1574 {
1575 *pbEnable = (regval37 & GOP_BIT13) == GOP_BIT13;
1576 }
1577 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1578 {
1579 *pbEnable = (regval38 & GOP_BIT5) == GOP_BIT5;
1580 }
1581 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1582 {
1583 *pbEnable = (regval38 & GOP_BIT13) == GOP_BIT13;
1584 }
1585 else
1586 {
1587 return GOP_FAIL;
1588 }
1589 return GOP_SUCCESS;
1590 }
1591
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1592 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1593 {
1594 /*T8
1595 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1596 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1597 */
1598 MS_U16 Mux3Gop, muxValue=0, i;
1599 MS_U16 MuxShift;
1600
1601 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1602
1603 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1604 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1605 {
1606 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1607 {
1608 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1609
1610 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1611 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1612 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1613 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1614 break;
1615
1616 }
1617
1618 }
1619 return GOP_SUCCESS;
1620 }
1621
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1622 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1623 {
1624 /*T8 GOP dst type:
1625 0: IP (Main)
1626 1: IP (Sub)
1627 2: OP
1628 3: MVOP
1629 */
1630
1631 if(gopNum >= MAX_GOP_SUPPORT)
1632 {
1633 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,gopNum);
1634 MS_ASSERT(0);
1635 return GOP_INVALID_PARAMETERS;
1636 }
1637 /* Monaco clkgen setting */
1638 /******************
1639 0: odclk
1640 1: idclk_f2 (ipm)
1641 2: idclk_f1 (ips)
1642 3: ocmixer
1643 4: ve
1644 5 : mvop main
1645 6 : mvop sub
1646 ******************/
1647
1648 switch(eDstType)
1649 {
1650 case E_DRV_GOP_DST_IP0:
1651
1652 if (gopNum==E_GOP1)
1653 {
1654 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1655 }
1656 else if (gopNum ==E_GOP2)
1657 {
1658 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1659 }
1660 else if (gopNum ==E_GOP3)
1661 {
1662 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1663 }
1664 else if (gopNum ==E_GOP4)
1665 {
1666 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1667 }
1668 else if (gopNum==E_GOP0)
1669 {
1670 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1671 }
1672 else
1673 {
1674 MS_ASSERT(0);
1675 return GOP_INVALID_PARAMETERS;
1676 }
1677 break;
1678
1679 case E_DRV_GOP_DST_IP0_SUB:
1680 if (gopNum==E_GOP1)
1681 {
1682 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1683 }
1684 else if (gopNum==E_GOP2)
1685 {
1686 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG1_IDCLK2, CKG_GOPG2_MASK);
1687 }
1688 else if (gopNum==E_GOP3)
1689 {
1690 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG1_IDCLK2, CKG_GOPG3_MASK);
1691 }
1692 else if (gopNum ==E_GOP4)
1693 {
1694 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG1_IDCLK2, CKG_GOPG4_MASK);
1695 }
1696 else if (gopNum==E_GOP0)
1697 {
1698 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG0_MASK);
1699 }
1700 else
1701 {
1702 MS_ASSERT(0);
1703 return GOP_INVALID_PARAMETERS;
1704 }
1705 break;
1706
1707 case E_DRV_GOP_DST_IP1:
1708 if (gopNum==E_GOP1)
1709 {
1710 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
1711 }
1712 else if (gopNum==E_GOP2)
1713 {
1714 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG1_IDCLK1, CKG_GOPG2_MASK);
1715 }
1716 else if (gopNum==E_GOP3)
1717 {
1718 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG1_IDCLK1, CKG_GOPG3_MASK);
1719 }
1720 else if (gopNum ==E_GOP4)
1721 {
1722 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG1_IDCLK1, CKG_GOPG4_MASK);
1723 }
1724 else if (gopNum==E_GOP0)
1725 {
1726 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG0_MASK);
1727 }
1728 else
1729 {
1730 MS_ASSERT(0);
1731 return GOP_INVALID_PARAMETERS;
1732 }
1733 break;
1734 case E_DRV_GOP_DST_MIXER2VE:
1735 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_VECLK, CKG_GOPMIXER_MASK);
1736
1737 if(gopNum == 0)
1738 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
1739 else if(gopNum == 1)
1740 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
1741 else if(gopNum == 2)
1742 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
1743 else if(gopNum == 3)
1744 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
1745 break;
1746
1747 case E_DRV_GOP_DST_OP0:
1748 if (gopNum==E_GOP1)
1749 {
1750 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
1751 }
1752 else if (gopNum==E_GOP2)
1753 {
1754 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
1755 }
1756 else if (gopNum==E_GOP3)
1757 {
1758 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
1759 }
1760 else if (gopNum ==E_GOP4)
1761 {
1762 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
1763 }
1764 else if (gopNum==E_GOP0)
1765 {
1766 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
1767 }
1768 else
1769 {
1770 MS_ASSERT(0);
1771 return GOP_INVALID_PARAMETERS;
1772 }
1773
1774 break;
1775
1776 case E_DRV_GOP_DST_DIP:
1777 if (gopNum==E_GOP1)
1778 {
1779 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
1780 }
1781 else if (gopNum==E_GOP2)
1782 {
1783 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
1784 }
1785 else if (gopNum==E_GOP3)
1786 {
1787 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
1788 }
1789 else if (gopNum ==E_GOP4)
1790 {
1791 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
1792 }
1793 else if (gopNum==E_GOP0)
1794 {
1795 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
1796 }
1797 else
1798 {
1799 MS_ASSERT(0);
1800 return GOP_INVALID_PARAMETERS;
1801 }
1802
1803 break;
1804 case E_DRV_GOP_DST_VOP:
1805 if (gopNum==E_GOP1)
1806 {
1807 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MVOP, CKG_GOPG1_MASK);
1808 }
1809 else if (gopNum==E_GOP2)
1810 {
1811 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_MVOP, CKG_GOPG2_MASK);
1812 }
1813 else if (gopNum==E_GOP3)
1814 {
1815 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_MVOP, CKG_GOPG3_MASK);
1816 }
1817 else if (gopNum ==E_GOP4)
1818 {
1819 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MVOP, CKG_GOPG4_MASK);
1820 }
1821 else if (gopNum==E_GOP0)
1822 {
1823 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MVOP, CKG_GOPG0_MASK);
1824 }
1825 else
1826 {
1827 MS_ASSERT(0);
1828 return GOP_INVALID_PARAMETERS;
1829 }
1830
1831 break;
1832 case E_DRV_GOP_DST_FRC:
1833 if (gopNum==E_GOP1)
1834 {
1835 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
1836 }
1837 else if (gopNum==E_GOP0)
1838 {
1839 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
1840 }
1841 else if (gopNum ==E_GOP2)
1842 {
1843 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
1844 }
1845 else if (gopNum ==E_GOP3)
1846 {
1847 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
1848 }
1849 else if (gopNum ==E_GOP4)
1850 {
1851 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
1852 }
1853 else
1854 {
1855 MS_ASSERT(0);
1856 return GOP_INVALID_PARAMETERS;
1857 }
1858
1859 break;
1860 case E_DRV_GOP_DST_BYPASS:
1861 if (gopNum==E_GOP0)
1862 {
1863 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_BYPASS_FRCCLK, CKG_GOPG0_MASK);
1864 }
1865 else if (gopNum==E_GOP1)
1866 {
1867 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_BYPASS_FRCCLK, CKG_GOPG1_MASK);
1868 }
1869 else if (gopNum==E_GOP2)
1870 {
1871 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_BYPASS_FRCCLK, CKG_GOPG2_MASK);
1872 }
1873 else if (gopNum==E_GOP3)
1874 {
1875 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_BYPASS_FRCCLK, CKG_GOPG3_MASK);
1876 }
1877 else if (gopNum ==E_GOP4)
1878 {
1879 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_BYPASS_FRCCLK, CKG_GOPG4_MASK);
1880 }
1881 else
1882 {
1883 MS_ASSERT(0);
1884 return GOP_INVALID_PARAMETERS;
1885 }
1886 break;
1887 case E_DRV_GOP_DST_MIXER2OP:
1888 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_ODCLK, CKG_GOPMIXER_MASK);
1889 break;
1890 case E_DRV_GOP_DST_OP1:
1891 if (gopNum==E_GOP1)
1892 {
1893 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OD1CLK, CKG_GOPG1_MASK);
1894 }
1895 else if (gopNum==E_GOP2)
1896 {
1897 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OD1CLK, CKG_GOPG2_MASK);
1898 }
1899 else if (gopNum==E_GOP3)
1900 {
1901 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OD1CLK, CKG_GOPG3_MASK);
1902 }
1903 else if (gopNum ==E_GOP4)
1904 {
1905 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OD1CLK, CKG_GOPG4_MASK);
1906 }
1907 else if (gopNum==E_GOP0)
1908 {
1909 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OD1CLK, CKG_GOPG0_MASK);
1910 }
1911 else
1912 {
1913 MS_ASSERT(0);
1914 return GOP_INVALID_PARAMETERS;
1915 }
1916 break;
1917
1918 default:
1919 MS_ASSERT(0);
1920 return GOP_ENUM_NOT_SUPPORTED;
1921 }
1922 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
1923 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
1924
1925 return GOP_SUCCESS;
1926 }
1927
1928
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)1929 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
1930 {
1931 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
1932 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
1933 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
1934 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
1935 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
1936 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
1937 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
1938 else
1939 return GOP_INVALID_PARAMETERS;
1940
1941 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
1942 return GOP_SUCCESS;
1943 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)1944 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
1945 {
1946 if (bEnable)
1947 {
1948 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
1949 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
1950 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
1951 }
1952 else
1953 {
1954 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
1955 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
1956 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
1957 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
1958 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
1959 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
1960 }
1961
1962 return GOP_SUCCESS;
1963 }
1964
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1965 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1966 {
1967 DRV_GOPDstType MixerDstType;
1968 MS_U16 regval = 0;
1969 MS_U8 u8MUXGOPNum = 0;
1970 int i = 0;
1971
1972 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
1973 #if 0 //TO DO: To disable mixer mux
1974 MS_U16 u16val;
1975 if( regval & 0x0001) //MIXER GOP0 enable -> enable GOP1
1976 {
1977 u16val = (bEnable? TRUE: FALSE);
1978 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
1979 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
1980 }
1981 else //enable GOP0
1982 {
1983 u16val = (bEnable? TRUE: FALSE);
1984 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
1985 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1986 }
1987 #else
1988 if((regval&(GOP_BIT0|GOP_BIT1)) == (GOP_BIT0|GOP_BIT1))
1989 {
1990 if((gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10)) && (gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12)))
1991 {
1992 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
1993 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
1994 }
1995 }
1996 else if(regval&GOP_BIT0)
1997 {
1998 if(gopNum != ((regval&(GOP_BIT10|GOP_BIT11))>>10))
1999 {
2000 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
2001 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2002 }
2003 }
2004 else if(regval&GOP_BIT1) //gop1Enable
2005 {
2006 if(gopNum != ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2007 {
2008 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT1, GOP_BIT1);
2009 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2010 }
2011 }
2012 else //no one enable
2013 {
2014 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2015 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2016 }
2017 #endif
2018
2019 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //disable pseudo hsync
2020
2021 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2022
2023 HAL_GOP_GetMixerDst(pGOPHalLocal,&MixerDstType);
2024 if(MixerDstType == E_DRV_GOP_DST_MIXER2OP)
2025 {
2026 for (i=0; i<MAX_GOP_MUX - 1; i++) //mux3 not supported to OP
2027 {
2028 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &u8MUXGOPNum, (Gop_MuxSel)i);
2029 if (0x4==u8MUXGOPNum)
2030 {
2031 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, TRUE);
2032 }
2033 else
2034 {
2035 HAL_GOP_EnableSCNewAlphaMode(pGOPHalLocal, (Gop_MuxSel)i, FALSE);
2036 }
2037 }
2038 }
2039 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_EN_VFIL, GOP_MIXER_EN_VFIL_MASK);
2040 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, GOP_MIXER_VS_FLD_ON, GOP_MIXER_VS_FLD_ON_MASK);
2041 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_REG_DUMMY, GOP_BIT0, GOP_BIT0);
2042 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15); //Enable Mixer
2043
2044 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2045 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2046
2047
2048 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2049
2050 #if 0 /* PAL System*/
2051 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2052 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2053 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_HSTART_OFST, GOP_REG_WORD_MASK);
2054 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_VSTART_OFST, GOP_REG_WORD_MASK);
2055 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, 0x330, GOP_REG_WORD_MASK);
2056 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, 0x25D, GOP_REG_WORD_MASK);
2057 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2058 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_HS_DELAY, GOP_REG_WORD_MASK);
2059 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HS_PIPE, GOP_MIXER_PD, GOP_REG_WORD_MASK);
2060 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2061 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2062 #endif
2063 return GOP_SUCCESS;
2064
2065 }
2066
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)2067 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
2068 {
2069 MS_U16 u16val;
2070
2071 if (muxNum >= MAX_MIXER_MUX)
2072 {
2073 MS_CRITICAL_MSG(printf("\n[%s] not support mux%d in this chip version!!",__FUNCTION__, muxNum));
2074 return GOP_FAIL;
2075 }
2076
2077 if(muxNum==MIXER_MUX0Id) //Set GOP to mux0
2078 {
2079 u16val = (bEnable? TRUE: FALSE);
2080 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, u16val, GOP_BIT0);
2081 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<10), (GOP_BIT10|GOP_BIT11));
2082 }
2083 else //Set GOP to mux1
2084 {
2085 u16val = (bEnable? TRUE: FALSE);
2086 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (u16val<<1), GOP_BIT1);
2087 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, (gopNum<<12), (GOP_BIT12|GOP_BIT13));
2088 }
2089 return GOP_SUCCESS;
2090
2091 }
2092
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2093 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
2094 {
2095 MS_U32 u32bankoffset = 0;
2096 DRV_GOPDstType gopDstType = E_DRV_GOP_DST_IP0;
2097 MS_U16 regval = 0x0;
2098
2099 HAL_GOP_GetGOPDst(pGOPHalLocal, u8GOP, &gopDstType);
2100
2101 if(gopDstType == E_DRV_GOP_DST_MIXER2VE)
2102 {
2103
2104 _GetBnkOfstByGop(u8GOP, &u32bankoffset);
2105
2106 if(bEn)
2107 {
2108
2109 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT2, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2110 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)~GOP_BIT15, GOP_BIT15);
2111
2112 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2113
2114 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2115 {
2116 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2117 }
2118 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2119 {
2120 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD1_EN, (~BIT(2))|BIT(1), BIT(1)|BIT(2));
2121 }
2122 else
2123 {
2124 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2125 return GOP_FAIL;
2126 }
2127 }
2128 else
2129 {
2130 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, 0x0, GOP_BIT2); //alpha mode: 0 bypass mode: 1
2131 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoffset + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2132
2133 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIXER_CTRL, ®val);
2134
2135 if(u8GOP == ((regval&(GOP_BIT10|GOP_BIT11))>>10))
2136 {
2137 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2138 }
2139 else if(u8GOP == ((regval&(GOP_BIT12|GOP_BIT13))>>12))
2140 {
2141 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3B, GOP_VE_TVS_OSD1_EN, (~BIT(1))|BIT(2), BIT(1)|BIT(2));
2142 }
2143 else
2144 {
2145 printf("[%s][%d]GOP not exisit in VE mux\n",__FUNCTION__,__LINE__);
2146 return GOP_FAIL;
2147 }
2148 }
2149 }
2150 else
2151 {
2152 printf("[%s][%d]GOP not on Mixer2VE path\n",__FUNCTION__,__LINE__);
2153 return GOP_FAIL;
2154 }
2155
2156 return GOP_SUCCESS;
2157
2158 }
2159
HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2160 GOP_Result HAL_GOP_EnableSCNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2161 {
2162 MS_U16 bankTemp = 0;
2163 MS_U16 u16val = 0;
2164
2165 u16val = (bEnable? TRUE: FALSE);
2166 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2167 switch (muxNum) //Enable OP new alpha mode
2168 {
2169 case 0:
2170 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2171 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<1), GOP_BIT1);
2172 break;
2173 case 1:
2174 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2175 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<6), GOP_BIT6);
2176 break;
2177 case 2:
2178 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2179 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<8), GOP_BIT8);
2180 break;
2181 default:
2182 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2183 break;
2184 }
2185 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2186 return GOP_SUCCESS;
2187 }
2188
HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel muxNum,MS_BOOL bEnable)2189 GOP_Result HAL_GOP_EnableSCPerPixelNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, Gop_MuxSel muxNum, MS_BOOL bEnable)
2190 {
2191 MS_U16 bankTemp = 0;
2192 MS_U16 u16val = 0;
2193
2194 u16val = (bEnable? TRUE: FALSE);
2195 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &bankTemp);
2196 switch (muxNum) //Enable OP per pixel new alpha mode
2197 {
2198 case 0:
2199 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x2F, GOP_REG_WORD_MASK);
2200 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BLEND0_GOP_SWITCH, (u16val<<3), GOP_BIT3);
2201 break;
2202 case 1:
2203 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2204 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<14), GOP_BIT14);
2205 break;
2206 case 2:
2207 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, 0x10, GOP_REG_WORD_MASK);
2208 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_ALPHAMODE, (u16val<<15), GOP_BIT15);
2209 break;
2210 default:
2211 printf("\n [%s],This chip is not support this MUX value!\n",__FUNCTION__);
2212 break;
2213 }
2214 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, bankTemp, GOP_REG_WORD_MASK);
2215 return GOP_SUCCESS;
2216 }
2217
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2218 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2219 {
2220 MS_U32 u32GopIdx;
2221
2222 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2223 pGOPHalLocal->pHALShared = pHALShared;
2224
2225 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2226 {
2227 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2228 }
2229 pGOPHalLocal->pGopChipPro = &pHALShared->gopChipProperty;
2230 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2231 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2232 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2233 {
2234 }
2235
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2236 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2237 {
2238 MS_U8 u8Miu=0xff;
2239 MS_U8 u8GOP=0;
2240
2241 if (gwinid<GOP1_GwinIdBase) //gop0
2242 {
2243 u8GOP=0;
2244 }
2245 else if (gwinid<GOP2_GwinIdBase) //gop1
2246 {
2247 u8GOP=1;
2248 }
2249 else if (gwinid<GOP3_GwinIdBase) //gop2
2250 {
2251 u8GOP=2;
2252 }
2253 else if (gwinid<GOP4_GwinIdBase) //gop3
2254 {
2255 u8GOP=3;
2256 }
2257 else
2258 {
2259 return GOP_FAIL;
2260 }
2261
2262 u8Miu = HAL_GOP_GetMIUDst(pGOPHalLocal, u8GOP);
2263 if (u8Miu < MAX_GOP_MIUCOUNT)
2264 {
2265 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2266 }
2267 else
2268 {
2269 printf("[%s] ERROR GOP miu client( = %d)\n", __FUNCTION__, u8Miu);
2270 return GOP_FAIL;
2271 }
2272 return GOP_SUCCESS;
2273 }
2274
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2275 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2276 {
2277 MS_U8 u8Miu=0xff;
2278 MS_U16 u16RegVal_L=0;
2279 MS_U32 u32BnkOfst=0xFFFF;
2280 #ifdef GOP_MIU_GROUP2
2281 MS_U16 u16RegVal_H=0;
2282 #endif
2283
2284 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2285 {
2286 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2287 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2288
2289 u8Miu= u16RegVal_L& (GOP_BIT1|GOP_BIT0);
2290 }
2291 else
2292 {
2293 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal_L);
2294
2295 #ifdef GOP_MIU_GROUP2
2296 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2297 #endif
2298 switch (gopnum)
2299 {
2300 case 0:
2301 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2302 #ifdef GOP_MIU_GROUP2
2303 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2304 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2305 #else
2306 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2307 #endif
2308 break;
2309 case 1:
2310 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2311 #ifdef GOP_MIU_GROUP2
2312 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2313 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2314 #else
2315 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2316 #endif
2317 break;
2318
2319 case 2:
2320 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2321 #ifdef GOP_MIU_GROUP2
2322 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2323 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2324 #else
2325 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2326 #endif
2327 break;
2328
2329 case 3:
2330 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2331 #ifdef GOP_MIU_GROUP2
2332 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2333 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2334 #else
2335 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2336 #endif
2337 break;
2338 case 4:
2339 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
2340 #ifdef GOP_MIU_GROUP2
2341 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
2342 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
2343 #else
2344 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
2345 #endif
2346 break;
2347 default:
2348 return 0xff;
2349 break;
2350 }
2351
2352 if(u8Miu > MAX_GOP_MIUSEL )
2353 {
2354 printf("[%s] ERROR GOP miu client\n",__FUNCTION__);
2355 return 0xff;
2356 }
2357
2358 }
2359 return u8Miu;
2360 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2361 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2362 {
2363 MS_U16 u16Regval;
2364 MS_U32 u32pBankOffSet=0;
2365 GOP_Result ret;
2366
2367 if(u8gopNum >= MAX_GOP_SUPPORT)
2368 {
2369 printf("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8gopNum);
2370 *pGopDst = E_DRV_GOP_DST_INVALID;
2371 return GOP_FAIL;
2372 }
2373
2374 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2375 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2376
2377 switch (u16Regval&GOP_DST_MASK)
2378 {
2379 case 0:
2380 *pGopDst = E_DRV_GOP_DST_IP0;
2381 ret = GOP_SUCCESS;
2382 break;
2383 case 2:
2384 *pGopDst = E_DRV_GOP_DST_OP0;
2385 ret = GOP_SUCCESS;
2386 break;
2387 case 5:
2388 *pGopDst = E_DRV_GOP_DST_IP1;
2389 ret = GOP_SUCCESS;
2390 break;
2391 case 6:
2392 *pGopDst = E_DRV_GOP_DST_OP1;
2393 ret = GOP_SUCCESS;
2394 break;
2395 case 7:
2396 *pGopDst = E_DRV_GOP_DST_VE;
2397 ret = GOP_SUCCESS;
2398 break;
2399 case 8:
2400 *pGopDst = E_DRV_GOP_DST_DIP;
2401 ret = GOP_SUCCESS;
2402 break;
2403 default:
2404 *pGopDst = E_DRV_GOP_DST_INVALID;
2405 ret = GOP_FAIL;
2406 printf("[%s][%d] Not Define DST = %lx !!!\n", __FUNCTION__, __LINE__ , (u16Regval&GOP_DST_MASK));
2407 break;
2408 }
2409
2410 return ret;
2411
2412 }
2413
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2414 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2415 {
2416 MS_U16 muxValue=0;
2417 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2418 MS_BOOL bSC1_OP=0,bSC1_IP=0;
2419
2420 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2421
2422 switch(ipSelGop)
2423 {
2424 case MS_DRV_IP0_SEL_GOP0:
2425 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2426 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2427 u16RegVal |= GOP_BIT12;//mux0
2428 else
2429 u16RegVal |= GOP_BIT13;//mux1
2430 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2431 bSC1_OP =FALSE;
2432 bSC1_IP =FALSE;
2433 break;
2434
2435 case MS_DRV_IP0_SEL_GOP1:
2436 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2437 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2438 u16RegVal |= GOP_BIT12;//mux0
2439 else
2440 u16RegVal |= GOP_BIT13;//mux1
2441 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2442 bSC1_OP =FALSE;
2443 bSC1_IP =FALSE;
2444 break;
2445 case MS_DRV_IP0_SEL_GOP2:
2446 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2447 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2448 u16RegVal |= GOP_BIT12;//mux0
2449 else
2450 u16RegVal |= GOP_BIT13;//mux1
2451 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2452 bSC1_OP =FALSE;
2453 bSC1_IP =FALSE;
2454 break;
2455
2456 case MS_DRV_NIP_SEL_GOP0:
2457 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2458 {
2459 u16RegVal = ~GOP_BIT12;//mux0
2460 u16RegMsk = GOP_BIT12;
2461 }
2462 else
2463 {
2464 u16RegVal = ~GOP_BIT13;//mux1
2465 u16RegMsk = GOP_BIT13;
2466 }
2467 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2468 bSC1_OP =FALSE;
2469 bSC1_IP =FALSE;
2470 break;
2471
2472 case MS_DRV_NIP_SEL_GOP1:
2473 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2474 {
2475 u16RegVal = ~GOP_BIT12;//mux0
2476 u16RegMsk = GOP_BIT12;
2477 }
2478 else
2479 {
2480 u16RegVal = ~GOP_BIT13;//mux1
2481 u16RegMsk = GOP_BIT13;
2482 }
2483 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2484 bSC1_OP =FALSE;
2485 bSC1_IP =FALSE;
2486 break;
2487 case MS_DRV_NIP_SEL_GOP2:
2488 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2489 {
2490 u16RegVal = ~GOP_BIT12;//mux0
2491 u16RegMsk = GOP_BIT12;
2492 }
2493 else
2494 {
2495 u16RegVal = ~GOP_BIT13;//mux1
2496 u16RegMsk = GOP_BIT13;
2497 }
2498 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2499 bSC1_OP =FALSE;
2500 bSC1_IP =FALSE;
2501 break;
2502 case MS_DRV_MVOP_SEL:
2503 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2504 u16RegVal |= GOP_BIT12; //mux0
2505 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2506 bSC1_OP =FALSE;
2507 bSC1_IP =FALSE;
2508 break;
2509 case MS_DRV_SC1OP_SEL:
2510 bSC1_OP =TRUE;
2511 bSC1_IP =FALSE;
2512 break;
2513 case MS_DRV_IP1_SEL:
2514 bSC1_OP =FALSE;
2515 bSC1_IP =TRUE;
2516 break;
2517 default:
2518 printf("[%s] ERROR invalid source select\n",__FUNCTION__);
2519 break;
2520 }
2521 if(0 != u16RegMsk)
2522 {
2523 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2524 }
2525
2526 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bSC1_OP<<14, GOP_BIT14);
2527 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, !bSC1_IP<<11, GOP_BIT11);
2528 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, bSC1_IP<<12, GOP_BIT12);
2529
2530 }
2531
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2532 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2533 {
2534 return GOP_FUN_NOT_SUPPORTED;
2535 }
2536
2537
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2538 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2539 {
2540 return GOP_FUN_NOT_SUPPORTED;
2541 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2542 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2543 {
2544 return GOP_FUN_NOT_SUPPORTED;
2545 }
2546
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2547 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2548 {
2549 return GOP_FUN_NOT_SUPPORTED;
2550 }
2551
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2552 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2553 {
2554 if(u32mode == E_GOP_PAL)
2555 {
2556 /* PAL System*/
2557 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x73;
2558 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0x13;
2559 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, ~GOP_BIT2, GOP_BIT2);
2560 }
2561 else if(u32mode == E_GOP_NTSC)
2562 {
2563 /* NTSC System*/
2564 pGOPHalLocal->pGopChipPro->GOP_VE_PD = 0x65;
2565 pGOPHalLocal->pGopChipPro->GOP_VE_V_Offset = 0xF;
2566 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_BOT_HS, GOP_BIT2, GOP_BIT2);
2567 }
2568 return GOP_SUCCESS;
2569 }
2570
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2571 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2572 {
2573
2574 if(u32mode == E_GOP_PAL)
2575 {
2576 /* PAL System*/
2577 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2578 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2579 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_PAL_HSTART_OFST, GOP_REG_WORD_MASK);
2580 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_PAL_VSTART_OFST, GOP_REG_WORD_MASK);
2581 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_PAL_WIDTH, GOP_REG_WORD_MASK);
2582 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_PAL_HEIGHT, GOP_REG_WORD_MASK);
2583 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_PAL_HTOTAL-1, GOP_REG_WORD_MASK);
2584 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_PAL_HS_DELAY, GOP_REG_WORD_MASK);
2585 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2586
2587 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2588 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2589 }
2590 else if(u32mode == E_GOP_NTSC)
2591 {
2592 /* NTSC System*/
2593 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2594 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2595 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, GOP_VE_NTSC_HSTART_OFST, GOP_REG_WORD_MASK);
2596 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, GOP_VE_NTSC_VSTART_OFST, GOP_REG_WORD_MASK);
2597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, GOP_VE_NTSC_WIDTH, GOP_REG_WORD_MASK);
2598 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, GOP_VE_NTSC_HEIGHT, GOP_REG_WORD_MASK);
2599 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, GOP_VE_NTSC_HTOTAL, GOP_REG_WORD_MASK);
2600 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, GOP_VE_NTSC_HS_DELAY, GOP_REG_WORD_MASK);
2601
2602 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2603
2604 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2605 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2606 }
2607 else if(u32mode == E_GOP_CUSTOM)
2608 {
2609 return GOP_FUN_NOT_SUPPORTED;
2610 /*
2611 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT0, GOP_BIT0);
2612 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_VE_ENABLE_OSD, GOP_BIT2, GOP_BIT2);
2613 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHST, pTM->hstart, GOP_REG_WORD_MASK);
2614 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVST, pTM->vstart, GOP_REG_WORD_MASK);
2615 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FHEND, pTM->hend, GOP_REG_WORD_MASK);
2616 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_FVEND, pTM->vend, GOP_REG_WORD_MASK);
2617 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HTT, pTM->htotal, GOP_REG_WORD_MASK);
2618 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_HS_DELAY, pTM->hsyncdelay, GOP_REG_WORD_MASK);
2619
2620 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_HS_PIPE, pGOPHalLocal->pGopChipPro->GOP_MIXER_PD, GOP_REG_WORD_MASK);
2621
2622 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT7, GOP_BIT7); //enable pseudo hsync
2623 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT15, GOP_BIT15);
2624 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_CTRL, GOP_BIT0, GOP_BIT0);
2625 */
2626 }
2627 else if(u32mode == E_GOP_CUSTOM_OP)
2628 {
2629 return GOP_FUN_NOT_SUPPORTED;
2630 }
2631 return GOP_SUCCESS;
2632 }
2633
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2634 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2635 {
2636 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIXER_VE, bEn, GOP_MIXER_EN_VFIL_MASK);
2637 return GOP_SUCCESS;
2638 }
2639
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2640 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2641 {
2642 //fix me need to modify tile_32bpp mode in 64b_bus
2643 if(E_DRV_GOP_TILE_DATA_16BPP == tilemode)
2644 {
2645 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2646 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2647 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2648 ~GOP_BIT7, GOP_BIT7);
2649
2650 }
2651 else if(E_DRV_GOP_TILE_DATA_32BPP == tilemode)
2652 {
2653 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_GWIN0_CTRL(u8win), \
2654 bEnable?GOP_BIT15:~GOP_BIT15, GOP_BIT15);
2655 HAL_GOP_Write16Reg(pGOPHalLocal, HAL_GOP_BankOffset(pGOPHalLocal)+GOP_4G_DRAM_FADE(u8win), \
2656 ~GOP_BIT7, GOP_BIT7);
2657 }
2658 else
2659 {
2660 return GOP_FUN_NOT_SUPPORTED;
2661 }
2662
2663 return GOP_SUCCESS;
2664
2665 }
2666
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2667 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2668 {
2669 MS_U32 u32BankOffSet =0;
2670
2671 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2672
2673 if (bEn)
2674 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2675 else
2676 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2677
2678 return GOP_SUCCESS;
2679 }
2680
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2681 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2682 {
2683 MS_U32 u32BankOffSet =0;
2684
2685 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2686
2687 if (bEn)
2688 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2689 else
2690 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2691
2692 return GOP_SUCCESS;
2693 }
2694
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2695 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2696 {
2697 MS_U16 u16Val =0x0;
2698 if (u8win < GOP1_GwinIdBase)
2699 {
2700 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2701 *pEnable = (MS_BOOL)(u16Val>>15);
2702 }
2703 else if (u8win < GOP2_GwinIdBase)
2704 {
2705 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2706 *pEnable = (MS_BOOL)(u16Val>>15);
2707 }
2708 else if (u8win < GOP3_GwinIdBase)
2709 {
2710 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2711 *pEnable = (MS_BOOL)(u16Val>>15);
2712 }
2713 else if (u8win < GOP4_GwinIdBase)
2714 {
2715 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2716 *pEnable = (MS_BOOL)(u16Val>>15);
2717 }
2718 else if (u8win < GOP5_GwinIdBase)
2719 {
2720 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2721 *pEnable = (MS_BOOL)(u16Val>>15);
2722 }
2723 else
2724 {
2725 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2726 return GOP_INVALID_PARAMETERS;
2727 }
2728
2729 return GOP_SUCCESS;
2730 }
2731
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2732 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2733 {
2734 MS_U16 u16Val = bEnable << 15;
2735 if (u8win < GOP1_GwinIdBase)
2736 {
2737 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2738 }
2739 else if (u8win < GOP2_GwinIdBase)
2740 {
2741 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2742 }
2743 else if (u8win < GOP3_GwinIdBase)
2744 {
2745 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2746 }
2747 else if (u8win < GOP4_GwinIdBase)
2748 {
2749 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2750 }
2751 else if (u8win < GOP5_GwinIdBase)
2752 {
2753 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2754 }
2755 else
2756 {
2757 printf("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2758 return GOP_INVALID_PARAMETERS;
2759 }
2760 return GOP_SUCCESS;
2761 }
2762
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2763 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2764 {
2765 MS_U16 u16Reg = 0;
2766 MS_U32 u32WordBase = 0;
2767 MS_U32 u32BankOffSet=0;
2768
2769 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2770
2771 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2772
2773 if(u16Reg & GOP_BIT7)
2774 {
2775 u32WordBase = 1;
2776 }
2777 else
2778 {
2779 u32WordBase = GOP_WordUnit;
2780 }
2781
2782 u32SubAddr /= u32WordBase;
2783
2784 if(u8GOP == E_GOP2)
2785 {
2786 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2787 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2788 }
2789 else if(u8GOP == E_GOP3)
2790 {
2791 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2792 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2793
2794 }
2795 else if(u8GOP == E_GOP4)
2796 {
2797 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2798 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2799 }
2800 else if(u8GOP == E_GOP1)
2801 {
2802 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2803 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2804 }
2805 else //gop0
2806 {
2807 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2808 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2809 }
2810
2811 return GOP_SUCCESS;
2812
2813 }
2814
2815 //------------------------------------------------------------------------------
2816 /// Set VE output with OSD
2817 /// @return none
2818 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2819 GOP_Result HAL_GOP_VE_SetOSDEnable(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2820 {
2821 if(eOSD == EN_OSD_0)
2822 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bEnable<<14, GOP_BIT14);
2823
2824 if(eOSD == EN_OSD_1)
2825 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_GOPEN, bEnable<<15, GOP_BIT15);
2826 return GOP_SUCCESS;
2827 }
2828
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2829 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2830 {
2831 /*
2832 MS_U32 u32BankOffSet=0;
2833 _GetBnkOfstByGop(gopNum, &u32BankOffSet);
2834
2835 //Direct to SC1 OP
2836 HAL_GOP_SetIPSel2SC(pGOPHalLocal, MS_DRV_SC1OP_SEL);
2837 HAL_GOP_SetGOPClk(pGOPHalLocal, gopNum, E_DRV_GOP_DST_OP1);
2838 HAL_GOP_GWIN_SetMUX(pGOPHalLocal,gopNum,E_GOP_OP1_MUX);
2839 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, (MS_U16)~GOP_BIT1, GOP_BIT1);
2840 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, (MS_U16)GOP_BIT15, GOP_BIT15);
2841 */
2842 return GOP_SUCCESS;
2843 }
2844
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2845 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2846 {
2847 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2848 MS_U16 u16MVOPMirrorCfg = 0;
2849 MS_U16 u16ScalerMirrorCfg = 0;
2850
2851 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2852 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2853 if(bHorizontal) // Horizontal
2854 {
2855 if(u16MVOPMirrorCfg & GOP_BIT1)
2856 {
2857 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2858 }
2859 else if(u16ScalerMirrorCfg & GOP_BIT12)
2860 {
2861 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2862 }
2863 }
2864 else //vertical
2865 {
2866 if(u16MVOPMirrorCfg & GOP_BIT0)
2867 {
2868 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2869 }
2870 else if(u16ScalerMirrorCfg & GOP_BIT13)
2871 {
2872 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2873 }
2874 }
2875 return enMirrorType;
2876 }
2877
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2878 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2879 {
2880 MS_U32 u32BankOffSet =0;
2881
2882 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2883 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2884 return GOP_SUCCESS;
2885 }
2886
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2887 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2888 {
2889 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2890 MS_U16 u16Val=0;
2891 MS_U16 u16Mux[MAX_GOP_MUX];
2892
2893 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2894 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2895 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2896 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2897 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2898
2899 switch(u8GOP)
2900 {
2901 case E_GOP0:
2902 case E_GOP1:
2903 case E_GOP2:
2904 case E_GOP3:
2905 case E_GOP4:
2906 for(i=0; i<MAX_GOP_MUX; i++)
2907 {
2908 if(u8GOP == u16Mux[i])
2909 {
2910 eGopMux = i;
2911 if(eGopMux == 4)
2912 {
2913 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2914 }
2915 else
2916 {
2917 FRCMuxOffset = 12 + eGopMux;
2918 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2919 }
2920 }
2921 }
2922 break;
2923 default:
2924 return GOP_FAIL;
2925 break;
2926 }
2927
2928 return GOP_SUCCESS;
2929 }
2930
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2931 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2932 {
2933 return GOP_FUN_NOT_SUPPORTED;
2934 }
2935
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2936 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2937 {
2938 return GOP_FUN_NOT_SUPPORTED;
2939 }
2940
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2941 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2942 {
2943 return GOP_FUN_NOT_SUPPORTED;
2944 }
2945
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2946 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2947 {
2948 MS_U32 u32BankOffSet = 0;
2949 MS_BOOL bInverse = 0xFF;
2950 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
2951
2952 switch (eDstType)
2953 {
2954 case E_DRV_GOP_DST_IP0:
2955 case E_DRV_GOP_DST_IP1:
2956 case E_DRV_GOP_DST_OP1:
2957 bInverse = TRUE;
2958 break;
2959 default:
2960 bInverse = FALSE;
2961 break;
2962 }
2963 if(bInverse == TRUE)
2964 {
2965 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 1<<4, 0x10);
2966 }
2967 else
2968 {
2969 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, 0<<4, 0x10);
2970 }
2971 return GOP_SUCCESS;
2972 }
2973
2974 /********************************************************************************/
2975 ///Test Pattern
2976 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)2977 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
2978 {
2979 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
2980 {
2981 return GOP_SUCCESS;
2982 }
2983 else
2984 {
2985 return GOP_FAIL;
2986 }
2987
2988 }
2989
2990
2991 /********************************************************************************/
2992 ///GOP Scaling down (internal)
2993 /********************************************************************************/
2994
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2995 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
2996 {
2997 MS_U16 u16MG_mask=0;
2998 MS_U16 u16Val=0;
2999 MS_U16 u16LB_mask=0;
3000 MS_U16 u16enable=0;
3001
3002 if(u8GOP==0)
3003 {
3004 u16MG_mask=CKG_GOPG0_MG_MASK;
3005 u16Val=GOP_BIT2;
3006 u16LB_mask=CKG_LB_SRAM1_MASK;
3007 u16enable=GOP_BIT2;
3008 }
3009 else if(u8GOP==2)
3010 {
3011 u16MG_mask=CKG_GOPG2_MG_MASK;
3012 u16Val=GOP_BIT6;
3013 u16LB_mask=CKG_LB_SRAM2_MASK;
3014 u16enable=GOP_BIT6;
3015 }
3016 else
3017 {
3018 printf("[%s] Error message GOP not support scaling down!!",__FUNCTION__);
3019 return GOP_FAIL;
3020 }
3021 if(bEn==TRUE)
3022 {
3023 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, u16Val, u16MG_mask);
3024 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, u16enable, u16LB_mask);
3025 }
3026 else
3027 {
3028 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, u16MG_mask);
3029 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, u16LB_mask);
3030 }
3031 return TRUE;
3032 }
3033
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3034 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3035 {
3036 MS_U32 ratio;
3037 MS_U32 u32BankOffSet=0xFFFF;
3038 MS_U16 u16VScalReg;
3039
3040 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3041 if(bEnable ==TRUE)
3042 {
3043 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, &u16VScalReg);
3044 if( u16VScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
3045 {
3046 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, 0x1000 , GOP_REG_WORD_MASK);
3047 printf("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
3048 }
3049 //Set scaling down ratio
3050 ratio = (dst * 0x100000) / src;
3051 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, ratio);
3052 }
3053 else
3054 {
3055 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, 0);
3056 }
3057
3058 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3059 {
3060 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3061 }
3062 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, bEnable , GOP_BIT0);
3063 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_H_OUTPUTSIZE, dst, GOP_REG_WORD_MASK);
3064
3065 return GOP_SUCCESS;
3066
3067 }
3068
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3069 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3070 {
3071 MS_U32 ratio =0;
3072 MS_U32 u32BankOffSet=0xFFFF;
3073 MS_U16 u16HScalReg;
3074
3075 if(pGOPHalLocal->pGopChipPro->bScalingDownSupport ==FALSE)
3076 {
3077 return GOP_FUN_NOT_SUPPORTED;
3078 }
3079
3080 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3081 if(bEnable ==TRUE)
3082 {
3083 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, &u16HScalReg);
3084 if( u16HScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
3085 {
3086 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, 0x1000 , GOP_REG_WORD_MASK);
3087 printf("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
3088 }
3089 ratio = (dst * 0x100000) / src;
3090 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, ratio);
3091 }
3092 else
3093 {
3094 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, 0);
3095 }
3096
3097 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3098 {
3099 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3100 }
3101 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, (bEnable<<4) , GOP_BIT4);
3102 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SVM_VEND, dst, GOP_REG_WORD_MASK);
3103
3104 return GOP_SUCCESS;
3105
3106 }
3107
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)3108 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
3109 {
3110 MS_U32 u32BankOffSet=0;
3111
3112 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3113 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
3114 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
3115 return GOP_SUCCESS;
3116 }
3117
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)3118 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
3119 {
3120 MS_U32 u32BankOffSet=0;
3121 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3122
3123 if (u32GopIdx < MAX_GOP_SUPPORT)
3124 {
3125 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
3126 }
3127 else
3128 {
3129 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3130 *u16Val = 0;
3131 }
3132 return GOP_SUCCESS;
3133 }
3134
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)3135 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
3136 {
3137 MS_U32 u32BankOffSet=0;
3138 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3139
3140 if (u32GopIdx < MAX_GOP_SUPPORT)
3141 {
3142 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
3143 }
3144 else
3145 {
3146 printf("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3147 }
3148 return GOP_SUCCESS;
3149 }
3150
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)3151 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
3152 {
3153 switch(u32PowerState)
3154 {
3155 case E_POWER_SUSPEND:
3156 {
3157 //CLK
3158 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
3159 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
3160 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
3161 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
3162 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
3163 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
3164
3165 //SRAM
3166 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
3167 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
3168 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
3169
3170 //XC
3171 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
3172 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
3173 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
3174 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
3175 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
3176 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
3177 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
3178 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
3179 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
3180 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
3181 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
3182 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
3183 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
3184 }
3185 break;
3186 case E_POWER_RESUME:
3187 {
3188 //CLK
3189 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
3190 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
3191 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
3192 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
3193 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
3194 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
3195
3196 //SRAM
3197 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
3198 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
3199 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
3200
3201 //XC
3202 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3203 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3204 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3205 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3206 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3207 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3208 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3209 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3210 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3211 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3212 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3213 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3214 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3215 }
3216 break;
3217 default:
3218 break;
3219 }
3220 return GOP_SUCCESS;
3221 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3222 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3223 {
3224 return GOP_FUN_NOT_SUPPORTED;
3225 }
3226
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3227 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3228 {
3229 MS_U32 u32BankOffSet=0xFFFF;
3230
3231 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3232 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3233
3234 return GOP_SUCCESS;
3235 }
3236
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3237 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3238 {
3239 MS_U32 u32BankOffSet=0xFFFF;
3240 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3241
3242 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3243 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3244
3245 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3246 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3247
3248 return GOP_SUCCESS;
3249 }
3250
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3251 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3252 {
3253 MS_U32 u32BankOffSet=0xFFFF;
3254 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3255
3256 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3257 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3258
3259 return GOP_SUCCESS;
3260 }
3261
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3262 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3263 {
3264 MS_U32 u32BankOffSet=0xFFFF;
3265 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3266
3267 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN MIU Select
3268 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN_3D MIU Select
3269
3270 return GOP_SUCCESS;
3271 }
3272
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3273 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3274 {
3275 GOP_Result ret = GOP_SUCCESS;
3276
3277 switch(u8GOP)
3278 {
3279 case E_GOP0:
3280 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3281 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3282 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VSTR(u8win), vstart, GOP_REG_WORD_MASK);
3283 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VEND(u8win), vend, GOP_REG_WORD_MASK);
3284 break;
3285
3286 case E_GOP1:
3287 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3288 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3289 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VSTR(u8win), vstart, GOP_REG_WORD_MASK); // 1 pixel
3290 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VEND(u8win), vend, GOP_REG_WORD_MASK); // 1 pixel
3291 break;
3292
3293 case E_GOP2:
3294 case E_GOP3:
3295 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HSTR:GOP_1GX_HSTR, hstart, GOP_REG_WORD_MASK); // word pixels
3296 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HEND:GOP_1GX_HEND, hend, GOP_REG_WORD_MASK); // word pixels
3297 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VSTR:GOP_1GX_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3298 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VEND:GOP_1GX_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3299 break;
3300
3301 case E_GOP4:
3302 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, hstart, GOP_REG_WORD_MASK);
3303 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, hend, GOP_REG_WORD_MASK);
3304 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3305 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3306 break;
3307
3308 case E_GOP5:
3309 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS1_HSTR, hstart, GOP_REG_WORD_MASK);
3310 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS1_HEND, hend, GOP_REG_WORD_MASK);
3311 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS1_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3312 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS1_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3313 break;
3314
3315 default:
3316 printf("invalid Gwin number:%d\n",u8win);
3317 break;
3318 }
3319
3320 return ret;
3321 }
3322
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3323 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3324 {
3325 MS_U32 u32BankOffSet=0xFFFF;
3326 MS_U16 mask_shift=0xFF;
3327
3328 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3329 switch(u8GOP)
3330 {
3331 case E_GOP0:
3332 mask_shift = GOP_MIU_CLIENT_GOP0;
3333 break;
3334 case E_GOP1:
3335 mask_shift = GOP_MIU_CLIENT_GOP1;
3336 break;
3337 case E_GOP2:
3338 mask_shift = GOP_MIU_CLIENT_GOP2;
3339 break;
3340 case E_GOP3:
3341 mask_shift = GOP_MIU_CLIENT_GOP3;
3342 break;
3343 case E_GOP4:
3344 mask_shift = GOP_MIU_CLIENT_GOP4;
3345 break;
3346 case E_GOP5:
3347 mask_shift = GOP_MIU_CLIENT_GOP5;
3348 break;
3349 case E_GOP_Dwin:
3350 mask_shift = GOP_MIU_CLIENT_DWIN;
3351 break;
3352 default:
3353 mask_shift = 0xFF;
3354 MS_CRITICAL_MSG(printf("ERROR gop miu client\n"));
3355 break;
3356 }
3357
3358 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3359 #ifdef GOP_MIU_GROUP2
3360 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3361 #endif
3362
3363 return GOP_SUCCESS;
3364 }
3365
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3366 GOP_Result Hal_SetCropWindow(
3367 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3368 MS_U8 u8GOP,
3369 EN_GOP_CROP_CTL crop_mode
3370 )
3371 {
3372 return GOP_SUCCESS;
3373 }
3374
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)3375 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
3376 {
3377 MS_U16 reg_val = 0;
3378
3379 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_USR_INTERLACE, ®_val);
3380 if(reg_val & BIT(1))
3381 *bInterlace = TRUE;
3382 else
3383 *bInterlace = FALSE;
3384 return GOP_SUCCESS;
3385 }
3386
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)3387 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
3388 {
3389 *pbHDREnable= FALSE;
3390 return GOP_FUN_NOT_SUPPORTED;
3391 }
3392
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3393 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3394 {
3395 if(u8GOP==0)
3396 {
3397 *u8Core=0;
3398 }
3399 else
3400 {
3401 *u8Core=1;
3402 }
3403 return GOP_SUCCESS;
3404 }
3405
3406 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3407 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3408 {
3409 MS_U16 u16xcSubbank=0;
3410 MS_U32 bank;
3411 MS_U32 direct_addr;
3412
3413 switch (u32addr & 0xFF00)
3414 {
3415 case GOP_REG_BASE:
3416 {
3417 bank = (u32addr & 0xFF0000) >> 8;
3418 #if 0 //for GOP4
3419 if(bank==0xE00)//GOP4: 0x121B00
3420 {
3421 bank=GOP_REG_GOP4_BK_OFFSET;
3422 }
3423 else if(bank==0xF00)//GWIN4: 0x121E00
3424 {
3425 bank=GOP_REG_GOP4_GW_OFFSET;
3426 }
3427 else if(bank==0x1000) //GOP4_ST
3428 {
3429 bank=GOP_REG_GOP4_ST_OFFSET;
3430 }
3431 #endif
3432 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3433
3434 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3435 cmdq_struct[(*number)].destionation_value = u16val;
3436 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3437 cmdq_struct[(*number)].operation = 0x57;
3438 (*number)++;
3439 break;
3440 }
3441 case SC1_REG_BASE:
3442 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3443 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3444
3445 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3446 cmdq_struct[(*number)].destionation_value = u16val;
3447 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3448 cmdq_struct[(*number)].operation = 0x57;
3449 (*number)++;
3450 break;
3451 case GE_REG_BASE:
3452 case CKG_REG_BASE:
3453 case MIU_REG_BASE:
3454 {
3455 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3456 cmdq_struct[(*number)].destionation_value = u16val;
3457 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3458 cmdq_struct[(*number)].operation = 0x57;
3459 (*number)++;
3460 break;
3461 }
3462 #ifdef GOP_MIU_GROUP2
3463 case (MIU2_REG_BASE & 0xFF00):
3464 {
3465 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3466
3467 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3468 cmdq_struct[(*number)].destionation_value = u16val;
3469 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3470 cmdq_struct[(*number)].operation = 0x57;
3471 (*number)++;
3472 break;
3473 }
3474 #endif
3475 default:
3476 {
3477 //Gop lib current do not support this HW ip base
3478 MS_ASSERT(0);
3479 break;
3480 }
3481
3482 }
3483 return GOP_SUCCESS;
3484 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3485 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3486 {
3487 MS_U32 u32BankOffSet=0xFFFF;
3488 MS_U16 u16RegVal1 = 0;
3489 MS_BOOL bCheckValidGop = FALSE;
3490 MS_U8 u8CheckTimeCnt = 0;
3491 MS_U8 u8CurrentCmdGop = 0;
3492
3493 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3494 {
3495 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3496 {
3497 u8CurrentCmdGop = 0;
3498 }
3499 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3500 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3501 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3502 {
3503 bCheckValidGop = FALSE;
3504 }
3505 else
3506 {
3507 bCheckValidGop = TRUE;
3508 break;
3509 }
3510
3511 // if current gop not init, use next gop instead, check order 0->2->1->3
3512 switch (u8CurrentCmdGop)
3513 {
3514 case 0:
3515 u8CurrentCmdGop = 2;
3516 break;
3517 case 1:
3518 u8CurrentCmdGop = 0;
3519 break;
3520 case 2:
3521 u8CurrentCmdGop = 3;
3522 break;
3523 case 3:
3524 u8CurrentCmdGop = 1;
3525 break;
3526 default:
3527 u8CurrentCmdGop = 0;
3528 break;
3529 }
3530 u8CheckTimeCnt++;
3531 }
3532 if (!bCheckValidGop)
3533 {
3534 printf("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3535 }
3536
3537 *u32GopIdx = u8CurrentCmdGop;
3538 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3539 (*number)++;
3540 return GOP_SUCCESS;
3541 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3542 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3543 {
3544 CH_Struct ch_fire;
3545 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3546 MS_U16 u16ret = 0,u16ret1 = 0;
3547 int i = 0;
3548
3549
3550 _GetBnkOfstByGop(0, &u32BankOffSet);
3551 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3552 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3553 #if 0 //for Debug
3554 for(i=0;i<(*number);i++)
3555 {
3556 printf("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3557 }
3558 #endif
3559 ch_fire.Command_Number = *number;
3560 ch_fire.Pointer_To_CAFArray = target;
3561 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3562 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3563 {
3564 Receive_Return_Value = 0;
3565 MDrv_CMDQ_Printf_Crash_Command();
3566 }
3567
3568 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3569 MsOS_DelayTask(1);
3570 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3571 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3572
3573 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3574 timer1 = MsOS_GetSystemTime();
3575 timer2 = MsOS_GetSystemTime();
3576 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3577 {
3578 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3579 MsOS_DelayTask(1);
3580 timer2 = MsOS_GetSystemTime();
3581 }
3582 if(u16ret1 != (u16ret+1))
3583 {
3584 printf("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3585 MDrv_CMDQ_Printf_Crash_Command();
3586 }
3587 return GOP_SUCCESS;
3588 }
3589
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3590 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3591 {
3592 CAF_Struct fire_struct[24];
3593 MS_U32 u32BankOffSet;
3594 MS_U32 number = 0;
3595 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3596 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3597 MS_U32 fireGOP=0;
3598
3599 _GetBnkOfstByGop(gop, &u32BankOffSet);
3600
3601 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3602 #ifdef GOP_MIU_GROUP2
3603 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3604 #endif
3605 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3606 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3607
3608 switch(gop)
3609 {
3610 case E_GOP0:
3611 {
3612 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3613 break;
3614 }
3615 case E_GOP1:
3616 {
3617 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3618 break;
3619 }
3620 case E_GOP2:
3621 {
3622 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3623 break;
3624 }
3625 case E_GOP3:
3626 {
3627 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3628 break;
3629 }
3630 case E_GOP4:
3631 {
3632 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3633 break;
3634 }
3635 default:
3636 {
3637 MS_ASSERT(0);
3638 break;
3639 }
3640 }
3641 if(bMIUSelect[gop] == TRUE)
3642 {
3643 if(u16MIUSelect[gop] == 0)
3644 {
3645 u16RegVal1 &= ~(1<<u16MiuClient);
3646 u16RegVal3 &= ~(1<<u16MiuClient);
3647 }
3648 else if(u16MIUSelect[gop] == 1)
3649 {
3650 u16RegVal1 |= (1<<u16MiuClient);
3651 u16RegVal3 &= ~(1<<u16MiuClient);
3652 }
3653 else if(u16MIUSelect[gop] == 2)
3654 {
3655 u16RegVal1 &= ~(1<<u16MiuClient);
3656 u16RegVal3 |= (1<<u16MiuClient);
3657 }
3658 else if(u16MIUSelect[gop] == 3)
3659 {
3660 u16RegVal1 |= (1<<u16MiuClient);
3661 u16RegVal3 |= (1<<u16MiuClient);
3662 }
3663 bMIUSelect[gop] = FALSE;
3664 }
3665
3666 if(bAFBCMIUSelect[gop] == TRUE)
3667 {
3668 bAFBCMIUSelect[gop] = FALSE;
3669 }
3670 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3671 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3672 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3673
3674 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
3675 {
3676 if(bAFBCMIUSelect[gop] == TRUE)
3677 {
3678 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3679 bAFBCMIUSelect[gop] = FALSE;
3680 }
3681 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3682 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
3683 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
3684 }
3685 #ifdef GOP_MIU_GROUP2
3686 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3687 #endif
3688
3689 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3690 return GOP_SUCCESS;
3691 }
3692
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)3693 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
3694 {
3695 CAF_Struct fire_struct[24];
3696 MS_U32 u32BankOffSet=0;
3697 MS_U32 number = 0;
3698 MS_U8 gop=0;
3699 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
3700 MS_U16 u16RegMiu=0,u16RegCoreEna=0;
3701 MS_U8 u8Core=0;
3702 MS_U32 fireGOP=0;
3703 MS_BOOL bCoreTrig[AFBC_CORE_COUNT];
3704 MS_BOOL bCoreMiu[AFBC_CORE_COUNT];
3705 MS_U8 i=0;
3706
3707 for(i=0;i<AFBC_CORE_COUNT;i++)
3708 {
3709 bCoreTrig[i]=FALSE;
3710 }
3711
3712
3713 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3714 #ifdef GOP_MIU_GROUP2
3715 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3716 #endif
3717 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3718
3719 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
3720 {
3721 switch(gop)
3722 {
3723 case E_GOP0:
3724 {
3725 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3726 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP0, &u8Core);
3727 bCoreTrig[u8Core]=TRUE;
3728 break;
3729 }
3730 case E_GOP1:
3731 {
3732 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3733 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP1, &u8Core);
3734 bCoreTrig[u8Core]=TRUE;
3735 break;
3736 }
3737 case E_GOP2:
3738 {
3739 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3740 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP2, &u8Core);
3741 bCoreTrig[u8Core]=TRUE;
3742 break;
3743 }
3744 case E_GOP3:
3745 {
3746 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3747 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP3, &u8Core);
3748 bCoreTrig[u8Core]=TRUE;
3749 break;
3750 }
3751 case E_GOP4:
3752 {
3753 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3754 HAL_GOP_AFBC_GetCore(pGOPHalLocal, (MS_U8)E_GOP4, &u8Core);
3755 bCoreTrig[u8Core]=TRUE;
3756 break;
3757 }
3758 default:
3759 {
3760 continue;
3761 }
3762 }
3763 if( ( u16GopMask & (1<<gop) ) )
3764 {
3765 _GetBnkOfstByGop(gop, &u32BankOffSet);
3766 if(bMIUSelect[gop] == TRUE)
3767 {
3768 if(u16MIUSelect[gop] == 0)
3769 {
3770 u16RegVal1 &= ~(1<<u16MiuClient);
3771 u16RegVal3 &= ~(1<<u16MiuClient);
3772 }
3773 else if(u16MIUSelect[gop] == 1)
3774 {
3775 u16RegVal1 |= (1<<u16MiuClient);
3776 u16RegVal3 &= ~(1<<u16MiuClient);
3777 }
3778 else if(u16MIUSelect[gop] == 2)
3779 {
3780 u16RegVal1 &= ~(1<<u16MiuClient);
3781 u16RegVal3 |= (1<<u16MiuClient);
3782 }
3783 else if(u16MIUSelect[gop] == 3)
3784 {
3785 u16RegVal1 |= (1<<u16MiuClient);
3786 u16RegVal3 |= (1<<u16MiuClient);
3787 }
3788 bMIUSelect[gop] = FALSE;
3789 }
3790 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3791 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
3792 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
3793 }
3794
3795 if(bAFBCMIUSelect[gop] == TRUE)
3796 {
3797 HAL_GOP_AFBC_GetCore(pGOPHalLocal, gop, &u8Core);
3798 bCoreMiu[gop]=TRUE;
3799 bAFBCMIUSelect[gop] = FALSE;
3800 }
3801 }
3802
3803 for(i=0;i<AFBC_CORE_COUNT;i++)
3804 {
3805 if(g_GopChipPro.bAFBC_Merge_GOP_Trig == FALSE)
3806 {
3807 if(bCoreTrig[i]==TRUE)
3808 {
3809 if((g_GopChipPro.bAFBCMIUSelDoubleBuffer == FALSE)&&(bCoreMiu[i]==TRUE))
3810 {
3811 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
3812 }
3813 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
3814 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
3815 }
3816 }
3817 }
3818
3819 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
3820 #ifdef GOP_MIU_GROUP2
3821 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
3822 #endif
3823 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
3824 return GOP_SUCCESS;
3825 }
3826 #endif
3827
3828