1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 #include "MsCommon.h"
96 #ifndef MSOS_TYPE_LINUX_KERNEL
97 #include <string.h>
98 #endif
99 #include "MsTypes.h"
100 #include "halGOP.h"
101 #include "regGOP.h"
102 #include "halCHIP.h"
103 #include "drvSYS.h"
104
105 //------------------------------------------------------------------------------
106 // Driver Compiler Options
107 //------------------------------------------------------------------------------
108
109
110 //------------------------------------------------------------------------------
111 // Local Defines
112 //------------------------------------------------------------------------------
113 #define RIU ((unsigned short volatile *) pGOPHalLocal->va_mmio_base)
114 #define GOP_WRITE2BYTE(addr, val) { RIU[addr] = val; }
115 #define GOP_READ2BYTE(addr) RIU[addr]
116 #define GOP_BANK_MASK 0x1FUL
117 #define GOP_DST_MASK 0xFUL
118
119 // Debug Log
120 #include "ULog.h"
121 MS_U32 u32GOPDbgLevel_hal;
122
123 // Debug Logs, level form low(INFO) to high(FATAL, always show)
124 // Function information, ex function entry
125 #define GOP_H_INFO(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_HIGH) {ULOGI("GOP HAL", x, ##args);}
126 // Warning, illegal paramter but can be self fixed in functions
127 #define GOP_H_WARN(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_HIGH) {ULOGW("GOP HAL", x, ##args);}
128 // Need debug, illegal paramter.
129 #define GOP_H_DBUG(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_MED) {ULOGD("GOP HAL", x, ##args);}
130 // Error, function will be terminated but system not crash
131 #define GOP_H_ERR(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_LOW) {ULOGE("GOP HAL", x, ##args);}
132 // Critical, system crash. (ex. assert)
133 #define GOP_H_FATAL(x, args...) if(u32GOPDbgLevel_hal >= E_GOP_Debug_Level_LOW){ULOGF("GOP HAL", x, ##args);}
134
135 #define GOP_ASSERT(_bool_){\
136 if ( ! ( _bool_ ) )\
137 {\
138 GOP_H_FATAL("\033[35m UTOPIA ASSERT: %s, %s %s %d\033[35m\n", #_bool_, __FILE__, __PRETTY_FUNCTION__, __LINE__);\
139 }\
140 }
141
142 //------------------------------------------------------------------------------
143 // Local Var
144 //------------------------------------------------------------------------------
145 MS_BOOL bIsMuxVaildToGopDst[MAX_GOP_MUX][MAX_DRV_GOP_DST_SUPPORT] =
146 {
147 /*IP0, IP0_SUB, MIXER2VE, OP0, VOP, IP1, IP1_SUB, MIXER2OP*/
148 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
149 {TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 1 */
150 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
151 {TRUE, FALSE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE}, /*All Gop Dst case is vaild or FALSE for mux 0 */
152 };
153 #ifdef GOP_CMDQ_ENABLE
154 extern MS_U16 u16MIUSelect[MAX_GOP_SUPPORT];
155 extern MS_BOOL bMIUSelect[MAX_GOP_SUPPORT];
156
157 extern MS_U16 u16AFBCMIUSelect[MAX_GOP_SUPPORT];
158 extern MS_BOOL bAFBCMIUSelect[MAX_GOP_SUPPORT];
159 #endif
160 GOP_CHIP_PROPERTY g_GopChipPro =
161 {
162 .bSetHSyncInverse = FALSE,
163 .bGop1GPalette = FALSE,
164 .bSetHPipeOfst = FALSE,
165 .bNeedCheckMVOP = FALSE,
166 .bNeedSetMUX1ToIP0 = FALSE,
167 .bNeedSetMUX3ToIP0 = FALSE,
168 .bNewMux = TRUE,
169 .bNewPalette = TRUE,
170 .bNewBwReg = TRUE,
171 .bGop2VStretch = TRUE,
172 .bIgnoreIPHPD = TRUE, //Uranus4 has handshack with XC, should not set HPD
173 .bIgnoreVEHPD = FALSE, //Uranus4 to VE through Mixer, do not need adjust HPD
174 .bhastilemode = TRUE,
175 .bInitNotEnableGOPToSC = TRUE, //For Uranus4 mux init setting, enable GOP to SC in GOP init would cause problem
176 .bAutoAdjustMirrorHSize = TRUE, //whether hw will auto adjust start addr when H mirror is enable
177 .bGOPWithVscale = {TRUE, TRUE, TRUE, TRUE, FALSE}, //setting GOP with/without Vscale
178 .bGOPWithScaleDown = {TRUE, FALSE, TRUE, FALSE, FALSE},
179
180 .bDWINSupport = FALSE,
181 .DwinVer = 0x1,
182 .bTstPatternAlpha = TRUE,
183 .bXCDirrectBankSupport = TRUE, /*XC Dirrect Bank R/W*/
184 .bFRCSupport = FALSE, /*OC path*/
185 .bGOPMixerToVE= FALSE, /*Mixer to VE path*/
186 .bBnkForceWrite = TRUE, /*Direct Bank Force Write*/
187 .bPixelModeSupport = TRUE, /*Pixel Mode Support*/
188 .bScalingDownSupport= TRUE,
189 .b2Pto1PSupport= TRUE,
190 .bTLBSupport= {TRUE, TRUE, TRUE, TRUE, FALSE, FALSE},
191 .GOP_TestPattern_Vaild= E_GOP0,
192 .bInternalMIUSelect= {TRUE, FALSE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE}, //{E_GOP0, E_GOP1, E_GOP2, E_GOP3, E_GOP4, E_GOP_Dwin, E_GOP_MIXER, E_GOP5}
193 .bAFBC_Support= {FALSE, FALSE, FALSE, FALSE, FALSE, FALSE}, // disable GOP before AFBC patch implement
194
195 #ifdef ENABLE_GOP_T3DPATCH
196 .GOP_PD = GOP_PD_T3D,
197 #else
198 .GOP_PD = 0x170,
199 #endif
200
201 .GOP_HDR_OP_PD = 0x0,
202 .GOP_IP_PD = 0x00,
203 .GOP_MVOP_PD = 0x69,
204 .GOP_VE_PD = 0x89,
205 .GOP_MIXER_PD = 0x0,
206 .GOP_NonVS_PD_Offset = 0x5, //GOP without Vsacle might need add offset on pipedelay
207 .GOP_NonVS_DualOpPD_Offset= 0x6,
208 .GOP_VE_V_Offset = 0x0,
209 .GOP_DUAL_OP_PD = 0x63,
210
211 .GOP_MUX_Delta = 0x1,
212 .GOP_Mux_Offset = {0x0, 0x42, 0x36, 0x3C, 0x48},
213 .GOP_MapLayer2Mux = {E_GOP_MUX0, E_GOP_MUX2, E_GOP_MUX3, E_GOP_MUX1, E_GOP_MUX4},
214 .GOP_MapLayer2DualOpMux = {E_GOP_DUALRATE_OP_MUX0, E_GOP_DUALRATE_OP_MUX1, E_GOP_DUALRATE_OP_MUX2},
215 .GOP_Mux_FRC_offset= 0x13,
216 .GOP_DualRateMux_Offset = {0x0, 0x6, 0xC},
217 .GOP_REF_POSITION_X = 0x418,
218
219 .WordUnit = GOP_WordUnit,
220 .TotalGwinNum = GOP_TotalGwinNum,
221 .Default_ConsAlpha_bits = DRV_VALID_8BITS,
222 .enGOP3DType = E_DRV_3D_DUP_FULL,
223 .bOpInterlace = FALSE,
224 .bAFBCMIUSelDoubleBuffer = TRUE,
225 .bAFBC_Merge_GOP_Trig = TRUE,
226 .bGOPVscalePipeDelay = {FALSE, FALSE, FALSE, FALSE, TRUE, FALSE},
227 .bGOPNeedSplitMode4DualRate = {FALSE, FALSE, FALSE, FALSE, TRUE},
228 .bGOPAutoClkGating = TRUE,
229 };
230
231 typedef struct
232 {
233 MS_U8 u8Gop;
234 MS_U8 mainGop;
235 MS_U8 subGop;
236 } GOP_4K120_COMBINE_PAIRS;
237
238 static const GOP_4K120_COMBINE_PAIRS gop_4k120_pairs[] =
239 {
240 {E_GOP0, E_GOP0, E_GOP3},
241 {E_GOP1, E_GOP2, E_GOP1},
242 {E_GOP2, E_GOP2, E_GOP1},
243 {E_GOP3, E_GOP0, E_GOP3},
244 {E_GOP4, E_GOP4, E_GOP4},
245 };
246
247 const MS_U8 GOP_4K120MUX_IDX_TABLE[GOP_4K120_MUX_COUNT] = {E_GOP0, E_GOP2, E_GOP4};
248
249 static const int GOP4_SPLITMODE_MAX_HSIZE = 256;
250 static const int GOP4_SPLITMODE_MAX_VSIZE = 512;
251
252 static MS_BOOL Hal_get4K120CombinedGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 * main_gop, MS_U8 * sub_gop);
253 static GOP_Result Hal_Ctrl4K120GopMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable);
254 static MS_U16 _findMuxNumberByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType dst_type, MS_U8 u8Gop);
255
256 //------------------------------------------------------------------------------
257 // Global Functions
258 //------------------------------------------------------------------------------
HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_TYPE_DEF * GOP_TYPE)259 void HAL_GOP_GetGOPEnum(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_TYPE_DEF* GOP_TYPE)
260 {
261 GOP_TYPE->GOP0 = E_GOP0;
262 GOP_TYPE->GOP1 = E_GOP1;
263 GOP_TYPE->GOP2 = E_GOP2;
264 GOP_TYPE->GOP3 = E_GOP3;
265 GOP_TYPE->GOP4 = E_GOP4;
266 GOP_TYPE->GOP5 = E_GOP5;
267 GOP_TYPE->DWIN = E_GOP_Dwin;
268 GOP_TYPE->MIXER = E_GOP_MIXER;
269 }
270
HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 regForm,MS_U8 u8GOPNum,MS_U8 u8GwinNum,MS_U16 colortype)271 GOP_Result HAL_GOP_SetWinFmt(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 regForm, MS_U8 u8GOPNum, MS_U8 u8GwinNum, MS_U16 colortype)
272 {
273 MS_U32 u32BankOffSet = 0;
274
275 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
276
277 if (((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T21G) || ((regForm & E_GOP_REG_FORM_MASK) == E_GOP_REG_FORM_T81G))
278 {
279 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(Gop23_GwinCtl_Ofet), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
280 }
281 else
282 {
283 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_GWIN0_CTRL(u8GwinNum), colortype, GOP_REG_COLORTYPE_MASK<<GOP_REG_COLORTYPE_SHIFT);
284 }
285
286 return GOP_SUCCESS;
287 }
288
HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn,E_DRV_GOP_PINPON_MODE pinpon_mode)289 GOP_Result HAL_GOP_Set_PINPON(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum, MS_BOOL bEn, E_DRV_GOP_PINPON_MODE pinpon_mode)
290 {
291 MS_U32 u32BankOffSet =0;
292 MS_U32 u32BitMask,Regval;
293
294 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
295
296 switch(pinpon_mode)
297 {
298 default:
299 case E_DRV_GOP_PINPON_G3D:
300 Regval = bEn << 5;
301 u32BitMask = GOP_BIT5;
302 break;
303 case E_DRV_GOP_PINPON_DWIN:
304 Regval = bEn << 6;
305 u32BitMask = GOP_BIT6;
306 break;
307 case E_DRV_GOP_PINPON_DIP:
308 Regval = bEn << 7;
309 u32BitMask = GOP_BIT7;
310 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT9,(GOP_BIT8|GOP_BIT9));
311 break;
312 case E_DRV_GOP_PINPON_DWIN0:
313 Regval = bEn << 7;
314 u32BitMask = GOP_BIT7;
315 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, 0x0,(GOP_BIT8|GOP_BIT9));
316 break;
317 case E_DRV_GOP_PINPON_DWIN1:
318 Regval = bEn << 7;
319 u32BitMask = GOP_BIT7;
320 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT8,(GOP_BIT8|GOP_BIT9));
321 break;
322 break;
323 }
324
325 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, Regval, u32BitMask);
326 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
327 MS_U32 u32CombineBankOffSet = 0x0;
328
329 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOPNum, &u8_mainGop, &u8_combinedGop) )
330 {
331 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
332 return GOP_FAIL;
333 }
334 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
335 {
336 _GetBnkOfstByGop(u8_combinedGop, &u32CombineBankOffSet);
337 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet+GOP_4G_CTRL1, 0x4100, GOP_REG_HW_MASK);
338 }
339
340 return GOP_SUCCESS;
341 }
342
343
_GetBnkOfstByGop(MS_U8 gop,MS_U32 * pBnkOfst)344 MS_BOOL _GetBnkOfstByGop(MS_U8 gop, MS_U32 *pBnkOfst)
345 {
346 if (gop==E_GOP0)
347 *pBnkOfst = GOP_4G_OFST<<16;
348 else if (gop==E_GOP1)
349 *pBnkOfst = GOP_2G_OFST<<16;
350 else if (gop==E_GOP2)
351 *pBnkOfst = GOP_1G_OFST<<16;
352 else if (gop==E_GOP3)
353 *pBnkOfst = GOP_1GX_OFST<<16;
354 else if (gop==E_GOP4)
355 *pBnkOfst = GOP_1GS0_OFST<<16;
356 else if (gop==E_GOP_MIXER)
357 *pBnkOfst = 0xD<<16;
358 else
359 return FALSE;
360
361 return TRUE;
362 }
363
_dumpGopNumFromBnkOffset(MS_U8 * gop,MS_U16 * subBnkOfst,MS_U32 pBnkOfst)364 MS_BOOL _dumpGopNumFromBnkOffset(MS_U8 * gop, MS_U16 * subBnkOfst, MS_U32 pBnkOfst)
365 {
366 MS_U32 subbnk = 0x0;
367 pBnkOfst = pBnkOfst >> 8;
368
369 if ((pBnkOfst >= GOP_4G_OFST) && (pBnkOfst < GOP_2G_OFST))
370 {
371 *gop = E_GOP0;
372 subbnk = pBnkOfst - GOP_4G_OFST;
373 }
374 else if ((pBnkOfst >= GOP_2G_OFST) && (pBnkOfst < GOP_1G_OFST))
375 {
376 *gop = E_GOP1;
377 subbnk = pBnkOfst - GOP_2G_OFST;
378 }
379 else if ((pBnkOfst >= GOP_1G_OFST) && (pBnkOfst < GOP_1GX_OFST))
380 {
381 *gop = E_GOP2;
382 subbnk = pBnkOfst - GOP_1G_OFST;
383 }
384 else if ((pBnkOfst >= GOP_1GX_OFST) && (pBnkOfst < GOP_1GS0_OFST))
385 {
386 *gop = E_GOP3;
387 subbnk = pBnkOfst - GOP_1GX_OFST;
388 }
389 else if ((pBnkOfst >= GOP_1GS0_OFST) || (pBnkOfst < GOP_1GS1_OFST))
390 {
391 *gop = E_GOP4;
392 subbnk = pBnkOfst - GOP_1GS0_OFST;
393 }
394 else
395 {
396 return FALSE;
397 }
398
399 *subBnkOfst = (MS_U16)(subbnk << 8);
400 return TRUE;
401 }
402
_isGopCommonRegs(MS_U16 reg)403 static MS_BOOL _isGopCommonRegs(MS_U16 reg)
404 {
405 MS_BOOL ret;
406
407 if ((reg >= (GOP_MUX_IPVOP & 0xFF)) && (reg <= (GOP_BAK_SEL & 0xFF)))
408 {
409 ret = TRUE;
410 }
411 else
412 {
413 ret = FALSE;
414 }
415
416 return ret;
417 }
418
_getLayerFromOpmux(Gop_MuxSel eGopMux)419 MS_U32 _getLayerFromOpmux(Gop_MuxSel eGopMux)
420 {
421 MS_U32 u32Layer = 0xFFFF;
422 int i=0;
423
424 for (i=0; i<MAX_GOP_MUX; i++)
425 {
426 if (g_GopChipPro.GOP_MapLayer2Mux[i] == eGopMux)
427 {
428 u32Layer = i;
429 break;
430 }
431 }
432
433 return u32Layer;
434 }
435
_SetDualOpMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,Gop_MuxSel eGopMux,MS_U8 u8GOPNum)436 void _SetDualOpMux(GOP_CTX_HAL_LOCAL*pGOPHalLocal, Gop_MuxSel eGopMux, MS_U8 u8GOPNum)
437 {
438 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
439
440 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOPNum, &u8_mainGop, &u8_combinedGop) )
441 {
442 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
443 return;
444 }
445
446 // if GOP0 on 4K120 mode, GOP3 can't set to other destination
447 if ((u8GOPNum == u8_combinedGop) && (u8_mainGop != E_GOP4))
448 {
449 GOP_H_ERR("[%s]GOP%d can't set to other mode when GOP%d is on 4K@120\n",
450 __FUNCTION__, u8_combinedGop, u8_mainGop);
451 return;
452 }
453
454 if (u8_mainGop == E_GOP0)
455 {
456 // for GOP0+GOP3
457 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 0 , GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
458 }
459 else if (u8_mainGop == E_GOP2)
460 {
461 // for GOP1+GOOP2
462 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 1 << (GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)) , GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
463 }
464 else if (u8_mainGop == E_GOP4)
465 {
466 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 2 << (GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)) , GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*(eGopMux-E_GOP_DUALRATE_OP_MUX0)));
467 }
468 }
469
_isAfbcFunctionEnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8AfbcCore)470 MS_BOOL _isAfbcFunctionEnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8AfbcCore)
471 {
472 MS_U16 reg_val = 0x0;
473 HAL_GOP_Read16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(u8AfbcCore), ®_val);
474
475 return (reg_val & GOP_BIT0) ? TRUE : FALSE;
476 }
477
HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)478 GOP_Result HAL_GOP_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
479 {
480 MS_U16 u16Mask0 = 0;
481 MS_U16 u16Mask1 = 0;
482 MS_U16 u16GopIdx = 0;
483 MS_U8 u8_mainGop =INVAILD_GOP_NUM, u8_combinedGop =INVAILD_GOP_NUM;
484 MS_U16 u16GopDst = 0x0;
485 MS_U32 u32MainBnkOfst = 0x0;
486
487 for (u16GopIdx = 0; u16GopIdx < MAX_GOP_SUPPORT; u16GopIdx++)
488 {
489 if ((u16GopMask | (1<<u16GopIdx))!=0)
490 {
491 break;
492 }
493 }
494
495 if (u16GopMask&GOP_BIT0)
496 {
497 u16Mask0 |= GOP_BIT12;
498 }
499 if (u16GopMask&GOP_BIT1)
500 {
501 u16Mask0 |= GOP_BIT13;
502 }
503 if (u16GopMask&GOP_BIT2)
504 {
505 u16Mask0 |= GOP_BIT14;
506 }
507 if (u16GopMask&GOP_BIT3)
508 {
509 u16Mask0 |= GOP_BIT15;
510 }
511 if (u16GopMask&GOP_BIT4)
512 {
513 u16Mask1 |= GOP_BIT4;
514 }
515
516 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, (MS_U8)u16GopIdx, &u8_mainGop, &u8_combinedGop) )
517 {
518 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
519 return GOP_FAIL;
520 }
521 _GetBnkOfstByGop(u8_mainGop, &u32MainBnkOfst);
522 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBnkOfst + GOP_4G_CTRL1, &u16GopDst);
523
524 if (u16Mask0 & (GOP_BIT12 | GOP_BIT15))
525 {
526 if ((u16GopDst & 0xf) == 0xB) //E_DRV_GOP_DST_OP_DUAL_RATE
527 {
528 u16Mask0 |= (GOP_BIT12 | GOP_BIT15);
529 }
530 }
531 if (u16Mask0 & (GOP_BIT13 | GOP_BIT14))
532 {
533 if ((u16GopDst & 0xf) == 0xB) //E_DRV_GOP_DST_OP_DUAL_RATE
534 {
535 u16Mask0 |= (GOP_BIT13 | GOP_BIT14);
536 }
537 }
538
539 if (u16Mask0 != 0)
540 {
541 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, 0xFFFF , u16Mask0);
542 }
543 if (u16Mask1 != 0)
544 {
545 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, 0xFFFF , u16Mask1);
546 }
547
548 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
549 {
550 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
551 }
552 return GOP_SUCCESS;
553 }
554
HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)555 GOP_Result HAL_GOP_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
556 {
557 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
558 MS_U16 u16GopDst = 0x0;
559 MS_U32 u32MainBnkOfst = 0x0;
560
561 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
562 {
563 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
564 return GOP_FAIL;
565 }
566 _GetBnkOfstByGop(u8_mainGop, &u32MainBnkOfst);
567 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBnkOfst + GOP_4G_CTRL1, &u16GopDst);
568
569 if ((u16GopDst & 0xf) == 0xB) //E_DRV_GOP_DST_OP_DUAL_RATE
570 {
571 switch (u8_mainGop)
572 {
573 case E_GOP0:
574 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, (GOP_BIT12 | GOP_BIT15), (GOP_BIT12 | GOP_BIT15));
575 break;
576 case E_GOP2:
577 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, (GOP_BIT13 | GOP_BIT14), (GOP_BIT13 | GOP_BIT14));
578 break;
579 case E_GOP4:
580 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
581 break;
582 default:
583 break;
584 }
585 }
586 else
587 {
588 switch(gop)
589 {
590 case E_GOP0:
591 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT12 , GOP_BIT12);
592 break;
593 case E_GOP1:
594 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT13 , GOP_BIT13);
595 break;
596 case E_GOP2:
597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT14 , GOP_BIT14);
598 break;
599 case E_GOP3:
600 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL, GOP_BIT15 , GOP_BIT15);
601 break;
602 case E_GOP4:
603 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_BAK_SEL_EX, GOP_BIT4 , GOP_BIT4);
604 break;
605 default:
606 break;
607 }
608 }
609
610 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
611 {
612 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0);
613 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT1, GOP_BIT1);
614 }
615 return GOP_SUCCESS;
616 }
617
HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)618 MS_U16 HAL_GOP_GetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
619 {
620 MS_U16 u16GopAck = FALSE, reg_val =0;
621 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
622
623 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
624 {
625 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
626 return u16GopAck;
627 }
628
629 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
630 {
631 switch (u8_mainGop)
632 {
633 case E_GOP0:
634 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
635 if ((reg_val&GOP_BIT12) || (reg_val&GOP_BIT15))
636 u16GopAck = FALSE;
637 else
638 u16GopAck = TRUE;
639 break;
640 case E_GOP2:
641 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
642 if ((reg_val&GOP_BIT13) || (reg_val&GOP_BIT14))
643 u16GopAck = FALSE;
644 else
645 u16GopAck = TRUE;
646 break;
647 case E_GOP4:
648 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
649 if(reg_val&GOP_BIT4)
650 u16GopAck = FALSE;
651 else
652 u16GopAck = TRUE;
653 break;
654 default:
655 break;
656 }
657 }
658 else
659 {
660 switch(gop)
661 {
662 case E_GOP0:
663 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
664 if(reg_val&GOP_BIT12)
665 u16GopAck = FALSE;
666 else
667 u16GopAck = TRUE;
668 break;
669 case E_GOP1:
670 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
671 if(reg_val&GOP_BIT13)
672 u16GopAck = FALSE;
673 else
674 u16GopAck = TRUE;
675 break;
676 case E_GOP2:
677 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
678 if(reg_val&GOP_BIT14)
679 u16GopAck = FALSE;
680 else
681 u16GopAck = TRUE;
682 break;
683 case E_GOP3:
684 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL,®_val);
685 if(reg_val&GOP_BIT15)
686 u16GopAck = FALSE;
687 else
688 u16GopAck = TRUE;
689 break;
690 case E_GOP4:
691 HAL_GOP_Read16Reg(pGOPHalLocal,GOP_BAK_SEL_EX,®_val);
692 if(reg_val&GOP_BIT4)
693 u16GopAck = FALSE;
694 else
695 u16GopAck = TRUE;
696 break;
697 default:
698 break;
699 }
700 }
701 return u16GopAck;
702 }
703
HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)704 GOP_Result HAL_GOP_EnableTwoLineBufferMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEnable)
705 {
706 MS_U32 u32BankOffSet;
707
708 if (u8GOP < 3) /* only GOP0~GOP2 can support two linebuufer mode */
709 {
710 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
711 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_TWO_LINEBUFFER, bEnable?GOP_BIT12:0, GOP_BIT12);
712 }
713
714 return GOP_SUCCESS;
715 }
716
HAL_GOP_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)717 void HAL_GOP_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
718 {
719 MS_U32 u32bankoff = 0;
720 MS_U16 mask_shift=0xFF;
721 MS_U16 u16RegVal=0xFF;
722 MS_U8 u8MIUSel=0xF;
723 MS_U8 u8Core=0;
724
725 _GetBnkOfstByGop(u8GOPNum, &u32bankoff);
726 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_CTRL0, 0x000, GOP_BIT9); // Genshot fast=0 for t3, for T4 and after no need to set this bit.
727
728 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_BW, 0xDFD0, GOP_REG_WORD_MASK); //set GOP DMA Burst length to "32", set DMA FIFO threhold to "0xD0"
729
730 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT14, GOP_BIT14);
731 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_NEW_BW, GOP_BIT12, GOP_BIT13|GOP_BIT12);
732
733 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_HW_USAGE, 0, GOP_BIT0);
734
735 if((u8GOPNum == 0)||(u8GOPNum == 1)||(u8GOPNum == 2))
736 {
737 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_TWO_LINEBUFFER, GOP_BIT12, GOP_BIT12);
738
739 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, GOP_BIT2|GOP_BIT3 , GOP_REG_WORD_MASK);
740 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, GOP_BIT2);
741 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, GOP_BIT8|GOP_BIT10|GOP_BIT12, (GOP_BIT8|GOP_BIT9)|(GOP_BIT10|GOP_BIT11)|(GOP_BIT12|GOP_BIT13));
742 }
743
744 /* enable GOP clock */
745 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, 0, CKG_SRAM1_DISABLE_CLK|CKG_SRAM0_DISABLE_CLK); /* GOP palette SRAM0&1 */
746 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, BMASK(7:0)); /* GOP Line buffer sram clock */
747
748 switch(u8GOPNum)
749 {
750 case E_GOP0:
751 mask_shift = GOP_MIU_CLIENT_GOP0;
752 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK); /* GOP 0 */
753 break;
754 case E_GOP1:
755 mask_shift = GOP_MIU_CLIENT_GOP1;
756 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK); /* GOP 1 */
757 break;
758 case E_GOP2:
759 mask_shift = GOP_MIU_CLIENT_GOP2;
760 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK); /* GOP 2 */
761 break;
762 case E_GOP3:
763 mask_shift = GOP_MIU_CLIENT_GOP3;
764 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK); /* GOP 3 */
765 break;
766 case E_GOP4:
767 mask_shift = GOP_MIU_CLIENT_GOP4;
768 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, 0, CKG_GOPG4_DISABLE_CLK_MASK); /* GOP 4 */
769 break;
770 case E_GOP_Dwin:
771 mask_shift = GOP_MIU_CLIENT_DWIN;
772 break;
773 default:
774 mask_shift = 0xFF;
775 break;
776 }
777 if(g_GopChipPro.bAFBC_Support[u8GOPNum] ==TRUE)
778 {
779 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, 0, CKG_AFBCCLK_DISABLE_CLK_MASK);
780 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(0), GOP_BIT5 , GOP_BIT5); //Half block
781 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_FMT(1), GOP_BIT5 , GOP_BIT5); //Half block
782 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_AFBCCLK, CKG_AFBCCLK_432, GOP_BIT2|GOP_BIT3); //Clk(Without resoluton)
783 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_TRIGGER, GOP_BIT0, GOP_BIT0); //Double buffer
784 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(0), GOP_BIT4, GOP_BIT4); //quick_preload_0
785 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_CORE_EN(1), GOP_BIT4, GOP_BIT4); //quick_preload_1
786 }
787
788
789 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOPNum] ==TRUE)
790 {
791 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal);
792 u8MIUSel = (u16RegVal>>mask_shift)&0x0000001UL;
793 #ifdef GOP_MIU_GROUP2
794 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal);
795 u8MIUSel = u8MIUSel|(((u16RegVal>>mask_shift)&0x0000001UL)<<1);
796 #endif
797
798 // Maserati Bug, AFBC disable need set bit15 = 1
799 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_MUX4_4K120, GOP_BIT7, GOP_BIT7 );
800
801 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
802 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
803 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_MIU_SEL, u8MIUSel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
804 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Get Control MIU select by GOP itself
805 if(g_GopChipPro.bAFBC_Support[u8GOPNum]==TRUE)
806 {
807 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8GOPNum, &u8Core);
808 HAL_GOP_Write16Reg(pGOPHalLocal, REG_AFBC_MIU, u8MIUSel<<4 , GOP_BIT4|GOP_BIT5);
809 }
810 }
811
812 //OC_RM_alpha
813 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, GOP_BIT0, GOP_BIT0);
814 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
815 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
816
817 // set VIP/VOP timing select, always select VOP should be OK.
818 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff+GOP_4G_VIP_VOP_TIMING_SEL, GOP_BIT10, GOP_BIT10);
819
820 // Set Gwin priority, prio0 : Gwin0; prio1:Gwin1, so set GOP_BIT4
821 if(u8GOPNum == E_GOP0 || u8GOPNum == E_GOP1)
822 {
823 HAL_GOP_Write16Reg(pGOPHalLocal, u32bankoff + GOP_4G_PRI0, GOP_BIT4, (GOP_BIT0 | GOP_BIT1 | GOP_BIT4 | GOP_BIT5 ));
824 }
825
826 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOP_HSYNC_START, g_GopChipPro.GOP_REF_POSITION_X, 0x1FFF);
827 }
828
HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL * pGOPHalLocal)829 void HAL_GOP_Chip_Proprity_Init(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
830 {
831 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
832 }
833
HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)834 MS_U8 HAL_GOP_GetMaxGwinNumByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
835 {
836 switch(u8GopNum)
837 {
838 case E_GOP0:
839 return (MS_U8)MAX_GOP0_GWIN;
840 break;
841 case E_GOP1:
842 return (MS_U8)MAX_GOP1_GWIN;
843 break;
844 case E_GOP2:
845 return (MS_U8)MAX_GOP2_GWIN;
846 break;
847 case E_GOP3:
848 return (MS_U8)MAX_GOP3_GWIN;
849 break;
850 case E_GOP4:
851 return (MS_U8)MAX_GOP4_GWIN;
852 break;
853 default:
854 GOP_ASSERT(0);
855 return 0xFF;
856 break;
857 }
858 }
859
HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8Gop,MS_U8 u8Idx)860 MS_U8 HAL_GOP_SelGwinIdByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8Gop, MS_U8 u8Idx)
861 {
862 MS_U8 u8GWinId = 0;
863
864 //Adjust GWIN ID by different Chip
865
866 switch(u8Gop)
867 {
868 case E_GOP0:
869 u8GWinId = GOP0_GwinIdBase + u8Idx;
870 break;
871 case E_GOP1:
872 u8GWinId = GOP1_GwinIdBase + u8Idx;
873 break;
874 case E_GOP2:
875 u8GWinId = GOP2_GwinIdBase + u8Idx;
876 break;
877 case E_GOP3:
878 u8GWinId = GOP3_GwinIdBase + u8Idx;
879 break;
880 case E_GOP4:
881 u8GWinId = GOP4_GwinIdBase + u8Idx;
882 break;
883 default:
884 break;
885 }
886 return u8GWinId;
887
888 }
889
HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum)890 GOP_Result HAL_GOP_GOPSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum)
891 {
892 switch(u8GOPNum)
893 {
894 case E_GOP0: // GOP4G
895 pGOPHalLocal->bank_offset = GOP_4G_OFST<<16;
896 return GOP_SUCCESS;
897 case E_GOP1: // GOP2G
898 pGOPHalLocal->bank_offset = GOP_2G_OFST<<16;
899 return GOP_SUCCESS;
900 case E_GOP2: // GOP1G
901 pGOPHalLocal->bank_offset = GOP_1G_OFST<<16;
902 return GOP_SUCCESS;
903 case E_GOP3: // GOP1GX
904 pGOPHalLocal->bank_offset = GOP_1GX_OFST<<16;
905 return GOP_SUCCESS;
906 case E_GOP4: // GOP1GS
907 pGOPHalLocal->bank_offset = GOP_1GS0_OFST<<16;
908 return GOP_SUCCESS;
909 default:
910 GOP_ASSERT(0);
911 return GOP_FAIL;
912 }
913 }
914
HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8bank)915 void HAL_GOP_BANK_SEL(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8bank)
916 {
917 MS_U16 u16Bank;
918 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL);
919 u16Bank &= ~BMASK(3:0);
920 u16Bank |= (u8bank&BMASK(3:0));
921 GOP_WRITE2BYTE(GOP_BAK_SEL, u16Bank);
922 u16Bank = GOP_READ2BYTE(GOP_BAK_SEL_EX);
923 u16Bank &= ~GOP_BIT4;
924 u16Bank |= ((u8bank&GOP_BIT4)<<GOP_BIT4);
925 GOP_WRITE2BYTE(GOP_BAK_SEL_EX, u16Bank);
926 }
927
HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL * pGOPHalLocal)928 MS_U8 HAL_GOP_Get_BANK(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
929 {
930 MS_U16 u16GetBank;
931 u16GetBank = ((GOP_READ2BYTE(GOP_BAK_SEL_EX)& GOP_BIT8)>> GOP_BIT4)| (GOP_READ2BYTE(GOP_BAK_SEL)&0xF);
932 return (u16GetBank&GOP_BANK_MASK);
933 }
934
HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 * pu16ret)935 void HAL_GOP_Read16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16* pu16ret)
936 {
937 MS_U16 u16xcSubbank=0, u16BankAddr=0, u16BankTemp=0;
938 MS_U32 bank;
939 MS_U32 direct_addr;
940
941 GOP_H_INFO("HAL_GOP_Read16Reg[%td]\n", (ptrdiff_t)u32addr);
942
943 //* Gop driver should access another HW IP register
944 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
945 switch (u32addr & 0xFF00)
946 {
947 case GOP_REG_BASE:
948 {
949 bank = (u32addr & 0xFF0000) >> 8;
950
951 if(bank==0xE00)//GOP4: 0x121B00
952 {
953 bank=GOP_REG_GOP4_BK_OFFSET;
954 }
955 else if(bank==0xF00)//GWIN4: 0x121E00
956 {
957 bank=GOP_REG_GOP4_GW_OFFSET;
958 }
959 else if(bank==0x1000)//GOP4_ST
960 {
961 bank=GOP_REG_GOP4_ST_OFFSET;
962 }
963 else if(bank==0x3100)//AFBC
964 {
965 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
966 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
967 break;
968 }
969
970 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF); //Direct_Base + bank + addr_offset
971 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
972 break;
973 }
974 case SC1_REG_BASE:
975 {
976 if(g_GopChipPro.bXCDirrectBankSupport)
977 {
978 u16xcSubbank = (u32addr & 0xFF0000)>>8;
979 u32addr = SC1_DIRREG_BASE+ u16xcSubbank + (u32addr & 0xFF);
980 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFFF));
981 }
982 else
983 {
984 u16xcSubbank = (u32addr & 0xFF0000)>>16;
985 u16BankAddr = GOP_SC_BANKSEL+0;
986 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
987
988 u16BankTemp = GOP_READ2BYTE(u16BankAddr&0xFFFF);
989 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16xcSubbank);
990 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
991 GOP_WRITE2BYTE(u16BankAddr&0xFFFF, u16BankTemp);
992 }
993 break;
994 }
995 case GE_REG_BASE:
996 case CKG_REG_BASE:
997 case MIU0_REG_BASE:
998 case MIU_REG_BASE:
999 case MVOP_REG_BASE:
1000 {
1001 *pu16ret = GOP_READ2BYTE((u32addr&0xFFFF));
1002 break;
1003 }
1004 #ifdef GOP_MIU_GROUP2
1005 case (MIU2_REG_BASE & 0xFF00):
1006 {
1007 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1008 *pu16ret = GOP_READ2BYTE((direct_addr&0xFFFFF));
1009
1010 break;
1011 }
1012 #endif
1013 default:
1014 {
1015 //Gop lib current do not support this HW ip base
1016 GOP_ASSERT(0);
1017 *pu16ret =0;
1018 break;
1019 }
1020 }
1021 }
1022
HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)1023 void HAL_GOP_Write16Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
1024 {
1025 MS_U16 u16tmp=0;
1026 MS_U16 u16xcSubbank=0,u16BankAddr=0,pu16ret=0;
1027 MS_U32 bank;
1028 MS_U32 direct_addr;
1029
1030 MS_U8 u8_gop =INVAILD_GOP_NUM;
1031 MS_U8 u8_mainGop =INVAILD_GOP_NUM, u8_combinedGop =INVAILD_GOP_NUM;
1032 MS_U16 u16SubBnkOfst = 0x0;
1033 MS_U16 u16GopDst = 0x0;
1034 MS_U32 u32MainBnkOfst = 0x0;
1035
1036 GOP_H_INFO("HAL_GOP_Write16Reg[%04tx] = %04x\n", (ptrdiff_t)u32addr, u16val);
1037
1038 if(mask!=0xffff)
1039 {
1040 HAL_GOP_Read16Reg(pGOPHalLocal, u32addr, &u16tmp);
1041 u16tmp &= ~mask;
1042 u16val &= mask;
1043 u16val |= u16tmp;
1044 }
1045
1046 //* Gop driver should access another HW IP register
1047 //* ex: SC's IP and OP setting, GE's det frame buffer setting, ChipTop GOP clk setting
1048 switch (u32addr & 0xFF00)
1049 {
1050 case GOP_REG_BASE:
1051 {
1052 bank = (u32addr & 0xFF0000) >> 8;
1053
1054 if(bank==0xE00)//GOP4: 0x121B00
1055 {
1056 bank=GOP_REG_GOP4_BK_OFFSET;
1057 }
1058 else if(bank==0xF00)//GWIN4: 0x121E00
1059 {
1060 bank=GOP_REG_GOP4_GW_OFFSET;
1061 }
1062 else if(bank==0x1000) //GOP4_ST
1063 {
1064 bank=GOP_REG_GOP4_ST_OFFSET;
1065 }
1066 else if(bank==0x3100)//AFBC
1067 {
1068 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1069 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1070 break;
1071 }
1072 else if (bank==0x7000)// Manual Crop
1073 {
1074 direct_addr = MANUAL_CROP_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1075 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1076 break;
1077 }
1078
1079
1080 if( FALSE == _dumpGopNumFromBnkOffset(&u8_gop, &u16SubBnkOfst, bank) )
1081 {
1082 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1083 return;
1084 }
1085
1086 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8_gop, &u8_mainGop, &u8_combinedGop) )
1087 {
1088 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1089 return;
1090 }
1091
1092 _GetBnkOfstByGop(u8_mainGop, &u32MainBnkOfst);
1093 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBnkOfst + GOP_4G_CTRL1, &u16GopDst);
1094 if ((u8_gop == u8_mainGop) &&
1095 ((u16GopDst & 0xf) == 0xB) &&
1096 (_isGopCommonRegs(u32addr & 0xFF) == FALSE) // combined register only the set once
1097 )
1098 {
1099 // to combine GOP0&GOP3, GOP1&GOP2
1100 MS_U8 u8_Copy2Gop = (u8_gop == u8_mainGop) ? u8_combinedGop : u8_mainGop;
1101 MS_U32 CopyGopbkofst = 0x0;
1102
1103 _GetBnkOfstByGop(u8_Copy2Gop, &CopyGopbkofst);
1104 CopyGopbkofst = (CopyGopbkofst >> 8) + u16SubBnkOfst;
1105
1106 direct_addr = GOP_REG_DIRECT_BASE + CopyGopbkofst + (u32addr & 0xFF);
1107 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1108 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
1109 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1110 }
1111 else
1112 {
1113 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
1114 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1115 }
1116 break;
1117 }
1118 case SC1_REG_BASE:
1119 if(g_GopChipPro.bXCDirrectBankSupport)
1120 { /*Derrick Bank*/
1121 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
1122 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
1123 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1124 }
1125 else
1126 { /*Sub Bank*/
1127 u16xcSubbank = (u32addr & 0xFF0000)>>16 ;
1128 u16BankAddr = GOP_SC_BANKSEL+0;
1129 u32addr = SC1_REG_BASE + (u32addr & 0xFF);
1130
1131 pu16ret = GOP_READ2BYTE(u16BankAddr&0xFFFF);
1132 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), u16xcSubbank);
1133 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
1134 GOP_WRITE2BYTE((u16BankAddr&0xFFFF), pu16ret);
1135 }
1136 break;
1137 case GE_REG_BASE:
1138 case CKG_REG_BASE:
1139 case MIU0_REG_BASE:
1140 case MIU_REG_BASE:
1141 {
1142 GOP_WRITE2BYTE((u32addr&0xFFFF), u16val);
1143 break;
1144 }
1145 #ifdef GOP_MIU_GROUP2
1146 case (MIU2_REG_BASE & 0xFF00):
1147 {
1148 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
1149 GOP_WRITE2BYTE((direct_addr&0xFFFFF), u16val);
1150 break;
1151 }
1152 #endif
1153 default:
1154 {
1155 //Gop lib current do not support this HW ip base
1156 GOP_ASSERT(0);
1157 break;
1158 }
1159
1160 }
1161 }
1162
1163
HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32addr,MS_U32 u32val)1164 void HAL_GOP_Write32Reg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32addr, MS_U32 u32val)
1165 {
1166 HAL_GOP_Write16Reg(pGOPHalLocal, u32addr, (MS_U16)(u32val&0xFFFF), 0xffff);
1167 HAL_GOP_Write16Reg(pGOPHalLocal, u32addr+2, (MS_U16)((u32val&0xFFFF0000)>>16), 0xffff);
1168 }
1169
1170 //extern E_BDMA_Ret MDrv_BDMA_Mem_Fill(MS_U32 u32Addr, MS_U32 u32Len, MS_U32 u32Pattern, E_BDMA_DstDev eDev);
1171
HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * pREGMAP_Base,MS_U16 * pREGMAP_Offset,MS_U32 u32REGMAP_Len,MS_U8 u8Index,MS_U8 u8A,MS_U8 u8R,MS_U8 u8G,MS_U8 u8B)1172 void HAL_GOP_Write32Pal(GOP_CTX_HAL_LOCAL *pGOPHalLocal,
1173 MS_U8 *pREGMAP_Base, MS_U16 *pREGMAP_Offset, MS_U32 u32REGMAP_Len,
1174 MS_U8 u8Index, MS_U8 u8A, MS_U8 u8R, MS_U8 u8G, MS_U8 u8B)
1175 {
1176 MS_U8 i=0;
1177 GOP_H_INFO("GOP_Write32Pal : i= %02x, ARGB = %02x,%02x,%02x,%02x\n",u8Index, u8A, u8R, u8G, u8B);
1178
1179 /* Don't care high byte */
1180 GOP_ASSERT((MS_U32)(*pREGMAP_Offset +GOP_WordUnit)<= u32REGMAP_Len);
1181
1182 for(i =(GOP_WordUnit-1);i>4;i--)
1183 {
1184 *(pREGMAP_Base + *pREGMAP_Offset + i) = 0;
1185 }
1186 *(pREGMAP_Base + *pREGMAP_Offset + 4) = u8Index;
1187 *(pREGMAP_Base + *pREGMAP_Offset + 3) = u8A;
1188 *(pREGMAP_Base + *pREGMAP_Offset + 2) = u8R;
1189 *(pREGMAP_Base + *pREGMAP_Offset + 1) = u8G;
1190 *(pREGMAP_Base + *pREGMAP_Offset) = u8B;
1191 *pREGMAP_Offset += GOP_WordUnit;
1192
1193 MsOS_FlushMemory(); //make sure cpu write data to dram
1194
1195 }
1196
HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPColorType fbFmt)1197 MS_U16 HAL_GOP_GetBPP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPColorType fbFmt)
1198 {
1199 MS_U16 bpp=0;
1200
1201 switch ( fbFmt )
1202 {
1203 case E_DRV_GOP_COLOR_RGB555_BLINK :
1204 case E_DRV_GOP_COLOR_RGB565 :
1205 case E_DRV_GOP_COLOR_ARGB1555:
1206 case E_DRV_GOP_COLOR_RGBA5551:
1207 case E_DRV_GOP_COLOR_ARGB4444 :
1208 case E_DRV_GOP_COLOR_RGBA4444 :
1209 case E_DRV_GOP_COLOR_RGB555YUV422:
1210 case E_DRV_GOP_COLOR_YUV422:
1211 case E_DRV_GOP_COLOR_2266:
1212 bpp = 16;
1213 break;
1214 case E_DRV_GOP_COLOR_ARGB8888 :
1215 case E_DRV_GOP_COLOR_ABGR8888 :
1216 bpp = 32;
1217 break;
1218
1219 case E_DRV_GOP_COLOR_I8 :
1220 bpp = 8;
1221 break;
1222
1223 default :
1224 //print err
1225 GOP_ASSERT(0);
1226 bpp = 0xFFFF;
1227 break;
1228 }
1229 return bpp;
1230
1231 }
1232
HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,MS_U8 u8coef)1233 void HAL_GOP_GWIN_SetBlending(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, MS_U8 u8coef)
1234 {
1235 MS_U16 regval;
1236 /*For compatibility
1237 Old chip only have alpha coeffient 6 bits. Charka2 define UI alpha value base on it.*/
1238 MS_U8 u8coef_cpt = u8coef;
1239
1240 //if UI alpha value based on alpha coeffient 6 bits, and our chip is 8bit, please do it.
1241 if( pGOPHalLocal->User_ConsAlpha_bits != g_GopChipPro.Default_ConsAlpha_bits)
1242 {
1243 switch(u8coef)
1244 {
1245 case 0x0 :
1246 u8coef_cpt = u8coef<<2;
1247 break;
1248 case 0x3f :
1249 u8coef_cpt = ((u8coef<<2)|0x3);
1250 break;
1251 default:
1252 u8coef_cpt = ((u8coef<<2)|0x1);
1253 break;
1254 }
1255 }
1256
1257 /*alpha coeffient 6/8bit chip has GOP0,GOP1*/
1258 if (u8win<(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1259 {
1260 regval = (MS_U16)(bEnable?(1<<14):0)|(MS_U16)((u8coef&0x3F)<<8);
1261 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN0_CTRL(u8win):GOP_2G_GWIN_CTRL(u8win-MAX_GOP0_GWIN), regval, 0x4000);
1262 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win < MAX_GOP0_GWIN)? GOP_4G_GWIN_ALPHA01(u8win):GOP_2G_GWIN_ALPHA01(u8win-MAX_GOP0_GWIN), u8coef_cpt, 0xFF);
1263 }
1264 /*Only alpha coeffient 8bit chip has GOP2,GOP3...*/
1265 else
1266 {
1267 if (u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN))
1268 {
1269 regval = (MS_U16)(bEnable?(1<<14):0);
1270 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN0_CTRL, regval, 0x4000);
1271 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u8coef, 0xFF);
1272 }
1273 else if ((u8win==(MAX_GOP0_GWIN+MAX_GOP1_GWIN+MAX_GOP2_GWIN)))
1274 {
1275 regval = (MS_U16)(bEnable?(1<<14):0);
1276 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN0_CTRL, regval, 0x4000);
1277 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u8coef, 0xFF);
1278 }
1279 else
1280 {
1281 regval = (MS_U16)(bEnable?(1<<14):0);
1282 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN0_CTRL, regval, 0x4000);
1283 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u8coef, 0xFF);
1284 }
1285 }
1286 }
1287
HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1288 void HAL_GOP_SetIOMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1289 {
1290 pGOPHalLocal->va_mmio_base = addr;
1291 }
HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1292 void HAL_GOP_SetIOFRCMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1293 {
1294 }
HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_VIRT addr)1295 void HAL_GOP_SetIOPMMapBase(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_VIRT addr)
1296 {
1297 }
1298
1299
HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)1300 GOP_Result HAL_GOP_GWIN_SetDstPlane(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType,MS_BOOL bOnlyCheck)
1301 {
1302 /*A5 GOP dst type:
1303 1: IP (Main)
1304 0: IP (Sub)
1305 2: OP
1306 3: MVOP
1307 4: MVOP (Sub)
1308 6: FRC
1309 11: InsideFRC
1310 */
1311 MS_U8 i=0, Cnt=0;
1312 MS_U16 u16RegVal;
1313 MS_U32 u32BankOffSet;
1314 DRV_GOPDstType pGopDst;
1315 MS_BOOL bEnable;
1316 MS_U16 u16HSyncMask=GOP_BIT14;
1317 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1318
1319 if( GopNum >= MAX_GOP_SUPPORT)
1320 {
1321 return GOP_INVALID_PARAMETERS;
1322 }
1323
1324 switch (eDstType)
1325 {
1326 case E_DRV_GOP_DST_IP0:
1327 u16RegVal = 0x0;
1328 bEnable = FALSE;
1329 u16HSyncMask=0;
1330 break;
1331
1332 case E_DRV_GOP_DST_IP0_SUB:
1333 u16RegVal = 0x1;
1334 bEnable = FALSE;
1335 u16HSyncMask=0;
1336 break;
1337
1338 case E_DRV_GOP_DST_OP0:
1339 u16RegVal = 0x2;
1340 bEnable = FALSE;
1341 u16HSyncMask=GOP_BIT14;
1342 break;
1343
1344 case E_DRV_GOP_DST_VOP:
1345 u16RegVal = 0x3;
1346 bEnable = FALSE;
1347 u16HSyncMask=GOP_BIT14;
1348 break;
1349
1350 case E_DRV_GOP_DST_VOP_SUB:
1351 u16RegVal = 0x4;
1352 bEnable = FALSE;
1353 u16HSyncMask=GOP_BIT14;
1354 break;
1355
1356 case E_DRV_GOP_DST_FRC:
1357 u16RegVal = 0x6;
1358 bEnable = TRUE;
1359 u16HSyncMask=GOP_BIT14;
1360 break;
1361
1362 case E_DRV_GOP_DST_VE:
1363 u16RegVal = 0x7;
1364 bEnable = TRUE;
1365 u16HSyncMask=GOP_BIT14;
1366 break;
1367 case E_DRV_GOP_DST_DIP:
1368 u16RegVal = 0x8;
1369 bEnable = TRUE;
1370 u16HSyncMask=GOP_BIT14;
1371 break;
1372 case E_DRV_GOP_DST_OP_DUAL_RATE:
1373 u16RegVal = 0xB;
1374 bEnable = FALSE;
1375 u16HSyncMask=0x0;
1376 break;
1377 default:
1378 return GOP_FUN_NOT_SUPPORTED;
1379 }
1380 if(bOnlyCheck == FALSE)
1381 {
1382 Hal_get4K120CombinedGOP(pGOPHalLocal, GopNum, &u8_mainGop, &u8_combinedGop);
1383 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1384 {
1385 pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] = eDstType;
1386 pGOPHalLocal->pHALShared->GOP_Dst[u8_combinedGop] = eDstType;
1387 }
1388 else
1389 {
1390 pGOPHalLocal->pHALShared->GOP_Dst[GopNum] = eDstType;
1391 }
1392
1393 _GetBnkOfstByGop(GopNum, &u32BankOffSet);
1394 HAL_GOP_SetGOP2Pto1P(pGOPHalLocal, GopNum, bEnable);
1395 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
1396
1397 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1398 {
1399 MS_U32 u32SubBnkOffSet=0;
1400 _GetBnkOfstByGop(u8_combinedGop, &u32SubBnkOffSet);
1401 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBnkOffSet+GOP_4G_CTRL1, u16RegVal, BMASK(GOP_BIT3:0));
1402 }
1403
1404 //For Bypass
1405 for(i=0; i<MAX_GOP_SUPPORT ;i++)
1406 {
1407 HAL_GOP_GetGOPDst(pGOPHalLocal, i, &pGopDst);
1408 if(pGopDst == E_DRV_GOP_DST_FRC)
1409 {
1410 Cnt++;
1411 }
1412 }
1413
1414 if (E_DRV_GOP_DST_OP_DUAL_RATE == eDstType)
1415 {
1416 Hal_Ctrl4K120GopMode(pGOPHalLocal, GopNum, TRUE);
1417 Hal_SetCropWindow(pGOPHalLocal, GopNum, EN_GOP_CROP_ENABLE);
1418 }
1419 else
1420 {
1421 Hal_Ctrl4K120GopMode(pGOPHalLocal, GopNum, FALSE);
1422 Hal_SetCropWindow(pGOPHalLocal, GopNum, EN_GOP_CROP_DISABLE);
1423 }
1424
1425 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_CTRL0, u16HSyncMask, GOP_BIT14); // Set mask Hsync when VFDE is low
1426 }
1427 return GOP_SUCCESS;
1428 }
1429
HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType eDstType)1430 GOP_Result HAL_GOP_SetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType eDstType)
1431 {
1432 return GOP_FUN_NOT_SUPPORTED;
1433 }
1434
HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType * pGopDst)1435 GOP_Result HAL_GOP_GetMixerDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType *pGopDst)
1436 {
1437 return GOP_FUN_NOT_SUPPORTED;
1438 }
1439
HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal)1440 GOP_Result HAL_GOP_InitMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
1441 {
1442 /*T8
1443 OP path: support 3 mux (mux0, mux 2, mux3) to blend with SC simultaneously
1444 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1445 SW default setting=> mux0:gop1g, mux1:gop1gx, mux2:gop2g, mux3:gop4g
1446 */
1447 MS_U8 gop4g=0, gop2g=1, gop1g=2, gop1gx=3, gop1gs=4;
1448 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, ((gop1gs<<(GOP_MUX_SHIFT*4))|(gop4g<<(GOP_MUX_SHIFT*3))|(gop2g<<(GOP_MUX_SHIFT*2))|(gop1gx<<(GOP_MUX_SHIFT*1))|gop1g), GOP_REG_WORD_MASK);
1449 //THEALE/utopia_release/UTPA2-205.0.x_Muji/mxlib/hal/muji/gop/
1450 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, 0x7<< GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1451
1452 // 4k120_mux0: GOP0+GOP3
1453 // 4k120_mux1: GOP2+GOP1
1454 // 4k120_mux2: GOP4
1455 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_4K120, 0x24, 0x3F);
1456
1457 return GOP_SUCCESS;
1458 }
1459
HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * u8GOPNum,Gop_MuxSel eGopMux)1460 void HAL_GOP_GWIN_GetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8* u8GOPNum, Gop_MuxSel eGopMux)
1461 {
1462 MS_U16 u16GopMux=0;
1463
1464 switch(eGopMux)
1465 {
1466 case E_GOP_MUX0:
1467 case E_GOP_MUX1:
1468 case E_GOP_MUX2:
1469 case E_GOP_MUX3:
1470 case E_GOP_MUX4:
1471 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16GopMux);
1472 *u8GOPNum = (u16GopMux >> (eGopMux*GOP_MUX_SHIFT))& GOP_REGMUX_MASK;
1473 break;
1474 case E_GOP_IP0_MUX:
1475 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1476 *u8GOPNum = (u16GopMux&GOP_IP_MAIN_MUX_MASK)>>GOP_IP_MAIN_MUX_SHIFT;
1477 break;
1478 case E_GOP_IP0_SUB_MUX:
1479 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1480 *u8GOPNum = (u16GopMux&GOP_IP_SUB_MUX_MASK)>>GOP_IP_SUB_MUX_SHIFT;
1481 break;
1482 case E_GOP_VOP0_MUX:
1483 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1484 *u8GOPNum = (u16GopMux&GOP_IP_VOP0_MUX_MASK)>>GOP_IP_VOP0_MUX_SHIFT;
1485 break;
1486 case E_GOP_VOP0_SUB_MUX:
1487 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &u16GopMux);
1488 *u8GOPNum = (u16GopMux&GOP_IP_VOP1_MUX_MASK)>>GOP_IP_VOP1_MUX_SHIFT;
1489 break;
1490 case E_GOP_Mix_MUX0:
1491 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1492 *u8GOPNum = (u16GopMux&GOP_Mix_MUX0_MASK)>>GOP_Mix_MUX0_SHIFT;
1493 break;
1494 case E_GOP_Mix_MUX1:
1495 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1496 *u8GOPNum = (u16GopMux&GOP_Mix_MUX1_MASK)>>GOP_Mix_MUX1_SHIFT;
1497 break;
1498 case E_GOP_VE0_MUX:
1499 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1500 *u8GOPNum = (u16GopMux&GOP_VE0_MUX_MASK)>>GOP_VE0_MUX_SHIFT;
1501 break;
1502 case E_GOP_VE1_MUX:
1503 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, &u16GopMux);
1504 *u8GOPNum = (u16GopMux&GOP_VE1_MUX_MASK)>>GOP_VE1_MUX_SHIFT;
1505 break;
1506 case E_GOP_DIP_MUX:
1507 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1508 *u8GOPNum = (u16GopMux&GOP_DIP_MUX_MASK)>>GOP_DIP_MUX_SHIFT;
1509 break;
1510 case E_GOP_FRC_MUX0:
1511 case E_GOP_FRC_MUX1:
1512 case E_GOP_FRC_MUX2:
1513 case E_GOP_FRC_MUX3:
1514 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u16GopMux);
1515 *u8GOPNum = (u16GopMux >> ((eGopMux%E_GOP_FRC_MUX0)*GOP_FRC_MUX_SHIFT))& GOP_FRC_REGMUX_MASK;
1516 break;
1517 case E_GOP_BYPASS_MUX0:
1518 break;
1519
1520 case E_GOP_DUALRATE_OP_MUX0:
1521 case E_GOP_DUALRATE_OP_MUX1:
1522 case E_GOP_DUALRATE_OP_MUX2:
1523 {
1524 MS_U8 mux_sel_idx;
1525 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_4K120, &u16GopMux);
1526
1527 mux_sel_idx = (u16GopMux >> ((eGopMux-E_GOP_DUALRATE_OP_MUX0)*GOP_4K120_MUX_SHIFT))& GOP_4K120_REGMUX_MASK;
1528 if (mux_sel_idx < GOP_4K120_MUX_COUNT)
1529 {
1530 *u8GOPNum = GOP_4K120MUX_IDX_TABLE[mux_sel_idx];
1531 }
1532 else
1533 {
1534 *u8GOPNum = MAX_GOP_DualMUX_Num;
1535 }
1536 }
1537 break;
1538 case E_GOP_IP1_MUX:
1539 case E_GOP_VOP1_MUX:
1540 case E_GOP_OP1_MUX:
1541 case E_GOP_GS_MUX:
1542 // to prevent warning log
1543 break;
1544 default:
1545 GOP_H_ERR("[%s]ERROR, not support the mux[%d]\n",__FUNCTION__,eGopMux);
1546 break;
1547 }
1548 }
1549
HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,Gop_MuxSel eGopMux)1550 void HAL_GOP_GWIN_SetMUX(GOP_CTX_HAL_LOCAL*pGOPHalLocal, MS_U8 u8GOPNum, Gop_MuxSel eGopMux)
1551 {
1552 MS_U16 u16Ret[4]={0};
1553
1554 switch(eGopMux)
1555 {
1556 case E_GOP_MUX0:
1557 case E_GOP_MUX1:
1558 case E_GOP_MUX2:
1559 case E_GOP_MUX3:
1560 case E_GOP_MUX4:
1561 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, u8GOPNum <<(GOP_MUX_SHIFT*eGopMux), GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*eGopMux));
1562
1563 // get layer from op mux
1564 MS_U32 u32Layer = _getLayerFromOpmux(eGopMux);
1565 if (u32Layer == 0xFFFF)
1566 {
1567 GOP_H_ERR("can't get layer from mux = %d !!", (MS_U16)eGopMux);
1568 break;
1569 }
1570
1571 // set dual op mux
1572 _SetDualOpMux(pGOPHalLocal, g_GopChipPro.GOP_MapLayer2DualOpMux[u32Layer], u8GOPNum);
1573 break;
1574
1575 case E_GOP_DUALRATE_OP_MUX0:
1576 case E_GOP_DUALRATE_OP_MUX1:
1577 case E_GOP_DUALRATE_OP_MUX2:
1578 _SetDualOpMux(pGOPHalLocal, eGopMux, u8GOPNum);
1579 break;
1580
1581 case E_GOP_IP0_MUX:
1582 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_MAIN_MUX_SHIFT, GOP_IP_MAIN_MUX_MASK);
1583 break;
1584 case E_GOP_IP1_MUX:
1585 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_SUB_MUX_SHIFT, GOP_IP_SUB_MUX_MASK);
1586 break;
1587 case E_GOP_VOP0_MUX:
1588 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP0_MUX_SHIFT, GOP_IP_VOP0_MUX_MASK);
1589 break;
1590 case E_GOP_VOP1_MUX:
1591 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, u8GOPNum << GOP_IP_VOP1_MUX_SHIFT, GOP_IP_VOP1_MUX_MASK);
1592 break;
1593 case E_GOP_Mix_MUX0:
1594 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX0_SHIFT, GOP_Mix_MUX0_MASK);
1595 break;
1596 case E_GOP_Mix_MUX1:
1597 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_Mix_MUX1_SHIFT, GOP_Mix_MUX1_MASK);
1598 break;
1599 case E_GOP_VE0_MUX:
1600 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE0_MUX_SHIFT, GOP_VE0_MUX_MASK);
1601 break;
1602 case E_GOP_VE1_MUX:
1603 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, u8GOPNum << GOP_VE1_MUX_SHIFT, GOP_VE1_MUX_MASK);
1604 break;
1605 case E_GOP_DIP_MUX:
1606 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum << GOP_DIP_MUX_SHIFT, GOP_DIP_MUX_MASK);
1607 break;
1608 case E_GOP_FRC_MUX0:
1609 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1610 break;
1611 case E_GOP_FRC_MUX1:
1612 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1613 break;
1614 case E_GOP_FRC_MUX2:
1615 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1616 break;
1617 case E_GOP_FRC_MUX3:
1618 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(eGopMux%E_GOP_FRC_MUX0)));
1619 break;
1620 case E_GOP_BYPASS_MUX0:
1621 //Check MUX is using? Checking from priority high to low
1622 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, &u16Ret[0]);
1623 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, &u16Ret[1]);
1624 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, &u16Ret[2]);
1625 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, &u16Ret[3]);
1626
1627 //Checking if un-use
1628 if((u16Ret[0] & GOP_BIT0) ==0)
1629 {
1630 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX2%E_GOP_FRC_MUX0)));
1631 }
1632 else if((u16Ret[1] & GOP_BIT0) ==0)
1633 {
1634 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX3%E_GOP_FRC_MUX0)));
1635 }
1636 else if((u16Ret[2] & GOP_BIT0) ==0)
1637 {
1638 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX0%E_GOP_FRC_MUX0)));
1639 }
1640 else if((u16Ret[3] & GOP_BIT0) ==0)
1641 {
1642 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, u8GOPNum <<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)) , GOP_REGMUX_MASK<<(GOP_FRC_MUX_SHIFT*(E_GOP_FRC_MUX1%E_GOP_FRC_MUX0)));
1643 }
1644 else
1645 {
1646 GOP_H_ERR("[%s][%d]FRC mux is already full.\n",__FUNCTION__,__LINE__);
1647 }
1648 break;
1649 break;
1650 default:
1651 GOP_H_ERR("[%s]ERROR mux setting\n",__FUNCTION__);
1652 break;
1653 }
1654 }
1655
HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1656 GOP_Result HAL_GOP_SetGOPEnable2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1657 {
1658 /* GOP OP Path enable to SC Setting
1659 A5: GOP OP Path blending with SC sequence
1660 mux1-->mux0-->mux2-->mux3
1661 */
1662 MS_U16 muxValue=0, regval=0;
1663
1664 DRV_GOPDstType pGopDst = E_DRV_GOP_DST_INVALID;
1665 MS_U16 u164K2KMuxValue=0;
1666 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1667 MS_U8 mux_need_ctrl = 0;
1668
1669 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1670 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, ®val);
1671
1672 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1673 {
1674 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT15):(regval & ~GOP_BIT15), GOP_BIT15);
1675 }
1676
1677 if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1678 {
1679 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval | GOP_BIT12):(regval & ~GOP_BIT12), GOP_BIT12);
1680 }
1681
1682 if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1683 {
1684 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT14):(regval & ~GOP_BIT14), GOP_BIT14);
1685 }
1686
1687 if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1688 {
1689 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT13):(regval & ~GOP_BIT13), GOP_BIT13);
1690 }
1691
1692 if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1693 {
1694 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, bEnable?(regval |GOP_BIT11):(regval & ~GOP_BIT11), GOP_BIT11);
1695 }
1696
1697 /*For FRC mux switch*/
1698 HAL_GOP_GetGOPDst(pGOPHalLocal, gopNum, &pGopDst);
1699 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_4K2K, &u164K2KMuxValue);
1700 if (gopNum== (u164K2KMuxValue & GOP_MUX0_MASK))
1701 {
1702 /* Switch FRC blending */
1703 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1704 }
1705
1706 if (gopNum== ((u164K2KMuxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1707 {
1708 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER1_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1709 }
1710
1711 if (gopNum== ((u164K2KMuxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1712 {
1713 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_L_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1714 }
1715
1716 if (gopNum== ((u164K2KMuxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1717 {
1718 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_FRC_LAYER2_R_EN, (pGopDst==E_DRV_GOP_DST_BYPASS)?GOP_BIT0: ~GOP_BIT0, GOP_BIT0);
1719 }
1720
1721 Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop);
1722
1723 if (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst)
1724 {
1725 // disable the xc OP blending mux of sub GOP
1726 if (u8_combinedGop== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1727 {
1728 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT15), GOP_BIT15);
1729 }
1730 else if (u8_combinedGop== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1)))
1731 {
1732 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT12), GOP_BIT12);
1733 }
1734 else if (u8_combinedGop== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2)))
1735 {
1736 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT14), GOP_BIT14);
1737 }
1738 else if (u8_combinedGop== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3)))
1739 {
1740 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT13), GOP_BIT13);
1741 }
1742 else if (u8_combinedGop== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4)))
1743 {
1744 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, (regval & ~GOP_BIT11), GOP_BIT11);
1745 }
1746 }
1747
1748 mux_need_ctrl = _findMuxNumberByGOP(pGOPHalLocal, pGopDst, u8_mainGop);
1749 if (GOP_4K120MUX_MUX0 == mux_need_ctrl)
1750 {
1751 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN0, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1752 }
1753 else if (GOP_4K120MUX_MUX1 == mux_need_ctrl)
1754 {
1755 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN1, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1756 }
1757 else if (GOP_4K120MUX_MUX2 == mux_need_ctrl)
1758 {
1759 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_4K120_EN2, (E_DRV_GOP_DST_OP_DUAL_RATE == pGopDst) ? GOP_BIT15 : ~GOP_BIT15, GOP_BIT15);
1760 }
1761
1762 return GOP_SUCCESS;
1763 }
1764
HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1765 GOP_Result HAL_GOP_SetGOP2Pto1P(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1766 {
1767 MS_U32 u32pBankOffSet=0;
1768 MS_U16 u16Regval;
1769
1770 if(g_GopChipPro.b2Pto1PSupport)
1771 {
1772 _GetBnkOfstByGop(gopNum, &u32pBankOffSet);
1773 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, &u16Regval);
1774 HAL_GOP_Write16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_SRAM_BORROW, bEnable?(u16Regval |0x0800):(u16Regval & ~0x0800), 0x0800);
1775 }
1776 return GOP_SUCCESS;
1777 }
1778
_IsGopInDualOpMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum,Gop_MuxSel * corr_mux)1779 static MS_BOOL _IsGopInDualOpMux(GOP_CTX_HAL_LOCAL* pGOPHalLocal, MS_U8 u8GopNum, Gop_MuxSel * corr_mux)
1780 {
1781 MS_U8 i=0x0;
1782 MS_U8 mux_val = 0x0;
1783 for (i=0; i<GOP_4K120_MUX_COUNT; i++)
1784 {
1785 HAL_GOP_GWIN_GetMUX(pGOPHalLocal, &mux_val, (Gop_MuxSel)i + E_GOP_DUALRATE_OP_MUX0);
1786 if (((u8GopNum == E_GOP0) && (mux_val == 0)) ||
1787 ((u8GopNum == E_GOP2) && (mux_val == 1)) ||
1788 ((u8GopNum == E_GOP4) && (mux_val == 2)))
1789 {
1790 *corr_mux = (Gop_MuxSel)i;
1791 return TRUE;
1792 }
1793 }
1794 return FALSE;
1795 }
1796
HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)1797 GOP_Result HAL_GOP_SetGOPEnable2Mode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
1798 {
1799 /* GOP OP Path enable to SC Setting
1800 A5: GOP OP Path blending with SC sequence
1801 mux1-->mux0-->mux2-->mux3
1802 */
1803 MS_U16 muxValue=0, regval=0;
1804 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1805
1806 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1807 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1808 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1809 {
1810 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x10):(regval & ~0x10), 0x30);
1811 }
1812 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1813 {
1814 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x1000):(regval & ~0x1000), 0x3000);
1815 }
1816 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1817 {
1818 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x40):(regval & ~0x40), 0xC0);
1819 }
1820 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1821 {
1822 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x100):(regval & ~0x100), 0x300);
1823 }
1824 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1825 {
1826 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, bEnable?(regval |0x4000):(regval & ~0x4000), 0xc000);
1827 }
1828 else
1829 {
1830 return GOP_FAIL;
1831 }
1832
1833 if( TRUE == Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop) )
1834 {
1835 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
1836 {
1837 MS_U16 mux4mainGop;
1838 MS_U16 mux4combinedGop;
1839 Gop_MuxSel mux_value = E_GOP_MUX_INVAILD;
1840 MS_U32 reg_num = 0x0;
1841
1842 mux4mainGop = _findMuxNumberByGOP(pGOPHalLocal, pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop], u8_mainGop);
1843 mux4combinedGop = _findMuxNumberByGOP(pGOPHalLocal, pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop], u8_combinedGop);
1844
1845 if ((mux4mainGop == INVALID_GOP_MUX_VAL) || (mux4combinedGop == INVALID_GOP_MUX_VAL))
1846 {
1847 return GOP_FAIL;
1848 }
1849
1850 if (_IsGopInDualOpMux(pGOPHalLocal, mux4mainGop, &mux_value) == TRUE)
1851 {
1852 if (mux_value == 0)
1853 {
1854 reg_num = GOP_SC_4K120_EN0;
1855 }
1856 else if (mux_value == 1)
1857 {
1858 reg_num = GOP_SC_4K120_EN1;
1859 }
1860 else if (mux_value == 2)
1861 {
1862 reg_num = GOP_SC_4K120_EN2;
1863 }
1864
1865 HAL_GOP_Write16Reg(pGOPHalLocal, reg_num, (bEnable == TRUE) ? GOP_BIT10 : ~GOP_BIT10, GOP_BIT10);
1866 }
1867 }
1868 }
1869
1870 return GOP_SUCCESS;
1871 }
1872
HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL * pbEnable)1873 GOP_Result HAL_GOP_GetGOPAlphaMode1(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL *pbEnable)
1874 {
1875 MS_U16 muxValue=0, regval=0;
1876 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
1877
1878 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop) )
1879 {
1880 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
1881 return GOP_FAIL;
1882 }
1883
1884 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
1885 {
1886 gopNum = u8_mainGop;
1887 }
1888
1889 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1890 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, ®val);
1891 if (gopNum== (muxValue & GOP_MUX0_MASK)) //enable mux0 to SC
1892 {
1893 *pbEnable = (regval & GOP_BIT4) == GOP_BIT4;
1894 }
1895 else if (gopNum== ((muxValue & GOP_MUX1_MASK)>>(GOP_MUX_SHIFT*1))) //enable mux1
1896 {
1897 *pbEnable = (regval & GOP_BIT12) == GOP_BIT12;
1898 }
1899 else if (gopNum== ((muxValue & GOP_MUX2_MASK)>>(GOP_MUX_SHIFT*2))) //enable mux2
1900 {
1901 *pbEnable = (regval & GOP_BIT6) == GOP_BIT6;
1902 }
1903 else if (gopNum== ((muxValue & GOP_MUX3_MASK)>>(GOP_MUX_SHIFT*3))) //enable mux3
1904 {
1905 *pbEnable = (regval & GOP_BIT8) == GOP_BIT8;
1906 }
1907 else if (gopNum== ((muxValue & GOP_MUX4_MASK)>> (GOP_MUX_SHIFT*4))) //enable mux4
1908 {
1909 *pbEnable = (regval & GOP_BIT14) == GOP_BIT14;
1910 }
1911 else
1912 {
1913 return GOP_FAIL;
1914 }
1915 return GOP_SUCCESS;
1916 }
1917
HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum)1918 GOP_Result HAL_GOP_SetGOPHighPri(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum)
1919 {
1920 /*T8
1921 OP path: support 4 mux (mux0, mux1, mux 2, mux3) to blend with SC simultaneously
1922 IP path: support mux0 and mux1 to IPMain/IPSub. Only one mux of mux0 and mux1 can be blended to IPMain/IPSub
1923 */
1924 MS_U16 Mux3Gop, muxValue=0, i;
1925 MS_U16 MuxShift;
1926
1927 MuxShift = GOP_MUX_SHIFT * E_GOP_MUX3;
1928
1929 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &muxValue);
1930 for (i=0; i<MAX_GOP_MUX;i++) //T8 4 mux
1931 {
1932 if (gopNum== ((muxValue&(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)))>>(i*GOP_MUX_SHIFT)))
1933 {
1934 Mux3Gop = (muxValue&GOP_MUX3_MASK)>> MuxShift; //save mux2 gop
1935
1936 muxValue &= ~GOP_MUX3_MASK; //clear mux2 setting
1937 muxValue &= ~(GOP_REGMUX_MASK<<(i*GOP_MUX_SHIFT)); //clear current mux setting
1938 muxValue |= ((gopNum<< MuxShift)|(Mux3Gop<<(i*GOP_MUX_SHIFT)));
1939 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX, muxValue, GOP_REG_WORD_MASK);
1940 break;
1941 }
1942 }
1943 return GOP_SUCCESS;
1944 }
1945
HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,DRV_GOPDstType eDstType)1946 GOP_Result HAL_GOP_SetGOPClk(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, DRV_GOPDstType eDstType)
1947 {
1948 /*T8 GOP dst type:
1949 0: IP (Main)
1950 1: IP (Sub)
1951 2: OP
1952 3: MVOP
1953 */
1954
1955 /* Monaco clkgen setting */
1956 /******************
1957 0: odclk
1958 1: idclk_f2 (ipm)
1959 2: idclk_f1 (ips)
1960 3: ocmixer
1961 4: ve
1962 5 : mvop main
1963 6 : mvop sub
1964 ******************/
1965 switch(eDstType)
1966 {
1967 case E_DRV_GOP_DST_IP0:
1968
1969 if (gopNum==E_GOP1)
1970 {
1971 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
1972 }
1973 else if (gopNum ==E_GOP2)
1974 {
1975 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
1976 }
1977 else if (gopNum ==E_GOP3)
1978 {
1979 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
1980 }
1981 else if (gopNum ==E_GOP4)
1982 {
1983 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
1984 }
1985 else if (gopNum==E_GOP0)
1986 {
1987 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
1988 }
1989 else
1990 {
1991 GOP_ASSERT(0);
1992 return GOP_INVALID_PARAMETERS;
1993 }
1994 break;
1995
1996 case E_DRV_GOP_DST_IP0_SUB:
1997 if (gopNum==E_GOP1)
1998 {
1999 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK1, CKG_GOPG1_MASK);
2000 }
2001 else if (gopNum==E_GOP2)
2002 {
2003 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_IDCLK1, CKG_GOPG2_MASK);
2004 }
2005 else if (gopNum==E_GOP3)
2006 {
2007 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_IDCLK1, CKG_GOPG3_MASK);
2008 }
2009 else if (gopNum ==E_GOP4)
2010 {
2011 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK1, CKG_GOPG4_MASK);
2012 }
2013 else if (gopNum==E_GOP0)
2014 {
2015 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK1, CKG_GOPG0_MASK);
2016 }
2017 else
2018 {
2019 GOP_ASSERT(0);
2020 return GOP_INVALID_PARAMETERS;
2021 }
2022 break;
2023
2024
2025 case E_DRV_GOP_DST_OP0:
2026 if (gopNum==E_GOP1)
2027 {
2028 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
2029 }
2030 else if (gopNum==E_GOP2)
2031 {
2032 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
2033 }
2034 else if (gopNum==E_GOP3)
2035 {
2036 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
2037 }
2038 else if (gopNum ==E_GOP4)
2039 {
2040 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
2041 }
2042 else if (gopNum==E_GOP0)
2043 {
2044 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
2045 }
2046 else
2047 {
2048 GOP_ASSERT(0);
2049 return GOP_INVALID_PARAMETERS;
2050 }
2051 break;
2052 case E_DRV_GOP_DST_DIP:
2053 if (gopNum==E_GOP1)
2054 {
2055 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_FCLK, CKG_GOPG1_MASK);
2056 }
2057 else if (gopNum==E_GOP2)
2058 {
2059 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_FCLK, CKG_GOPG2_MASK);
2060 }
2061 else if (gopNum==E_GOP3)
2062 {
2063 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_FCLK, CKG_GOPG3_MASK);
2064 }
2065 else if (gopNum ==E_GOP4)
2066 {
2067 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_FCLK, CKG_GOPG4_MASK);
2068 }
2069 else if (gopNum==E_GOP0)
2070 {
2071 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_FCLK, CKG_GOPG0_MASK);
2072 }
2073 else
2074 {
2075 GOP_ASSERT(0);
2076 return GOP_INVALID_PARAMETERS;
2077 }
2078
2079 break;
2080
2081 case E_DRV_GOP_DST_VOP:
2082 if (gopNum==E_GOP1)
2083 {
2084 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_IDCLK2, CKG_GOPG1_MASK);
2085 }
2086 else if (gopNum ==E_GOP2)
2087 {
2088 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG2_IDCLK2, CKG_GOPG2_MASK);
2089 }
2090 else if (gopNum ==E_GOP3)
2091 {
2092 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG3_IDCLK2, CKG_GOPG3_MASK);
2093 }
2094 else if (gopNum ==E_GOP4)
2095 {
2096 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_IDCLK2, CKG_GOPG4_MASK);
2097 }
2098 else if (gopNum==E_GOP0)
2099 {
2100 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_IDCLK2, CKG_GOPG0_MASK);
2101 }
2102 else
2103 {
2104 GOP_ASSERT(0);
2105 return GOP_INVALID_PARAMETERS;
2106 }
2107
2108 break;
2109 case E_DRV_GOP_DST_FRC:
2110 if (gopNum==E_GOP1)
2111 {
2112 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_OCC_FRCCLK, CKG_GOPG1_MASK);
2113 }
2114 else if (gopNum==E_GOP0)
2115 {
2116 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_OCC_FRCCLK, CKG_GOPG0_MASK);
2117 }
2118 else if (gopNum==E_GOP2)
2119 {
2120 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_OCC_FRCCLK, CKG_GOPG2_MASK);
2121 }
2122 else if (gopNum==E_GOP3)
2123 {
2124 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_OCC_FRCCLK, CKG_GOPG3_MASK);
2125 }
2126 else if (gopNum ==E_GOP4)
2127 {
2128 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_OCC_FRCCLK, CKG_GOPG4_MASK);
2129 }
2130 else
2131 {
2132 GOP_ASSERT(0);
2133 return GOP_INVALID_PARAMETERS;
2134 }
2135
2136 break;
2137
2138 case E_DRV_GOP_DST_MIXER2VE:
2139 //HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPMIXER_CLK, CKG_GOPMIXER_VECLK, CKG_GOPMIXER_MASK);
2140
2141 if(gopNum == 0)
2142 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
2143 else if(gopNum == 1)
2144 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
2145 else if(gopNum == 2)
2146 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
2147 else if(gopNum == 3)
2148 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
2149 else if(gopNum == 4)
2150 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
2151
2152 break;
2153
2154 case E_DRV_GOP_DST_VE:
2155 if(gopNum == 0)
2156 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_MIXERCLK_VE, CKG_GOPG0_MASK);
2157 else if(gopNum == 1)
2158 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_MIXERCLK_VE, CKG_GOPG1_MASK);
2159 else if(gopNum == 2)
2160 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_MIXERCLK_VE, CKG_GOPG2_MASK);
2161 else if(gopNum == 3)
2162 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_MIXERCLK_VE, CKG_GOPG3_MASK);
2163 else if(gopNum == 4)
2164 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_MIXERCLK_VE, CKG_GOPG4_MASK);
2165 break;
2166 case E_DRV_GOP_DST_OP_DUAL_RATE:
2167 {
2168 MS_U8 u8_mainGop=0, u8_combinedGop=0;
2169
2170 Hal_get4K120CombinedGOP(pGOPHalLocal, gopNum, &u8_mainGop, &u8_combinedGop);
2171 if (u8_mainGop == E_GOP0)
2172 {
2173 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG0_DISABLE_CLK_MASK);
2174 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, 0, CKG_GOPG3_DISABLE_CLK_MASK);
2175
2176 // for GOP0+GOP3
2177 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_ODCLK, CKG_GOPG0_MASK);
2178 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, CKG_GOPG3_ODCLK, CKG_GOPG3_MASK);
2179 }
2180 else if (u8_mainGop == E_GOP2)
2181 {
2182 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, CKG_GOPG2_DISABLE_CLK_MASK);
2183 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, 0, CKG_GOPG1_DISABLE_CLK_MASK);
2184
2185 // for GOP1+GOOP2
2186 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_ODCLK, CKG_GOPG2_MASK);
2187 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_ODCLK, CKG_GOPG1_MASK);
2188 }
2189 else if (u8_mainGop == E_GOP4)
2190 {
2191 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, CKG_GOPG4_ODCLK, CKG_GOPG4_MASK);
2192 }
2193 }
2194 break;
2195 default:
2196 GOP_ASSERT(0);
2197 return GOP_ENUM_NOT_SUPPORTED;
2198 }
2199 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &pGOPHalLocal->u16Clk0Setting); //Backup current GOPG clock settings
2200 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK,&pGOPHalLocal->u16Clk2Setting); //Backup current SRAM clock settings
2201
2202 return GOP_SUCCESS;
2203 }
2204
2205
HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2206 GOP_Result HAL_GOP_SetClkForCapture(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2207 {
2208 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, 0, GOP_BIT8);
2209 if (enSrcSel==GOP_DRV_DWIN_SRC_OP)
2210 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_ODCLK, CKG_GOPD_MASK);
2211 else if (enSrcSel==GOP_DRV_DWIN_SRC_MVOP)
2212 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_DC0CLK, CKG_GOPD_MASK);
2213 else if (enSrcSel==GOP_DRV_DWIN_SRC_IP)
2214 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_CLK_IDCLK2, CKG_GOPD_MASK);
2215 else
2216 return GOP_INVALID_PARAMETERS;
2217
2218 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &pGOPHalLocal->u16Clk1Setting); //Backup current GOPD clock settings
2219 return GOP_SUCCESS;
2220 }
HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2221 GOP_Result HAL_GOP_SetClock(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_BOOL bEnable)
2222 {
2223 if (bEnable)
2224 {
2225 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOPHalLocal->u16Clk0Setting, GOP_REG_WORD_MASK);
2226 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOPHalLocal->u16Clk1Setting, GOP_REG_WORD_MASK);
2227 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOPHalLocal->u16Clk2Setting, GOP_REG_WORD_MASK);
2228 }
2229 else
2230 {
2231 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG0_DISABLE_CLK, CKG_GOPG0_MASK);
2232 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, CKG_GOPG1_DISABLE_CLK, CKG_GOPG1_MASK);
2233 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPG2_DISABLE_CLK, CKG_GOPG2_MASK);
2234 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, CKG_GOPD_DISABLE_CLK, CKG_GOPD_MASK);
2235 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM0_DISABLE_CLK, CKG_SRAM0_MASK);
2236 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, CKG_SRAM1_DISABLE_CLK, CKG_SRAM1_MASK);
2237 }
2238
2239 return GOP_SUCCESS;
2240 }
2241
HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEnable)2242 GOP_Result HAL_GOP_MIXER_SetGOPEnable2Mixer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEnable)
2243 {
2244 return GOP_FUN_NOT_SUPPORTED;
2245 }
2246
HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_U8 muxNum,MS_BOOL bEnable)2247 GOP_Result HAL_GOP_MIXER_SetMux(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_U8 muxNum, MS_BOOL bEnable)
2248 {
2249 return GOP_FUN_NOT_SUPPORTED;
2250 }
2251
HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2252 GOP_Result HAL_GOP_MIXER_EnableOldBlendMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bEn)
2253 {
2254 return GOP_FUN_NOT_SUPPORTED;
2255 }
2256
HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL * pGOPHalLocal,GOP_CTX_HAL_SHARED * pHALShared,MS_BOOL bNeedInitShared)2257 void HAL_GOP_Init_Context(GOP_CTX_HAL_LOCAL *pGOPHalLocal, GOP_CTX_HAL_SHARED *pHALShared, MS_BOOL bNeedInitShared)
2258 {
2259 MS_U32 u32GopIdx;
2260
2261 memset(pGOPHalLocal, 0, sizeof(*pGOPHalLocal));
2262 pGOPHalLocal->pHALShared = pHALShared;
2263
2264 for(u32GopIdx=0; u32GopIdx<MAX_GOP_SUPPORT; u32GopIdx++)
2265 {
2266 pGOPHalLocal->drvGFlipGOPDst[u32GopIdx] = E_DRV_GOP_DST_OP0;
2267 }
2268 pGOPHalLocal->pGopChipPro = &g_GopChipPro;
2269 pGOPHalLocal->pbIsMuxVaildToGopDst = (MS_BOOL *)bIsMuxVaildToGopDst;
2270 }
HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2271 void HAL_GOP_Restore_Ctx(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2272 {
2273 }
2274
HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,MS_PHY * u64Adr)2275 GOP_Result HAL_ConvertAPIAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gwinid, MS_PHY* u64Adr)
2276 {
2277 MS_U8 u8Miu=0xff;
2278 MS_U8 u8GOP=0;
2279
2280 if (gwinid<MAX_GOP0_GWIN) //gop0
2281 {
2282 u8GOP=0;
2283 }
2284 else if (gwinid>=MAX_GOP0_GWIN && gwinid<MAX_GOP0_GWIN+MAX_GOP1_GWIN) //gop1
2285 {
2286 u8GOP=1;
2287 }
2288 else if (gwinid==GOP2_GwinIdBase) //gop2
2289 {
2290 u8GOP=2;
2291 }
2292 else if (gwinid==GOP3_GwinIdBase) //gop3
2293 {
2294 u8GOP=3;
2295 }
2296 else if (gwinid==GOP4_GwinIdBase) //gop4
2297 {
2298 u8GOP=4;
2299 }
2300 else
2301 {
2302 return GOP_FAIL;
2303 }
2304
2305 u8Miu = HAL_GOP_GetMIUDst(pGOPHalLocal, u8GOP);
2306
2307 if (u8Miu <= 2)
2308 {
2309 _miu_offset_to_phy(u8Miu, *u64Adr, *u64Adr);
2310 }
2311 else
2312 {
2313 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
2314 return GOP_FAIL;
2315 }
2316 return GOP_SUCCESS;
2317 }
2318
HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopnum)2319 MS_U8 HAL_GOP_GetMIUDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopnum)
2320 {
2321 MS_U8 u8Miu=0xff;
2322 MS_U16 u16RegVal_L=0;
2323 MS_U32 u32BnkOfst=0xFFFF;
2324 #ifdef GOP_MIU_GROUP2
2325 MS_U16 u16RegVal_H=0;
2326 #endif
2327
2328 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[gopnum]==TRUE)
2329 {
2330 _GetBnkOfstByGop(gopnum, &u32BnkOfst);
2331 HAL_GOP_Read16Reg(pGOPHalLocal, u32BnkOfst+GOP_4G_MIU_SEL, &u16RegVal_L);
2332
2333 u8Miu= u16RegVal_L&(GOP_BIT1|GOP_BIT0) ;
2334 }
2335 else
2336 {
2337 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIU_SEL, &u16RegVal_L);
2338
2339 #ifdef GOP_MIU_GROUP2
2340 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal_H);
2341 #endif
2342 switch (gopnum)
2343 {
2344 case 0:
2345 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP0);
2346 #ifdef GOP_MIU_GROUP2
2347 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP0);
2348 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP0)<<1;
2349 #else
2350 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP0);
2351 #endif
2352 break;
2353 case 1:
2354 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP1);
2355 #ifdef GOP_MIU_GROUP2
2356 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP1);
2357 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP1)<<1;
2358 #else
2359 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP1);
2360 #endif
2361 break;
2362
2363 case 2:
2364 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP2);
2365 #ifdef GOP_MIU_GROUP2
2366 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP2);
2367 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP2)<<1;
2368 #else
2369 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP2);
2370 #endif
2371 break;
2372
2373 case 3:
2374 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP3);
2375 #ifdef GOP_MIU_GROUP2
2376 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP3);
2377 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP3)<<1;
2378 #else
2379 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP3);
2380 #endif
2381 break;
2382 case 4:
2383 u16RegVal_L &= BIT(GOP_MIU_CLIENT_GOP4);
2384 #ifdef GOP_MIU_GROUP2
2385 u16RegVal_H &= BIT(GOP_MIU_CLIENT_GOP4);
2386 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4) | (u16RegVal_H>>GOP_MIU_CLIENT_GOP4)<<1;
2387 #else
2388 u8Miu = (u16RegVal_L>>GOP_MIU_CLIENT_GOP4);
2389 #endif
2390 break;
2391 default:
2392 return 0xff;
2393 break;
2394 }
2395
2396 if(u8Miu > MAX_GOP_MIUSEL )
2397 {
2398 GOP_H_ERR("[%s] ERROR GOP miu client\n",__FUNCTION__);
2399 return 0xff;
2400 }
2401
2402 }
2403 return u8Miu;
2404 }
HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8gopNum,DRV_GOPDstType * pGopDst)2405 GOP_Result HAL_GOP_GetGOPDst(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8gopNum, DRV_GOPDstType *pGopDst)
2406 {
2407 MS_U16 u16Regval;
2408 MS_U32 u32pBankOffSet=0;
2409 GOP_Result ret;
2410
2411 _GetBnkOfstByGop(u8gopNum, &u32pBankOffSet);
2412 HAL_GOP_Read16Reg(pGOPHalLocal, u32pBankOffSet + GOP_4G_CTRL1, &u16Regval);
2413
2414 switch (u16Regval&GOP_DST_MASK)
2415 {
2416 case 0:
2417 *pGopDst = E_DRV_GOP_DST_IP0;
2418 ret = GOP_SUCCESS;
2419 break;
2420 case 1:
2421 *pGopDst = E_DRV_GOP_DST_IP0_SUB;
2422 ret = GOP_SUCCESS;
2423 break;
2424 case 2:
2425 *pGopDst = E_DRV_GOP_DST_OP0;
2426 ret = GOP_SUCCESS;
2427 break;
2428 case 3:
2429 *pGopDst = E_DRV_GOP_DST_VOP;
2430 ret = GOP_SUCCESS;
2431 break;
2432 case 4:
2433 *pGopDst = E_DRV_GOP_DST_VOP_SUB;
2434 ret = GOP_SUCCESS;
2435 break;
2436 case 6:
2437 *pGopDst = E_DRV_GOP_DST_FRC;
2438 ret = GOP_SUCCESS;
2439 break;
2440 case 0xB:
2441 *pGopDst = E_DRV_GOP_DST_OP_DUAL_RATE;
2442 ret = GOP_SUCCESS;
2443 break;
2444 case 8:
2445 *pGopDst = E_DRV_GOP_DST_DIP;
2446 ret = GOP_SUCCESS;
2447 break;
2448 default:
2449 *pGopDst = E_DRV_GOP_DST_INVALID;
2450 ret = GOP_FAIL;
2451 break;
2452 }
2453
2454 return ret;
2455
2456 }
2457
HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_IPSEL_GOP ipSelGop)2458 void HAL_GOP_SetIPSel2SC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_IPSEL_GOP ipSelGop)
2459 {
2460 MS_U16 muxValue=0;
2461 MS_U16 u16RegVal= 0, u16RegMsk = 0;
2462
2463 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX_IPVOP, &muxValue);
2464
2465 switch(ipSelGop)
2466 {
2467 case MS_DRV_IP0_SEL_GOP0:
2468 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2469 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2470 u16RegVal |= GOP_BIT12;//mux0
2471 else
2472 u16RegVal |= GOP_BIT13;//mux1
2473 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2474 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2475 break;
2476
2477 case MS_DRV_IP0_SEL_GOP1:
2478 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2479 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2480 u16RegVal |= GOP_BIT12;//mux0
2481 else
2482 u16RegVal |= GOP_BIT13;//mux1
2483 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2484 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2485 break;
2486 case MS_DRV_IP0_SEL_GOP2:
2487 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2488 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2489 u16RegVal |= GOP_BIT12;//mux0
2490 else
2491 u16RegVal |= GOP_BIT13;//mux1
2492 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2493 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2494 break;
2495
2496 case MS_DRV_NIP_SEL_GOP0:
2497 if(E_GOP0 == (muxValue &GOP_MUX0_MASK))
2498 {
2499 u16RegVal = ~GOP_BIT12;//mux0
2500 u16RegMsk = GOP_BIT12;
2501 }
2502 else
2503 {
2504 u16RegVal = ~GOP_BIT13;//mux1
2505 u16RegMsk = GOP_BIT13;
2506 }
2507 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2508 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2509 break;
2510
2511 case MS_DRV_NIP_SEL_GOP1:
2512 if(E_GOP1 == (muxValue &GOP_MUX0_MASK))
2513 {
2514 u16RegVal = ~GOP_BIT12;//mux0
2515 u16RegMsk = GOP_BIT12;
2516 }
2517 else
2518 {
2519 u16RegVal = ~GOP_BIT13;//mux1
2520 u16RegMsk = GOP_BIT13;
2521 }
2522 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2523 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2524
2525 break;
2526 case MS_DRV_NIP_SEL_GOP2:
2527 if(E_GOP2 == (muxValue &GOP_MUX0_MASK))
2528 {
2529 u16RegVal = ~GOP_BIT12;//mux0
2530 u16RegMsk = GOP_BIT12;
2531 }
2532 else
2533 {
2534 u16RegVal = ~GOP_BIT13;//mux1
2535 u16RegMsk = GOP_BIT13;
2536 }
2537 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2538 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, GOP_BIT11, GOP_BIT11);
2539
2540 break;
2541 case MS_DRV_MVOP_SEL:
2542 u16RegVal = GOP_BIT7 | GOP_BIT5 ;
2543 u16RegVal |= GOP_BIT12; //mux0
2544 u16RegMsk = 0xFFE7;//Skip bit3/4 for GOP_SUB_IP control
2545 break;
2546 default:
2547 GOP_H_ERR("[%s] ERROR invalid source select\n",__FUNCTION__);
2548 break;
2549 }
2550 if(0 != u16RegMsk)
2551 {
2552 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, u16RegVal, u16RegMsk);
2553 }
2554 }
2555
HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_DWIN_SRC_SEL enSrcSel)2556 GOP_Result HAL_GOP_DWIN_SetSourceSel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_DWIN_SRC_SEL enSrcSel)
2557 {
2558 return GOP_FUN_NOT_SUPPORTED;
2559 }
2560
2561
HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal)2562 MS_U8 HAL_GOP_GetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal)
2563 {
2564 return GOP_FUN_NOT_SUPPORTED;
2565 }
HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 miu)2566 GOP_Result HAL_GOP_SetDWINMIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 miu)
2567 {
2568 return GOP_FUN_NOT_SUPPORTED;
2569 }
2570
HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEnable)2571 GOP_Result HAL_GOP_DWIN_EnableR2YCSC(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEnable)
2572 {
2573 return GOP_FUN_NOT_SUPPORTED;
2574 }
2575
HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode)2576 GOP_Result HAL_GOP_VE_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode)
2577 {
2578 return GOP_FUN_NOT_SUPPORTED;
2579 }
2580
HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32mode,GOP_DRV_MixerTiming * pTM)2581 GOP_Result HAL_GOP_MIXER_SetOutputTiming(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32mode, GOP_DRV_MixerTiming *pTM)
2582 {
2583 return GOP_FUN_NOT_SUPPORTED;
2584 }
2585
HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bEn)2586 GOP_Result HAL_GOP_MIXER_EnableVfilter(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bEn)
2587 {
2588 return GOP_FUN_NOT_SUPPORTED;
2589 }
2590
HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable,E_GOP_TILE_DATA_TYPE tilemode)2591 GOP_Result HAL_GOP_GWIN_EnableTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable, E_GOP_TILE_DATA_TYPE tilemode)
2592 {
2593 return GOP_FUN_NOT_SUPPORTED;
2594 }
2595
2596
HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2597 GOP_Result HAL_GOP_SetUVSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2598 {
2599 MS_U32 u32BankOffSet =0;
2600
2601 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2602
2603 if (bEn)
2604 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT14, GOP_BIT14);
2605 else
2606 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, ~GOP_BIT14, GOP_BIT14);
2607
2608 return GOP_SUCCESS;
2609 }
2610
HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOPNum,MS_BOOL bEn)2611 GOP_Result HAL_GOP_SetYCSwap(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOPNum,MS_BOOL bEn)
2612 {
2613 MS_U32 u32BankOffSet =0;
2614
2615 _GetBnkOfstByGop(u8GOPNum, &u32BankOffSet);
2616
2617 if (bEn)
2618 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, GOP_BIT15, GOP_BIT15);
2619 else
2620 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_YUV_SWAP, 0x0, GOP_BIT15);
2621
2622 return GOP_SUCCESS;
2623 }
2624
HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL * pEnable)2625 GOP_Result HAL_GOP_GWIN_GetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL* pEnable)
2626 {
2627 MS_U16 u16Val =0x0;
2628 if (u8win < GOP1_GwinIdBase)
2629 {
2630 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), &u16Val);
2631 *pEnable = (MS_BOOL)(u16Val>>15);
2632 }
2633 else if (u8win < GOP2_GwinIdBase)
2634 {
2635 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), &u16Val);
2636 *pEnable = (MS_BOOL)(u16Val>>15);
2637 }
2638 else if (u8win < GOP3_GwinIdBase)
2639 {
2640 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, &u16Val);
2641 *pEnable = (MS_BOOL)(u16Val>>15);
2642 }
2643 else if (u8win < GOP4_GwinIdBase)
2644 {
2645 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, &u16Val);
2646 *pEnable = (MS_BOOL)(u16Val>>15);
2647 }
2648 else if (u8win < GOP5_GwinIdBase)
2649 {
2650 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, &u16Val);
2651 *pEnable = (MS_BOOL)(u16Val>>15);
2652 }
2653 else
2654 {
2655 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2656 return GOP_INVALID_PARAMETERS;
2657 }
2658
2659 return GOP_SUCCESS;
2660 }
2661
HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8win,MS_BOOL bEnable)2662 GOP_Result HAL_GOP_GWIN_SetNewAlphaMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8win, MS_BOOL bEnable)
2663 {
2664 MS_U16 u16Val = bEnable << 15;
2665 if (u8win < GOP1_GwinIdBase)
2666 {
2667 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_GWIN_ALPHA01(u8win), u16Val, GOP_BIT15);
2668 }
2669 else if (u8win < GOP2_GwinIdBase)
2670 {
2671 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_GWIN_ALPHA01(u8win - MAX_GOP0_GWIN), u16Val, GOP_BIT15);
2672 }
2673 else if (u8win < GOP3_GwinIdBase)
2674 {
2675 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_GWIN_ALPHA01, u16Val, GOP_BIT15);
2676 }
2677 else if (u8win < GOP4_GwinIdBase)
2678 {
2679 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_GWIN_ALPHA01, u16Val, GOP_BIT15);
2680 }
2681 else if (u8win < GOP5_GwinIdBase)
2682 {
2683 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_GWIN_ALPHA01, u16Val, GOP_BIT15);
2684 }
2685 else
2686 {
2687 GOP_H_ERR("%s Not support this GWIN num%d!!!\n",__FUNCTION__, u8win);
2688 return GOP_INVALID_PARAMETERS;
2689 }
2690 return GOP_SUCCESS;
2691 }
2692
HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8Gwin,MS_PHY u32SubAddr)2693 GOP_Result HAL_GOP_GWiN_Set3DOSD_Sub(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP ,MS_U8 u8Gwin, MS_PHY u32SubAddr)
2694 {
2695 MS_U16 u16Reg = 0;
2696 MS_U32 u32WordBase = 0;
2697 MS_U32 u32BankOffSet=0;
2698
2699 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2700
2701 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_FWR, &u16Reg);
2702
2703 if(u16Reg & GOP_BIT7)
2704 {
2705 u32WordBase = 1;
2706 }
2707 else
2708 {
2709 u32WordBase = GOP_WordUnit;
2710 }
2711
2712 u32SubAddr /= u32WordBase;
2713
2714 if(u8GOP == E_GOP2)
2715 {
2716 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2717 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1G_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2718 }
2719 else if(u8GOP == E_GOP3)
2720 {
2721 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2722 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GX_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2723
2724 }
2725 else if(u8GOP == E_GOP4)
2726 {
2727 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_L, u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2728 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_3DOSD_SUB_RBLK_H, u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2729 }
2730 else if(u8GOP == E_GOP1)
2731 {
2732 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_L(u8Gwin - MAX_GOP0_GWIN), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2733 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_3DOSD_SUB_RBLK_H(u8Gwin - MAX_GOP0_GWIN), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2734 }
2735 else //gop0
2736 {
2737 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_L(u8Gwin), u32SubAddr&GOP_REG_WORD_MASK ,GOP_REG_WORD_MASK );
2738 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_3DOSD_SUB_RBLK_H(u8Gwin), u32SubAddr>>16 ,GOP_REG_WORD_MASK );
2739 }
2740
2741 return GOP_SUCCESS;
2742
2743 }
2744
2745 //------------------------------------------------------------------------------
2746 /// Set VE output with OSD
2747 /// @return none
2748 //------------------------------------------------------------------------------
HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable,EN_VE_OSD_ENABLE eOSD,MS_U8 gopNum)2749 GOP_Result HAL_GOP_VE_SetOSDEnable(MS_BOOL bEnable, EN_VE_OSD_ENABLE eOSD, MS_U8 gopNum)
2750 {
2751 #ifndef MSOS_TYPE_LINUX_KERNEL
2752 MS_U32 u32Reg = GOP_VE_TVS_OSD_EN;
2753 MS_U16 u16Val = BIT(2)|BIT(3);
2754
2755 if( EN_OSD_0 == eOSD)
2756 {
2757 u32Reg = GOP_VE_TVS_OSD_EN;
2758 }
2759 else if( EN_OSD_1 == eOSD)
2760 {
2761 u32Reg = GOP_VE_TVS_OSD1_EN;
2762 }
2763
2764 if(bEnable) // enable OSD
2765 {
2766 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, ~u16Val, u16Val);
2767 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(5), BIT(5));
2768 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(1), BIT(1));
2769 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, BIT(0), BIT(0));
2770 }
2771 else // disable OSD
2772 {
2773 MApi_VE_W2BYTE_MSK(MS_VE_REG_BANK_3F, u32Reg, 0x0, BIT(0));
2774 }
2775 #endif
2776 return GOP_SUCCESS;
2777 }
2778
HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gopNum,MS_BOOL bEn)2779 GOP_Result HAL_GOP_SetGOPToVE(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 gopNum, MS_BOOL bEn )
2780 {
2781 MS_U16 regval = 0x0;
2782
2783 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, ®val);
2784 // there are only 2 mux, the 3rd gop will be set to 2nd mux(osd1).
2785 if((gopNum != (regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8)>>6)) && (gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9)))
2786 {
2787 // if have to overwrite one, overwriting INIT VALUE is better.
2788 if (VE_MUX_INIT_VALUE == ((regval&(GOP_BIT6|GOP_BIT7|GOP_BIT8))>>6))
2789 {
2790 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6), (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2791 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2792 }
2793 else
2794 {
2795 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2796 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2797 }
2798 }
2799 else if(gopNum != ((regval&(GOP_BIT9|GOP_BIT10|GOP_BIT11))>>9))
2800 {
2801 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<9), (GOP_BIT9|GOP_BIT10|GOP_BIT11));
2802 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_1, gopNum);
2803 }
2804 else
2805 {
2806 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX4_MIX_VE, (gopNum<<6) , (GOP_BIT6|GOP_BIT7|GOP_BIT8));
2807 HAL_GOP_VE_SetOSDEnable(bEn, EN_OSD_0, gopNum);
2808 }
2809 return GOP_SUCCESS;
2810
2811 }
2812
HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL bHorizontal)2813 E_GOP_VIDEOTIMING_MIRRORTYPE HAL_GOP_GetVideoTimingMirrorType(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL bHorizontal)
2814 {
2815 E_GOP_VIDEOTIMING_MIRRORTYPE enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2816 MS_U16 u16MVOPMirrorCfg = 0;
2817 MS_U16 u16ScalerMirrorCfg = 0;
2818
2819 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MVOP_MIRRORCFG, &u16MVOPMirrorCfg);
2820 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &u16ScalerMirrorCfg);
2821 if(bHorizontal) // Horizontal
2822 {
2823 if(u16MVOPMirrorCfg & GOP_BIT1)
2824 {
2825 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2826 }
2827 else if(u16ScalerMirrorCfg & GOP_BIT12)
2828 {
2829 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2830 }
2831 }
2832 else //vertical
2833 {
2834 if(u16MVOPMirrorCfg & GOP_BIT0)
2835 {
2836 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYMVOP;
2837 }
2838 else if(u16ScalerMirrorCfg & GOP_BIT13)
2839 {
2840 enMirrorType = E_GOP_VIDEOTIMING_MIRROR_BYSCALER;
2841 }
2842 }
2843 return enMirrorType;
2844 }
2845
HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)2846 GOP_Result HAL_GOP_3D_SetMiddle(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16Middle)
2847 {
2848 MS_U32 u32BankOffSet =0;
2849
2850 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2851 HAL_GOP_Write16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_3D_MIDDLE, u16Middle, GOP_REG_WORD_MASK);
2852 return GOP_SUCCESS;
2853 }
2854
HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bOCEn)2855 GOP_Result HAL_GOP_OC_SetOCEn(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_BOOL bOCEn)
2856 {
2857 MS_U8 i=0, eGopMux=0, FRCMuxOffset=0;
2858 MS_U16 u16Val=0;
2859 MS_U16 u16Mux[MAX_GOP_MUX];
2860
2861 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX, &u16Val);
2862 u16Mux[0] =( u16Val & GOP_MUX0_MASK);
2863 u16Mux[1] =( u16Val & GOP_MUX1_MASK) >> (GOP_MUX_SHIFT*1);
2864 u16Mux[2] =( u16Val & GOP_MUX2_MASK) >> (GOP_MUX_SHIFT*2);
2865 u16Mux[3] =( u16Val & GOP_MUX3_MASK) >> (GOP_MUX_SHIFT*3);
2866 u16Mux[4] =( u16Val & GOP_MUX4_MASK) >> (GOP_MUX_SHIFT*4);
2867
2868 switch(u8GOP)
2869 {
2870 case E_GOP0:
2871 case E_GOP1:
2872 case E_GOP2:
2873 case E_GOP3:
2874 case E_GOP4:
2875 for(i=0; i<MAX_GOP_MUX; i++)
2876 {
2877 if(u8GOP == u16Mux[i])
2878 {
2879 eGopMux = i;
2880 if(eGopMux == 4)
2881 {
2882 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_4K2K, bOCEn<<15, GOP_BIT15);
2883 }
2884 else
2885 {
2886 FRCMuxOffset = 12 + eGopMux;
2887 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MUX_IPVOP, bOCEn<<FRCMuxOffset, 1<<FRCMuxOffset);
2888 }
2889 }
2890 }
2891 break;
2892 default:
2893 return GOP_FAIL;
2894 break;
2895 }
2896
2897 return GOP_SUCCESS;
2898 }
2899
HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOP_OC_INFO * pOCinfo)2900 GOP_Result HAL_GOP_OC_SetOCInfo(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOP_OC_INFO* pOCinfo)
2901 {
2902 return GOP_FUN_NOT_SUPPORTED;
2903 }
2904
HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 * MIUId)2905 GOP_Result HAL_GOP_OC_Get_MIU_Sel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 *MIUId)
2906 {
2907 return GOP_FUN_NOT_SUPPORTED;
2908 }
2909
HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32RingSize,MS_U32 u32BufSize)2910 GOP_Result HAL_GOP_DWIN_SetRingBuffer(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32RingSize,MS_U32 u32BufSize)
2911 {
2912 return GOP_FUN_NOT_SUPPORTED;
2913 }
2914
HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 GopNum,DRV_GOPDstType eDstType)2915 GOP_Result HAL_GOP_AdjustField(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 GopNum, DRV_GOPDstType eDstType)
2916 {
2917 return GOP_FUN_NOT_SUPPORTED;
2918 }
2919
2920 /********************************************************************************/
2921 ///Test Pattern
2922 /********************************************************************************/
HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GopNum)2923 GOP_Result HAL_GOP_TestPattern_IsVaild(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GopNum)
2924 {
2925 if(u8GopNum == pGOPHalLocal->pGopChipPro->GOP_TestPattern_Vaild)
2926 {
2927 return GOP_SUCCESS;
2928 }
2929 else
2930 {
2931 return GOP_FAIL;
2932 }
2933
2934 }
2935
2936
2937 /********************************************************************************/
2938 ///GOP Scaling down (internal)
2939 /********************************************************************************/
2940
HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)2941 MS_BOOL HAL_GOP_EnableScalingDownSram(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEn)
2942 {
2943 MS_U16 u16MG_mask=0;
2944 MS_U16 u16Val=0;
2945 MS_U16 u16LB_mask=0;
2946 MS_U16 u16enable=0;
2947
2948 if(u8GOP==0)
2949 {
2950 u16MG_mask=CKG_GOPG0_MG_MASK;
2951 u16Val=GOP_BIT2;
2952 u16LB_mask=CKG_LB_SRAM1_MASK;
2953 u16enable=GOP_BIT2;
2954 }
2955 else if(u8GOP==2)
2956 {
2957 u16MG_mask=CKG_GOPG2_MG_MASK;
2958 u16Val=GOP_BIT6;
2959 u16LB_mask=CKG_LB_SRAM2_MASK;
2960 u16enable=GOP_BIT6;
2961 }
2962 else
2963 {
2964 GOP_H_ERR("[%s] Error message GOP not support scaling down!!",__FUNCTION__);
2965 return GOP_FAIL;
2966 }
2967 if(bEn==TRUE)
2968 {
2969 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, u16Val, u16MG_mask);
2970 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, u16enable, u16LB_mask);
2971 }
2972 else
2973 {
2974 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, 0, u16MG_mask);
2975 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, 0, u16LB_mask);
2976 }
2977 return TRUE;
2978 }
2979
HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)2980 GOP_Result HAL_GOP_HScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
2981 {
2982 MS_U32 ratio;
2983 MS_U32 u32BankOffSet=0xFFFF;
2984 MS_U16 u16VScalReg;
2985
2986 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
2987 if(bEnable ==TRUE)
2988 {
2989 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, &u16VScalReg);
2990 if( u16VScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
2991 {
2992 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, 0x1000 , GOP_REG_WORD_MASK);
2993 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
2994 }
2995 //Set scaling down ratio
2996 ratio = (dst * 0x100000) / src;
2997 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, ratio);
2998 }
2999 else
3000 {
3001 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_HRATIO_L, 0);
3002 }
3003
3004 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3005 {
3006 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3007 }
3008 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, bEnable , GOP_BIT0);
3009 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_H_OUTPUTSIZE, dst, GOP_REG_WORD_MASK);
3010
3011 return GOP_SUCCESS;
3012
3013 }
3014
HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable,MS_U16 src,MS_U16 dst)3015 GOP_Result HAL_GOP_VScalingDown(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable,MS_U16 src, MS_U16 dst)
3016 {
3017 MS_U32 ratio =0;
3018 MS_U32 u32BankOffSet=0xFFFF;
3019 MS_U16 u16HScalReg;
3020
3021 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3022 if(bEnable ==TRUE)
3023 {
3024 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_HSTRCH, &u16HScalReg);
3025 if( u16HScalReg != 0x1000 ) //Not support H/V scaling up and down at same time.
3026 {
3027 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_VSTRCH, 0x1000 , GOP_REG_WORD_MASK);
3028 GOP_H_WARN("[%s] Warning message about GOP not support H/V scaling up and down at same time!!!!",__FUNCTION__);
3029 }
3030 ratio = (dst * 0x100000) / src;
3031 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, ratio);
3032 }
3033 else
3034 {
3035 HAL_GOP_Write32Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_VRATIO_L, 0);
3036 }
3037
3038 if(g_GopChipPro.bGOPWithScaleDown[u8GOP] ==TRUE)
3039 {
3040 HAL_GOP_EnableScalingDownSram(pGOPHalLocal, u8GOP, bEnable);
3041 }
3042 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SCALING_CFG, (bEnable<<4) , GOP_BIT4);
3043 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SVM_VEND, dst, GOP_REG_WORD_MASK);
3044
3045 return GOP_SUCCESS;
3046
3047 }
3048
HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U16 u16HSize,MS_U16 u16VSize)3049 GOP_Result HAL_GOP_DeleteWinHVSize(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_U16 u16HSize, MS_U16 u16VSize)
3050 {
3051 MS_U32 u32BankOffSet=0;
3052
3053 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3054 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_HVAILDSIZE, u16HSize, GOP_REG_WORD_MASK);
3055 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_BANK_VVAILDSIZE, u16VSize, GOP_REG_WORD_MASK);
3056 return GOP_SUCCESS;
3057 }
3058
HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 * u16Val)3059 GOP_Result HAL_GOP_DumpGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16* u16Val)
3060 {
3061 MS_U32 u32BankOffSet=0;
3062 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3063
3064 if (u32GopIdx < MAX_GOP_SUPPORT)
3065 {
3066 HAL_GOP_Read16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val);
3067 }
3068 else
3069 {
3070 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3071 *u16Val = 0;
3072 }
3073 return GOP_SUCCESS;
3074 }
3075
HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32GopIdx,MS_U16 u16BankIdx,MS_U16 u16Addr,MS_U16 u16Val)3076 GOP_Result HAL_GOP_RestoreGOPReg(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32GopIdx, MS_U16 u16BankIdx, MS_U16 u16Addr, MS_U16 u16Val)
3077 {
3078 MS_U32 u32BankOffSet=0;
3079 _GetBnkOfstByGop(u32GopIdx, &u32BankOffSet);
3080
3081 if (u32GopIdx < MAX_GOP_SUPPORT)
3082 {
3083 HAL_GOP_Write16Reg(pGOPHalLocal, (u32BankOffSet+ (u16BankIdx<<16) + u16Addr +GOP_4G_CTRL0), u16Val, GOP_REG_WORD_MASK);
3084 }
3085 else
3086 {
3087 GOP_H_DBUG("[%s][%d] Data is zero!!!\n",__FUNCTION__,__LINE__);
3088 }
3089 return GOP_SUCCESS;
3090 }
3091
HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U32 u32PowerState,GFLIP_REGS_SAVE_AREA * pGOP_STRPrivate)3092 GOP_Result HAL_GOP_PowerState(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U32 u32PowerState, GFLIP_REGS_SAVE_AREA* pGOP_STRPrivate)
3093 {
3094 switch(u32PowerState)
3095 {
3096 case E_POWER_SUSPEND:
3097 {
3098 //CLK
3099 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOPCLK, &(pGOP_STRPrivate->CKG_GopReg[0]));
3100 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP2CLK, &(pGOP_STRPrivate->CKG_GopReg[1]));
3101 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP3CLK, &(pGOP_STRPrivate->CKG_GopReg[2]));
3102 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_GOP4CLK, &(pGOP_STRPrivate->CKG_GopReg[3]));
3103 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[4]));
3104 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, &(pGOP_STRPrivate->CKG_GopReg[5]));
3105
3106 //SRAM
3107 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, &(pGOP_STRPrivate->GS_GopReg[0]));
3108 HAL_GOP_Read16Reg(pGOPHalLocal, CKG_GOPG0_MG, &(pGOP_STRPrivate->GS_GopReg[1]));
3109 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->GS_GopReg[2]));
3110
3111 //XC
3112 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_BANKSEL, &(pGOP_STRPrivate->XC_GopReg[0]));
3113 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[1]));
3114 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPEN, &(pGOP_STRPrivate->XC_GopReg[2]));
3115 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, &(pGOP_STRPrivate->XC_GopReg[3]));
3116 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, &(pGOP_STRPrivate->XC_GopReg[4]));
3117 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, &(pGOP_STRPrivate->XC_GopReg[5]));
3118 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_VOPNBL, &(pGOP_STRPrivate->XC_GopReg[6]));
3119 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, &(pGOP_STRPrivate->XC_GopReg[7]));
3120 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, &(pGOP_STRPrivate->XC_GopReg[8]));
3121 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMIXER, &(pGOP_STRPrivate->XC_GopReg[9]));
3122 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCMISC, &(pGOP_STRPrivate->XC_GopReg[10]));
3123 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_OCALPHA, &(pGOP_STRPrivate->XC_GopReg[11]));
3124 // HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, &(pGOP_STRPrivate->XC_GopReg[12]));
3125 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, &(pGOP_STRPrivate->XC_GopReg[13]));
3126 }
3127 break;
3128 case E_POWER_RESUME:
3129 {
3130 //CLK
3131 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOPCLK, pGOP_STRPrivate->CKG_GopReg[0], GOP_REG_WORD_MASK);
3132 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP2CLK, pGOP_STRPrivate->CKG_GopReg[1], GOP_REG_WORD_MASK);
3133 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP3CLK, pGOP_STRPrivate->CKG_GopReg[2], GOP_REG_WORD_MASK);
3134 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_GOP4CLK, pGOP_STRPrivate->CKG_GopReg[3], GOP_REG_WORD_MASK);
3135 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[4], GOP_REG_WORD_MASK);
3136 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_LB_SRAMCLK, pGOP_STRPrivate->CKG_GopReg[5], GOP_REG_WORD_MASK);
3137
3138 //SRAM
3139 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_SCALING, pGOP_STRPrivate->GS_GopReg[0], GOP_REG_WORD_MASK);
3140 HAL_GOP_Write16Reg(pGOPHalLocal, CKG_GOPG0_MG, pGOP_STRPrivate->GS_GopReg[1], GOP_REG_WORD_MASK);
3141 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->GS_GopReg[2], GOP_REG_WORD_MASK);
3142
3143 //XC
3144 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_BANKSEL, pGOP_STRPrivate->XC_GopReg[0], GOP_REG_WORD_MASK);
3145 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[1], GOP_BIT11);
3146 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPEN, pGOP_STRPrivate->XC_GopReg[2], GOP_REG_WORD_MASK);
3147 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP_SYNC, pGOP_STRPrivate->XC_GopReg[3], GOP_REG_WORD_MASK);
3148 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_IP2GOP_SRCSEL, pGOP_STRPrivate->XC_GopReg[4], GOP_BIT15);
3149 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OSD_CHECK_ALPHA, pGOP_STRPrivate->XC_GopReg[5], GOP_BIT6);
3150 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_VOPNBL, pGOP_STRPrivate->XC_GopReg[6], GOP_BIT5);
3151 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPENMODE1, pGOP_STRPrivate->XC_GopReg[7], GOP_REG_WORD_MASK);
3152 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIRRORCFG, pGOP_STRPrivate->XC_GopReg[8], GOP_REG_WORD_MASK);
3153 //HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMIXER, pGOP_STRPrivate->XC_GopReg[9], GOP_REG_WORD_MASK);
3154 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCMISC, pGOP_STRPrivate->XC_GopReg[10], GOP_BIT2);
3155 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_OCALPHA, pGOP_STRPrivate->XC_GopReg[11], GOP_BIT2);
3156 // HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_GOPSC_SRAM_CTRL, pGOP_STRPrivate->XC_GopReg[12], GOP_REG_WORD_MASK);
3157 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC1_CHANNELSYNC, pGOP_STRPrivate->XC_GopReg[13], GOP_BIT11);
3158 }
3159 break;
3160 default:
3161 break;
3162 }
3163 return GOP_SUCCESS;
3164 }
HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gwinid,EN_DRV_GOP_GPU_TILE_MODE tile_mode)3165 GOP_Result HAL_GOP_GWIN_SetGPUTileMode(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gwinid, EN_DRV_GOP_GPU_TILE_MODE tile_mode)
3166 {
3167 return GOP_FUN_NOT_SUPPORTED;
3168 }
3169
HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3170 GOP_Result HAL_GOP_EnableTLB(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 u8GOP, MS_BOOL bEnable)
3171 {
3172 MS_U32 u32BankOffSet=0xFFFF;
3173
3174 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3175 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_SRAM_BORROW, bEnable?GOP_BIT10:0, GOP_BIT10);
3176 return GOP_SUCCESS;
3177 }
3178
HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr,MS_U32 u32size)3179 GOP_Result HAL_GOP_SetTLBAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr, MS_U32 u32size)
3180 {
3181 MS_U32 u32BankOffSet=0xFFFF;
3182 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3183 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_L, u32size&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3184 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_TAG_ADDR_H, u32size>>16, GOP_REG_WORD_MASK);
3185
3186 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3187 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3188 return GOP_SUCCESS;
3189 }
3190
HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_PHY u64TLBAddr)3191 GOP_Result HAL_GOP_SetTLBSubAddr(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_PHY u64TLBAddr)
3192 {
3193 MS_U32 u32BankOffSet=0xFFFF;
3194 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3195
3196 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_L, u64TLBAddr&GOP_REG_WORD_MASK, GOP_REG_WORD_MASK);
3197 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+REG_TLB_BASE_ADDR_RVIEW_H, u64TLBAddr>>16, GOP_REG_WORD_MASK);
3198
3199 return GOP_SUCCESS;
3200 }
3201
HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3202 GOP_Result HAL_GOP_Set_GWIN_INTERNAL_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3203 {
3204 MS_U32 u32BankOffSet=0xFFFF;
3205 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3206
3207 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
3208 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
3209 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
3210
3211 return GOP_SUCCESS;
3212 }
3213
HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 miusel)3214 GOP_Result HAL_GOP_Set_MIU(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8 miusel)
3215 {
3216 MS_U32 u32BankOffSet=0xFFFF;
3217 MS_U16 mask_shift=0xFF;
3218 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
3219 MS_U32 u32CombineBankOffSet=0xFFFF;
3220
3221 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3222
3223
3224 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP]==TRUE)
3225 {
3226 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<0, (GOP_BIT0|GOP_BIT1));//GWIN Palette MIU Select
3227 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<2, (GOP_BIT2|GOP_BIT3));//GWIN MIU Select
3228 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_MIU_SEL, miusel<<4, (GOP_BIT4|GOP_BIT5));//GWIN_3D MIU Select
3229 }
3230 else
3231 {
3232 switch(u8GOP)
3233 {
3234 case E_GOP0:
3235 mask_shift = GOP_MIU_CLIENT_GOP0;
3236 break;
3237 case E_GOP1:
3238 mask_shift = GOP_MIU_CLIENT_GOP1;
3239 break;
3240 case E_GOP2:
3241 mask_shift = GOP_MIU_CLIENT_GOP2;
3242 break;
3243 case E_GOP3:
3244 mask_shift = GOP_MIU_CLIENT_GOP3;
3245 break;
3246 case E_GOP4:
3247 mask_shift = GOP_MIU_CLIENT_GOP4;
3248 break;
3249 case E_GOP_Dwin:
3250 mask_shift = GOP_MIU_CLIENT_DWIN;
3251 break;
3252 default:
3253 mask_shift = 0xFF;
3254 MS_CRITICAL_MSG(GOP_H_DBUG("ERROR gop miu client\n"));
3255 break;
3256 }
3257
3258 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3259 #ifdef GOP_MIU_GROUP2
3260 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3261 #endif
3262
3263 }
3264
3265 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop) )
3266 {
3267 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3268 return GOP_FAIL;
3269 }
3270 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
3271 {
3272 if(u8GOP != u8_mainGop)
3273 u8GOP = u8_mainGop;
3274 else
3275 u8GOP = u8_combinedGop;
3276 _GetBnkOfstByGop(u8GOP, &u32CombineBankOffSet);
3277
3278 switch(u8GOP)
3279 {
3280 case E_GOP0:
3281 mask_shift = GOP_MIU_CLIENT_GOP0;
3282 break;
3283 case E_GOP1:
3284 mask_shift = GOP_MIU_CLIENT_GOP1;
3285 break;
3286 case E_GOP2:
3287 mask_shift = GOP_MIU_CLIENT_GOP2;
3288 break;
3289 case E_GOP3:
3290 mask_shift = GOP_MIU_CLIENT_GOP3;
3291 break;
3292 case E_GOP4:
3293 mask_shift = GOP_MIU_CLIENT_GOP4;
3294 break;
3295 case E_GOP_Dwin:
3296 mask_shift = GOP_MIU_CLIENT_DWIN;
3297 break;
3298 default:
3299 mask_shift = 0xFF;
3300 MS_CRITICAL_MSG(GOP_H_DBUG("ERROR gop miu client\n"));
3301 break;
3302 }
3303
3304 if(pGOPHalLocal->pGopChipPro->bInternalMIUSelect[u8GOP]==TRUE)
3305 {
3306 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_SC_MIU_IP_SEL, 1<<mask_shift, 1<<mask_shift );//Set Control MIU select by GOP itself
3307 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<0, GOP_BIT0|GOP_BIT1 );//GWIN Palette MIU Select
3308 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<2, GOP_BIT2|GOP_BIT3 );//GWIN MIU Select
3309 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_MIU_SEL, miusel<<4, GOP_BIT4|GOP_BIT5 );//GWIN_3D MIU Select
3310 }
3311 else
3312 {
3313
3314 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP1, miusel<<mask_shift, 1<<mask_shift );
3315 #ifdef GOP_MIU_GROUP2
3316 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_MIU_GROUP2, (miusel>>1)<<mask_shift, 1<<mask_shift );
3317 #endif
3318
3319 }
3320
3321 }
3322
3323
3324 return GOP_SUCCESS;
3325 }
3326
HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * bInterlace)3327 GOP_Result HAL_GOP_GetIPInterlace(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *bInterlace)
3328 {
3329 MS_U16 reg_val = 0;
3330
3331 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_SC_IP_MAIN_INTERLACE, ®_val);
3332 if(reg_val & BIT(11))
3333 *bInterlace = TRUE;
3334 else
3335 *bInterlace = FALSE;
3336 return GOP_SUCCESS;
3337 }
3338
HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_BOOL * pbHDREnable)3339 GOP_Result HAL_GOP_IsHDREnabled(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_BOOL *pbHDREnable)
3340 {
3341 *pbHDREnable= FALSE;
3342 return GOP_FUN_NOT_SUPPORTED;
3343 }
3344
Hal_get4K120CombinedGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * main_gop,MS_U8 * sub_gop)3345 static MS_BOOL Hal_get4K120CombinedGOP(
3346 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3347 MS_U8 u8GOP,
3348 MS_U8 * main_gop,
3349 MS_U8 * sub_gop)
3350 {
3351 if ((NULL == main_gop) || (NULL == sub_gop))
3352 {
3353 return FALSE;
3354 }
3355
3356 if (u8GOP >= MAX_GOP_SUPPORT)
3357 {
3358 GOP_H_ERR("[%s][%d] Out of GOP support!!! GOP=%d\n",__FUNCTION__,__LINE__ ,u8GOP);
3359 return FALSE;
3360 }
3361
3362 *main_gop = gop_4k120_pairs[u8GOP].mainGop;
3363 *sub_gop = gop_4k120_pairs[u8GOP].subGop;
3364
3365 return TRUE;
3366 }
3367
Hal_SetCropWindow(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,EN_GOP_CROP_CTL crop_mode)3368 GOP_Result Hal_SetCropWindow(
3369 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3370 MS_U8 u8GOP,
3371 EN_GOP_CROP_CTL crop_mode
3372 )
3373 {
3374 MS_U32 u32MainBankOffSet=0xFFFF;
3375 MS_U32 u32CombineBankOffSet=0xFFFF;
3376 MS_U8 u8_mainGop, u8_combinedGop;
3377 MS_U16 crop_hstart;
3378 MS_U16 crop_hend;
3379 MS_U16 crop_vstart;
3380 MS_U16 crop_vend;
3381 MS_U16 gop_stretch_width = 0x0;
3382 MS_U16 gop_stretch_height = 0x0;
3383 MS_U16 u16Gop_stretch_vstart = 0x0;
3384 MS_U16 u16HScalingRatio = 0x0;
3385 MS_U16 u16VScalingRatio = 0x0;
3386
3387 if (FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop))
3388 {
3389 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3390 return GOP_INVALID_PARAMETERS;
3391 }
3392
3393 if (u8GOP != u8_mainGop)
3394 {
3395 return GOP_ENUM_NOT_SUPPORTED;
3396 }
3397
3398 if (E_GOP4 == u8_mainGop)
3399 {
3400 // no crop for GOP4
3401 return GOP_ENUM_NOT_SUPPORTED;
3402 }
3403
3404 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
3405 _GetBnkOfstByGop(u8_combinedGop, &u32CombineBankOffSet);
3406
3407 if (EN_GOP_CROP_DISABLE == crop_mode)
3408 {
3409 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT4);
3410 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT4);
3411 }
3412 else
3413 {
3414 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, 0, GOP_BIT5); // use precal mode
3415
3416 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_HSZ, &gop_stretch_width);
3417 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_VSZ, &gop_stretch_height);
3418 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_VSTR, &u16Gop_stretch_vstart);
3419 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_HSTRCH, &u16HScalingRatio);
3420 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_VSTRCH, &u16VScalingRatio);
3421
3422 // crop left part
3423 crop_hstart = 0x0;
3424 crop_hend = (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] != 0) ?
3425 ((pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] >> 1) - 1) : 0x77F;
3426 crop_vstart = 0x0;
3427 crop_vend = (u16VScalingRatio != 0) ? ((SCALING_MULITPLIER * (MS_U32)gop_stretch_height) / u16VScalingRatio + u16Gop_stretch_vstart) : 0x870;
3428 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_HSTART, crop_hstart, GOP_REG_WORD_MASK);
3429 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_HEND, crop_hend, GOP_REG_WORD_MASK);
3430 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_VSTART, crop_vstart, GOP_REG_WORD_MASK);
3431 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_CROP_VEND, crop_vend, GOP_REG_WORD_MASK);
3432
3433 // crop right part
3434 crop_hstart = (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] != 0) ?
3435 (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] >> 1): 0x780;
3436 crop_hend = (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] != 0) ?
3437 (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8_mainGop] - 1): 0xeff;
3438 crop_vstart = 0x0;
3439 crop_vend = (u16VScalingRatio != 0) ? ((SCALING_MULITPLIER * (MS_U32)gop_stretch_height) / u16VScalingRatio + u16Gop_stretch_vstart) : 0x870;
3440 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_HSTART, crop_hstart, GOP_REG_WORD_MASK);
3441 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_HEND, crop_hend, GOP_REG_WORD_MASK);
3442 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_VSTART, crop_vstart, GOP_REG_WORD_MASK);
3443 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_CROP_VEND, crop_vend, GOP_REG_WORD_MASK);
3444
3445 #if ENABLE_MANUAL_CROP==1
3446 MS_U16 u16ManualCropHstart = 0x0, u16ManualCropHend = 0x0;
3447
3448 u16ManualCropHstart = 0x0;
3449 u16ManualCropHend = gop_stretch_width - 1;
3450 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHSTART(u8_mainGop), u16ManualCropHstart, GOP_REG_WORD_MASK);
3451 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHEND(u8_mainGop), u16ManualCropHend, GOP_REG_WORD_MASK);
3452
3453 u16ManualCropHstart = gop_stretch_width - 2;
3454 u16ManualCropHend = (gop_stretch_width<<1) - 1;
3455 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHSTART(u8_combinedGop), u16ManualCropHstart, GOP_REG_WORD_MASK);
3456 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_ORIHEND(u8_combinedGop), u16ManualCropHend, GOP_REG_WORD_MASK);
3457
3458 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_PRECALDONE(u8_mainGop), GOP_BIT0, GOP_BIT0);
3459 HAL_GOP_Write16Reg(pGOPHalLocal, REG_GOP_CROP_PRECALDONE(u8_combinedGop), GOP_BIT0, GOP_BIT0);
3460
3461 // if afbc enable, use manual crop mode
3462 MS_U8 u8afbc_core_number = 0x0;
3463 HAL_GOP_AFBC_GetCore(pGOPHalLocal, u8_mainGop, &u8afbc_core_number);
3464 if (_isAfbcFunctionEnabled(pGOPHalLocal, u8afbc_core_number))
3465 {
3466 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MANUAL_CROP1, GOP_BIT4 | GOP_BIT5, GOP_BIT4 | GOP_BIT5);
3467 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4 | GOP_BIT5, GOP_BIT4 | GOP_BIT5);
3468 }
3469 #endif
3470
3471 // crop enable
3472 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4, GOP_BIT4);
3473 HAL_GOP_Write16Reg(pGOPHalLocal, u32CombineBankOffSet + GOP_4G_BANK_FWR, GOP_BIT4, GOP_BIT4);
3474 }
3475
3476 return GOP_SUCCESS;
3477 }
3478
Hal_Ctrl4K120GopMode(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_BOOL bEnable)3479 static GOP_Result Hal_Ctrl4K120GopMode(
3480 GOP_CTX_HAL_LOCAL *pGOPHalLocal,
3481 MS_U8 u8GOP,
3482 MS_BOOL bEnable
3483 )
3484 {
3485 MS_U32 u32MainBankOffSet=0xFFFF;
3486 MS_U32 u32SubBankOffSet=0xFFFF;
3487 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
3488 MS_U8 miuClient4MainGop = 0, miuClient4SubGop = 0;
3489
3490 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, u8GOP, &u8_mainGop, &u8_combinedGop) )
3491 {
3492 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
3493 return GOP_FAIL;
3494 }
3495
3496 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
3497 _GetBnkOfstByGop(u8_combinedGop, &u32SubBankOffSet);
3498
3499 // enable GOP to 4K120 mode
3500 if ((E_GOP0 == u8_mainGop) || (E_GOP2 == u8_mainGop))
3501 {
3502 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MIU_SEL, (TRUE == bEnable) ? GOP_BIT8 : ~GOP_BIT8, GOP_BIT8);
3503 }
3504
3505 if (E_GOP3 == u8_combinedGop)
3506 {
3507 if (TRUE == bEnable)
3508 {
3509 // set GOP3 v-stretch method to duplicate mode
3510 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet + GOP_4G_YUV_SWAP, 0, GOP_BIT9);
3511 }
3512 else if (FALSE == bEnable)
3513 {
3514 // restore GOP3 v-stretch method to duplicate mode
3515 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet + GOP_4G_YUV_SWAP, GOP_BIT9, GOP_BIT9);
3516 }
3517 }
3518
3519 if ((E_GOP0 == u8_mainGop) || (E_GOP2 == u8_mainGop))
3520 {
3521 // crop trigger & GOP trigger tie together
3522 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_BOT_HS, GOP_BIT12, GOP_BIT12);
3523 }
3524
3525 if ((bEnable == TRUE) && (E_GOP1 == u8_combinedGop))
3526 {
3527 HAL_GOP_Write16Reg(pGOPHalLocal, u32SubBankOffSet+GOP_4G_CTRL1, 0x4100, GOP_REG_HW_MASK);
3528 }
3529
3530 #ifdef GOP_SUPPORT_SPLIT_MODE
3531 if (E_GOP4 == u8_mainGop)
3532 {
3533 if ((bEnable == TRUE))
3534 {
3535 MS_U16 gwin_width, gwin_height;
3536 MS_U16 gwin_hstart, gwin_hend;
3537 MS_U16 gwin_vstart, gwin_vend;
3538
3539 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_HSTR, &gwin_hstart);
3540 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_HEND, &gwin_hend);
3541 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_VSTR, &gwin_vstart);
3542 HAL_GOP_Read16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_1GS0_VEND, &gwin_vend);
3543
3544 gwin_width = (gwin_hend > gwin_hstart) ? gwin_hend - gwin_hstart : 0;
3545 gwin_height = (gwin_vend > gwin_vstart) ? gwin_vend - gwin_vstart : 0;
3546
3547 // change the mouse moving method to split shift mode
3548 // 1. gwin size must smaller than 512 * 256
3549 if (gwin_width > GOP4_SPLITMODE_MAX_HSIZE)
3550 {
3551 gwin_hstart = 0;
3552 gwin_hend = GOP4_SPLITMODE_MAX_HSIZE;
3553 gwin_width = GOP4_SPLITMODE_MAX_HSIZE;
3554
3555 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3556 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3557 }
3558 if (gwin_height > GOP4_SPLITMODE_MAX_VSIZE)
3559 {
3560 gwin_vstart = 0;
3561 gwin_vend = GOP4_SPLITMODE_MAX_VSIZE;
3562 gwin_height = GOP4_SPLITMODE_MAX_VSIZE;
3563
3564 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3565 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3566 }
3567
3568 // 2. move to gwin hstart = 0 because pipe shift tie with GWIN position.
3569 gwin_hend -= gwin_hstart;
3570 gwin_hstart = 0;
3571 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, gwin_hstart, GOP_REG_WORD_MASK);
3572 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, gwin_hend, GOP_REG_WORD_MASK);
3573
3574 // 2. sync GOP4 stretch window & gwin size
3575 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_STRCH_HSZ, GOP_SPLIT_SUPPORT_MAXW/GOP_STRETCH_WIDTH_UNIT, GOP_REG_WORD_MASK);
3576
3577 // 3. garband = 0
3578 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_SLPIT_GUARDBAND, 0, GOP_REG_WORD_MASK);
3579
3580 // 4. each L/R size of OP, unit: 2pix (when 2p engine), reg_op_hsize = target timing / 2
3581 // but 4k@120 always on 2P mode
3582 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_SPLIT_LRSZ, (pGOPHalLocal->pHALShared->u16GopSplitMode_LRWIDTH[u8GOP] >> 1), GOP_REG_WORD_MASK);
3583
3584 // 5. enable split mode
3585 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MULTI_ALPHA, GOP_BIT15, GOP_BIT15);
3586 }
3587 else
3588 {
3589 // 5. disable split mode
3590 HAL_GOP_Write16Reg(pGOPHalLocal, u32MainBankOffSet + GOP_4G_MULTI_ALPHA, 0x0, GOP_BIT15);
3591 }
3592 }
3593
3594 #endif
3595
3596 if (TRUE == bEnable)
3597 {
3598 // if on 4K@120 mode, we need to sync the MIU client
3599 miuClient4MainGop = HAL_GOP_GetMIUDst(pGOPHalLocal, u8_mainGop);
3600 miuClient4SubGop = HAL_GOP_GetMIUDst(pGOPHalLocal, u8_combinedGop);
3601 if (miuClient4MainGop != miuClient4SubGop)
3602 {
3603 HAL_GOP_Set_MIU(pGOPHalLocal, u8_combinedGop, miuClient4MainGop);
3604 }
3605 }
3606
3607 return GOP_SUCCESS;
3608 }
3609
HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 u8win,MS_U16 hstart,MS_U16 hend,MS_U16 vstart,MS_U16 vend)3610 GOP_Result HAL_GOP_SetGopGwinHVPixel(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP, MS_U8 u8win, MS_U16 hstart, MS_U16 hend, MS_U16 vstart, MS_U16 vend)
3611 {
3612 GOP_Result ret = GOP_SUCCESS;
3613
3614 switch(u8GOP)
3615 {
3616 case E_GOP0:
3617 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3618 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3619 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VSTR(u8win), vstart, GOP_REG_WORD_MASK);
3620 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_4G_VEND(u8win), vend, GOP_REG_WORD_MASK);
3621 break;
3622
3623 case E_GOP1:
3624 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HSTR(u8win), hstart, GOP_REG_WORD_MASK);
3625 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_HEND(u8win), hend, GOP_REG_WORD_MASK);
3626 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VSTR(u8win), vstart, GOP_REG_WORD_MASK); // 1 pixel
3627 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_2G_VEND(u8win), vend, GOP_REG_WORD_MASK); // 1 pixel
3628 break;
3629
3630 case E_GOP2:
3631 case E_GOP3:
3632 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HSTR:GOP_1GX_HSTR, hstart, GOP_REG_WORD_MASK); // word pixels
3633 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_HEND:GOP_1GX_HEND, hend, GOP_REG_WORD_MASK); // word pixels
3634 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VSTR:GOP_1GX_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3635 HAL_GOP_Write16Reg(pGOPHalLocal, (u8win==GOP2_Gwin0Id)?GOP_1G_VEND:GOP_1GX_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3636 break;
3637
3638 case E_GOP4:
3639 if (pGOPHalLocal->pHALShared->GOP_Dst[u8GOP] == E_DRV_GOP_DST_OP_DUAL_RATE)
3640 {
3641 MS_U32 u32BankOffSet;
3642 _GetBnkOfstByGop(u8GOP, &u32BankOffSet);
3643
3644 // read the gwin hstart+hend might be a bad method
3645 // using varaiable directly
3646 MS_U16 win_hsz = (hend > hstart) ? hend - hstart : 0;
3647 MS_U16 win_vsz = (vend > vstart) ? vend - vstart : 0;
3648 MS_U16 gwin_hstart, gwin_hend;
3649 MS_U16 gwin_hsz;
3650 MS_U16 u16GopHScaleRatio;
3651
3652 if ((win_hsz > GOP4_SPLITMODE_MAX_HSIZE) || (win_vsz > GOP4_SPLITMODE_MAX_VSIZE))
3653 {
3654 // not support bigger than GOP4_SPLITMODE_MAX_HSIZE
3655 GOP_H_DBUG("cursor not support bigger than size : (%d, %d), set value : (%d, %d) \n", GOP4_SPLITMODE_MAX_HSIZE, GOP4_SPLITMODE_MAX_VSIZE, win_hsz, win_vsz);
3656 break;
3657 }
3658
3659 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_HSTR, &gwin_hstart);
3660 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_1GS0_HSTR, &gwin_hend);
3661 gwin_hsz = (gwin_hend > gwin_hstart) ? gwin_hend - gwin_hstart : 0;
3662
3663 if (win_hsz != gwin_hsz) // gwin size changed
3664 {
3665 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, 0, GOP_REG_WORD_MASK);
3666 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, win_hsz, GOP_REG_WORD_MASK);
3667 }
3668
3669 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_HSTRCH, &u16GopHScaleRatio);
3670 hstart = (MS_U16)(((MS_U32)hstart * SCALING_MULITPLIER) / u16GopHScaleRatio);
3671 HAL_GOP_Write16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_SLPIT_SHIFT_PIPE, hstart, GOP_REG_WORD_MASK);
3672
3673 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3674 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3675 }
3676 else
3677 {
3678 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HSTR, hstart, GOP_REG_WORD_MASK);
3679 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_HEND, hend, GOP_REG_WORD_MASK);
3680 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VSTR, vstart, GOP_REG_WORD_MASK); // 1 pixel
3681 HAL_GOP_Write16Reg(pGOPHalLocal, GOP_1GS0_VEND, vend, GOP_REG_WORD_MASK); // 1 pixel
3682 }
3683 break;
3684
3685 default:
3686 GOP_H_DBUG("invalid Gwin number:%d\n",u8win);
3687 break;
3688 }
3689
3690 return ret;
3691 }
3692
_findMuxNumberByGOP(GOP_CTX_HAL_LOCAL * pGOPHalLocal,DRV_GOPDstType dst_type,MS_U8 u8Gop)3693 static MS_U16 _findMuxNumberByGOP(GOP_CTX_HAL_LOCAL *pGOPHalLocal, DRV_GOPDstType dst_type, MS_U8 u8Gop)
3694 {
3695 MS_U16 ret_mux = INVALID_GOP_MUX_VAL;
3696
3697 if (E_DRV_GOP_DST_OP_DUAL_RATE == dst_type)
3698 {
3699 MS_U16 finding_mux_value = 0xFFFF;
3700 MS_U16 muxValue;
3701
3702 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MUX4_4K120, &muxValue);
3703
3704 if (E_GOP0 == u8Gop)
3705 {
3706 finding_mux_value = GOP_4K120MUX_MUX0;
3707 }
3708 else if (E_GOP2 == u8Gop)
3709 {
3710 finding_mux_value = GOP_4K120MUX_MUX1;
3711 }
3712 else if (E_GOP4 == u8Gop)
3713 {
3714 finding_mux_value = GOP_4K120MUX_MUX2;
3715 }
3716
3717 if (finding_mux_value == ((muxValue & GOP_4K120_MUX0_MASK) >> (GOP_4K120_MUX_SHIFT*0)))
3718 {
3719 ret_mux = GOP_4K120MUX_MUX0;
3720 }
3721 else if (finding_mux_value == ((muxValue & GOP_4K120_MUX1_MASK) >> (GOP_4K120_MUX_SHIFT*1)))
3722 {
3723 ret_mux = GOP_4K120MUX_MUX1;
3724 }
3725 else if (finding_mux_value == ((muxValue & GOP_4K120_MUX2_MASK) >> (GOP_4K120_MUX_SHIFT*2)))
3726 {
3727 ret_mux = GOP_4K120MUX_MUX2;
3728 }
3729 }
3730
3731 return ret_mux;
3732 }
3733
HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 u8GOP,MS_U8 * u8Core)3734 GOP_Result HAL_GOP_AFBC_GetCore(GOP_CTX_HAL_LOCAL *pGOPHalLocal, MS_U8 u8GOP,MS_U8* u8Core)
3735 {
3736 if(u8GOP==0)
3737 {
3738 *u8Core=0;
3739 }
3740 else
3741 {
3742 *u8Core=1;
3743 }
3744 return GOP_SUCCESS;
3745 }
3746
3747 #ifdef GOP_CMDQ_ENABLE
HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * cmdq_struct,MS_U32 * number,MS_U32 u32addr,MS_U16 u16val,MS_U16 mask)3748 GOP_Result HAL_GOP_CMDQ_WriteCommand(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *cmdq_struct,MS_U32 *number,MS_U32 u32addr, MS_U16 u16val, MS_U16 mask)
3749 {
3750 MS_U16 u16xcSubbank=0;
3751 MS_U32 bank;
3752 MS_U32 direct_addr;
3753
3754 switch (u32addr & 0xFF00)
3755 {
3756 case GOP_REG_BASE:
3757 {
3758 bank = (u32addr & 0xFF0000) >> 8;
3759
3760 if(bank==0xE00)//GOP4: 0x121B00
3761 {
3762 bank=GOP_REG_GOP4_BK_OFFSET;
3763 }
3764 else if(bank==0xF00)//GWIN4: 0x121E00
3765 {
3766 bank=GOP_REG_GOP4_GW_OFFSET;
3767 }
3768 else if(bank==0x1000) //GOP4_ST
3769 {
3770 bank=GOP_REG_GOP4_ST_OFFSET;
3771 }
3772
3773 if(bank==0x3100)//AFBC
3774 {
3775 direct_addr = AFBC_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3776 }
3777 else
3778 {
3779 direct_addr = GOP_REG_DIRECT_BASE + bank + (u32addr & 0xFF);
3780 }
3781 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3782 cmdq_struct[(*number)].destionation_value = u16val;
3783 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3784 cmdq_struct[(*number)].operation = 0x57;
3785 (*number)++;
3786 break;
3787 }
3788 case SC1_REG_BASE:
3789 u16xcSubbank = (u32addr & 0xFF0000)>>8 ;
3790 direct_addr = SC1_DIRREG_BASE + u16xcSubbank+ (u32addr & 0xFF);
3791
3792 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3793 cmdq_struct[(*number)].destionation_value = u16val;
3794 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3795 cmdq_struct[(*number)].operation = 0x57;
3796 (*number)++;
3797 break;
3798 case GE_REG_BASE:
3799 case CKG_REG_BASE:
3800 case MIU_REG_BASE:
3801 {
3802 cmdq_struct[(*number)].destionation_address = (u32addr&0xFFFFF)+0x100000;
3803 cmdq_struct[(*number)].destionation_value = u16val;
3804 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3805 cmdq_struct[(*number)].operation = 0x57;
3806 (*number)++;
3807 break;
3808 }
3809 #ifdef GOP_MIU_GROUP2
3810 case (MIU2_REG_BASE & 0xFF00):
3811 {
3812 direct_addr = MIU2_REG_BASE + (u32addr & 0xFF); //Direct_Base + addr_offset
3813
3814 cmdq_struct[(*number)].destionation_address = (direct_addr&0xFFFFFF);
3815 cmdq_struct[(*number)].destionation_value = u16val;
3816 cmdq_struct[(*number)].mask = ((~mask)&0xFFFF);
3817 cmdq_struct[(*number)].operation = 0x57;
3818 (*number)++;
3819 break;
3820 }
3821 #endif
3822 default:
3823 {
3824 //Gop lib current do not support this HW ip base
3825 GOP_ASSERT(0);
3826 break;
3827 }
3828
3829 }
3830 return GOP_SUCCESS;
3831 }
HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 * u32GopIdx)3832 GOP_Result HAL_GOP_CMDQ_BegineDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 *u32GopIdx)
3833 {
3834 MS_U32 u32BankOffSet;
3835 MS_U16 u16RegVal1 = 0;
3836 MS_BOOL bCheckValidGop = FALSE;
3837 MS_U8 u8CheckTimeCnt = 0;
3838 MS_U8 u8CurrentCmdGop = 0;
3839
3840 while (!bCheckValidGop && (u8CheckTimeCnt < (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0 + 2)))
3841 {
3842 if (u8CurrentCmdGop > (GOPG3_GOP_CMDQ_INT_3 - GOPG0_GOP_CMDQ_INT_0))
3843 {
3844 u8CurrentCmdGop = 0;
3845 }
3846 _GetBnkOfstByGop(u8CurrentCmdGop, &u32BankOffSet);
3847 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet + GOP_4G_CTRL0, &u16RegVal1);
3848 if ((u16RegVal1 & GOP_BIT0) != 0) // gop not init, cmdq won't work
3849 {
3850 bCheckValidGop = FALSE;
3851 }
3852 else
3853 {
3854 bCheckValidGop = TRUE;
3855 break;
3856 }
3857
3858 // if current gop not init, use next gop instead, check order 0->2->1->3
3859 switch (u8CurrentCmdGop)
3860 {
3861 case 0:
3862 u8CurrentCmdGop = 2;
3863 break;
3864 case 1:
3865 u8CurrentCmdGop = 0;
3866 break;
3867 case 2:
3868 u8CurrentCmdGop = 3;
3869 break;
3870 case 3:
3871 u8CurrentCmdGop = 1;
3872 break;
3873 default:
3874 u8CurrentCmdGop = 0;
3875 break;
3876 }
3877 u8CheckTimeCnt++;
3878 }
3879 if (!bCheckValidGop)
3880 {
3881 GOP_H_DBUG("[%s] Error message no avalible gop can support current cmdq!!\n",__FUNCTION__);
3882 }
3883
3884 *u32GopIdx = u8CurrentCmdGop;
3885 MDrv_CMDQ_Gen_WaitTrigger_Bus_Command(&(target[(*number)]),GOPG0_GOP_CMDQ_INT_0 + u8CurrentCmdGop,FALSE);
3886 (*number)++;
3887 return GOP_SUCCESS;
3888 }
HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL * pGOPHalLocal,CAF_Struct * target,MS_U32 * number,MS_U32 u32GopIdx)3889 GOP_Result HAL_GOP_CMDQ_EndDraw(GOP_CTX_HAL_LOCAL *pGOPHalLocal,CAF_Struct *target,MS_U32 *number, MS_U32 u32GopIdx)
3890 {
3891 CH_Struct ch_fire;
3892 MS_U32 Receive_Return_Value = 0,u32BankOffSet = 0,u32FireBankOffSet = 0,timer1 = 0x0,timer2 = 0x0;
3893 MS_U16 u16ret = 0,u16ret1 = 0;
3894 int i = 0;
3895
3896
3897 _GetBnkOfstByGop(0, &u32BankOffSet);
3898 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret);
3899 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,target,number,u32BankOffSet+GOP_4G_BG_CLR(1),u16ret+1,0xFFFF);//current GOP force write dis
3900 #if 0 //for Debug
3901 for(i=0;i<(*number);i++)
3902 {
3903 GOP_H_INFO("\33[0;36m [%d]op = %d, addr = %lx,value = %x,mask = %x\33[m \n",i,target[i].operation,target[i].destionation_address,target[i].destionation_value,target[i].mask);
3904 }
3905 #endif
3906 ch_fire.Command_Number = *number;
3907 ch_fire.Pointer_To_CAFArray = target;
3908 Receive_Return_Value = MDrv_CMDQ_Receive(&ch_fire);
3909 if(Receive_Return_Value == DRVCMDQ_CMDQ_FULL)
3910 {
3911 Receive_Return_Value = 0;
3912 MDrv_CMDQ_Printf_Crash_Command();
3913 }
3914
3915 _GetBnkOfstByGop(u32GopIdx, &u32FireBankOffSet);
3916 MsOS_DelayTask(1);
3917 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, GOP_BIT4, GOP_BIT4);//reset mask
3918 HAL_GOP_Write16Reg(pGOPHalLocal, u32FireBankOffSet+GOP_4G_MULTI_ALPHA, 0, GOP_BIT4); //reset nable detect
3919
3920 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3921 timer1 = MsOS_GetSystemTime();
3922 timer2 = MsOS_GetSystemTime();
3923 while( u16ret1 != (u16ret+1) && ((timer2 - timer1)<100))
3924 {
3925 HAL_GOP_Read16Reg(pGOPHalLocal,u32BankOffSet+GOP_4G_BG_CLR(1),&u16ret1);
3926 MsOS_DelayTask(1);
3927 timer2 = MsOS_GetSystemTime();
3928 }
3929 if(u16ret1 != (u16ret+1))
3930 {
3931 GOP_H_DBUG("\33[0;36m %s:%d timeout = %ld org = %d target = %d\33[m \n",__FUNCTION__,__LINE__,(timer2 - timer1),u16ret1,(u16ret+1));
3932 MDrv_CMDQ_Printf_Crash_Command();
3933 }
3934 return GOP_SUCCESS;
3935 }
3936
HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U8 gop)3937 GOP_Result HAL_GOP_CMDQ_SetGOPACK(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U8 gop)
3938 {
3939 CAF_Struct fire_struct[24];
3940 MS_U32 u32BankOffSet;
3941 MS_U32 number = 0;
3942 MS_U16 u16RegVal1 = 0,u16RegVal2 = 0,u16RegVal3 = 0,u16MiuClient = 0;
3943 MS_U16 u16RegMiu=0, u16RegCoreEna=0;
3944 MS_U32 fireGOP=0;
3945
3946 _GetBnkOfstByGop(gop, &u32BankOffSet);
3947
3948 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
3949 #ifdef GOP_MIU_GROUP2
3950 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
3951 #endif
3952 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
3953 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
3954
3955 switch(gop)
3956 {
3957 case E_GOP0:
3958 {
3959 u16MiuClient = GOP_MIU_CLIENT_GOP0;
3960 break;
3961 }
3962 case E_GOP1:
3963 {
3964 u16MiuClient = GOP_MIU_CLIENT_GOP1;
3965 break;
3966 }
3967 case E_GOP2:
3968 {
3969 u16MiuClient = GOP_MIU_CLIENT_GOP2;
3970 break;
3971 }
3972 case E_GOP3:
3973 {
3974 u16MiuClient = GOP_MIU_CLIENT_GOP3;
3975 break;
3976 }
3977 case E_GOP4:
3978 {
3979 u16MiuClient = GOP_MIU_CLIENT_GOP4;
3980 break;
3981 }
3982 default:
3983 {
3984 GOP_ASSERT(0);
3985 break;
3986 }
3987 }
3988 if(bMIUSelect[gop] == TRUE)
3989 {
3990 if(u16MIUSelect[gop] == 0)
3991 {
3992 u16RegVal1 &= ~(1<<u16MiuClient);
3993 u16RegVal3 &= ~(1<<u16MiuClient);
3994 }
3995 else if(u16MIUSelect[gop] == 1)
3996 {
3997 u16RegVal1 |= (1<<u16MiuClient);
3998 u16RegVal3 &= ~(1<<u16MiuClient);
3999 }
4000 else if(u16MIUSelect[gop] == 2)
4001 {
4002 u16RegVal1 &= ~(1<<u16MiuClient);
4003 u16RegVal3 |= (1<<u16MiuClient);
4004 }
4005 else if(u16MIUSelect[gop] == 3)
4006 {
4007 u16RegVal1 |= (1<<u16MiuClient);
4008 u16RegVal3 |= (1<<u16MiuClient);
4009 }
4010 bMIUSelect[gop] = FALSE;
4011 }
4012
4013 if(bAFBCMIUSelect[gop] == TRUE)
4014 {
4015 bAFBCMIUSelect[gop] = FALSE;
4016 }
4017 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4018 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4019 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
4020
4021 if(g_GopChipPro.bAFBC_Merge_GOP_Trig ==FALSE)
4022 {
4023 if(bAFBCMIUSelect[gop] == TRUE)
4024 {
4025 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
4026 bAFBCMIUSelect[gop] = FALSE;
4027 }
4028 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
4029 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
4030 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
4031 }
4032 #ifdef GOP_MIU_GROUP2
4033 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
4034 #endif
4035
4036 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
4037 return GOP_SUCCESS;
4038 }
4039
HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL * pGOPHalLocal,MS_U16 u16GopMask)4040 GOP_Result HAL_GOP_CMDQ_SetGOPACKMask(GOP_CTX_HAL_LOCAL *pGOPHalLocal,MS_U16 u16GopMask)
4041 {
4042 CAF_Struct fire_struct[24];
4043 MS_U32 u32BankOffSet=0;
4044 MS_U32 number = 0;
4045 MS_U8 gop=0;
4046 MS_U16 u16RegVal1=0,u16RegVal2=0,u16RegVal3 = 0,u16MiuClient = 0;
4047 MS_U16 u16RegMiu=0,u16RegCoreEna=0;
4048 MS_U32 fireGOP=0;
4049 MS_U16 bMiuChanged = FALSE;
4050 MS_U32 u32MainBankOffSet=0xFFFF;
4051 MS_U32 u32SubBankOffSet=0xFFFF;
4052 MS_U8 u8_mainGop = INVAILD_GOP_NUM, u8_combinedGop = INVAILD_GOP_NUM;
4053 MS_U8 miuClient4MainGop = 0, miuClient4SubGop = 0;
4054
4055 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP1, &u16RegVal1);
4056 #ifdef GOP_MIU_GROUP2
4057 HAL_GOP_Read16Reg(pGOPHalLocal, GOP_MIU_GROUP2, &u16RegVal3);
4058 #endif
4059 HAL_GOP_CMDQ_BegineDraw(pGOPHalLocal,fire_struct,&number,&fireGOP);
4060
4061 for(gop = 0; gop<MAX_GOP_SUPPORT; gop++)
4062 {
4063 switch(gop)
4064 {
4065 case E_GOP0:
4066 {
4067 u16MiuClient = GOP_MIU_CLIENT_GOP0;
4068 break;
4069 }
4070 case E_GOP1:
4071 {
4072 u16MiuClient = GOP_MIU_CLIENT_GOP1;
4073 break;
4074 }
4075 case E_GOP2:
4076 {
4077 u16MiuClient = GOP_MIU_CLIENT_GOP2;
4078 break;
4079 }
4080 case E_GOP3:
4081 {
4082 u16MiuClient = GOP_MIU_CLIENT_GOP3;
4083 break;
4084 }
4085 case E_GOP4:
4086 {
4087 u16MiuClient = GOP_MIU_CLIENT_GOP4;
4088 break;
4089 }
4090 default:
4091 {
4092 continue;
4093 }
4094 }
4095
4096 if( FALSE == Hal_get4K120CombinedGOP(pGOPHalLocal, gop, &u8_mainGop, &u8_combinedGop) )
4097 {
4098 GOP_H_ERR("Skipped [%s] Line %d !!", __FUNCTION__, __LINE__);
4099 return GOP_FAIL;
4100 }
4101 _GetBnkOfstByGop(u8_mainGop, &u32MainBankOffSet);
4102 _GetBnkOfstByGop(u8_combinedGop, &u32SubBankOffSet);
4103
4104 if ((gop == u8_combinedGop) && (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE))
4105 {
4106 continue;
4107 }
4108
4109 if( ( u16GopMask & (1<<gop) ) )
4110 {
4111 _GetBnkOfstByGop(gop, &u32BankOffSet);
4112 if(bMIUSelect[gop] == TRUE)
4113 {
4114 if(u16MIUSelect[gop] == 0)
4115 {
4116 u16RegVal1 &= ~(1<<u16MiuClient);
4117 u16RegVal3 &= ~(1<<u16MiuClient);
4118 }
4119 else if(u16MIUSelect[gop] == 1)
4120 {
4121 u16RegVal1 |= (1<<u16MiuClient);
4122 u16RegVal3 &= ~(1<<u16MiuClient);
4123 }
4124 else if(u16MIUSelect[gop] == 2)
4125 {
4126 u16RegVal1 &= ~(1<<u16MiuClient);
4127 u16RegVal3 |= (1<<u16MiuClient);
4128 }
4129 else if(u16MIUSelect[gop] == 3)
4130 {
4131 u16RegVal1 |= (1<<u16MiuClient);
4132 u16RegVal3 |= (1<<u16MiuClient);
4133 }
4134 bMIUSelect[gop] = FALSE;
4135 bMiuChanged = TRUE;
4136 }
4137
4138 if (pGOPHalLocal->pHALShared->GOP_Dst[u8_mainGop] == E_DRV_GOP_DST_OP_DUAL_RATE)
4139 {
4140 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
4141 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32MainBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4142 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32MainBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4143 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32SubBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4144 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32SubBankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4145 }
4146 else
4147 {
4148 HAL_GOP_Read16Reg(pGOPHalLocal, u32BankOffSet+GOP_4G_BANK_FWR,&u16RegVal2);
4149 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2|(GOP_BIT0)) ,0xFFFF);//current GOP force write en
4150 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,u32BankOffSet+GOP_4G_BANK_FWR,(u16RegVal2&(~GOP_BIT0)) ,0xFFFF);//current GOP force write en
4151 }
4152 }
4153 if(bAFBCMIUSelect[gop] == TRUE)
4154 {
4155 bAFBCMIUSelect[gop] = FALSE;
4156 }
4157 }
4158
4159 if(g_GopChipPro.bAFBC_Merge_GOP_Trig == FALSE)
4160 {
4161 if(g_GopChipPro.bAFBCMIUSelDoubleBuffer == FALSE)
4162 {
4163 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_MIU,u16AFBCMIUSelect[gop]<<4, 0xFFFF);
4164 }
4165 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT1, 0xFFFF);
4166 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,REG_AFBC_TRIGGER,GOP_BIT0, 0xFFFF);
4167 }
4168
4169 if (TRUE == bMiuChanged)
4170 {
4171 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP1,u16RegVal1,0xFFFF);
4172 #ifdef GOP_MIU_GROUP2
4173 HAL_GOP_CMDQ_WriteCommand(pGOPHalLocal,fire_struct,&number,GOP_MIU_GROUP2,u16RegVal3,0xFFFF);
4174 #endif
4175 }
4176
4177 HAL_GOP_CMDQ_EndDraw(pGOPHalLocal,fire_struct,&number,fireGOP);
4178 return GOP_SUCCESS;
4179 }
4180 #endif
4181
HAL_GOP_SetDbgLevel(EN_GOP_DEBUG_LEVEL level)4182 GOP_Result HAL_GOP_SetDbgLevel(EN_GOP_DEBUG_LEVEL level)
4183 {
4184 u32GOPDbgLevel_hal= level;
4185 return GOP_SUCCESS;
4186 }
4187
4188