1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 #ifndef _GPD_REG_H_ 79 #define _GPD_REG_H_ 80 81 #include "gpd.h" 82 83 #define GPD_SCALING_SUPPORT 84 85 typedef enum { 86 reg_gif_go_le, 87 reg_act_chk_le, 88 reg_gpd_bsaddr_go_le, 89 reg_gpd_rst_le, 90 reg_png_go_le, 91 reg_png_blk_go_le, 92 reg_gif_ltbl_size , 93 reg_gif_local_tbl , 94 reg_gif_done , 95 reg_ofifo_abort , 96 reg_ififo_full , 97 reg_ififo_empty , 98 reg_bsadr_full , 99 reg_ififo_diff , 100 reg_bitpos , 101 reg_png_dtbl_size , 102 reg_gif_state , 103 reg_gpd_pitch , 104 reg_gpd_iwidth , 105 reg_gpd_iheight , 106 reg_gpd_bstart , 107 reg_gpd_bend , 108 reg_gpd_istart , 109 reg_spare1 , 110 reg_gpd_boffset , 111 reg_iofifo_state , 112 reg_gpd_roi_hstart , 113 reg_gpd_roi_vstart , 114 reg_gpd_roi_width , 115 reg_gpd_roi_height , 116 reg_gpd_roi_en , 117 reg_gpd_default_alpha , 118 reg_spare2_rst0 , 119 reg_png_trans_r , 120 reg_png_trans_g , 121 reg_png_blk_done , 122 reg_png_mincode1 , 123 reg_png_mincode2 , 124 reg_png_mincode3 , 125 reg_png_mincode4 , 126 reg_png_mincode5 , 127 reg_png_mincode6 , 128 reg_png_mincode7 , 129 reg_gpd_ipm_en , 130 reg_gpd_ipm_size , 131 reg_gpd_ocolor , 132 reg_gpd_en, 133 reg_ofifo_done , 134 reg_miu_domain_empty , 135 reg_mreq_always_active , 136 reg_eng_always_active , 137 reg_png_ltbl_size , 138 reg_gpd_act_chk , 139 reg_png_sca , 140 reg_png_eob , 141 reg_png_mincode8 , 142 reg_png_mincode9 , 143 reg_png_mincode10 , 144 reg_png_mincode11 , 145 reg_png_mincode12 , 146 reg_png_mincode13 , 147 reg_png_mincode14 , 148 reg_png_mincode15 , 149 reg_png2_mincode1 , 150 reg_png2_mincode2 , 151 reg_png2_mincode3 , 152 reg_png2_mincode4 , 153 reg_png2_mincode5 , 154 reg_png2_mincode6 , 155 reg_png2_mincode7 , 156 reg_png2_mincode8 , 157 reg_png2_mincode9 , 158 reg_png2_mincode10 , 159 reg_png2_mincode11 , 160 reg_png2_mincode12 , 161 reg_png2_mincode13 , 162 reg_png2_mincode14 , 163 reg_png2_mincode15 , 164 reg_png_lbase2 , 165 reg_png_lbase3 , 166 reg_png_lbase4 , 167 reg_png_lbase5 , 168 reg_png_lbase6 , 169 reg_png_lbase7 , 170 reg_png_lbase8 , 171 reg_png_lbase9 , 172 reg_png_lbase10 , 173 reg_png_lbase11 , 174 reg_png_lbase12 , 175 reg_png_lbase13 , 176 reg_png_lbase14 , 177 reg_png_lbase15 , 178 reg_png_dbase2 , 179 reg_png_dbase3 , 180 reg_png_dbase4 , 181 reg_png_dbase5 , 182 reg_png_dbase6 , 183 reg_png_dbase7 , 184 reg_png_dbase8 , 185 reg_png_dbase9 , 186 reg_png_dbase10 , 187 reg_png_dbase11 , 188 reg_png_dbase12 , 189 reg_png_dbase13 , 190 reg_png_dbase14 , 191 reg_png_dbase15 , 192 reg_png_scline0_width , 193 reg_png_scline1_width , 194 reg_png_scline2_width , 195 reg_png_scline3_width , 196 reg_png_scline4_width , 197 reg_png_scline5_width , 198 reg_png_scline6_width , 199 reg_png_scline0_height , 200 reg_png_scline1_height , 201 reg_png_scline2_height , 202 reg_png_scline3_height , 203 reg_png_scline4_height , 204 reg_png_scline5_height , 205 reg_png_scline6_height , 206 reg_png_mincode_valid , 207 reg_png2_mincode_valid , 208 reg_gpd_only_decom_en , 209 reg_png_done , 210 reg_png_color_type , 211 reg_gpd_interlace , 212 reg_spare6 , 213 reg_png_compress_type , 214 reg_png_color_depth , 215 reg_miu_act_chk , 216 reg_png_trans_en , 217 reg_png_trans_b , 218 reg_png_state , 219 reg_ififo_cnt , 220 reg_hipri , 221 reg_gpd_premult_alpha_en, 222 reg_gpd_gif_alpha_mask_en, 223 reg_frun_cnt , 224 reg_png_burst_en , 225 reg_gif_mask , 226 reg_deflt_fast_on , 227 reg_ififo_radr , 228 reg_gpd_time_out , 229 reg_gif_code_size_err , 230 reg_gif_err , 231 reg_gpd_pgend , 232 reg_miu64 , 233 reg_gpd2mi_adr , 234 reg_wait_last_done , 235 reg_miu_wait_cyc , 236 reg_fixed_pri , 237 reg_last_done_md , 238 reg_gpd_read_data , 239 reg_io_read_gpd , 240 reg_cbuf_bas , 241 reg_zbuf_bas , 242 reg_bist_fail_lz_psram , 243 reg_bist_fail_bst_psram, 244 reg_bist_fail_lit_psram, 245 reg_bist_fail_flt_psram, 246 reg_bist_fail_lmem , 247 reg_bist_fail_cmem , 248 reg_bist_fail_omem , 249 reg_bist_fail_imem , 250 reg_bist_fail_dc0_cmem , 251 reg_bist_fail_dc1_cmem , 252 reg_bist_fail_stk_psram, 253 reg_bist_fail_dma1 , 254 reg_bist_fail_dma0 , 255 reg_bist_fail_cmd , 256 reg_bist_fail_data , 257 reg_bist_fail_cc_cmem , 258 reg_bist_fail_cc_dmem , 259 reg_bist_fail_cc_rdmem , 260 reg_bist_fail_cc_wdmem , 261 reg_bist_fail_zc_cmem , 262 reg_bist_fail_zc_dmem , 263 reg_bist_fail_zc_rdmem , 264 reg_bist_fail_zc_wdmem , 265 reg_int_mask , 266 reg_int_rst , 267 reg_debug_mux , 268 reg_dram_imi , 269 reg_gpd_istr_8b , 270 reg_gif_act_clr , 271 reg_int_status , 272 reg_int_sw_force , 273 reg_cache_hit_cmp , 274 reg_scale_en , 275 reg_scale_md , 276 reg_lb_addr , 277 reg_ub_addr , 278 reg_gpd_xiu_byte_sel , 279 reg_gpd_read_bits , 280 reg_gpd_reserved1 , 281 reg_gpd_cmem_wdata, 282 reg_png_ltbl_wdata, 283 reg_png_dtbl_wdata, 284 reg_debug2_mux , 285 reg_wbe_bypass_go_chk, 286 reg_gpd_sram_sd_en, 287 reg_gpd_debug , 288 reg_gpd_debug2, 289 reg_gpd_version, 290 reg_gpd_tlb 291 } gpd_reg_index; 292 293 294 #define reg_gif_go reg_gif_go_le 295 #define reg_act_chk reg_act_chk_le 296 #define reg_gpd_bsaddr_go reg_gpd_bsaddr_go_le 297 #define reg_gpd_rst reg_gpd_rst_le 298 #define reg_png_go reg_png_go_le 299 #define reg_png_blk_go reg_png_blk_go_le 300 #define reg_png_en reg_gpd_en 301 #define reg_gpd_cmem_wd reg_gpd_cmem_wdata 302 #define reg_png_ltbl_wd reg_png_ltbl_wdata 303 #define reg_png_dtbl_wd reg_png_dtbl_wdata 304 305 306 MS_U32 GPD_GET_MS_U32REG_dbg(MS_U32 index); 307 MS_U32 GPD_GET_MS_U32REG(MS_U32 index); 308 void GPD_SET_MS_U32REG(MS_U32 index, MS_U32 value); 309 MS_U32 hal_gpd_get_clkbase(void); 310 MS_U32 hal_gpd_get_clkoffset(void); 311 void hal_gpd_reg_base(MS_U32* u32RIUBase, MS_U32* u32XIUBase); 312 void hal_gpd_miu_client(MS_U8* u8Offset, MS_U16* u16BitMask); 313 void hal_gpd_init_outside_reg(MS_VIRT BankBaseAddr); 314 void hal_gpd_power_on(MS_VIRT BankBaseAddr); 315 void hal_gpd_power_off(MS_VIRT BankBaseAddr); 316 void hal_gpd_init_chip_specific_reg(void); 317 void hal_gpd_SetMIUProtectMask(MS_VIRT BankBaseAddr, MS_U8 bEnable); 318 319 320 #endif 321