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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regSERFLASH.h 98 /// @brief Serial Flash Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_SERFLASH_H_ 103 #define _REG_SERFLASH_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 // !!! Uranus Serial Flash Notes: !!! 111 // - The clock of DMA & Read via XIU operations must be < 3*CPU clock 112 // - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only 113 // - DMA program can't run on DRAM, but in flash ONLY 114 // - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned 115 116 117 //------------------------------------------------------------------------------------------------- 118 // Macro and Define 119 //------------------------------------------------------------------------------------------------- 120 121 // BASEADDR & BK 122 123 #define BASEADDR_RIU 0x1F000000 // TODO: <-@@@ CHIP SPECIFIC 124 #define BASEADDR_XIU 0x14000000 // FLASH0 // TODO: <-@@@ CHIP SPECIFIC 125 // #define BASEADDR_XIU 0xB8000000 // FLASH1 // TODO: use define instead of hard code e.g. CONFIG_SERFLASH1_SEL 126 #define BK_ISP 0x1000 127 #define BK_PIU 0x7800 128 #define BK_MHEG5 0x1E00 129 #define BK_PMSLP 0x1C00 130 #define BK_CLK0 0x1600 131 #define BK_QSPI 0x1400 132 #define BK_FSP 0x1200 133 #define BK_BDMA 0x1200 134 //----- Chip flash ------------------------- 135 #define REG_SPI_BASE 0x7F 136 137 // ISP_CMD 138 139 #define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive 140 #define REG_ISP_SPI_COMMAND 0x01 141 // please refer to the serial flash datasheet 142 #define ISP_SPI_CMD_WDSR BITS(7:0, 0x01) 143 #define ISP_SPI_CMD_READ BITS(7:0, 0x03) 144 #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) 145 #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) 146 #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) 147 #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) 148 #define ISP_SPI_CMD_SE BITS(7:0, 0x20) 149 #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) 150 #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) 151 #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) 152 #define ISP_SPI_CMD_PP BITS(7:0, 0x02) 153 #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) 154 #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash 155 #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) 156 #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) 157 #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) 158 #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) 159 #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) 160 #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash 161 #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) 162 #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) 163 #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) 164 /* MXIC Individual Block Protection Mode */ 165 #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) 166 #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) 167 #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) 168 #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) 169 #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) 170 #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) 171 #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) 172 #define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] 173 #define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] 174 #define REG_ISP_SPI_WDATA 0x04 175 #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) 176 #define REG_ISP_SPI_RDATA 0x05 177 #define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div 178 #define ISP_SPI_CLKDIV2 BIT(0) 179 #define ISP_SPI_CLKDIV4 BIT(2) 180 #define ISP_SPI_CLKDIV8 BIT(6) 181 #define ISP_SPI_CLKDIV16 BIT(7) 182 #define ISP_SPI_CLKDIV32 BIT(8) 183 #define ISP_SPI_CLKDIV64 BIT(9) 184 #define ISP_SPI_CLKDIV128 BIT(10) 185 #define REG_ISP_DEV_SEL 0x07 186 #define REG_ISP_SPI_CECLR 0x08 187 #define ISP_SPI_CECLR BITS(0:0, 1) 188 #define REG_ISP_SPI_RDREQ 0x0C 189 #define ISP_SPI_RDREQ BITS(0:0, 1) 190 #define REG_ISP_SPI_ENDIAN 0x0F 191 #define REG_ISP_SPI_RD_DATARDY 0x15 192 #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) 193 #define ISP_SPI_RD_DATARDY BITS(0:0, 1) 194 #define REG_ISP_SPI_WR_DATARDY 0x16 195 #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) 196 #define ISP_SPI_WR_DATARDY BITS(0:0, 1) 197 #define REG_ISP_SPI_WR_CMDRDY 0x17 198 #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) 199 #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) 200 #define REG_ISP_TRIGGER_MODE 0x2a 201 #define REG_ISP_CHIP_SEL 0x36 202 #define SFSH_CHIP_SEL_MASK BMASK(6:0) 203 #define SFSH_CHIP_SEL_FLASH1 BIT(0) 204 #define SFSH_CHIP_SEL_FLASH2 BIT(1) 205 #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) 206 #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) 207 #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) 208 #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) 209 #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) 210 // #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define 211 #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) 212 #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 213 #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 214 #define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel 215 #define SFSH_CHIP_RESET_MASK BMASK(2:2) 216 #define SFSH_CHIP_RESET BITS(2:2, 0) 217 #define SFSH_CHIP_NOTRESET BITS(2:2, 1) 218 #define REG_ISP_SPI_MODE 0x72 219 #define SFSH_CHIP_FAST_MASK BMASK(0:0) // SPI CMD [0x0B] 220 #define SFSH_CHIP_FAST_ENABLE BITS(0:0, 1) 221 #define SFSH_CHIP_FAST_DISABLE BITS(0:0, 0) 222 #define SFSH_CHIP_2XREAD_MASK BMASK(1:1) // SPI CMD [0xBB] 223 #define SFSH_CHIP_2XREAD_DADD_ENABLE BITS(1:1, 1) 224 #define SFSH_CHIP_2XREAD_DISABLE BITS(1:1, 0) 225 #define SFSH_CHIP_QUAD_MASK BMASK(3:0) 226 #define SFSH_CHIP_QUAD_ENABLE BITS(3:0, 0xA) 227 #define SFSH_CHIP_QUAD_DISABLE BITS(3:0, 0x0) 228 229 #define REG_ISP_SPI_CHIP_SELE 0x7A 230 #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; 231 #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) 232 #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) 233 #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) 234 #define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B 235 #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) 236 #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) 237 #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) 238 239 // PIU_DMA 240 241 #define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state 242 #define PIU_DMA_DONE_MASK BMASK(0:0) 243 #define PIU_DMA_DONE BITS(0:0, 1) 244 #define PIU_DMA_BUSY_MASK BMASK(1:1) 245 #define PIU_DMA_BUSY BITS(1:1, 1) 246 #define PIU_DMA_STATE_MASK BMASK(15:8) 247 #define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel 248 #define PIU_SPI_RESET_MASK BMASK(8:8) 249 #define PIU_SPI_RESET BITS(8:8, 1) 250 #define PIU_SPI_NOTRESET BITS(8:8, 0) 251 #define PSCS_DISABLE_MASK BMASK(0:0) 252 #define PSCS_INVERT_MASK BMASK(1:1) 253 #define PSCS_CLK_SEL_MASK BMASK(4:2) 254 #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) 255 #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) 256 #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) 257 #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) 258 #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) 259 #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) 260 #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) 261 #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) 262 #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) 263 #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) 264 #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) 265 #define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] 266 #define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] 267 #define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned 268 #define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] 269 #define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned 270 #define REG_PIU_DMA_SIZE_H 0x75 // [23:16] 271 #define REG_PIU_DMA_CMD 0x76 272 #define PIU_DMA_CMD_FIRE 0x0001 273 #define PIU_DMA_CMD_LE 0x0000 274 #define PIU_DMA_CMD_BE 0x0020 275 276 // Serial Flash Register // please refer to the serial flash datasheet 277 #define SF_SR_WIP_MASK BMASK(0:0) 278 #define SF_SR_WEL_MASK BMASK(1:1) 279 #define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) 280 #define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) 281 #define SF_SR_SRWD_MASK BMASK(7:7) 282 #define SF_SR_SRWD BITS(7:7, 1) 283 284 // PM_SLEEP CMD. 285 #define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. 286 #define PM_SPI_CLK_SEL_MASK BMASK(13:10) 287 #define PM_SPI_CLK_XTALI BITS(13:10, 0) 288 #define PM_SPI_CLK_54MHZ BITS(13:10, 1) 289 #define PM_SPI_CLK_86MHZ BITS(13:10, 2) 290 #define PM_SPI_CLK_108MHZ BITS(13:10, 3) 291 #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) 292 #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) 293 #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) 294 #define REG_PM_CHK_51MODE 0x53 295 #define PM_51_ON_SPI BITS(0:0, 0x1) 296 #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) 297 298 // For Power Consumption 299 #define REG_PM_GPIO_SPICZ_OEN 0x17 300 #define REG_PM_GPIO_SPICK_OEN 0x18 301 #define REG_PM_GPIO_SPIDI_OEN 0x19 302 #define REG_PM_GPIO_SPIDO_OEN 0x1A 303 #define REG_PM_SPI_IS_GPIO 0x35 304 #define PM_SPI_GPIO_MASK BMASK(3:0) 305 #define PM_SPI_IS_GPIO BITS(3:0, 0xF) 306 #define PM_SPI_NOT_GPIO BITS(3:0, 0x0) 307 308 // CLK_GEN0 309 #define REG_CLK0_CKG_SPI 0x16 310 #define CLK0_CKG_SPI_MASK BMASK(5:2) 311 #define CLK0_CKG_SPI_XTALI BITS(5:2, 0) 312 #define CLK0_CKG_SPI_54MHZ BITS(5:2, 1) 313 #define CLK0_CKG_SPI_86MHZ BITS(5:2, 2) 314 #define CLK0_CKG_SPI_108MHZ BITS(5:2, 3) 315 #define CLK0_CLK_SWITCH_MASK BMASK(6:6) 316 #define CLK0_CLK_SWITCH_OFF BITS(6:6, 0) 317 #define CLK0_CLK_SWITCH_ON BITS(6:6, 1) 318 319 //QSPI 320 #define REG_QSPI_MASK_GRANT 0x60 321 #define REG_DEBUG_BUS_0 0x76 322 #define REG_SPI_BURST_WRITE 0x6A 323 #define REG_SPI_DISABLE_BURST 0x02 324 #define REG_SPI_ENABLE_BURST 0x01 325 // please refer to the serial flash datasheet 326 #define SPI_CMD_READ (0x03) 327 #define SPI_CMD_FASTREAD (0x0B) 328 #define SPI_CMD_RDID (0x9F) 329 #define SPI_CMD_WREN (0x06) 330 #define SPI_CMD_WRDI (0x04) 331 #define SPI_CMD_SE (0x20) 332 #define SPI_CMD_32BE (0x52) 333 #define SPI_CMD_64BE (0xD8) 334 #define SPI_CMD_CE (0xC7) 335 #define SPI_CMD_PP (0x02) 336 #define SPI_CMD_RDSR (0x05) 337 #define SPI_CMD_RDSR2 (0x35) // support for new WinBond Flash#define SPI_CMD_WRSR (0x01) 338 #define FLASH_OIP 0x01 339 // FSP Register 340 // FSP 341 #define REG_FSP_WDB0 0x60 342 #define REG_FSP_WDB0_MASK BMASK(7:0) 343 #define REG_FSP_WDB0_DATA(d) BITS(7:0, d) 344 #define REG_FSP_WDB1 0x60 345 #define REG_FSP_WDB1_MASK BMASK(15:8) 346 #define REG_FSP_WDB1_DATA(d) BITS(15:8, d) 347 #define REG_FSP_WDB2 0x61 348 #define REG_FSP_WDB2_MASK BMASK(7:0) 349 #define REG_FSP_WDB2_DATA(d) BITS(7:0, d) 350 #define REG_FSP_WDB3 0x61 351 #define REG_FSP_WDB3_MASK BMASK(15:8) 352 #define REG_FSP_WDB3_DATA(d) BITS(15:8, d) 353 #define REG_FSP_WDB4 0x62 354 #define REG_FSP_WDB4_MASK BMASK(7:0) 355 #define REG_FSP_WDB4_DATA(d) BITS(7:0, d) 356 #define REG_FSP_WDB5 0x62 357 #define REG_FSP_WDB5_MASK BMASK(15:8) 358 #define REG_FSP_WDB5_DATA(d) BITS(15:8, d) 359 #define REG_FSP_WDB6 0x63 360 #define REG_FSP_WDB6_MASK BMASK(7:0) 361 #define REG_FSP_WDB6_DATA(d) BITS(7:0, d) 362 #define REG_FSP_WDB7 0x63 363 #define REG_FSP_WDB7_MASK BMASK(15:8) 364 #define REG_FSP_WDB7_DATA(d) BITS(15:8, d) 365 #define REG_FSP_WDB8 0x64 366 #define REG_FSP_WDB8_MASK BMASK(7:0) 367 #define REG_FSP_WDB8_DATA(d) BITS(7:0, d) 368 #define REG_FSP_WDB9 0x64 369 #define REG_FSP_WDB9_MASK BMASK(15:8) 370 #define REG_FSP_WDB9_DATA(d) BITS(15:8, d) 371 #define REG_FSP_RDB0 0x65 372 #define REG_FSP_RDB1 0x65 373 #define REG_FSP_RDB2 0x66 374 #define REG_FSP_RDB3 0x66 375 #define REG_FSP_RDB4 0x67 376 #define REG_FSP_RDB5 0x67 377 #define REG_FSP_RDB6 0x68 378 #define REG_FSP_RDB7 0x68 379 #define REG_FSP_RDB8 0x69 380 #define REG_FSP_RDB9 0x69 381 #define REG_FSP_WBF_SIZE 0x6a 382 #define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) 383 #define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) 384 #define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) 385 #define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) 386 #define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) 387 #define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) 388 #define REG_FSP_RBF_SIZE 0x6b 389 #define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) 390 #define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) 391 #define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) 392 #define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) 393 #define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) 394 #define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) 395 #define REG_FSP_CTRL 0x6c 396 #define REG_FSP_ENABLE_MASK BMASK(0:0) 397 #define REG_FSP_ENABLE BITS(0:0,1) 398 #define REG_FSP_DISABLE BITS(0:0,0) 399 #define REG_FSP_RESET_MASK BMASK(1:1) 400 #define REG_FSP_RESET BITS(1:1,0) 401 #define REG_FSP_NRESET BITS(1:1,1) 402 #define REG_FSP_INT_MASK BMASK(2:2) 403 #define REG_FSP_INT BITS(2:2,1) 404 #define REG_FSP_INT_OFF BITS(2:2,0) 405 #define REG_FSP_CHK_MASK BMASK(3:3) 406 #define REG_FSP_CHK BITS(3:3,1) 407 #define REG_FSP_CHK_OFF BITS(3:3,0) 408 #define REG_FSP_RDSR_MASK BMASK(12:11) 409 #define REG_FSP_1STCMD BITS(12:11,0) 410 #define REG_FSP_2NDCMD BITS(12:11,1) 411 #define REG_FSP_3THCMD BITS(12:11,2) 412 #define REG_FSP_FSCHK_MASK BMASK(13:13) 413 #define REG_FSP_FSCHK_ON BITS(13:13,1) 414 #define REG_FSP_FSCHK_OFF BITS(13:13,0) 415 #define REG_FSP_3THCMD_MASK BMASK(14:14) 416 #define REG_FSP_3THCMD_ON BITS(14:14,1) 417 #define REG_FSP_3THCMD_OFF BITS(14:14,0) 418 #define REG_FSP_2NDCMD_MASK BMASK(15:15) 419 #define REG_FSP_2NDCMD_ON BITS(15:15,1) 420 #define REG_FSP_2NDCMD_OFF BITS(15:15,0) 421 #define REG_FSP_TRIGGER 0x6d 422 #define REG_FSP_TRIGGER_MASK BMASK(0:0) 423 #define REG_FSP_FIRE BITS(0:0,1) 424 #define REG_FSP_DONE_FLAG 0x6e 425 #define REG_FSP_DONE_FLAG_MASK BMASK(0:0) 426 #define REG_FSP_DONE BITS(0:0,1) 427 #define REG_FSP_DONE_CLR 0x6f 428 #define REG_FSP_DONE_CLR_MASK BMASK(0:0) 429 #define REG_FSP_CLR BITS(0:0,1) 430 // Serial Flash Register // please refer to the serial flash datasheet 431 #define SF_SR_WIP_MASK BMASK(0:0) 432 #define SF_SR_WEL_MASK BMASK(1:1) 433 #define SF_SR_BP_MASK BMASK(5:2) 434 // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) 435 #define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) 436 #define SF_SR_SRWD_MASK BMASK(7:7) 437 #define SF_SR_SRWD BITS(7:7, 1) 438 #define REG_FSP_WRITEDATA_SIZE 0x4 439 #define REG_FSP_MAX_WRITEDATA_SIZE 0xA 440 #define REG_FSP_READDATA_SIZE 0xA 441 // FSP BUF definition 442 #define MAX_READ_BUF_CNT 0xA 443 #define SPI_FLASH_ADDR_LEN 0x3 444 #define SINGLE_WRITE_SIZE 0x4 445 #define ENABLE_SECOND_CMD 0x8000 446 #define ENABLE_THIRD_CMD 0x4000 447 #define ENABLE_AUTO_CHECK 0x2000 448 #define CHECK_CMD_OFFSET 0x1000 449 #define FLASH_PAGE_SIZE 0x100 450 #endif // _REG_SERFLASH_H_ 451