1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halPVR.h 20 // @brief PVR HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_PVR_H__ 24 #define __HAL_PVR_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM 4 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 //VQ define 36 #define VQ_NUM 4 37 #define VQ_PACKET_UNIT_LEN 208 38 39 #define TSP_TSIF0 0x00 40 #define TSP_TSIF1 0x01 41 #define TSP_TSIF2 0x02 42 #define TSP_TSIF3 0x03 43 44 //u32Cmd of MApi_DMX_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config, MS_U32 u32DataNum, void *pData); 45 #define HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK 0x00000001 //[u32Config] 1:disable cc check on fw, 0: enable cc check on fw; [u32DataNum,*pData] do not use 46 //######################################################################### 47 //#### Software Capability Macro Start 48 //######################################################################### 49 50 #define TSP_CA_RESERVED_FLT_NUM 1 51 #define TSP_RECFLT_NUM 1 52 #define TSP_PIDFLT_REC_NUM (TSP_PIDFLT_NUM - TSP_PCRFLT_NUM) // 0~189 (0 for CA) 53 // 193 for Err 54 // 192 for REC 55 // 191 for PCR1 56 // 190 for PCR0 57 58 ///#if HW_PCRFLT_ENABLE 59 //#define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 60 //#else 61 #define TSP_PIDFLT_NUM_ALL TSP_PIDFLT_NUM 62 //#endif 63 64 //######################################################################### 65 //#### Software Capability Macro End 66 //######################################################################### 67 68 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 69 #define TSP_CAFLT_START_ID 0 70 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) 71 72 // section FLT ID 73 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID 74 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID 75 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM - TSP_PCRFLT_NUM) 76 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM - TSP_PCRFLT_NUM) 77 78 // PID 79 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID 80 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM - TSP_PCRFLT_NUM) 81 82 // PCR 83 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID 84 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 85 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) 86 87 // REC 88 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID 89 90 //-------------------------------------------------------------------------------------------------- 91 // Driver Compiler Option 92 //-------------------------------------------------------------------------------------------------- 93 94 95 //-------------------------------------------------------------------------------------------------- 96 // PVR Hardware Abstraction Layer 97 //-------------------------------------------------------------------------------------------------- 98 99 // HW characteristic 100 101 typedef enum _PVRENG_SEQ 102 { 103 E_TSP_PVR_PVRENG_START = 0, 104 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 105 E_TSP_PVR_PVRENG_1, 106 E_TSP_PVR_PVRENG_2, 107 E_TSP_PVR_PVRENG_3, 108 E_TSP_PVR_PVRENG_END, 109 E_TSP_PVR_RASPENG_START = E_TSP_PVR_PVRENG_END, 110 E_TSP_PVR_RASPENG_0 = E_TSP_PVR_RASPENG_START, 111 E_TSP_PVR_RASPENG_1, 112 E_TSP_PVR_RASPENG_END, 113 E_TSP_PVR_CBPVRENG_START = E_TSP_PVR_RASPENG_END, 114 E_TSP_PVR_ENG_INVALID, 115 } PVRENG_SEQ; 116 117 typedef enum _FILEENG_SEQ 118 { 119 E_FILEENG_TSIF0 = TSP_TSIF0, 120 E_FILEENG_TSIF1 = TSP_TSIF1, 121 E_FILEENG_TSIF2 = TSP_TSIF2, 122 E_FILEENG_TSIF3 = TSP_TSIF3, 123 E_FILEENG_INVALID, 124 125 } FILEENG_SEQ; 126 127 #if 1 // Destination type 128 typedef enum _TSP_DST_SEQ 129 { 130 E_TSP_DST_FIFO_VIDEO, 131 E_TSP_DST_FIFO_VIDEO3D, 132 E_TSP_DST_FIFO_AUDIO, 133 E_TSP_DST_FIFO_AUDIO2, 134 E_TSP_DST_FIFO_AUDIO3, 135 E_TSP_DST_SEC, 136 E_TSP_DST_PVR_PVR0, 137 E_TSP_DST_PVR_PVR1, 138 E_TSP_DST_PVR_PVR2, 139 E_TSP_DST_PVR_PVR3, 140 E_TSP_DST_PVR_PVRCB, //Not support 141 E_TSP_DST_PVR_RASP0, //Not support 142 E_TSP_DST_PVR_RASP1, //Not support 143 E_TSP_DST_TSO_TSO0, 144 E_TSP_DST_TSO_TSO1, //Not support 145 E_TSP_DST_FIFO_AUDIO4, 146 E_TSP_DST_FIFO_VIDEO3, //Not support 147 E_TSP_DST_FIFO_VIDEO4, //Not support 148 E_TSP_DST_INVALID, 149 } TSP_DST_SEQ; 150 #else 151 #define TSP_FltType MS_U32 152 /// TS stream fifo type (Exclusive usage) 153 #define E_TSP_FLT_FIFO_MASK 0x000000FF 154 #define E_TSP_FLT_FIFO_VIDEO 0x00000001 155 #define E_TSP_FLT_FIFO_AUDIO 0x00000002 156 #define E_TSP_FLT_FIFO_AUDIO2 0x00000004 157 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000008 158 #endif 159 160 typedef enum _TSP_SRC_SEQ{ 161 E_TSP_SRC_PKTDMX0, 162 E_TSP_SRC_PKTDMX1, 163 E_TSP_SRC_PKTDMX2, 164 E_TSP_SRC_PKTDMX3, 165 E_TSP_SRC_PKTDMX4, //not used 166 E_TSP_SRC_PKTDMX5, //not used 167 E_TSP_SRC_MMFI0, 168 E_TSP_SRC_MMFI1, 169 170 E_TSP_SRC_INVALID, 171 } TSP_SRC_SEQ; 172 173 typedef enum _TSIF_CFG 174 { 175 // @NOTE should be Exclusive usage 176 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 177 E_TSP_TSIF_CFG_EN = 0x0001, 178 E_TSP_TSIF_CFG_PARA = 0x0002, 179 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 180 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 181 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 182 E_TSP_TSIF_CFG_3WIRE = 0x0010 183 } TSP_TSIF_CFG; 184 185 // for stream input source 186 typedef enum _HAL_TS_PAD 187 { 188 E_TSP_TS_PAD_EXT0, 189 E_TSP_TS_PAD_EXT1, 190 E_TSP_TS_PAD_EXT2, 191 E_TSP_TS_PAD_EXT3, // 4/3 wired serial mode 192 E_TSP_TS_PAD_EXT4, // 4/3 wired serial mode 193 E_TSP_TS_PAD_EXT5, // 4/3 wired serial mode 194 E_TSP_TS_PAD_EXT6, // 3 wired serial mode 195 E_TSP_TS_PAD_INTER0, 196 E_TSP_TS_PAD_INTER1, //not support, 197 E_TSP_TS_PAD_TSOUT0, 198 E_TSP_TS_PAD_TSOUT1, //not support,, 199 E_TSP_TS_PAD_INVALID, 200 } TSP_TS_PAD; 201 202 // for ts pad mode 203 typedef enum _HAL_TS_PAD_MUX_MODE 204 { 205 E_TSP_TS_PAD_MUX_PARALLEL, // in 206 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, // in 207 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, // in 208 E_TSP_TS_PAD_MUX_TSO, // out 209 E_TSP_TS_PAD_MUX_S2P, // out 210 E_TSP_TS_PAD_MUX_S2P1, // out 211 E_TSP_TS_PAD_MUX_DEMOD, // out 212 213 E_TSP_TS_PAD_MUX_INVALID 214 } TSP_TS_PAD_MUX_MODE; 215 216 217 // for pkt converter mode 218 typedef enum _HAL_TS_PKT_CONVERTER_MODE 219 { 220 E_TSP_PKT_CONVERTER_188Mode = 0, 221 E_TSP_PKT_CONVERTER_CIMode = 1, 222 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 223 E_TSP_PKT_CONVERTER_ATSMode = 3, 224 E_TSP_PKT_CONVERTER_MxLMode = 4, 225 E_TSP_PKT_CONVERTER_Invalid, 226 } TSP_TS_PKT_CONVERTER_MODE; 227 228 typedef enum _HAL_TS_MXL_PKT_MODE 229 { 230 E_TSP_TS_MXL_PKT_192 = 4, 231 E_TSP_TS_MXL_PKT_196 = 8, 232 E_TSP_TS_MXL_PKT_200 = 12, 233 E_TSP_TS_MXL_PKT_INVALID, 234 } TSP_TS_MXL_PKT_MODE; 235 236 237 typedef enum _HAL_DMX_FLOW_DST 238 { 239 E_TSP_DMX_FLOW_PLAYBACK, 240 E_TSP_DMX_FLOW_PLAYBACK1, 241 E_TSP_DMX_FLOW_PLAYBACK2, 242 E_TSP_DMX_FLOW_PLAYBACK3, 243 }_HAL_DMX_FLOW_DST; 244 245 246 typedef enum _HAL_TSP_CLK_TYPE 247 { 248 E_TSP_HAL_TSP_CLK, 249 E_TSP_HAL_STC_CLK, 250 E_TSP_HAL_INVALID 251 } EN_TSP_HAL_CLK_TYPE; 252 253 254 typedef struct _HAL_TSP_CLK_STATUS 255 { 256 MS_BOOL bEnable; 257 MS_BOOL bInvert; 258 MS_U8 u8ClkSrc; 259 } ST_TSP_HAL_CLK_STATUS; 260 261 262 typedef enum _PCR_SRC 263 { 264 /* register setting for kaiser pcr 265 0: tsif0 266 1: tsif1 267 2: tsif2 268 3: tsif3 269 4: tsif4 270 5: tsif5 271 6: un-used 272 7: un-used 273 8: pkt merge 0 274 9: pkt merge 1 275 a: MM file in 1 276 b: MM file in 2 277 */ 278 E_TSP_PCR_SRC_TSIF0 = 0, 279 E_TSP_PCR_SRC_TSIF1, 280 E_TSP_PCR_SRC_TSIF2, 281 E_TSP_PCR_SRC_TSIF3, 282 E_TSP_PCR_SRC_TSIF4, 283 E_TSP_PCR_SRC_TSIF5, 284 E_TSP_PCR_SRC_PKT_MERGE0 = 8, 285 E_TSP_PCR_SRC_PKT_MERGE1, 286 E_TSP_PCR_SRC_MMFI0, 287 E_TSP_PCR_SRC_MMFI1, 288 E_TSP_PCR_SRC_INVALID, 289 } TSP_PCR_SRC; 290 291 typedef enum _CLR_SRC 292 { 293 E_TSP_CLR_SRC_TSIF0, 294 E_TSP_CLR_SRC_TSIF1, 295 E_TSP_CLR_SRC_TSIF2, //not support 296 E_TSP_CLR_SRC_TSIF3, //not support 297 E_TSP_CLR_SRC_MMFI0, 298 E_TSP_CLR_SRC_MMFI1, 299 E_TSP_CLR_SRC_INVALID, 300 } TSP_CLR_SRC; 301 302 303 typedef enum _HAL_TSP_TSIF // for HW TSIF 304 { 305 E_TSP_HAL_TSIF_0 , 306 E_TSP_HAL_TSIF_1 , 307 E_TSP_HAL_TSIF_2 , 308 E_TSP_HAL_TSIF_3 , 309 E_TSP_HAL_TSIF_TSP_MAX , 310 E_TSP_HAL_TSIF_CB , //not support 311 E_TSP_HAL_TSIF_TSO0 , 312 E_TSP_HAL_TSIF_TSO1 , //not support 313 E_TSP_HAL_TSIF_RASP0 , 314 E_TSP_HAL_TSIF_RASP1 , 315 E_TSP_HAL_TSIF_EMMFLT , 316 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 317 E_TSP_HAL_TSIF_PVR0 , 318 E_TSP_HAL_TSIF_PVR1 , 319 E_TSP_HAL_TSIF_PVR2 , 320 E_TSP_HAL_TSIF_PVR3 , 321 E_TSP_HAL_TSIF_INVALID , 322 } TSP_HAL_TSIF; 323 324 325 typedef enum _TSP_HAL_FileState 326 { 327 /// Command Queue is Idle 328 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 329 /// Command Queue is Busy 330 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 331 /// Command Queue is Paused. 332 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 333 334 E_TSP_HAL_FILE_STATE_INVALID, 335 }TSP_HAL_FileState; 336 337 typedef enum 338 { 339 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 340 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 341 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 342 343 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 344 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 345 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 346 347 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 348 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 349 350 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 351 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 352 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 353 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 354 355 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 356 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 357 358 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 359 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 360 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 361 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 362 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 363 364 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 365 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 366 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 367 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 368 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 369 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 370 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 371 372 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 373 374 //27 is reserved, and can not be used 375 376 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 377 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 378 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 379 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 380 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 381 382 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 383 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 384 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 385 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 386 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 387 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 388 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 389 E_TSP_HAL_CAP_FIQ_NUM = 40, 390 E_TSP_HAL_CAP_TYPE_NULL, 391 } TSP_HAL_CAP_TYPE; 392 393 // @F_TODO remove unused enum member 394 typedef enum 395 { 396 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), 397 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), 398 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), 399 400 E_TSP_HAL_CAP_VAL_RECENG_NUM = 4, 401 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, 402 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, 403 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, 404 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 405 406 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 4, //MMFI0 filters 407 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 4, //MMFI1 filters 408 409 E_TSP_HAL_CAP_VAL_TSIF_NUM = 4, 410 E_TSP_HAL_CAP_VAL_DEMOD_NUM = 2, //internal demod 411 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 3, 412 E_TSP_HAL_CAP_VAL_VQ_NUM = 4, 413 414 E_TSP_HAL_CAP_VAL_CAFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), //@NOTE: flt number for descrypt purpose 415 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 416 417 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 418 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 419 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 420 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 421 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 422 423 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 424 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 425 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 426 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 427 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 428 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 429 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 430 431 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 432 433 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 2, 434 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 2, 435 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 436 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 437 438 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x4000, 439 440 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 441 } TSP_HAL_CAP_VAL; 442 443 /// TSP TEI Remove Error Packet Infomation 444 typedef enum 445 { 446 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 447 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT ///< TEI Remoce Video Packet 448 449 }TSP_HAL_TEI_RmPktType; 450 451 /// TSP Packet Converter Input Mode 452 typedef enum 453 { 454 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 455 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 456 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 457 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 458 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 459 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 460 E_TSP_HAL_PKT_MODE_MXL_200 ///< MXL mode (200 bytes) 461 462 }TSP_HAL_PKT_MODE; 463 464 //---------------------------------- 465 /// DMX debug table information structure 466 //---------------------------------- 467 468 typedef enum 469 { 470 E_TSP_HAL_FLOW_LIVE0, 471 E_TSP_HAL_FLOW_LIVE1, 472 E_TSP_HAL_FLOW_LIVE2, 473 E_TSP_HAL_FLOW_LIVE3, 474 E_TSP_HAL_FLOW_FILE0, 475 E_TSP_HAL_FLOW_FILE1, 476 E_TSP_HAL_FLOW_FILE2, 477 E_TSP_HAL_FLOW_FILE3, 478 E_TSP_HAL_FLOW_MMFI0, 479 E_TSP_HAL_FLOW_MMFI1, 480 481 E_TSP_HAL_FLOW_INVALID, 482 483 } TSP_HAL_FLOW; 484 485 486 //-------------------------------------------------------------------------------------------------- 487 // PVR HAL API 488 //-------------------------------------------------------------------------------------------------- 489 // Static Register Mapping for external access 490 #define REG_PIDFLT_BASE0 (0x00240000UL) 491 #define REG_PIDFLT_BASE1 (0x00241000UL) 492 #define REG_SECFLT_BASE (0x00221000UL) 493 #define REG_SECBUF_BASE (0x00221024UL) 494 #define REG_CTRL_BASE (0x00210200UL) 495 496 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 497 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 498 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 499 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 500 //#define _REGSynth ((REG_Synth*)(REG_SYNTH_BASE )) 501 502 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 503 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 504 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE+(_fltid>>5)*0x1000))->Flt[_fltid&(0x1F)])) 505 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE+(_bufid>>5)*0x1000))->Buf[_bufid&(0x1F)])) 506 507 #define TSIF2PKTDMX(_tsif) (((_tsif)<2)?(_tsif):((_tsif > 3)?(_tsif+2):(_tsif+1))) 508 509 #define PKTDMX2TSIF(_pktdmx) ((_pktdmx)>2)?(((_pktdmx)==2)?(_pktdmx-1):(_pktdmx)):(((_pktdmx)==5)?(_pktdmx-2):(_pktdmx-1)) 510 511 512 513 //******************** PIDFLT DEFINE START ********************// 514 // PID 515 #define TSP_PIDFLT_PID_MASK 0x00001FFF 516 #define TSP_PIDFLT_PID_SHFT 0 517 518 // Continuous counter 519 #define TSP_PIDFLT_CC_MASK 0xFF000000 520 #define TSP_PIDFLT_CC_SHFT 24 521 522 // PIDFLT SRC 523 typedef enum _TSP_PIDFLT_SRC 524 { 525 E_TSP_PIDFLT_LIVE0, 526 E_TSP_PIDFLT_LIVE1, 527 E_TSP_PIDFLT_LIVE2, 528 E_TSP_PIDFLT_LIVE3, 529 E_TSP_PIDFLT_FILE0, 530 E_TSP_PIDFLT_FILE1, 531 E_TSP_PIDFLT_FILE2, 532 E_TSP_PIDFLT_FILE3, 533 E_TSP_PIDFLT_INVALID, 534 } TSP_PIDFLT_SRC; 535 536 #define TSP_PIDFLT_IN_MASK 0x0000E000 537 #define TSP_PIDFLT_TSIF_SHFT 13 538 #define TSP_PIDFLT_TSIF0 0x00 539 #define TSP_PIDFLT_TSIF1 0x01 540 #define TSP_PIDFLT_TSIF2 0x02 541 #define TSP_PIDFLT_TSIF3 0x03 542 #define TSP_PIDFLT_TSIF_MAX 0x04 543 544 // Section filter Id (0~63) 545 #define TSP_PIDFLT_SECFLT_MASK 0x000000FF // [21:16] secflt id 546 #define TSP_PIDFLT_SECFLT_SHFT 0 547 548 // AF/Sec/Video/V3D/Audio/AudioB/AudioC/AudioD/PVR1/PVR2/PVR3/PVR4 549 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 550 #define TSP_PIDFLT_OUT_MASK 0x001FBF00 551 #define TSP_PIDFLT_OUT_SHFT 8 552 #define TSP_PIDFLT_OUT_NONE 0x00000000 553 #define TSP_PIDFLT_OUT_SECAF 0x00000100 554 #define TSP_PIDFLT_OUT_SECFLT 0x00000200 555 #define TSP_PIDFLT_OUT_VFIFO 0x00000400 556 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000800 557 #define TSP_PIDFLT_OUT_AFIFO 0x00001000 558 #define TSP_PIDFLT_OUT_AFIFO2 0x00002000 559 #define TSP_PIDFLT_OUT_VFIFO3 0x00000000 //Not Support 560 #define TSP_PIDFLT_OUT_AFIFO3 0x00080000 561 #define TSP_PIDFLT_OUT_AFIFO4 0x00100000 562 #define TSP_PIDFLT_OUT_VFIFO4 0x00000000 //Not Support 563 564 // SRC ID 565 #define TSP_PIDFLT_SRCID_MASK 0xF0000000 566 #define TSP_PIDFLT_SRCID_SHIFT 28 567 568 569 570 #define TSP_PIDFLT_PVRFLT_MASK 0x00078000 571 #define TSP_PIDFLT_PVRFLT_SHFT 15 572 #define TSP_PIDFLT_OUT_PVR1 0x00008000 573 #define TSP_PIDFLT_OUT_PVR2 0x00010000 574 #define TSP_PIDFLT_OUT_PVR3 0x00020000 575 #define TSP_PIDFLT_OUT_PVR4 0x00040000 576 577 578 #define TSP_PIDFLT_PKTPUSH_PASS_MASK 0x00200000 579 #define TSP_PIDFLT_PKTPUSH_PASS_SHFT 21 580 #define TSP_PID_FLT_PKTPUSH_PASS 0x00200000 581 582 #define TSP_PIDFLT_TSOFLT_MASK 0x00400000 583 #define TSP_PIDFLT_TSOFLT_SHFT 22 584 #define TSP_PID_FLT_OUT_TSO0 0x00400000 585 586 //******************** PIDFLT DEFINE END ********************// 587 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 588 MS_U32 TSP32_IdrR(TSP32 *preg); 589 590 //=========================TSIF================================ 591 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 592 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable); 593 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 594 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 595 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 596 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 597 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 598 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 599 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 600 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 601 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 602 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 603 void HAL_TSP_GetTSIF_Status(MS_U32 u32TsIfId, MS_U16* pu16Pad, MS_U16* pu16Clk, MS_BOOL* pbClkInv, MS_BOOL* pbExtSync, MS_BOOL* pbParl); 604 MS_BOOL HAL_TSP_GET_TSIF_FileEnStatus(MS_U32 u32FileEn); 605 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 606 607 //=========================TSP================================ 608 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn); 609 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 610 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn); 611 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 612 void HAL_TSP_Reset(MS_BOOL bEn); 613 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn); 614 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus); 615 void HAL_TSP_Power(MS_BOOL bEn); 616 void HAL_TSP_CPU(MS_BOOL bEn); 617 void HAL_TSP_ResetCPU(MS_BOOL bReset); 618 void HAL_TSP_HwPatch(void); 619 void HAL_TSP_RestoreFltState(void); 620 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 621 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn); 622 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 623 void HAL_TSP_PktBuf_Reset(MS_U32 pktBufId, MS_BOOL bEn); 624 void HAL_TSP_SaveFltState(void); 625 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 626 void HAL_TSP_FIFOPBFltFullSel(MS_U32 u32FIFOFullLevel); 627 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 628 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 629 void HAL_TSP_Bank1137_Write(MS_U32 u32Offset,MS_U16 u16Value); 630 631 //=========================TSO================================ 632 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 633 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 634 635 //=========================Filein================================ 636 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 637 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 638 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 639 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 640 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 641 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 642 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 643 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 644 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 645 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 646 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 647 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 648 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 649 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 650 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 651 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 652 653 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 654 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 655 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 656 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 657 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 658 /* 659 // Only used by [HW test code] 660 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 661 */ 662 663 //=========================PCR FLT================================ 664 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 665 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 666 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 667 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc);//[Jason] 668 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 669 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 670 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 671 672 //=========================STC================================ 673 void HAL_TSP_STC_Init(void); 674 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 675 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 676 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 677 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 678 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 679 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); 680 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); 681 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable); 682 683 //=========================FIFO================================ 684 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 685 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 686 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 687 void HAL_TSP_FIFO_ClearAll (void); 688 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 689 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 690 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 691 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 692 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 693 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 694 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 695 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 696 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 697 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 698 void HAL_TSP_PS_SRC(MS_U32 tsIf); 699 //void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 700 void HAL_TSP_Filein_Bypass(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 701 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType); // read A/V fifo data 702 MS_U16 HAL_TSP_FIFO_ReadPkt(void); // 703 void HAL_TSP_FIFO_Connect(MS_BOOL bEn); // 704 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 705 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn); 706 707 //=========================VQ================================ 708 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 709 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 710 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 711 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 712 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn); 713 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 714 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 715 716 //=========================Pid Flt================================ 717 //void HAL_TSP_PidFlt_SetFltOut(MS_U32 pPidFlt, MS_U32 u32FltOu); 718 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 719 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 720 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 721 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 722 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 723 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 724 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn); 725 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 726 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 727 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 728 729 //=========================SecFlt================================ 730 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 731 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 732 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 733 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 734 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 735 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 736 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 737 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 738 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 739 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFlt, MS_U32 u32ReqCount); 740 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 741 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFlt); 742 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 743 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 744 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 745 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 746 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 747 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 748 749 //=========================Sec Buf================================ 750 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 751 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 752 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 753 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 754 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 755 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 756 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 757 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 758 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 759 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 760 761 //=========================PVR================================ 762 void HAL_PVR_SetBank(MS_U32 u32BankAddr); 763 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 764 void HAL_PVR_Exit(MS_U32 u32PVREng); 765 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 766 /* 767 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 768 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 769 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 770 */ 771 void HAL_PVR_FlushData(MS_U32 u32PVREng); 772 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 773 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 774 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 775 void HAL_PVR_Start(MS_U32 u32PVREng); 776 void HAL_PVR_Stop(MS_U32 u32PVREng); 777 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 778 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 779 void HAL_PVR_RecNull(MS_BOOL bSet); 780 void HAL_PVR_SetPidflt(MS_U32 u32PVREng, MS_U16 u16Fltid, MS_U16 u16Pid); 781 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 782 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 783 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 784 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 785 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 786 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 787 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 788 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 789 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 790 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 791 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable); 792 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime); 793 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 794 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 795 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 796 /* 797 void HAL_TSP_PVR_SPSConfig(MS_U8 u8Eng, MS_BOOL CTR_mode); 798 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode); 799 */ 800 801 //=========================RASP================================ 802 MS_U32 HAL_RASP_Set_Source(MS_U32 u32RASPEng, MS_U32 pktDmxId); 803 MS_U32 HAL_RASP_Get_Source(MS_U32 u32RASPEng, TSP_SRC_SEQ *eSrc); 804 805 //=========================HCMD================================ 806 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 807 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 808 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 809 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 810 MS_BOOL HAL_TSP_HCMD_Alive(void); 811 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 812 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 813 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 814 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 815 816 //=========================INT================================ 817 void HAL_TSP_INT_Enable(MS_U32 u16Mask); 818 void HAL_TSP_INT_Disable(MS_U32 u16Mask); 819 void HAL_TSP_INT_ClrHW(MS_U32 u16Mask); 820 MS_U32 HAL_TSP_INT_GetHW(void); 821 void HAL_TSP_INT_ClrSW(void); 822 MS_U32 HAL_TSP_INT_GetSW(void); 823 824 //=========================Mapping================================ 825 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 826 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 827 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 828 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 829 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 830 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 831 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 832 MS_U32 HAL_TSP_PVRRASPEngMapping(MS_U32 u32Eng); 833 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 834 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 835 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 836 837 //========================DSCMB Functions=================================== 838 extern MS_BOOL HAL_DSCMB_GetBank(MS_U32 *u32Bank); 839 extern MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 840 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 841 842 //========================MOBF Functions===================================== 843 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 844 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 845 846 //========================Protection range=================================== 847 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 848 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 849 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 850 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 851 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 852 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 853 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 854 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 855 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 856 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 857 858 //========================Debug table============================= 859 void HAL_TSP_FltNullPkt_En(MS_BOOL bEn); 860 861 // @TODO Renaming Load and Get 862 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 863 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 864 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_BOOL bLock); 865 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif); 866 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 867 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 868 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 869 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 870 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 871 872 // @TODO Implement Drop and Dis Hal 873 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId); 874 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn); 875 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload); 876 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop); 877 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 878 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 879 880 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 881 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 882 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void); 883 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif); 884 885 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); 886 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 887 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); 888 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); 889 890 //========================MergeStream Functions============================= 891 void HAL_TSP_PktConverter_Init(void); 892 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 893 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet); 894 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet); 895 /* 896 void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen); 897 */ 898 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 899 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId); 900 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 901 902 #endif // #ifndef __HAL_PVR_H__ 903