1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 ////////////////////////////////////////////////////////////////////////////////
93 #define _HAL_NSK2_C
94
95 ////////////////////////////////////////////////////////////////////////////////
96 /// @file halEMMflt.c
97 /// @author MStar Semiconductor Inc.
98 /// @brief
99 ////////////////////////////////////////////////////////////////////////////////
100
101 ////////////////////////////////////////////////////////////////////////////////
102 // Header Files
103 ////////////////////////////////////////////////////////////////////////////////
104 #ifdef MSOS_TYPE_LINUX_KERNEL
105 #include <linux/string.h>
106 #else
107 #include "string.h"
108 #endif
109
110 #include "MsCommon.h"
111 #include "MsTypes.h"
112 #include "drvSYS.h"
113
114 #include "halNSK2.h"
115 #include "regNSK2.h"
116 #include "MsOS.h"
117
118 #include "regTSP.h"
119 #include "halTSP.h"
120 #include "drvDSCMB.h"
121 #include "halDSCMB.h"
122
123 #include "drvNSK2Type.h"
124 #include "drvCA.h"
125
126 #include "nsk_282.h"
127
128 ////////////////////////////////////////////////////////////////////////////////
129 // Define & data type
130 ///////////////////////////////////////////////////////////////////////////////
131
132 #define POLLING_CNT 100
133 #define BUSYCHECK_CNT 100
134
135 static MS_U32 _gBasicAddr = 0;
136 static MS_U32 _gNSK2_Addr = 0;
137 static MS_U32 _gOTP_Addr = 0;
138 static MS_U32 _gOTP_CTRL_Addr = 0;
139 static MS_U32 _gNI_Addr = 0;
140 static MS_U32 _gRSA_Addr = 0;
141 static MS_U32 _gKeyTable_Addr = 0;
142 static MS_U32 _gNDSJTagPwd_Addr = 0;
143 static MS_U32 _gCipherCH0_Addr = 0;
144 static MS_U32 _gCryptoDMA_Addr = 0;
145
146 static MS_U32 _g32NSK2HalDbgLv = NSK2_DBGLV_DEBUG;
147
148 #define HALNSK2_DBG(lv, x, args...) if (lv <= _g32NSK2HalDbgLv ) \
149 {printf(x, ##args);}
150
151 //bank 0x1700
152 #define OTP_REG(addr) (*((volatile MS_U32*)(_gOTP_Addr + addr )))
153
154 //bank 0x1a13
155 #define OTP_CTRL_REG(addr) (*((volatile MS_U32*)(_gOTP_CTRL_Addr + (addr<<2) )))
156
157 //bank 0x1620
158 #define NI_REG(addr) (*((volatile MS_U32*)(_gNI_Addr + (addr<<2) )))
159
160 //bank 1630
161 #define RSA_REG(addr) (*((volatile MS_U32*)(_gRSA_Addr + (addr<<2) )))
162
163 //bank 1626
164 #define KeyTable_REG(addr) (*((volatile MS_U32*)(_gKeyTable_Addr + (addr<<2) )))
165
166 //bank xxxxxx
167 #define NDSJTagPwd_REG(addr) (*((volatile MS_U16*)(_gNDSJTagPwd_Addr + (addr<<2) )))
168
169 //bank 1621
170 #define CMCHANNEL0_REG(addr) (*((volatile MS_U32*)(_gCipherCH0_Addr + (addr<<2) )))
171
172
173 //#define FPGAMode
174 //#define NSK2SelfTest
175
176 //#define TestGenIn
177 //#define ReadSwitchInfoNSK2
178
179
180 #define StatusCheck(status) do { if(status == FALSE) \
181 { \
182 printf("status error %s, %d\n",__FUNCTION__,__LINE__); \
183 return status; \
184 } \
185 } while(0);
186
187 #define NSK2HDI_CMCHANNEL_WITH_ALL_PARITY ( NSK2HDI_CMCHANNEL_CLEAR_PARITY | NSK2HDI_CMCHANNEL_EVEN_PARITY | NSK2HDI_CMCHANNEL_EVEN_CLEAR_PARITY | NSK2HDI_CMCHANNEL_ODD_PARITY | \
188 NSK2HDI_CMCHANNEL_ODD_CLEAR_PARITY | NSK2HDI_CMCHANNEL_ODD_EVEN_PARITY | NSK2HDI_CMCHANNEL_ODD_EVEN_CLEAR_PARITY )
189
190 #define CMCHANNEL_NSK_All_CAPABILITY (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG)
191
192 ////////////////////////////////////////////////////////////////////////////////
193 // Local variable
194 ////////////////////////////////////////////////////////////////////////////////
195
196 static MS_BOOL _gReset = FALSE;
197 static MS_BOOL _gCheckBusyFlag = FALSE;
198 static MS_U32 dead_polling_cnt = 1;
199
200 static cmchannel_group_capability_descriptor_t cm_capb =
201 {
202 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_CAPABILITY_DESC_TAG,
203 .descriptor_length = sizeof(cmchannel_group_capability_descriptor_t) - 2,
204 .number_of_channels[3] = 40,
205 .switch_combination_bitmap[0] = 0xff,
206 .user_context[0] = 'M',
207 .user_context[1] = 'S',
208 .user_context[2] = 't',
209 .user_context[3] = 'a',
210 .user_context[4] = 'r',
211 .user_context[5] = 0x00,
212 .user_context[6] = 0x00,
213 .user_context[7] = 0x00,
214 };
215
216 static cmchannel_group_algorithm_record_descriptor_t cm_algo[] =
217 {
218
219 //-------------------------------LSA---------------------------------------//
220 {
221 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
222 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
223 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
224 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_CBC,
225 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
226 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
227 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
228 },
229
230 {
231 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
232 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
233 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
234 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_RCBC,
235 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
236 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
237 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
238 },
239
240 {
241 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
242 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
243 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
244 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_CBC,
245 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
246 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
247 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
248 },
249
250 {
251 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
252 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
253 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
254 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_RCBC,
255 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
256 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
257 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
258 },
259
260 {
261 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
262 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
263 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
264 .algorithm = NSK2HDI_SPROFILE_SYNAMEDIA_AES,
265 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
266 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
267 },
268
269 {
270 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
271 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
272 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
273 .algorithm = NSK2HDI_SPROFILE_AES_ECB_CLEARTAIL,
274 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
275 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
276 },
277
278 {
279 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
280 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
281 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
282 .algorithm = NSK2HDI_SPROFILE_CIPLUS_AES,
283 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
284 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
285 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
286 },
287
288 {
289 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
290 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
291 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
292 .algorithm = NSK2HDI_SPROFILE_SCTE41_DES,
293 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
294 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
295 },
296
297 {
298 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
299 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
300 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
301 .algorithm = NSK2HDI_SPROFILE_SCTE52_DES,
302 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
303 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
304 .capability = CMCHANNEL_NSK_All_CAPABILITY,
305 },
306
307 {
308 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
309 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
310 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
311 .algorithm = NSK2HDI_SPROFILE_TDES_ECB_CLEARTAIL,
312 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
313 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
314 },
315
316
317 //-------------------------------LSA---------------------------------------//
318 //10
319
320
321
322 //-------------------------------ESA---------------------------------------//
323 {
324 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
325 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
326 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
327 .algorithm = NSK2HDI_SPROFILE_DVB_CSA2,
328 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
329 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
330 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
331 },
332
333
334 {
335 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
336 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
337 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
338 .algorithm = NSK2HDI_SPROFILE_DVB_CSA_CONFORMANCE,
339 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
340 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
341 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
342 },
343
344 {
345 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
346 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
347 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
348 .algorithm = NSK2HDI_SPROFILE_DVB_CSA3,
349 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
350 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
351 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
352 },
353
354
355 {
356 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
357 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
358 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
359 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_CBC,
360 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
361 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
362 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
363 },
364
365 {
366 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
367 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
368 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
369 .algorithm = NSK2HDI_SPROFILE_SYNAMEDIA_AES,
370 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
371 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
372 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
373 },
374
375 {
376 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
377 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
378 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
379 .algorithm = NSK2HDI_SPROFILE_AES_ECB_CLEARTAIL,
380 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
381 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
382 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
383 },
384
385
386 {
387 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
388 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
389 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
390 .algorithm = NSK2HDI_SPROFILE_CIPLUS_AES,
391 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
392 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
393 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
394 },
395
396 {
397 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
398 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
399 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
400 .algorithm = NSK2HDI_SPROFILE_SCTE41_DES,
401 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
402 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
403 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
404 },
405
406 {
407 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
408 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
409 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
410 .algorithm = NSK2HDI_SPROFILE_SCTE52_DES,
411 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
412 .capability = CMCHANNEL_NSK_All_CAPABILITY,
413 },
414
415 {
416 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
417 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
418 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
419 .algorithm = NSK2HDI_SPROFILE_TDES_ECB_CLEARTAIL,
420 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
421 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
422 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
423 },
424
425
426 {
427 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
428 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
429 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
430 .algorithm = NSK2HDI_SPROFILE_MULTI2_TS,
431 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
432 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
433 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
434 },
435 //-------------------------------ESA---------------------------------------//
436 //24
437
438 //-------------------------------LDA---------------------------------------//
439 {
440 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
441 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
442 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
443 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_CBC,
444 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
445 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
446 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
447 },
448
449 {
450 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
451 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
452 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
453 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_RCBC,
454 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
455 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
456 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
457 },
458
459 {
460 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
461 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
462 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
463 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_CBC,
464 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
465 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
466 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
467 },
468
469 {
470 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
471 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
472 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
473 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_RCBC,
474 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
475 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
476 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
477 },
478
479 {
480 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
481 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
482 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
483 .algorithm = NSK2HDI_SPROFILE_SYNAMEDIA_AES,
484 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
485 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
486 },
487
488 {
489 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
490 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
491 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
492 .algorithm = NSK2HDI_SPROFILE_AES_ECB_CLEARTAIL,
493 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
494 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
495 },
496
497 {
498 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
499 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
500 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
501 .algorithm = NSK2HDI_SPROFILE_CIPLUS_AES,
502 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
503 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
504 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
505 },
506
507 {
508 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
509 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
510 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
511 .algorithm = NSK2HDI_SPROFILE_SCTE41_DES,
512 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
513 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
514 },
515
516 {
517 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
518 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
519 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
520 .algorithm = NSK2HDI_SPROFILE_SCTE52_DES,
521 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
522 .capability = CMCHANNEL_NSK_All_CAPABILITY,
523 },
524
525 {
526 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
527 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
528 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
529 .algorithm = NSK2HDI_SPROFILE_TDES_ECB_CLEARTAIL,
530 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
531 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
532 },
533
534 //-------------------------------LDA---------------------------------------//
535 //34
536
537 };
538
539 static M2MChGr_Capa_Desc_t m2m_capa_desc = {
540 .descriptor_tag = NSK2HDI_M2MCHANNELGROUP_CAPABILITY_DESC_TAG,
541 .descriptor_length = sizeof(M2MChGr_Capa_Desc_t) - 2,
542 .number_of_channels[3] = 0x1,
543 .user_context[0] = 0x4e,
544 .user_context[1] = 0x44,
545 .user_context[2] = 0x53,
546 .user_context[3] = 0x5f,
547 .user_context[4] = 0x44,
548 .user_context[5] = 0x52,
549 .user_context[6] = 0x4d,
550 .user_context[7] = 0x00,
551 };
552
553 static M2MChGr_AlgoRecord_Desc_t m2m_algo[] =
554 {
555 {
556 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
557 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
558 .algorithm = NSK2HDI_SPROFILE_M2M_DES_ECB_CLR_CLR,
559 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
560 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
561 },
562
563 {
564 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
565 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
566 .algorithm = NSK2HDI_SPROFILE_M2M_DES_CBC_SCTE52_IV1,
567 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
568 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
569 },
570
571 {
572 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
573 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
574 .algorithm = NSK2HDI_SPROFILE_M2M_DES_CBC_SCTE52_IV2,
575 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
576 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
577 },
578
579 {
580 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
581 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
582 .algorithm = NSK2HDI_SPROFILE_M2M_DES_CBC_CLR_CLR,
583 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
584 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
585 },
586
587 {
588 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
589 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
590 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_ECB_CLR_CLR,
591 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
592 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
593 },
594
595 {
596 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
597 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
598 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_CBC_SCTE52_IV1,
599 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
600 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
601 },
602
603 {
604 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
605 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
606 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_CBC_SCTE52_IV2,
607 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
608 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
609 },
610
611 {
612 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
613 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
614 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_CBC_CLR_CLR,
615 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
616 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
617 },
618
619 {
620 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
621 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
622 .algorithm = NSK2HDI_SPROFILE_M2M_AES_ECB_CLR_CLR,
623 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
624 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
625 },
626
627 {
628 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
629 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
630 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_CTS_IV1,
631 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
632 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
633 },
634
635 {
636 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
637 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
638 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_CTS_CLR,
639 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
640 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
641 },
642
643 {
644 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
645 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
646 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_SCTE52_IV1,
647 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
648 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
649 },
650
651 {
652 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
653 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
654 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_SCTE52_CLR,
655 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
656 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
657 },
658
659 {
660 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
661 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
662 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_CLR_CLR,
663 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
664 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
665 },
666
667 {
668 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
669 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
670 .algorithm = NSK2HDI_SPROFILE_M2M_RC4_64,
671 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
672 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
673 },
674
675 {
676 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
677 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
678 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CTR,
679 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
680 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
681 },
682 };
683
684
685 static DMA_Capa_Desc_t dma_capa_desc = {
686 .descriptor_tag = NSK2HDI_DMA_CAPABILITY_DESC_TAG,
687 .descriptor_length = sizeof(DMA_Capa_Desc_t) - 2,
688 .maximum_data_size[0] = 0,
689 .maximum_data_size[1] = 0,
690 .maximum_data_size[2] = 0,
691 .maximum_data_size[3] = 1,
692 .minimum_data_size[0] = 0x01,
693 .data_size_granularity[0] = 0x4,
694 .data_alignment[0] = 0x4,
695 .capability[0] = NSK2HDI_DMA_CONTIGUOUS_MEMORY_TYPE,
696 };
697 ////////////////////////////////////////////////////////////////////////////////
698 // Global variable
699 ////////////////////////////////////////////////////////////////////////////////
700
701
702
703 ////////////////////////////////////////////////////////////////////////////////
704 // Extern Function
705 ////////////////////////////////////////////////////////////////////////////////
706
707 extern MS_U32 TSP32_IdrR(TSP32 *preg);
708 extern void TSP32_IdrW(TSP32 *preg, MS_U32 value);
709 extern int ChkForNskTest(volatile unsigned int *OtpMemBase, volatile unsigned int *RSABase,
710 volatile unsigned int *NIBase, volatile unsigned int *CCh0Base);
711 extern int HW_CompareKTvalid(unsigned int pid_no, unsigned int scb, unsigned int compare, volatile unsigned int *KTBase);
712 extern void acpu_w_pidslotmap (unsigned char indx, unsigned char wmux, unsigned char wdata, volatile unsigned int *KTBase);
713 extern void acpu_r_keyslot (unsigned char key_indx, unsigned char key_field, volatile unsigned int *KTBase);
714
715
716 ////////////////////////////////////////////////////////////////////////////////
717 // Function Declaration
718 ////////////////////////////////////////////////////////////////////////////////
719
720 ////////////////////////////////////////////////////////////////////////////////
721 // Local Function
722 ////////////////////////////////////////////////////////////////////////////////
723
724
HAL_NSK2_ReadReg(MS_U32 u32RegAddr)725 static MS_U32 HAL_NSK2_ReadReg(MS_U32 u32RegAddr)
726 {
727 if(_gReset == FALSE)
728 return 0;
729 MS_U32 u32reg;
730 MS_U32 u32Data;
731 u32reg = u32RegAddr + _gNSK2_Addr;
732 u32Data = (*(volatile MS_U32*)(u32reg));
733
734 HALNSK2_DBG(NSK2_DBGLV_ARRAY, "read NSK2 %x = %x\n",u32RegAddr,u32Data);
735
736 return u32Data;
737 }
738
HAL_NSK2_WriteReg(MS_U32 u32RegAddr,MS_U32 u32Data)739 static void HAL_NSK2_WriteReg(MS_U32 u32RegAddr,MS_U32 u32Data)
740 {
741 if(_gReset == FALSE)
742 return ;
743 MS_U32 u32reg;
744 u32reg = u32RegAddr + _gNSK2_Addr;
745 (*(volatile MS_U32*)(u32reg)) = u32Data;
746
747 HALNSK2_DBG(NSK2_DBGLV_ARRAY, "write NSK2 %x = %x\n",u32RegAddr,u32Data);
748 }
749
HAL_NSK2_KIW_BusyPolling(void)750 static MS_U32 HAL_NSK2_KIW_BusyPolling(void)
751 {
752 MS_U32 xiu_rdata;
753 MS_U32 cnt = 0;
754
755 xiu_rdata = NI_REG(REG_NI_STATUS);
756 while( (xiu_rdata & NI_KIW_BUSY) && (cnt < POLLING_CNT) )
757 {
758 xiu_rdata = NI_REG(REG_NI_STATUS);
759 HALNSK2_DBG(NSK2_DBGLV_INFO," read NI (STATUS = %x)\n",xiu_rdata);
760
761 cnt ++;
762 MsOS_DelayTask(1);
763 }
764
765 if(cnt >= POLLING_CNT)
766 {
767 HALNSK2_DBG(NSK2_DBGLV_ERR,"KIW_BusyPolling TimeOut\n");
768 return FALSE;
769 }
770 else
771 {
772 return TRUE;
773 }
774 }
775
HAL_NSK2_CheckBusy(void)776 static MS_U32 HAL_NSK2_CheckBusy(void)
777 {
778 //printf("_gCheckBusyFlag = %x\n",_gCheckBusyFlag);
779 if(_gCheckBusyFlag == TRUE)
780 {
781 MS_U32 cnt = 0;
782
783 while( (cnt < BUSYCHECK_CNT) && (HAL_NSK2_ReadReg(REG_NSK2_ACPU_WARNING) & NSK2_ACPU_BUSY) )
784 {
785 cnt ++;
786 MsOS_DelayTask(1);
787 }
788
789 if(cnt == BUSYCHECK_CNT)
790 {
791 HALNSK2_DBG(NSK2_DBGLV_ERR, "NSK2 is still busy\n");
792 return FALSE;
793 }
794 }
795 else
796 {
797 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NSK2 does't check busy\n");
798 }
799 return TRUE;
800 }
801
802
HAL_NSK2_DeadPolling(void)803 static void HAL_NSK2_DeadPolling(void)
804 {
805 #if 0
806 MS_U32 polling_cnt = dead_polling_cnt;
807 while(polling_cnt){
808 MsOS_DelayTask(10);
809 HALNSK2_DBG(NSK2_DBGLV_ERR, "Error, Dead Polling\n");
810 polling_cnt --;
811 }
812
813 //read ACPU Error....
814 printf("ACPU Error = %x\n", HAL_NSK2_ReadReg(REG_NSK2_ACPU_ERROR));
815 #endif
816 }
817
818
HAL_NSK2_OTP_Get(MS_U32 Addr,MS_U8 Msb,MS_U8 Lsb,MS_U32 * pValue)819 void HAL_NSK2_OTP_Get(MS_U32 Addr, MS_U8 Msb, MS_U8 Lsb, MS_U32 *pValue)
820 {
821 MS_U32 u32Data;
822
823 u32Data = OTP_REG(Addr);
824
825 //read back first....
826 //HALNSK2_DBG(NSK2_DBGLV_DEBUG, "read OTP %x = %x\n",Addr,u32Data);
827
828 //write value next
829
830 if( (Msb == 31) && (Lsb == 0) )
831 {
832 *pValue = u32Data;
833 }
834 else
835 {
836 *pValue = ((u32Data & BMASK(Msb:Lsb) ) >> Lsb);
837 }
838
839 }
840
841 ////////////////////////////////////////////////////////////////////////////////
842 // Global Function
843 ////////////////////////////////////////////////////////////////////////////////
844
HAL_NSK2_Init(void)845 MS_U32 HAL_NSK2_Init(void)
846 {
847 #if 0
848 MS_U32 u32Data;
849 {
850 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
851 MsOS_DelayTaskUs(1);
852
853 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
854 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA 0x1 = %x\n",u32Data);
855 }
856 #endif
857
858
859 //self test....
860 #ifdef NSK2SelfTest
861 NI_REG(REG_NI_NSK2_FREERUN) |= NI_NSK2_FREERUN_ENABLE;
862
863
864 MsOS_DelayTaskUs(1);
865 u32Data = NI_REG(REG_NI_NSK2_FREERUN);
866 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI 0x1 = %x\n",u32Data);
867 #endif
868
869
870 //set OTP timing...
871 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CC<<1)))) = 0xd;
872 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CD<<1)))) = 0x17;
873 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CE<<1)))) = 0x01;
874 MsOS_DelayTask(1);
875 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CE<<1)))) = 0x00;
876
877 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"finish NSK2.1 init\n");
878
879 return TRUE;
880 }
881
HAL_NSK2_Exit(void)882 MS_U32 HAL_NSK2_Exit(void)
883 {
884 NI_REG(REG_NI_NSK2_CTRL) &= (~NI_NSK2_RESET_DISABLE);
885 return TRUE;
886 }
887
HAL_NSK2_UnlockOTPCtrl(void)888 MS_U32 HAL_NSK2_UnlockOTPCtrl(void)
889 {
890 HALNSK2_DBG(NSK2_DBGLV_INFO, "OTP control to unlock NDS secret key\n");
891 OTP_CTRL_REG(0x10) = 0x99885a5a;
892 OTP_CTRL_REG(0x11) = 0x00114433;
893 OTP_CTRL_REG(0x12) = 0x23456789;
894 OTP_CTRL_REG(0x13) = 0xabcdef01;
895
896 return TRUE;
897 }
898
HAL_NSK2_ColdReset(void)899 MS_U32 HAL_NSK2_ColdReset(void)
900 {
901 MS_U32 u32Data;
902
903 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "%s \n",__FUNCTION__);
904
905 {
906 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
907 MsOS_DelayTaskUs(1);
908
909 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
910 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA 0x1 = %x\n",u32Data);
911 }
912
913 u32Data = NI_REG(REG_NI_NSK2_CTRL);
914
915 NI_REG(REG_NI_NSK2_CTRL) = (u32Data & (~NI_NSK2_RESET_DISABLE));
916 MsOS_DelayTaskUs(1);
917
918 u32Data &= (~NI_N2ROM_PD);
919 //u32Data &= (~NI_N2ROM_PD);
920
921 //bit 0 set to 1...
922 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_TS2NSK_ENABLE | NI_NSK2_CLK_ENABLE | NI_NSK2_RESET_DISABLE;
923
924 //MsOS_DelayTaskUs(1);
925
926 u32Data = NI_REG(REG_NI_NSK2_CTRL);
927 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI 0x0 = %x\n",u32Data);
928
929 _gReset = TRUE;
930 _gCheckBusyFlag = TRUE;
931
932 HAL_NSK2_EnableInt();
933 return TRUE;
934 }
935
936
HAL_NSK2_EndSubtest(void)937 MS_U32 HAL_NSK2_EndSubtest(void)
938 {
939 MS_U32 u32Data;
940
941 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "%s \n",__FUNCTION__);
942
943 HAL_NSK2_DisableInt();
944
945 u32Data = NI_REG(REG_NI_NSK2_CTRL);
946 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "REG_NI_NSK2_CTRL = %x \n",u32Data);
947
948 if(u32Data & NI_NSK2_RESET_DISABLE)
949 {
950
951 NI_REG(REG_NI_NSK2_CTRL) = (u32Data & (~NI_NSK2_RESET_DISABLE));
952 //NI_REG(REG_NI_NSK2_CTRL) = 0;
953 //printf("wait here\n");
954 //while(1);
955 MsOS_DelayTaskUs(1);
956 }
957
958 _gReset = FALSE;
959 _gCheckBusyFlag = FALSE;
960 return TRUE;
961 }
962
963
HAL_NSK2_SetBase(MS_U32 u32Base)964 void HAL_NSK2_SetBase(MS_U32 u32Base)
965 {
966 HALNSK2_DBG(NSK2_DBGLV_INFO, "u32Base = %x\n",u32Base);
967
968 _gBasicAddr = u32Base;
969
970 _gOTP_Addr = _gBasicAddr + REG_OTP_BASE;
971 _gRSA_Addr = _gBasicAddr + REG_RSA_BASE;
972 _gOTP_CTRL_Addr = _gBasicAddr + REG_OTP_CTRL_BASE;
973 _gNSK2_Addr = _gBasicAddr + REG_NSK2_BASE;
974
975 _gNI_Addr = _gBasicAddr + REG_NI_BASE;
976
977 _gKeyTable_Addr = _gBasicAddr + REG_KEY_TABLE_BASE;
978 _gNDSJTagPwd_Addr= _gBasicAddr + REG_JTAG_PWD_BASE;
979 _gCipherCH0_Addr = _gBasicAddr + REG_CIPHER_CH0_BASE;
980 _gCryptoDMA_Addr = _gBasicAddr + REG_CRYPTO_DMA_BASE;
981 HALNSK2_DBG(NSK2_DBGLV_INFO, "%s _gNSK2_Addr : %x\n", __FUNCTION__, _gNSK2_Addr);
982
983 //OTP_CTRL_REG(0x3A) = 0x0;
984 }
985
986
987
988
989 //compare the contect of a buffer in the NSK2's memory map to an expected value.
HAL_NSK2_CompareMem(MS_U32 reserved,MS_U32 StartAddr,MS_U32 CompareLens,MS_U32 CompareSim,MS_U32 ExpectResult,void * pGolden)990 MS_U32 HAL_NSK2_CompareMem(MS_U32 reserved, MS_U32 StartAddr, MS_U32 CompareLens,
991 MS_U32 CompareSim, MS_U32 ExpectResult, void *pGolden)
992 {
993 MS_U32 u32ReadData, u32GoldenData;
994 MS_U32 u32Addr = StartAddr;
995 MS_U32 *pGoldenData = (MS_U32 *)pGolden;
996 MS_U32 u32CompLens = CompareLens;
997 MS_U32 status = TRUE;
998 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s \n",__FUNCTION__);
999 //check lengths
1000 if(u32CompLens == 0)
1001 {
1002 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s CompareLens = %x\n",__FUNCTION__,u32CompLens);
1003 }
1004
1005 do
1006 {
1007 HAL_NSK2_CheckBusy();
1008
1009 u32ReadData = HAL_NSK2_ReadReg(u32Addr);
1010 u32GoldenData = *pGoldenData;
1011
1012 if(u32ReadData != u32GoldenData)
1013 {
1014 HALNSK2_DBG(NSK2_DBGLV_ERR,"%s, Addr = %x, u32ReadData = %x, u32GoldenData = %x\n",__FUNCTION__,u32Addr, u32ReadData, u32GoldenData);
1015 HAL_NSK2_DeadPolling();
1016 //return FALSE;
1017 status = FALSE;
1018 }
1019 else
1020 {
1021 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Data Correct, Addr = %x, u32GoldenData = %x\n",u32Addr, u32GoldenData);
1022 }
1023
1024 pGoldenData ++;
1025 u32Addr += 4;
1026 u32CompLens --; //32 bit bus
1027
1028 } while(u32CompLens > 0);
1029
1030 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s, successful = %x\n",__FUNCTION__,StartAddr);
1031 return status;
1032 }
1033
HAL_NSK2_Compare(MS_U32 StartAddr,MS_U32 CompareLens,MS_U32 CompareSim,MS_U32 Mask,MS_U32 ExpectResult)1034 MS_U32 HAL_NSK2_Compare(MS_U32 StartAddr, MS_U32 CompareLens, MS_U32 CompareSim,
1035 MS_U32 Mask, MS_U32 ExpectResult)
1036 {
1037
1038 MS_U32 u32ReadData, u32GoldenData = ExpectResult;
1039 MS_U32 u32Addr = StartAddr;
1040
1041 StatusCheck(HAL_NSK2_CheckBusy());
1042
1043 u32ReadData = HAL_NSK2_ReadReg(u32Addr);
1044 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Mask = %x\n",Mask);
1045 u32ReadData &= Mask;
1046
1047 if(u32ReadData != u32GoldenData)
1048 {
1049 HALNSK2_DBG(NSK2_DBGLV_ERR,"%s fail, Addr = %x, u32ReadData = %x, u32GoldenData = %x\n",__FUNCTION__,u32Addr, u32ReadData, u32GoldenData);
1050 HAL_NSK2_DeadPolling();
1051 return FALSE;
1052 }
1053 else
1054 {
1055 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"compare data correct, Addr = %x, u32GoldenData = %x\n",u32Addr,u32GoldenData);
1056 }
1057
1058 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s, successful\n",__FUNCTION__);
1059 return TRUE;
1060 }
1061
HAL_NSK2_WriteMem(MS_U32 reserved,MS_U32 StartAddr,MS_U32 WriteLens,void * pWriteData)1062 MS_U32 HAL_NSK2_WriteMem(MS_U32 reserved, MS_U32 StartAddr, MS_U32 WriteLens,
1063 void *pWriteData)
1064 {
1065
1066 MS_U32 *pWriteD = (MS_U32 *)pWriteData;
1067 MS_U32 u32Data;
1068 while(WriteLens > 0)
1069 {
1070 StatusCheck(HAL_NSK2_CheckBusy());
1071
1072 u32Data = *pWriteD ;
1073
1074 HAL_NSK2_WriteReg(StartAddr,u32Data);
1075 HALNSK2_DBG(NSK2_DBGLV_ARRAY,"WriteMem (Addr,Data) = (%x,%x)\n",StartAddr,u32Data);
1076
1077 WriteLens --;
1078 StartAddr += 4;
1079 pWriteD ++;
1080 }
1081
1082 StatusCheck(HAL_NSK2_CheckBusy());
1083 return TRUE;
1084 }
1085
HAL_NSK2_WriteSFR(MS_U32 StartAddr,MS_U32 Data)1086 MS_U32 HAL_NSK2_WriteSFR(MS_U32 StartAddr, MS_U32 Data)
1087 {
1088 StatusCheck(HAL_NSK2_CheckBusy());
1089 HALNSK2_DBG(NSK2_DBGLV_ARRAY,"WriteSFR (Addr,Data) = (%x,%x)\n",StartAddr,Data);
1090 HAL_NSK2_WriteReg(StartAddr,Data);
1091 StatusCheck(HAL_NSK2_CheckBusy());
1092 return TRUE;
1093 }
1094
HAL_NSK2_NSKBasicInitializationComplete(void)1095 MS_U32 HAL_NSK2_NSKBasicInitializationComplete(void)
1096 {
1097 //$display($time,"NS NSKBasicInitializationComplete ");
1098 //xiu_w_ni(16'h6,4'b0001,32'h0000000F);
1099
1100 MS_U32 data;
1101 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_NSKBasicInitializationComplete\n");
1102 StatusCheck(HAL_NSK2_CheckBusy());
1103
1104 data = NI_REG(REG_NI_COMMAND);
1105 //NI_REG(REG_NI_COMMAND) = (data | NI_NSKBIComplete | NI_COMMAND_START);
1106 NI_REG(REG_NI_COMMAND) = (NI_NSKBIComplete | NI_COMMAND_START);
1107
1108 MsOS_DelayTaskUs(1);
1109 //NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_NopNop);
1110 NI_REG(REG_NI_NSK2_CLK_CSA) = NSK2_EN_CSA_VAR;
1111
1112
1113 return TRUE;
1114 }
1115
HAL_NSK2_SCBTransToHW(MS_U8 ForceSCB)1116 MS_U8 HAL_NSK2_SCBTransToHW(MS_U8 ForceSCB)
1117 {
1118 MS_U8 NewForceSCB = 0;
1119
1120 NewForceSCB = ForceSCB;
1121 if(ForceSCB == 0)
1122 {
1123 NewForceSCB = 1;
1124 }
1125 else if(ForceSCB == 1)
1126 {
1127 NewForceSCB = 0;
1128 }
1129
1130 return NewForceSCB;
1131 }
1132
1133
HAL_NSK2_WriteESA(MS_U8 ESASelect,MS_U8 ESASubSelect,MS_U8 pid_no)1134 MS_U32 HAL_NSK2_WriteESA(MS_U8 ESASelect, MS_U8 ESASubSelect, MS_U8 pid_no)
1135 {
1136 #if 0
1137 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteESA pid_no = %x, ESASelect = %x, ESASubSelect = %x\n",pid_no, ESASelect, ESASubSelect);
1138 //scb = 2'b00; pid_no = 1; ESAselect = 4'h0; ESAsubselect =4'h0;
1139 //wdata = {10'b0,ESAselect[3:0],ESAsubselect[2:0],3'b0,pid_no[12:0]};
1140 //xiu_w_ni(16'h7,4'b1111,wdata[31:0]);
1141 //xiu_w_ni(16'h6,4'b1111,32'h00000003);
1142 //xiu_rdata = 32'h8; while(xiu_rdata[3]===1'b1)begin xiu_r_ni(16'hc); end
1143 StatusCheck(HAL_NSK2_CheckBusy());
1144
1145 MS_U32 data;
1146
1147 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteESA pid_no = %x\n",pid_no);
1148 data = (((MS_U32)ESASelect<<NI_WriteESA_ESASel_Shift) & NI_WriteESA_ESASel_MASK) +
1149 (((MS_U32)ESASubSelect<<NI_WriteESA_ESASubSel_Shift) & NI_WriteESA_ESASubSel_MASK) +
1150 ((MS_U32)pid_no & NI_WriteESA_PidNo);
1151
1152
1153 HALNSK2_DBG(NSK2_DBGLV_INFO," write NI (REG_NI_PARAMETERS = %x)\n",data);
1154 NI_REG(REG_NI_PARAMETERS) = data;
1155 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteESA);
1156
1157 StatusCheck(HAL_NSK2_KIW_BusyPolling());
1158 #endif
1159 return TRUE;
1160 }
1161
HAL_NSK2_WriteTransportKey(MS_U8 SCB,MS_U8 ForceSCB,void * pLabel,MS_U8 pid_no)1162 MS_U32 HAL_NSK2_WriteTransportKey(MS_U8 SCB, MS_U8 ForceSCB, void *pLabel, MS_U8 pid_no)
1163 {
1164 #if 0
1165 //$display($time,"NS WriteTransportKey 0134 00 01 IV__0");
1166 //wait_nsk_busy;
1167 //xiu_r_ni(16'hd);
1168 //if((xiu_rdata & 7)==0) begin
1169 // scb = 2'b00; fscb = 2'b00; pid_no = 1;
1170 // wdata = {12'b0,fscb[1:0],scb[1:0],3'b0,pid_no[12:0]};
1171 // xiu_w_ni(16'h7,4'b1111,wdata[31:0]);
1172 // xiu_w_ni(16'hb,4'b1111,32'h00000000);
1173 // xiu_w_ni(16'ha,4'b1111,32'h00000000);
1174 // xiu_w_ni(16'h9,4'b1111,32'h00000000);
1175 // xiu_w_ni(16'h8,4'b1111,32'h00000000);
1176 // xiu_w_ni(16'h6,4'b1111,32'h00000005);
1177 // xiu_rdata = 32'h8; while(xiu_rdata[3]===1'b1)begin xiu_r_ni(16'hc); end
1178 //end
1179 //else $display("WriteTransportKey abnormal ignored: KteDest not zero");
1180 #define N 0xfffffff0
1181 #define N1 0xfffffff1
1182 #define N2 0xfffffff2
1183
1184 MS_U32 data = 0;
1185 MS_U32 data2 = 0;
1186 MS_U32 pIV[4] = {0,0,0,0};
1187
1188 MS_U32* pIV_copy = (MS_U32*)pLabel;
1189
1190 if((pLabel != NULL) && (pLabel != (MS_U32*)N) && (pLabel != (MS_U32*)N1) && (pLabel != (MS_U32*)N2))
1191 {
1192 memcpy(pIV,pIV_copy,16);
1193 }
1194
1195 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteTransportKey pid_no = %x, SCB = %x, ForceSCB = %x\n",pid_no, SCB, ForceSCB);
1196 StatusCheck(HAL_NSK2_CheckBusy());
1197
1198 data = NI_REG(REG_NI_KTE_STATUS);
1199 if( ( data & NI_KTE_DEST_MASK ) == 0 )
1200 {
1201
1202 ForceSCB = HAL_NSK2_SCBTransToHW(ForceSCB);
1203
1204 HALNSK2_DBG(NSK2_DBGLV_INFO,"pid_no: %x\n", pid_no);
1205 data2 = pid_no + ( ( (MS_U32)SCB<<NI_WriteTKey_SCB_Shift) & NI_WriteTKey_SCB_MASK)
1206 + ( ( (MS_U32)ForceSCB<<NI_WriteTKey_FSCB_Shift) & NI_WriteTKey_FSCB_MASK) ;
1207
1208
1209 NI_REG(REG_NI_PARAMETERS) = data2;
1210 NI_REG(REG_NI_IV_127_96) = pIV[0];
1211 NI_REG(REG_NI_IV_95_64) = pIV[1];
1212 NI_REG(REG_NI_IV_63_31) = pIV[2];
1213 NI_REG(REG_NI_IV_31_00) = pIV[3];
1214 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteTransportKey);
1215
1216 HALNSK2_DBG(NSK2_DBGLV_INFO,"NI 7 : %x, NI 6 = %x\n", NI_REG(REG_NI_PARAMETERS) , NI_REG(REG_NI_COMMAND));
1217
1218 StatusCheck(HAL_NSK2_KIW_BusyPolling());
1219 }
1220 else
1221 {
1222 HALNSK2_DBG(NSK2_DBGLV_ERR,"WriteTransportKey abnormal ignored: KteDest not zero\n");
1223 return FALSE;
1224 }
1225
1226 HAL_NSK2_ReadSwitchFromNSK2();
1227 #endif
1228 return TRUE;
1229 }
1230
HAL_NSK2_wait_kte_valid(void)1231 MS_U32 HAL_NSK2_wait_kte_valid(void)
1232 {
1233 MS_U32 xiu_rdata = HAL_NSK2_ReadReg(REG_NSK2_KTE_VALID);
1234 MS_U32 cnt = 0;
1235 while( ( (xiu_rdata & NSK2_KTE_VALID_TRUE) == 0 ) && (cnt < POLLING_CNT) )
1236 {
1237 xiu_rdata = HAL_NSK2_ReadReg(REG_NSK2_KTE_VALID);
1238 HALNSK2_DBG(NSK2_DBGLV_INFO,"xiu_rdata = %x\n",xiu_rdata);
1239 cnt ++;
1240 MsOS_DelayTask(1);
1241 }
1242
1243 if(cnt == POLLING_CNT)
1244 {
1245 HALNSK2_DBG(NSK2_DBGLV_ERR,"HAL_NSK2_wait_kte_valid time out\n");
1246 return FALSE;
1247 }
1248
1249 return TRUE;
1250 }
1251
HAL_NSK2_CompareKTE(MS_U32 reserved_1,MS_U32 reserved_2,void * pLabel)1252 MS_U32 HAL_NSK2_CompareKTE(MS_U32 reserved_1, MS_U32 reserved_2, void *pLabel)
1253 {
1254
1255 #ifdef FPGAMode
1256 MS_U32 data;
1257 MS_U32 *pKTEGolden = (MS_U32 *)pLabel;
1258 MS_U32 KTE_Index = REG_KT_KEYS_START_FPGA;
1259 MS_U32 status = TRUE;
1260
1261 StatusCheck(HAL_NSK2_CheckBusy());
1262 //StatusCheck(HAL_NSK2_wait_kte_valid());
1263 data = NI_REG(REG_NI_NSK2_KTE_VALID_FPGA);
1264 HALNSK2_DBG(NSK2_DBGLV_INFO,"NSK2_KTE_VALID_FPGA = %x\n",data);
1265
1266 for(KTE_Index = REG_KT_KEYS_END_FPGA; KTE_Index<=REG_KT_KEYS_START_FPGA; KTE_Index--)
1267 {
1268 data = NI_REG(KTE_Index);
1269
1270 if(data != *pKTEGolden)
1271 {
1272 HALNSK2_DBG(NSK2_DBGLV_ERR," %x, (%x , %x)\n",KTE_Index,data,*pKTEGolden);
1273 status = FALSE;
1274 }
1275
1276 pKTEGolden ++;
1277 }
1278
1279 return status;
1280
1281 #else
1282
1283 #endif
1284
1285 return TRUE;
1286 }
1287
HAL_NSK2_CompareOut(MS_U32 reserved_1,MS_U32 reserved_2,MS_U32 HighDWord,MS_U32 LowDWord)1288 MS_U32 HAL_NSK2_CompareOut(MS_U32 reserved_1, MS_U32 reserved_2, MS_U32 HighDWord, MS_U32 LowDWord)
1289 {
1290
1291 //wait_nsk_busy;
1292 //$display($time,"NS CompareOut 1 1 0000001555400000");
1293 //xiu_r_ni(16'd24); genout = xiu_rdata; genout = genout << 32;
1294 //xiu_r_ni(16'd23); genout = genout | {6'b0,xiu_rdata[31:0]};
1295 //$display("CompareOut read PS",genout[37:0]);
1296 // if(genout!==38'h0000001555400000)begin
1297 //$display("CompareOut Expected=38'h0000001555400000 Read=38'hPS",genout[37:0]);
1298 // nsk2_GeneralOut_test_fail = 1;
1299 // #2000;
1300 //$finish;
1301 //end
1302
1303
1304 MS_U32 high_data,low_data;
1305 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_CompareOut HighDWord = %x, LowDWord = %x\n",HighDWord, LowDWord);
1306 StatusCheck(HAL_NSK2_CheckBusy());
1307 low_data = NI_REG(REG_NI_COMPARE_GENOUT_L);
1308 high_data = (NI_REG(REG_NI_COMPARE_GENOUT_H)&NI_GENOUT_H_MASK);
1309 HALNSK2_DBG(NSK2_DBGLV_INFO,"NI 24 = %x , 23 = %x\n",high_data,low_data);
1310
1311 if( (HighDWord != high_data) || (LowDWord!= low_data) )
1312 {
1313 HAL_NSK2_DeadPolling();
1314 return FALSE;
1315 }
1316 else
1317 {
1318 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_CompareOut successfully\n");
1319 }
1320
1321 return TRUE;
1322 }
1323
HAL_NSK2_SetRNG(MS_U32 reserved_1,MS_U32 RNG_Value)1324 MS_U32 HAL_NSK2_SetRNG(MS_U32 reserved_1,MS_U32 RNG_Value)
1325 {
1326
1327 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_SetRNG = %x\n",RNG_Value);
1328 NI_REG(REG_NI_SW_SET_RNG) = (RNG_Value&NI_SW_RNG_MASK);
1329 return TRUE;
1330 }
1331
HAL_NSK2_WriteM2MKey(void * pIV,MS_U8 SubAlgo)1332 MS_U32 HAL_NSK2_WriteM2MKey(void *pIV, MS_U8 SubAlgo)
1333 {
1334 #if 0
1335 //wait_nsk_busy;
1336 //WriteM2MKey IV__1 0
1337 //$display($time,"NS WriteM2MKey IV__1 0");
1338 //wdata = {12'b0,4'h0,16'b0};
1339 //xiu_w_ni(16'h7,4'b1111,wdata[31:0]);
1340 //xiu_w_ni(16'hb,4'b1111,32'h00010203);
1341 //xiu_w_ni(16'ha,4'b1111,32'h04050607);
1342 //xiu_w_ni(16'h9,4'b1111,32'h08090a0b);
1343 //xiu_w_ni(16'h8,4'b1111,32'h0c0d0e0f);
1344 //xiu_w_ni(16'h6,4'b1111,32'h00000007);
1345 //xiu_rdata = 32'h8; while(xiu_rdata[3]===1'b1)begin xiu_r_ni(16'hc); end
1346
1347 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteM2MKey, SubAlgo = %x \n", SubAlgo);
1348 HAL_NSK2_CheckBusy();
1349
1350 MS_U32 wdata = 0;
1351 MS_U32 pWIV[4];
1352
1353 memset(pWIV, 0x0, 4*4);
1354 if(pIV != NULL)
1355 {
1356 memcpy(pWIV,pIV,4*4);
1357 }
1358
1359
1360 wdata = ( ((MS_U32)SubAlgo << NI_WriteM2MKey_Shift) & NI_WriteM2MKey_MASK); //write sub algorithm....[19:16]
1361 NI_REG(REG_NI_PARAMETERS) = wdata;
1362
1363 NI_REG(REG_NI_IV_127_96) = pWIV[0];
1364 NI_REG(REG_NI_IV_95_64) = pWIV[1];
1365 NI_REG(REG_NI_IV_63_31) = pWIV[2];
1366 NI_REG(REG_NI_IV_31_00) = pWIV[3];
1367
1368 HALNSK2_DBG(NSK2_DBGLV_INFO,"pwIV = (%x, %x, %x, %x)\n",pWIV[0],pWIV[1],pWIV[2],pWIV[3]);
1369 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteM2MKey); //write M2M key and start...
1370 #endif
1371 return TRUE;
1372 }
1373
HAL_NSK2_WriteSCPUKey(void)1374 MS_U32 HAL_NSK2_WriteSCPUKey(void)
1375 {
1376 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n", __FUNCTION__);
1377 StatusCheck(HAL_NSK2_CheckBusy());
1378 NI_REG(REG_NI_COMMAND) = (NI_WriteSCPUKey | NI_COMMAND_START);
1379 MsOS_DelayTaskUs(1);
1380
1381 return HAL_NSK2_ReadKTEResp();
1382 }
1383
1384 static MS_U32 KeyNum = 0;
HAL_NSK2_WriteReservedKey(void)1385 MS_U32 HAL_NSK2_WriteReservedKey(void)
1386 {
1387 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n", __FUNCTION__);
1388 StatusCheck(HAL_NSK2_CheckBusy());
1389 NI_REG(REG_NI_COMMAND) = (NI_WriteReservedKey | NI_COMMAND_START);
1390 MsOS_DelayTaskUs(1);
1391
1392 HALNSK2_DBG(NSK2_DBGLV_INFO,"write key = %x, %x\n", NI_REG(REG_NI_COMPARE_GENOUT_L), NI_REG(REG_NI_COMPARE_GENOUT_H));
1393 KeyNum = NI_REG(REG_NI_COMPARE_GENOUT_L)>>17;
1394
1395 return HAL_NSK2_ReadKTEResp();
1396 }
1397
HAL_NSK2_GetReserveKeyNum(void)1398 MS_U32 HAL_NSK2_GetReserveKeyNum(void)
1399 {
1400 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s KeyNum = %x\n", __FUNCTION__,KeyNum);
1401 return KeyNum;
1402 }
1403
HAL_NSK2_DriveKteAck(void)1404 MS_U32 HAL_NSK2_DriveKteAck(void)
1405 {
1406 //DriveKteAck
1407 //$display($time,"NS DriveKteAck");
1408 //xiu_w_ni(16'h6,4'b1111,32'h0000000B);
1409
1410 StatusCheck(HAL_NSK2_CheckBusy());
1411 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n", __FUNCTION__);
1412
1413 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_DriveAck);
1414 MsOS_DelayTaskUs(1);
1415 StatusCheck(HAL_NSK2_CheckBusy());
1416 return TRUE;
1417 }
1418
HAL_NSK2_SetJTagPswd(void)1419 MS_U32 HAL_NSK2_SetJTagPswd(void)
1420 {
1421
1422 #if 0
1423 #define JTagPwd0Addr 0x64
1424 #define InputPwd0Addr 0x4
1425 MS_U32 JTagPwd0[4];
1426
1427 NDSJTagPwd_REG(3) = 0x0;
1428 NDSJTagPwd_REG(2) = 0x0;
1429 NDSJTagPwd_REG(1) = 0x0;
1430 NDSJTagPwd_REG(0) = 0x1;
1431
1432 NDSJTagPwd_REG(0x14) = 0x1;
1433
1434 JTagPwd0[0] = KeyTable_REG(JTagPwd0Addr);
1435 JTagPwd0[1] = KeyTable_REG((JTagPwd0Addr+1));
1436 JTagPwd0[2] = KeyTable_REG((JTagPwd0Addr+2));
1437 JTagPwd0[3] = KeyTable_REG((JTagPwd0Addr+3));
1438
1439 HALNSK2_DBG(0,"JTagPwd0 = %x, %x, %x, %x\n",JTagPwd0[0],JTagPwd0[1],JTagPwd0[2],JTagPwd0[3]);
1440
1441 NDSJTagPwd_REG((InputPwd0Addr+7)) = (MS_U16) ((JTagPwd0[3]>>16)&0xffff);
1442 NDSJTagPwd_REG((InputPwd0Addr+6)) = (MS_U16) (JTagPwd0[3]&0xffff);
1443 NDSJTagPwd_REG((InputPwd0Addr+5)) = (MS_U16) ((JTagPwd0[2]>>16)&0xffff);
1444 NDSJTagPwd_REG((InputPwd0Addr+4)) = (MS_U16) (JTagPwd0[2]&0xffff);
1445 NDSJTagPwd_REG((InputPwd0Addr+3)) = (MS_U16) ((JTagPwd0[1]>>16)&0xffff);
1446 NDSJTagPwd_REG((InputPwd0Addr+2)) = (MS_U16) (JTagPwd0[1]&0xffff);
1447 NDSJTagPwd_REG((InputPwd0Addr+1)) = (MS_U16) ((JTagPwd0[0]>>16)&0xffff);
1448 NDSJTagPwd_REG((InputPwd0Addr+0)) = (MS_U16) (JTagPwd0[0]&0xffff);
1449
1450 NDSJTagPwd_REG(0x14) = 0x7;
1451 #else
1452 MS_U32 jtag_status;
1453 jtag_status = KeyTable_REG(88);
1454 //88 bit 0 and 1 = 1
1455
1456 HALNSK2_DBG(NSK2_DBGLV_INFO,"KeyTable 88 jtag_status = %x\n",jtag_status);
1457 #endif
1458
1459 return TRUE;
1460 }
1461
1462 //MS_BOOL HAL_CA_OTP_GetCfg(MS_U32 u32Idx, MS_U32 *pu32Value);
1463
HAL_NSK2_CheckPubOTPConfig(void * pCheck)1464 MS_BOOL HAL_NSK2_CheckPubOTPConfig(void *pCheck)
1465 {
1466 #if 0
1467 OTP bits OTP name function
1468 [127:64] V_PubOtpUniqueID Unique ID, 0x3da8~0x3daf
1469 [63:48] V_PubOtpGP General Purpose Field (bit-by-bit lock),3b08~3b09
1470 [47:40] V_PubOtpMinConfVer Minimum Configuration Version,3b14
1471 [39:36] V_PubOtpRSAIndex RSA Index, 3b10
1472 [35:32] V_PubOtpBID BlackBox ID, 0x3b0c
1473 [31:16] V_PubOtpVID Version ID, 0x3b04
1474 [15:0] V_PubOtpOID Owner ID, 0x3b00
1475 #endif
1476
1477 MS_U32 *pDataArray;
1478 MS_U32 OTP_PubOtpOID,OTP_PubOtpVID,OTP_PubOtpBID,OTP_PubOtpRsaIndex,OTP_PubOtpMinConfVer ;
1479 MS_U32 OTP_PubOtpGP,OTP_PubOtpUniqueID[2];
1480
1481 MS_U32 CHK_PubOtpOID,CHK_PubOtpVID,CHK_PubOtpBID,CHK_PubOtpRsaIndex,CHK_PubOtpMinConfVer ;
1482 MS_U32 CHK_PubOtpGP,CHK_PubOtpUniqueID[2];
1483
1484 MS_BOOL status = TRUE;
1485 if(pCheck == NULL)
1486 {
1487 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, pCheck = NULL\n",__LINE__,__FUNCTION__);
1488 return FALSE;
1489 }
1490 pDataArray = (MS_U32 *)pCheck;
1491
1492 HAL_NSK2_OTP_Get(0x3da8,31,0, &OTP_PubOtpUniqueID[0]);
1493 HAL_NSK2_OTP_Get(0x3dac,31,0, &OTP_PubOtpUniqueID[1]);
1494
1495 CHK_PubOtpUniqueID[1] = pDataArray[0];
1496 CHK_PubOtpUniqueID[0] = pDataArray[1];
1497
1498 HALNSK2_DBG(NSK2_DBGLV_INFO,"uniqueID = (%x%x, %x%x)\n",CHK_PubOtpUniqueID[1],CHK_PubOtpUniqueID[0],OTP_PubOtpUniqueID[1],OTP_PubOtpUniqueID[0]);
1499
1500 if( (CHK_PubOtpUniqueID[1] != OTP_PubOtpUniqueID[1]) || (CHK_PubOtpUniqueID[0] != OTP_PubOtpUniqueID[0]))
1501 {
1502 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, UniqueID WRONG\n",__LINE__,__FUNCTION__);
1503 status = FALSE;
1504 }
1505
1506 HAL_NSK2_OTP_Get(0x3b08,15,0, &OTP_PubOtpGP);
1507 CHK_PubOtpGP = (pDataArray[2]>>16)&0xffff;
1508
1509 if(OTP_PubOtpGP != CHK_PubOtpGP)
1510 {
1511 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpGP WRONG\n",__LINE__,__FUNCTION__);
1512 printf("OtpGP = (%x, %x)\n",CHK_PubOtpGP,OTP_PubOtpGP);
1513 status = FALSE;
1514 }
1515
1516 HAL_NSK2_OTP_Get(0x3b14,7,0, &OTP_PubOtpMinConfVer);
1517 CHK_PubOtpMinConfVer = (pDataArray[2]>>8)&0xff;
1518
1519 if(OTP_PubOtpMinConfVer != CHK_PubOtpMinConfVer)
1520 {
1521 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpMinConfVer WRONG\n",__LINE__,__FUNCTION__);
1522 printf("OtpMinConfVer = (%x, %x)\n",CHK_PubOtpMinConfVer,OTP_PubOtpMinConfVer);
1523 status = FALSE;
1524 }
1525
1526 HAL_NSK2_OTP_Get(0x3b10,3,0, &OTP_PubOtpRsaIndex);
1527 CHK_PubOtpRsaIndex = (pDataArray[2]>>4)&0xf;
1528
1529 if(OTP_PubOtpRsaIndex != CHK_PubOtpRsaIndex)
1530 {
1531 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpRsaIndex WRONG\n",__LINE__,__FUNCTION__);
1532 printf("OtpRsaIndex = (%x, %x)\n",CHK_PubOtpRsaIndex,OTP_PubOtpRsaIndex);
1533 status = FALSE;
1534 }
1535
1536 HAL_NSK2_OTP_Get(0x3b0C,3,0, &OTP_PubOtpBID);
1537 CHK_PubOtpBID = (pDataArray[2])&0xf;
1538
1539 if(OTP_PubOtpBID != CHK_PubOtpBID)
1540 {
1541 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpBID WRONG\n",__LINE__,__FUNCTION__);
1542 printf("OtpBID = (%x, %x)\n",CHK_PubOtpBID,OTP_PubOtpBID);
1543 status = FALSE;
1544 }
1545
1546 HAL_NSK2_OTP_Get(0x3b04,15,0, &OTP_PubOtpVID);
1547 CHK_PubOtpVID = (pDataArray[3]>>16)&0xffff;
1548
1549 if(OTP_PubOtpVID != CHK_PubOtpVID)
1550 {
1551 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpVID WRONG\n",__LINE__,__FUNCTION__);
1552 printf("OtpVID = (%x, %x)\n",CHK_PubOtpVID,CHK_PubOtpVID);
1553 status = FALSE;
1554 }
1555
1556 HAL_NSK2_OTP_Get(0x3b00,15,0, &OTP_PubOtpOID);
1557 CHK_PubOtpOID = (pDataArray[3])&0xffff;
1558
1559 if(OTP_PubOtpOID != CHK_PubOtpOID)
1560 {
1561 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpOID WRONG\n",__LINE__,__FUNCTION__);
1562 printf("OtpOID = (%x, %x)\n",CHK_PubOtpOID,OTP_PubOtpOID);
1563 status = FALSE;
1564 }
1565
1566 MS_U32 KeyValid;
1567 HAL_NSK2_OTP_Get(0x3b1c,31,24, &KeyValid);
1568 HALNSK2_DBG(NSK2_DBGLV_INFO,"KeyValid = %x\n",KeyValid);
1569
1570 MS_U32 CheckSum[4];
1571 HAL_NSK2_OTP_Get(0x3c30,31,0, &CheckSum[0]);
1572 HAL_NSK2_OTP_Get(0x3c34,31,0, &CheckSum[1]);
1573 HAL_NSK2_OTP_Get(0x3c38,31,0, &CheckSum[2]);
1574 HAL_NSK2_OTP_Get(0x3c3c,31,0, &CheckSum[3]);
1575 HALNSK2_DBG(NSK2_DBGLV_INFO,"CheckSum = %x, %x, %x, %x\n",CheckSum[0],CheckSum[1],CheckSum[2],CheckSum[3]);
1576 return status;
1577 }
1578
HAL_NSK2_ReadDataTrans(MS_U32 read_data,MS_U8 * data)1579 static void HAL_NSK2_ReadDataTrans(MS_U32 read_data, MS_U8 *data)
1580 {
1581 data[3] = (MS_U8)(read_data & 0xff);
1582 data[2] = (MS_U8)((read_data>>8) & 0xff);
1583 data[1] = (MS_U8)((read_data>>16) & 0xff);
1584 data[0] = (MS_U8)((read_data>>24) & 0xff);
1585 }
1586
HAL_NSK2_WriteDataTrans(MS_U8 * data)1587 static MS_U32 HAL_NSK2_WriteDataTrans(MS_U8 *data)
1588 {
1589 MS_U32 write_data = 0;
1590
1591 write_data = (MS_U32)data[3] + ((MS_U32)data[2]<<8) + ((MS_U32)data[1]<<16) + ((MS_U32)data[0]<<24) ;
1592 return write_data;
1593 }
1594
HAL_NSK2_ReadData(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1595 MS_U32 HAL_NSK2_ReadData(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1596 {
1597 MS_U32 read_data, read_data_size;
1598 MS_U8 *read_ptr;
1599
1600 if(data_size < 4)
1601 {
1602 return FALSE;
1603 }
1604
1605 read_data_size = data_size;
1606 read_ptr = data;
1607
1608 while(read_data_size >= 4)
1609 {
1610 StatusCheck(HAL_NSK2_CheckBusy());
1611
1612 read_data = HAL_NSK2_ReadReg(addr_offset);
1613 HAL_NSK2_ReadDataTrans(read_data,read_ptr);
1614
1615 addr_offset += 4;
1616 read_ptr += 4;
1617 read_data_size -= 4;
1618 }
1619
1620 return TRUE;
1621 }
1622
HAL_NSK2_WriteData(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1623 MS_U32 HAL_NSK2_WriteData(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1624 {
1625 MS_U32 write_data, write_data_size;
1626 MS_U8 *write_ptr;
1627
1628 if(data_size < 4)
1629 {
1630 return FALSE;
1631 }
1632
1633 write_data_size = data_size;
1634 write_ptr = data;
1635
1636 while(write_data_size >= 4)
1637 {
1638 StatusCheck(HAL_NSK2_CheckBusy());
1639
1640 write_data = HAL_NSK2_WriteDataTrans(write_ptr);
1641 HAL_NSK2_WriteReg(addr_offset,write_data);
1642
1643 addr_offset += 4;
1644 write_ptr += 4;
1645 write_data_size -= 4;
1646 }
1647
1648
1649 return TRUE;
1650 }
1651
HAL_NSK2_ReadData8(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1652 MS_U32 HAL_NSK2_ReadData8(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1653 {
1654 MS_U32 read_data, read_data_size;
1655 MS_U8 *read_ptr;
1656
1657 if(data_size < 4)
1658 {
1659 return FALSE;
1660 }
1661
1662 read_data_size = data_size;
1663 read_ptr = data;
1664
1665 while(read_data_size >= 4)
1666 {
1667 StatusCheck(HAL_NSK2_CheckBusy());
1668
1669 read_data = HAL_NSK2_ReadReg(addr_offset);
1670 HAL_NSK2_ReadDataTrans(read_data,read_ptr);
1671
1672 //HALNSK2_DBG(0,"addr = %x, read_data = %x\n",addr_offset,read_data);
1673 addr_offset += 4;
1674 read_ptr += 4;
1675 read_data_size -= 4;
1676 }
1677
1678 return TRUE;
1679 }
1680
HAL_NSK2_WriteData8(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1681 MS_U32 HAL_NSK2_WriteData8(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1682 {
1683 MS_U32 write_data, write_data_size;
1684 MS_U8 *write_ptr;
1685
1686 if(data_size < 4)
1687 {
1688 return FALSE;
1689 }
1690
1691 write_data_size = data_size;
1692 write_ptr = data;
1693
1694 while(write_data_size >= 4)
1695 {
1696 StatusCheck(HAL_NSK2_CheckBusy());
1697
1698 write_data = HAL_NSK2_WriteDataTrans(write_ptr);
1699 HAL_NSK2_WriteReg(addr_offset,write_data);
1700 //HALNSK2_DBG(0,"addr = %x, write_data = %x\n",addr_offset, write_data);
1701 addr_offset += 4;
1702 write_ptr += 4;
1703 write_data_size -= 4;
1704 }
1705
1706 return TRUE;
1707 }
1708
1709
HAL_NSK2_ReadData32(MS_U32 addr_offset,MS_U32 data_size,MS_U32 * data)1710 MS_U32 HAL_NSK2_ReadData32(MS_U32 addr_offset, MS_U32 data_size, MS_U32 *data)
1711 {
1712 MS_U32 read_data, read_data_size;
1713 MS_U32 *read_ptr;
1714 //MS_U32 test_read_data;
1715
1716 if(data_size < 1)
1717 {
1718 return FALSE;
1719 }
1720
1721 read_data_size = data_size;
1722 read_ptr = data;
1723
1724 while(read_data_size >= 1)
1725 {
1726 StatusCheck(HAL_NSK2_CheckBusy());
1727
1728 read_data = HAL_NSK2_ReadReg(addr_offset);
1729 *read_ptr = read_data;
1730
1731 //HALNSK2_DBG(0,"addr = %x, read_data = %x\n",addr_offset,read_data);
1732 addr_offset += 4;
1733 read_ptr ++;
1734 read_data_size --;
1735 }
1736
1737 return TRUE;
1738 }
1739
HAL_NSK2_WriteData32(MS_U32 addr_offset,MS_U32 data_size,MS_U32 * data)1740 MS_U32 HAL_NSK2_WriteData32(MS_U32 addr_offset, MS_U32 data_size, MS_U32 *data)
1741 {
1742 MS_U32 write_data, write_data_size;
1743 MS_U32 *write_ptr;
1744
1745 if(data_size < 1)
1746 {
1747 return FALSE;
1748 }
1749
1750 write_data_size = data_size;
1751 write_ptr = data;
1752
1753 while(write_data_size >= 1)
1754 {
1755 StatusCheck(HAL_NSK2_CheckBusy());
1756
1757 write_data = *write_ptr;
1758 HAL_NSK2_WriteReg(addr_offset,write_data);
1759 //HALNSK2_DBG(0,"addr = %x, write_data = %x\n",addr_offset, write_data);
1760 addr_offset += 4;
1761 write_ptr ++;
1762 write_data_size --;
1763 }
1764
1765
1766 return TRUE;
1767 }
1768
HAL_NSK2_EnableInt(void)1769 MS_U32 HAL_NSK2_EnableInt(void)
1770 {
1771 MS_U32 u32IntReg = 0;
1772 /*
1773 #define REG_NSK2_ACPU_INT 0xFC08
1774 #define NSK2_INT_CMD_EXIT __BIT0
1775 #define NSK2_INT_ASYNC_EVENT __BIT1
1776 #define NSK2_INT_ILLEGAL_CMD __BIT2
1777 #define NSK2_INT_ILLEGAL_ACCESS __BIT3
1778 #define NSK2_INT_RESET __BIT4
1779 #define NSK2_INT_HANG __BIT5
1780 #define NSK2_INT_KTE_VALID __BIT6
1781 #define NSK2_INT_MASK_CLEAR __BIT31
1782 */
1783
1784 u32IntReg = (NSK2_INT_CMD_EXIT | NSK2_INT_ASYNC_EVENT | NSK2_INT_ILLEGAL_CMD | \
1785 NSK2_INT_RESET | NSK2_INT_HANG | NSK2_INT_KTE_VALID | NSK2_INT_MASK_CLEAR);
1786
1787 HAL_NSK2_WriteReg(REG_NSK2_ACPU_INT,u32IntReg);
1788 return TRUE;
1789 }
1790
HAL_NSK2_DisableInt(void)1791 MS_U32 HAL_NSK2_DisableInt(void)
1792 {
1793 MS_U32 u32IntReg = 0;
1794
1795 HAL_NSK2_WriteReg(REG_NSK2_ACPU_INT,u32IntReg);
1796 return TRUE;
1797 }
1798
1799
HAL_NSK2_GetIntStatus(void)1800 MS_U32 HAL_NSK2_GetIntStatus(void)
1801 {
1802 MS_U32 u32IntValue;
1803 u32IntValue = HAL_NSK2_ReadReg(REG_NSK2_ACPU_INT);
1804
1805 //HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Int status = %x\n",u32IntValue);
1806 return u32IntValue;
1807 }
1808
HAL_NSK2_ClearInt(MS_U32 u32IntValue)1809 MS_U32 HAL_NSK2_ClearInt(MS_U32 u32IntValue)
1810 {
1811 //HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Clear Int = %x\n",u32IntValue);
1812 HAL_NSK2_WriteReg(REG_NSK2_ACPU_INT,u32IntValue);
1813 return TRUE;
1814 }
1815
1816
HAL_NSK2_WriteControl(MS_U32 control)1817 MS_U32 HAL_NSK2_WriteControl(MS_U32 control)
1818 {
1819 HAL_NSK2_WriteReg(REG_NSK2_ACPU_CTRL_BLOCK, control);
1820 return TRUE;
1821 }
1822
1823
HAL_NSK2_WriteCommand(MS_U32 command)1824 MS_U32 HAL_NSK2_WriteCommand(MS_U32 command)
1825 {
1826 HAL_NSK2_WriteReg(REG_NSK2_ACPU_CMD, command);
1827 return TRUE;
1828 }
1829
1830
HAL_NSK2_GetMaxXConn(void)1831 MS_U32 HAL_NSK2_GetMaxXConn(void)
1832 {
1833 return MaximumXConnection;
1834 }
1835
1836
HAL_NSK2_CMChannelNum(void)1837 MS_U32 HAL_NSK2_CMChannelNum(void)
1838 {
1839 return 1;
1840 }
1841
1842
1843 typedef struct
1844 {
1845 MS_U8 u8Tag;
1846 MS_U8 u8Length;
1847 MS_U32 Offset;
1848 MS_U32 MSB;
1849 MS_U32 LSB;
1850 } ASST_t;
1851
1852
1853 static ASST_t K7Asst[] =
1854 {
1855 //the first tag is the same called pub otp, we should implement one function to obtain this,
1856 //becasue this the same as HW test, we can check at HW Test also.
1857 {0x20, 9, 0x3DA8, 63, 0}, //U_OTP_v_pubOtpUniqueID1
1858 {0x21, 16, 0x3500, 127, 0}, //Bulk data 1
1859 {0x22, 16, 0x3510, 127, 0}, //Bulk data 2
1860 {0x23, 16, 0x3520, 127, 0}, //Bulk data 3
1861 {0x24, 16, 0x3530, 127, 0}, //Bulk data 4
1862
1863 {0x40, 1, 0x3B20, 17, 16}, //U_OTP_allow_NDSKey_BlankChk
1864 {0x41, 1, 0x3B24, 3, 0}, //U_OTP_ena_ACPUUseNSK2
1865 {0x42, 1, 0x3B24, 7, 4}, //U_OTP_ena_DBUSUseNSK2
1866 {0x43, 1, 0x3B24, 11, 8}, //U_OTP_ena_ForceOneMilSec
1867 {0x44, 1, 0x3B24, 15, 12}, //U_OTP_allow_SCCheck
1868 {0x45, 1, 0x3B24, 19, 16}, //U_OTP_ena_TestRCFreq
1869 {0x46, 1, 0x3B24, 23, 20}, //U_OTP_ena_SWRN
1870 {0x47, 1, 0x3B24, 27, 24}, //U_OTP_ena_NSKSeedPRNG
1871 {0x48, 1, 0x3B24, 31, 28}, //U_OTP_OTPWritePWDProtect
1872 {0x49, 1, 0x3B28, 11, 8}, //U_OTP_ena_EMMFilter
1873 {0x4A, 1, 0x3B28, 15, 12}, //U_OTP_ena_TestGenIN
1874 {0x4B, 1, 0x3B28, 7, 6}, //U_OTP_allow_NSK2_PWD_Mode
1875 {0x4C, 1, 0x3B2C, 3, 2}, //U_OTP_allow_NDSSC_ReadFail_BadPkt
1876 {0x4D, 1, 0x3B2C, 5, 4}, //U_OTP_allow_RANDOM_keybus
1877 {0x4E, 1, 0x3B2C, 7, 6}, //U_OTP_allow_RANDOM_byteacc
1878 {0x4F, 1, 0x3B2C, 9, 8}, //U_OTP_allow_NDS_Rd55AA
1879 {0x50, 1, 0x3B2C, 11, 10}, //U_OTP_allow_NDS_Parity_chk
1880 {0x51, 1, 0x3B2C, 15, 14}, //U_OTP_forbid_OTPBuiltInTest
1881 {0x52, 1, 0x3C58, 3, 0}, //U_OTP_ena_ESAAlgo_invalidate
1882 {0x53, 1, 0x3C58, 7, 4}, //U_OTP_ena_LocalAlgo_Invalidate
1883 {0x54, 1, 0x3C58, 11, 8}, //U_OTP_ContentProtEn
1884 {0x55, 1, 0x3C58, 13, 12}, //U_OTP_concurrency_configuration
1885 {0x56, 1, 0x3C58, 15, 14}, //U_OTP_allow_NSK_RNG_ROSC
1886 {0x57, 1, 0x3C58, 16, 16}, //U_OTP_nds_fc_disable
1887 {0x58, 1, 0x3C58, 17, 17}, //U_OTP_NDS_CPNR0_sel
1888 {0x59, 1, 0x3C58, 18, 18}, //U_OTP_NDS_CPNR_off
1889 {0x5A, 1, 0x3C60, 3, 2}, //U_OTP_OBFUSCATEVideoStream
1890 {0x5B, 1, 0x3C60, 1, 1}, //U_OTP_MOBF_TOP_use_DES
1891 {0x5C, 1, 0x3C74, 11, 8}, //U_OTP_ena_PlayBackRec0
1892 {0x5D, 1, 0x3C74, 15, 12}, //U_OTP_ena_PlayBackRec1
1893 {0x5E, 1, 0x3C74, 19, 16}, //U_OTP_ena_PlayBackRec2
1894 {0x5F, 1, 0x3C74, 23, 20}, //U_OTP_ena_PlayBackRec3
1895 {0x60, 1, 0x3C78, 3, 0}, //U_OTP_ena_PVR_secure_protect_0
1896 {0x61, 1, 0x3C78, 19, 16}, //U_OTP_dis_TSO
1897 {0x62, 1, 0x3C80, 13, 12}, //U_OTP_forbid_SW_SPSD_Key
1898 {0x63, 1, 0x3C80, 17, 16}, //U_OTP_allow_TSPCPUCodeProt
1899 {0x64, 1, 0x3CC0, 13, 12}, //U_OTP_allow_RANDOM
1900 {0x65, 1, 0x3CC8, 3, 0}, //U_OTP_SBoot
1901 {0x66, 1, 0x3CC8, 7, 4}, //U_OTP_SecretAreaEnable
1902 {0x67, 2, 0x3CCC, 8, 0}, //U_OTP_SCAN_MODE
1903 {0x68, 1, 0x3CCC, 15, 10}, //U_OTP_MBIST_MODE
1904 {0x69, 1, 0x3CCC, 21, 16}, //U_OTP_I2C_MODE
1905 {0x6A, 1, 0x3CCC, 31, 26}, //U_OTP_EJTAG_MODE
1906 {0x6B, 1, 0x3CD0, 11, 8}, //U_OTP_forbid_USBSlaveMode
1907 {0x6C, 1, 0x3CD0, 13, 12}, //U_OTP_allow_DRAM_MOBF
1908 {0x6D, 1, 0x3CD4, 15, 14}, //U_OTP_forbid_BCKGND_CHK
1909 {0x6E, 1, 0x3CD4, 21, 16}, //U_OTP_SCPUBootMode
1910 {0x6F, 1, 0x3CE0, 31, 30}, //U_OTP_forbid_STR
1911 {0x70, 1, 0x3D24, 11, 8}, //U_OTP_ena_NSK2
1912 {0x71, 1, 0x3D24, 15, 14}, //U_OTP_ena_DMA
1913 {0x72, 1, 0x3D24, 19, 16}, //U_OTP_ena_SCPU
1914 {0x73, 1, 0x3D44, 3, 0}, //U_OTP_ena_ACPU2KT
1915 {0x74, 1, 0x3D44, 7, 4}, //U_OTP_ena_NSK2KT
1916 {0x75, 1, 0x3D44, 19, 16}, //U_OTP_ena_ACPUWrNSKKey2KT
1917 {0x76, 1, 0x3D44, 27, 24}, //U_OTP_ena_NSKCW2CryptoDMA
1918 {0x77, 1, 0x3D4C, 7, 4}, //U_OTP_ena_DMA_DESBasedCipher
1919 {0x78, 1, 0x3D6C, 19, 16}, //U_OTP_ena_LowerPathRec
1920 {0x79, 1, 0x3B2C, 17, 16}, //U_OTP_forbid_Kilo_ProgRepair
1921 {0x7A, 1, 0x3CC8, 19, 16}, //U_OTP_SecR2_Sboot
1922 {0x7B, 1, 0x3C88, 27, 24}, //U_OTP_NDS_CODE_INTEGRITY_RSA_KEY_SEL
1923 {0x7C, 1, 0x3CC8, 23, 20}, //U_OTP_xCPU_Sboot
1924 };
1925
1926
endian_change(MS_U8 * ptr,MS_U32 bytes)1927 void endian_change(MS_U8* ptr, MS_U32 bytes)
1928 {
1929
1930 MS_U32 u32halve;
1931 MS_U32 u32tmp;
1932 MS_U32 i;
1933
1934 u32halve = bytes/2;
1935 for(i=0; i<u32halve; i++)
1936 {
1937 u32tmp = ptr[i];
1938 ptr[i] = ptr[bytes-i-1];
1939 ptr[bytes-i-1] = u32tmp;
1940 }
1941 }
1942
HAL_NSK2_GetOTPProperties(MS_U32 * desc_size,MS_U8 * desc)1943 MS_U32 HAL_NSK2_GetOTPProperties(MS_U32 *desc_size, MS_U8 *desc)
1944 {
1945 MS_U32 NumOfTag = sizeof(K7Asst)/sizeof(ASST_t);
1946 MS_U32 ret_size = 0, i, j;
1947 MS_U8 *pDesc = (MS_U8 *)desc;
1948 MS_U32 OTPValue;
1949 MS_U8 RunLens;
1950 MS_U32 RunOffset;
1951
1952 ret_size = 0;
1953 for( i=0; i<NumOfTag; i++)
1954 {
1955 ret_size += (K7Asst[i].u8Length + 2);
1956 }
1957
1958 *desc_size = ret_size;
1959
1960 //printf("length of OTP Tag = %lx\n",ret_size);
1961 if(desc == NULL)
1962 {
1963
1964 return TRUE;
1965 }
1966
1967 for( i=0; i<NumOfTag; i++)
1968 {
1969 *pDesc++ = K7Asst[i].u8Tag;
1970 *pDesc++ = K7Asst[i].u8Length;
1971
1972 if(0x20 == K7Asst[i].u8Tag) //pubOTP...special case....
1973 {
1974 *pDesc++ = 0;
1975 //4 Chip ID
1976 MS_U8 PubOTP[8];
1977 for(j=0;j<8;j+=4)
1978 {
1979 MS_U32 u32Tmp;
1980 u32Tmp = MDrv_CA_OTP_Read(K7Asst[i].Offset + j);
1981 memcpy(&PubOTP[j], &u32Tmp, 4);
1982 }
1983 endian_change(PubOTP, 8);
1984
1985 memcpy(pDesc,PubOTP,8);
1986 pDesc += 8;
1987 }
1988 else if (0x25 == K7Asst[i].u8Tag) //NV Counter...special case....
1989 {
1990 MS_U32 MaxNVCounter = 1024;
1991 *pDesc++ = (MS_U8)((MaxNVCounter>>24)&0xff);
1992 *pDesc++ = (MS_U8)((MaxNVCounter>>16)&0xff);
1993 *pDesc++ = (MS_U8)((MaxNVCounter>>8)&0xff);
1994 *pDesc++ = (MS_U8)(MaxNVCounter&0xff);
1995
1996 *pDesc++ = 0;
1997 *pDesc++ = 0;
1998 *pDesc++ = 0;
1999 *pDesc++ = 0;
2000
2001 }
2002 else
2003 {
2004 RunLens = K7Asst[i].u8Length;
2005 RunOffset = K7Asst[i].Offset;
2006 //printf("Offset = %lx, length = %x\n",RunOffset, RunLens);
2007 if(K7Asst[i].u8Length <= 4)
2008 {
2009 HAL_NSK2_OTP_Get(K7Asst[i].Offset, K7Asst[i].MSB, K7Asst[i].LSB, &OTPValue);
2010 if(1 == RunLens)
2011 *pDesc++ = (MS_U8)(OTPValue&0xff);
2012 else if(2 == RunLens)
2013 {
2014 *pDesc++ = (MS_U8)((OTPValue>>8)&0xff);
2015 *pDesc++ = (MS_U8)(OTPValue&0xff);
2016 }
2017 else if(4 == RunLens)
2018 {
2019 *pDesc++ = (MS_U8)((OTPValue>>24)&0xff);
2020 *pDesc++ = (MS_U8)((OTPValue>>16)&0xff);
2021 *pDesc++ = (MS_U8)((OTPValue>>8)&0xff);
2022 *pDesc++ = (MS_U8)(OTPValue&0xff);
2023 }
2024 }
2025 else //length > 4, tmp solution
2026 {
2027 //printf("length = %x\n",RunLens);
2028 MS_U8 BulkData[16];
2029 for( j=0; j<RunLens; j+=4 )
2030 {
2031 HAL_NSK2_OTP_Get(RunOffset + j, 31, 0, &OTPValue);
2032 //printf("run offset = %lx, Value = %lx\n", (RunOffset + j),OTPValue);
2033 memcpy(&BulkData[j],&OTPValue,4);
2034 }
2035 endian_change(BulkData, 16);
2036 memcpy(pDesc,BulkData,16);
2037 pDesc += 16;
2038
2039 //printf("endian change\n");
2040 //endian_change(desc, RunLens);
2041 }
2042 }
2043 }
2044
2045 #if 0
2046 MS_U32 size = *desc_size;
2047
2048 for(i=0;i<size;i++)
2049 {
2050 printf(" (%ld, %x) \n", i , desc[i]);
2051 }
2052 #endif
2053 return TRUE;
2054 }
2055
2056
2057
2058 typedef struct
2059 {
2060 MS_U32 Offset;
2061 MS_U32 MSB;
2062 MS_U32 LSB;
2063 MS_U32 Bits;
2064 } ChipOTPCfg_t;
2065
2066
2067 static ChipOTPCfg_t K7ChipCfg[] =
2068 {
2069 {0x3B20, 7, 0, 8}, //[127:120] U_OTP_forbid_NSK_wr_sck[7:0] 11111111
2070 {0x3B20, 15, 8, 8}, //[119:112] U_OTP_UseCheckSum[7:0] 11111111
2071 {0x3B20, 17, 16, 2}, //[111:110] U_OTP_allow_NDSKey_BlankChk[1:0] 11
2072 {0x3B20, 19, 18, 2}, //[109:108] U_OTP_allow_ProgFail_RuinNDSKey[1:0] 11
2073 {0x3B20, 21, 20, 2}, //[107:106] U_OTP_allow_NDSReadKeyWait200ms[1:0] 11
2074 {0x3B20, 23, 22, 2}, //[105:104] U_OTP_allow_ReadErrorRstOtp[1:0] 11
2075 {0x3B20, 27, 24, 4}, //[103:100] U_OTP_allow_illegalNDSFlagChk[3:0] 1111
2076 {0x3B20, 31, 28, 4}, //[99:96] U_OTP_allow_Rst_NDS_SCFlag_ParityFail[3:0] 1111
2077 {0x3B24, 3, 0, 4}, //[95:92] U_OTP_ena_ACPUUseNSK2[3:0] 0001
2078 {0x3B28, 7, 6, 2}, //[91:90] U_OTP_allow_NSK2_PWD_Mode[1:0] 11
2079 {0x3B2C, 15, 14, 2}, //[[89:88] U_OTP_forbid_OTPBuiltInTest[1:0] 11
2080 {0x3B2C, 17, 16, 2}, //[87:86] U_OTP_forbid_Kilo_ProgRepair[1:0] 11
2081 {0x3C50, 1, 0, 2}, //[85:84] U_OTP_NDS_ESCK_Key1_obfuscation[1:0] 11
2082 {0x3C50, 3, 2, 2}, //[83:82] U_OTP_NDS_Key1_integrity_chk[1:0] 11
2083 {0x3C50, 5, 4, 2}, //[81:80] U_OTP_NDS_ESCK_Key2_obfuscation[1:0] 11
2084 {0x3C50, 7, 6, 2}, //[79:78] U_OTP_NDS_Key2_integrity_chk[1:0] 11
2085 {0x3C50, 9, 8, 2}, //[77:76] U_OTP_NDS_ESCK_Key3_obfuscation[1:0] 11
2086 {0x3C50, 11, 10, 2}, //[75:74] U_OTP_NDS_Key3_integrity_chk[1:0] 11
2087 {0x3C50, 13, 12, 2}, //[73:72] U_OTP_NDS_ESCK_Key4_obfuscation[1:0] 11
2088 {0x3C50, 15, 14, 2}, //[71:70] U_OTP_NDS_Key4_integrity_chk[1:0] 11
2089 {0x3C50, 17, 16, 2}, //[69:68] U_OTP_NDS_ESCK_Key5_obfuscation[1:0] 11
2090 {0x3C50, 19, 18, 2}, //[67:66] U_OTP_NDS_Key5_integrity_chk[1:0] 11
2091 {0x3C50, 21, 20, 2}, //[65:64] U_OTP_NDS_ESCK_Key6_obfuscation[1:0] 11
2092 {0x3C50, 23, 22, 2}, //[63:62] U_OTP_NDS_Key6_integrity_chk[1:0] 11
2093 {0x3C50, 25, 24, 2}, //[61:60] U_OTP_NDS_ESCK_Key7_obfuscation[1:0] 11
2094 {0x3C50, 27, 26, 2}, //[59:58] U_OTP_NDS_Key7_integrity_chk[1:0] 11
2095 {0x3C50, 29, 28, 2}, //[57:56] U_OTP_NDS_ESCK_Key8_obfuscation[1:0] 11
2096 {0x3C50, 31, 30, 2}, //[55:54] U_OTP_NDS_Key8_integrity_chk[1:0] 11
2097 {0x3C58, 11, 8, 4}, //[53:50] U_OTP_ContentProtEn[3:0] 1111
2098 {0x3C58, 13, 12, 2}, //[49:48] U_OTP_concurrency_configuration[1:0] 10
2099 {0x3C58, 15, 14, 2}, //[47:46] U_OTP_allow_NSK_RNG_ROSC[1:0] 11
2100 {0x3C60, 0, 0, 1}, //[45] U_OTP_forbid_CLK_SEED_TEST 1
2101 {0x3C60, 3, 2, 2}, //[44:43] U_OTP_OBFUSCATEVideoStream[1:0] 00
2102 {0x3C78, 3, 0, 4}, //[42:39] U_OTP_ena_PVR_secure_protect_0[3:0] 0001
2103 {0x3C78, 19, 16, 4}, //[38:35] U_OTP_dis_TSO[3:0] 0001
2104 {0x3CC0, 13, 12, 2}, //[34:33] U_OTP_allow_RANDOM[1:0] 11
2105 {0x3CC8, 3, 0, 4}, //[32:29] U_OTP_SBoot[3:0] 0000
2106 {0x3CD0, 11, 8, 4}, //[28:25] U_OTP_forbid_USBSlaveMode[3:0] 1111
2107 {0x3CD0, 13, 12, 2}, //[24:23] U_OTP_allow_DRAM_MOBF[1:0] 00
2108 {0x3CD0, 20, 18, 3}, //[22:20] U_OTP_forbid_clk_otp_sel[2:0] 111
2109 {0x3CE0, 31, 30, 2}, //[19:18] U_OTP_forbid_STR[1:0] 00
2110 {0x3D24, 11, 8, 4}, //[17:14] U_OTP_ena_NSK2[3:0] 0001
2111 {0x3D24, 15, 14, 2}, //[13:12] U_OTP_ena_DMA[1:0] 01
2112 {0x3D24, 19, 16, 4}, //[11:8] U_OTP_ena_SCPU[3:0] 0001
2113 {0x3D44, 3, 0, 4}, //[7:4] U_OTP_ena_ACPU2KT[3:0] 0001
2114 {0x3D44, 7, 4, 4}, //[3:0] U_OTP_ena_NSK2KT[3:0] 0001
2115
2116 {0x3D44, 19, 16, 4}, //[127:124] U_OTP_ena_ACPUWrNSKKey2KT[3:0] 0111
2117 {0x3D50, 3, 0, 4}, //[123:120] U_OTP_ena_LSACPCM[3:0] 0001
2118 {0x3D50, 7, 4, 4}, //[119:116] U_OTP_ena_AESBasedCipher[3:0] 0001
2119 {0x3D50, 11, 8, 4}, //[115:112] U_OTP_ena_DESBasedCipher[3:0] 0001
2120 {0x3D50, 15, 12, 4}, //[111:108] U_OTP_ena_3DESBasedCipher[3:0] 0001
2121 {0x3D50, 19, 16, 4}, //[107:104] U_OTP_ena_Multi2BasedCipher[3:0] 0001
2122 {0x3D50, 23, 20, 4}, //[103:100] U_OTP_ena_DVBCSA2ConfCipher[3:0] 0001
2123 {0x3D50, 27, 24, 4}, //[99:96] U_OTP_ena_DVBCSA2Cipher[3:0] 0001
2124 {0x3D50, 31, 28, 4}, //[95:92] U_OTP_ena_DVBCSA3BasedCipher[3:0] 0001
2125 {0x3D54, 31, 0, 32}, //[91:28] U_OTP_Ch_SwitchComb[63:0] 1111111111111111111111111111111111111111111111111111111111111111
2126 {0x3D58, 31, 0, 32}, //[91:28] U_OTP_Ch_SwitchComb[63:0] 1111111111111111111111111111111111111111111111111111111111111111
2127 {0x3D5C, 3, 0, 4}, //[27:24] U_OTP_ena_LSAD_MDI[3:0] 0001
2128 {0x3D5C, 7, 4, 4}, //[23:20] U_OTP_ena_LSAD_MDD[3:0] 0001
2129 {0x3D5C, 11, 8, 4}, //[19:16] U_OTP_ena_LSAD_CIPLUS_AES[3:0] 0001
2130 {0x3D5C, 15, 12, 4}, //[15:12] U_OTP_ena_LSAD_AES_ECB_CLEAR[3:0] 0001
2131 {0x3D5C, 19, 16, 4}, //[11:8] U_OTP_ena_LSAD_SCTE41_SCTE52_DES[3:0] 0001
2132 {0x3D60, 3, 0, 4}, //[7:4] U_OTP_ena_ESA_CIPLUS_AES[3:0] 0001
2133 {0x3D60, 7, 4, 4}, //[3:0] U_OTP_ena_ESA_CIPLUS_DES[3:0] 0001
2134
2135 {0x3D60, 11, 8, 4}, //[127:124] U_OTP_ena_ESA_SCTE52_DES[3:0] 0001
2136 {0x3D60, 15, 12, 4}, //[123:120] U_OTP_ena_ESA_tDES_CBC_CLEAR[3:0] 0001
2137 {0x3D64, 3, 0, 4}, //[119:116] U_OTP_ena_LSAS_MDI[3:0] 0001
2138 {0x3D64, 7, 4, 4}, //[115:112] U_OTP_ena_LSAS_MDD[3:0] 0001
2139 {0x3D64, 11, 8, 4}, //[111:108] U_OTP_ena_LSAS_CIPLUS_AES[3:0] 0001
2140 {0x3D64, 15, 12, 4}, //[107:104] U_OTP_ena_LSAS_AES_ECB_CLEAR[3:0] 0001
2141 {0x3D64, 19, 16, 4}, //[103:100] U_OTP_ena_LSAS_SCTE41_SCTE52_DES[3:0] 0001
2142 {0x3D68, 7, 4, 4}, //[99:96] U_OTP_ena_ReviewFailPkt[3:0] 0001
2143 {0x3D68, 11, 8, 4}, //[95:92] U_OTP_dis_NonSecRangeEncrypt[3:0] 0001
2144 {0x3D6C, 3, 0, 4}, //[91:88] U_OTP_ena_CA_PVR_secure_protect_0[3:0] 0001
2145 {0x3D6C, 7, 4, 4}, //[87:84] U_OTP_ena_CA_PVR_secure_protect_1[3:0] 0001
2146 {0x3D6C, 11, 8, 4}, //[83:80] U_OTP_ena_CA_PVR_secure_protect_2[3:0] 0001
2147 {0x3D6C, 15, 12, 4}, //[79:76] U_OTP_ena_CA_PVR_secure_protect_3[3:0] 0001
2148 {0x3D6C, 19, 16, 4}, //[75:72] U_OTP_ena_LowerPathRec[3:0] 0111
2149 {0x3FA0, 9, 8, 2}, //[71:70] U_OTP_I2C_PWD_obfuscation[1:0] 11
2150 {0x3FA0, 11, 10, 2}, //[69:68] U_OTP_EJTAG_PWD_obfuscation[1:0] 11
2151 {0x3FA0, 13, 12, 2}, //[67:66] U_OTP_SCAN_PWD_obfuscation[1:0] 11
2152 {0x3FA0, 15, 14, 2}, //[65:64] U_OTP_MBIST_PWD_obfuscation[1:0] 11
2153 //[63:0] 0 0000000000000000000000000000000000000000000000000000000000000000
2154
2155 };
2156
2157 #define FullChipConfigSize 0x28
2158
HAL_NSK2_GetFullChipSize(void)2159 MS_U32 HAL_NSK2_GetFullChipSize(void)
2160 {
2161 return FullChipConfigSize;
2162 }
2163
HAL_NSK2_GetFullChipConfig(MS_U32 * desc_size,MS_U8 * desc)2164 MS_U32 HAL_NSK2_GetFullChipConfig(MS_U32 *desc_size, MS_U8 *desc)
2165 {
2166 *desc_size = FullChipConfigSize;
2167 if(desc == NULL)
2168 {
2169 return TRUE;
2170 }
2171
2172 MS_U32 i, j, remain_bits, shift_bits;
2173 MS_U32 NumOfConfigs = sizeof(K7ChipCfg)/sizeof(ChipOTPCfg_t);
2174 MS_U32 TotalOTPValue[100];
2175
2176 memset(desc, 0x0, FullChipConfigSize);
2177 //desc[0x40-1] = 0x28;
2178 //desc[0x28] = 0x80;
2179
2180 for(i=0; i<NumOfConfigs; i++)
2181 {
2182 HAL_NSK2_OTP_Get(K7ChipCfg[i].Offset, K7ChipCfg[i].MSB, K7ChipCfg[i].LSB, &TotalOTPValue[i]);
2183 //printf("%d, %x\n",i, TotalOTPValue[i]);
2184 }
2185
2186 j = 0;
2187 remain_bits = 8;
2188 for(i=0; i<NumOfConfigs; i++)
2189 {
2190 if(K7ChipCfg[i].Bits>remain_bits)
2191 {
2192 if(K7ChipCfg[i].Bits == 32)
2193 {
2194 if(remain_bits != 8)
2195 {
2196 shift_bits = 8-remain_bits;
2197 desc[j] |= 0xf;
2198 j++;
2199 desc[j] = 0xff;
2200 j++;
2201 desc[j] = 0xff;
2202 j++;
2203 desc[j] = 0xff;
2204 j++;
2205 desc[j] = 0xf0;
2206 remain_bits = 4;
2207 }
2208 else
2209 {
2210 memcpy(&desc[j], &TotalOTPValue[i], 4);
2211 j += 4;
2212 remain_bits = 0;
2213 }
2214 }
2215 else
2216 {
2217
2218 shift_bits = K7ChipCfg[i].Bits-remain_bits;
2219 //printf("not equal case (%d), shift_bits = %x\n",i,shift_bits);
2220 desc[j] |= (TotalOTPValue[i] >> shift_bits);
2221 j++;
2222
2223 remain_bits = (8-shift_bits);
2224 desc[j] |= (( TotalOTPValue[i] << remain_bits ) & 0xff);
2225
2226 }
2227
2228 }
2229 else
2230 {
2231 remain_bits -= K7ChipCfg[i].Bits;
2232 desc[j] |= (TotalOTPValue[i] << (remain_bits));
2233 }
2234
2235 if(remain_bits == 0)
2236 {
2237 remain_bits = 8;
2238 j++;
2239 }
2240 }
2241
2242 return TRUE;
2243 }
2244
2245
2246 static NVCounter_Desc_t nvcounter_desc = {
2247 .descriptor_tag = NSK2HDI_OTP_NVCOUNTER_DESC_TAG,
2248 .descriptor_length = 8, //sizeof(NVCounter_Desc_t) - 2,
2249 .max_nvcounter[0] = 0x00,
2250 .max_nvcounter[1] = 0x00,
2251 .max_nvcounter[2] = 0x04,
2252 .max_nvcounter[3] = 0x00,
2253 .left_nvcounter[0] = 0x00,
2254 .left_nvcounter[1] = 0x00,
2255 .left_nvcounter[2] = 0x04,
2256 .left_nvcounter[3] = 0x00,
2257 };
2258
2259 #define TotalNVNumber 1024
2260
2261
2262
HAL_NSK2_GetNVCounterConfig(MS_U32 * desc_size,MS_U8 * desc)2263 MS_U32 HAL_NSK2_GetNVCounterConfig(MS_U32 *desc_size, MS_U8 *desc)
2264 {
2265 MS_U32 u32NvCounter = 0;
2266 MS_U32 u32LeftNvCounter = 0;
2267
2268 if(desc == NULL)
2269 {
2270 *desc_size = sizeof(nvcounter_desc);
2271 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_NVCounterUpdates return desc_size = %x\n",*desc_size);
2272 return TRUE;
2273 }
2274
2275 *desc_size = sizeof(nvcounter_desc);
2276
2277 if( (MDrv_SYS_GetChipRev() == 1) || (MDrv_SYS_GetChipRev() == 0) )
2278 {
2279 HAL_NSK2_WriteControl(0x1);
2280 MsOS_DelayTaskUs(10);
2281 HAL_NSK2_WriteCommand(0x73);
2282 MsOS_DelayTaskUs(10);
2283 StatusCheck(HAL_NSK2_CheckBusy());
2284 HAL_NSK2_ReadData32(0x1C, 0x1, &u32NvCounter);
2285 }
2286 else //after U03
2287 {
2288 u32NvCounter = NI_REG(REG_NI_NSK21_GET_NVCOUNTER);
2289 }
2290
2291
2292 u32LeftNvCounter = TotalNVNumber - u32NvCounter;
2293
2294 printf("NVValue = %d, LeftNVCounter = %d \n", u32NvCounter, u32LeftNvCounter);
2295
2296 nvcounter_desc.left_nvcounter[0] = (MS_U8)((u32LeftNvCounter>>24)&0xff);
2297 nvcounter_desc.left_nvcounter[1] = (MS_U8)((u32LeftNvCounter>>16)&0xff);
2298 nvcounter_desc.left_nvcounter[2] = (MS_U8)((u32LeftNvCounter>>8)&0xff);
2299 nvcounter_desc.left_nvcounter[3] = (MS_U8)(u32LeftNvCounter&0xff);
2300
2301 memcpy(desc,&nvcounter_desc,sizeof(nvcounter_desc));
2302
2303 return TRUE;
2304 }
2305
HAL_NSK2_SetDbgLevel(MS_U32 u32Level)2306 void HAL_NSK2_SetDbgLevel(MS_U32 u32Level)
2307 {
2308 _g32NSK2HalDbgLv = u32Level;
2309 HALNSK2_DBG(NSK2_DBGLV_INFO, "%s level: %x\n", __FUNCTION__, u32Level);
2310 return;
2311 }
2312
HAL_NSK2_SetPollingCnt(MS_U32 u32Cnt)2313 void HAL_NSK2_SetPollingCnt(MS_U32 u32Cnt)
2314 {
2315 dead_polling_cnt = u32Cnt;
2316 }
2317
2318 #if 0
2319 void HAL_NSK2_BurstLen(MS_U32 u32PVREng, MS_U32 u32BurstMode)
2320 {
2321 HAL_PVR_BurstLen(u32PVREng, u32BurstMode);
2322 }
2323 #endif
2324
HAL_NSK2_ClockTest(MS_U32 testnum)2325 void HAL_NSK2_ClockTest(MS_U32 testnum)
2326 {
2327
2328 MS_U32 u32Data;
2329 switch(testnum)
2330 {
2331 case 0:
2332 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
2333 MsOS_DelayTaskUs(1);
2334
2335 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2336 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2337
2338
2339 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2340
2341 //bit 0 set to 1...
2342 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_NSK2_RESET_DISABLE | NI_NSK2_CLK_ENABLE;
2343
2344 MsOS_DelayTaskUs(1);
2345 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2346 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2347 break;
2348
2349
2350 case 1:
2351 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
2352 MsOS_DelayTaskUs(1);
2353
2354 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2355 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2356
2357
2358 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2359 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2360
2361 //disable nsk2 clock
2362 NI_REG(REG_NI_NSK2_CTRL) = u32Data & ~(NI_NSK2_CLK_ENABLE) ;
2363 MsOS_DelayTask(1);
2364 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2365 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2366
2367 break;
2368
2369 case 2:
2370 RSA_REG(REG_RSA_CLK_ENABLE) &= (~RSA_PM_NSKCLK_ENABLE);
2371 MsOS_DelayTaskUs(1);
2372
2373 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2374 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2375
2376
2377 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2378 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2379
2380 //bit 0 set to 1...
2381 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_NSK2_RESET_DISABLE | NI_NSK2_CLK_ENABLE;
2382
2383 MsOS_DelayTaskUs(1);
2384 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2385 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2386 break;
2387
2388 case 3:
2389 RSA_REG(REG_RSA_CLK_ENABLE) &= (~RSA_PM_NSKCLK_ENABLE);
2390 MsOS_DelayTaskUs(1);
2391
2392 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2393 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2394
2395 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2396 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2397
2398 //disable nsk2 clock
2399 NI_REG(REG_NI_NSK2_CTRL) = u32Data & ~(NI_NSK2_CLK_ENABLE) ;
2400 MsOS_DelayTask(1);
2401 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2402 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2403 break;
2404 }
2405 }
2406
HAL_NSK2_GetRNGThroughPut(void * pRngData,MS_U32 u32DataSize,MS_BOOL bDump)2407 void HAL_NSK2_GetRNGThroughPut(void *pRngData, MS_U32 u32DataSize, MS_BOOL bDump)
2408 {
2409 MS_U32 u32StartTime;
2410 MS_U32 *pRNG_Data = (MS_U32 *)pRngData;
2411 MS_U32 valid = 0;
2412 MS_U32 i = 0;
2413
2414 NI_REG(REG_NI_NSK2_CTRL) = NI_REG(REG_NI_NSK2_CTRL) & (~NI_NSK2_RESET_DISABLE);
2415 NI_REG(REG_NI_NSK2_FREERUN) = NI_REG(REG_NI_NSK2_FREERUN) & (~ (NI_NSK2_RANDOM_FREERUN | NI_NSK2_RANDOM_ONEBYONE) );
2416
2417 u32StartTime = MsOS_GetSystemTime();
2418
2419 for(i=0; i< u32DataSize; i++)
2420 {
2421 do
2422 {
2423 valid = NI_REG(REG_NI_NSK2_TRNG_VALID) & NI_NSK2_TRNG_VALID_MASK; //trng_sw_read_valid_nsk ;
2424 }while(valid != 1);
2425
2426 pRNG_Data[i] = NI_REG(REG_NI_NSK2_TRNG_DATA);//trng_sw_read_data_nsk;
2427 NI_REG(REG_NI_NSK2_FREERUN) = NI_REG(REG_NI_NSK2_FREERUN) | NI_NSK2_RANDOM_ONEBYONE; //lfsr_get_go_nsk = 1 ;
2428 }
2429 MS_U32 u32EndTime = MsOS_GetSystemTime();
2430
2431 HALNSK2_DBG(NSK2_DBGLV_ERR, "1M bit data size, total Time = %1d ms\n", (MS_U32)(u32EndTime - u32StartTime));
2432
2433 if(bDump)
2434 {
2435 for(i = 0 ; i < u32DataSize ; i ++)
2436 {
2437 HALNSK2_DBG(NSK2_DBGLV_ERR, "%08x\n", (unsigned int)(pRNG_Data[i]));
2438 }
2439 }
2440 }
2441
HAL_NSK2_RunFree(MS_BOOL bRunFree)2442 void HAL_NSK2_RunFree(MS_BOOL bRunFree)
2443 {
2444 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "bRunFree = %d\n", bRunFree);
2445
2446 if(bRunFree)
2447 {
2448 _gCheckBusyFlag = FALSE;
2449 }
2450 else
2451 {
2452 _gCheckBusyFlag = TRUE;
2453 }
2454 }
2455
2456
HAL_NSK2_PushSlowClock(MS_BOOL HaltClk,MS_U32 NumOfMs)2457 MS_U32 HAL_NSK2_PushSlowClock ( MS_BOOL HaltClk, MS_U32 NumOfMs)
2458 {
2459 //HALNSK2_DBG(NSK2_DBGLV_DEBUG, "HaltClk = %d NumofTenSecond = %d\n", HaltClk, NumofTenSecond);
2460
2461 StatusCheck(HAL_NSK2_CheckBusy());
2462 MS_U32 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2463 MS_U32 i = 0;
2464
2465 if(HaltClk == TRUE)//close clk
2466 {
2467 NI_REG(REG_NI_NSK2_CTRL) = u32Data & (~NI_NSK2_CLK_ENABLE) ;
2468 RSA_REG(REG_RSA_CLK_ENABLE) &= (~RSA_PM_NSKCLK_ENABLE);
2469 _gCheckBusyFlag = FALSE;
2470 }
2471 else //open clk
2472 {
2473 _gCheckBusyFlag = TRUE;
2474 if( (u32Data & NI_NSK2_CLK_ENABLE) == 0)
2475 {
2476 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_NSK2_CLK_ENABLE ;
2477 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
2478 //MsOS_DelayTaskUs(1);
2479 }
2480 }
2481
2482 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"REG_NI_NSK2_CTRL = %x\n",NI_REG(REG_NI_NSK2_CTRL));
2483
2484 #if 0
2485 u32Data = NI_REG(REG_NI_NSK2_CLK_CSA);
2486 printf("REG_NI_NSK2_CLK_CSA = %x\n",u32Data);
2487 #else
2488 //u32Data = 0;
2489 u32Data = NI_REG(REG_NI_NSK2_CLK_CSA);
2490 #endif
2491
2492 if(NumOfMs == 0)
2493 return TRUE;
2494
2495 for(i = 0 ; i < (NumOfMs-1) ; i++)
2496 {
2497 //u32Data = NI_REG(REG_NI_NSK2_CLK_CSA);
2498 //printf("REG_NI_NSK2_CLK_CSA = %x\n",u32Data);
2499 NI_REG(REG_NI_NSK2_CLK_CSA) = u32Data | NSK2_PUSH_SLOW_CLK;
2500 MsOS_DelayTaskUs(1);
2501 }
2502
2503 return TRUE;
2504 }
2505
2506
2507
HAL_NSK2_GetCMProperties(MS_U32 * desc_size,MS_U8 * desc)2508 MS_U32 HAL_NSK2_GetCMProperties(MS_U32 *desc_size, MS_U8 *desc)
2509 {
2510 MS_U32 i;
2511 if(desc == NULL)
2512 {
2513 *desc_size = sizeof(cmchannel_group_capability_descriptor_t) + sizeof(cm_algo) /*sizeof(cmchannel_group_algorithm_record_descriptor_t)*CMChannelDescSize*/ ;
2514 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetCMProperties return desc_size = %x\n",*desc_size);
2515 return TRUE;
2516 }
2517
2518 for(i=0;i<32;i++)
2519 {
2520 cm_capb.switch_combination_bitmap[i] = 0xFF;
2521 }
2522
2523 *desc_size = sizeof(cmchannel_group_capability_descriptor_t) + sizeof(cm_algo);
2524
2525 memcpy(desc,&cm_capb,sizeof(cmchannel_group_capability_descriptor_t));
2526 memcpy(desc+sizeof(cmchannel_group_capability_descriptor_t), &cm_algo[0] , sizeof(cm_algo) /*sizeof(cmchannel_group_algorithm_record_descriptor_t)*CMChannelDescSize*/ );
2527
2528 HALNSK2_DBG(NSK2_DBGLV_INFO,"\nHAL_NSK2_GetCMProperties return *desc_size = %x,desc = %x\n",*desc_size,(MS_U32)desc);
2529
2530 return TRUE;
2531 }
2532
HAL_NSK2_GetM2MProperties(MS_U32 * desc_size,MS_U8 * desc)2533 MS_U32 HAL_NSK2_GetM2MProperties(MS_U32 *desc_size, MS_U8 *desc)
2534 {
2535 if(desc == NULL)
2536 {
2537 *desc_size = sizeof(m2m_capa_desc) + sizeof(m2m_algo);
2538 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetM2MProperties #1 return desc_size = %x\n",*desc_size);
2539 return TRUE;
2540 }
2541
2542 *desc_size = sizeof(m2m_capa_desc) + sizeof(m2m_algo);
2543
2544 memcpy(desc, &m2m_capa_desc, sizeof(m2m_capa_desc));
2545 memcpy(desc+sizeof(m2m_capa_desc), &m2m_algo[0], sizeof(m2m_algo));
2546
2547 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetM2MProperties #2 return desc_size = %x\n",*desc_size);
2548 return TRUE;
2549 }
2550
HAL_NSK2_GetDMAProperties(MS_U32 * desc_size,MS_U8 * desc)2551 MS_U32 HAL_NSK2_GetDMAProperties(MS_U32 *desc_size, MS_U8 *desc)
2552 {
2553 if(desc == NULL)
2554 {
2555 *desc_size = sizeof(dma_capa_desc);
2556 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetDMAProperties return desc_size = %x\n",*desc_size);
2557 return TRUE;
2558 }
2559
2560 *desc_size = sizeof(dma_capa_desc);
2561
2562 memcpy(desc, &dma_capa_desc, *desc_size);
2563
2564 return TRUE;
2565 }
2566
2567 //---------------Debug Information----------------------------//
2568 //------------------------------------------------------------//
2569
HAL_NSK2_ReadTSPInfo(MS_U32 pid_no)2570 void HAL_NSK2_ReadTSPInfo(MS_U32 pid_no)
2571 {
2572 MS_U32 pid_data;
2573 MS_U32 FltPid, TS_SRC, dscmb_key_en, prim, pid_pair;
2574
2575 FltPid = TS_SRC = dscmb_key_en = prim = pid_pair = 0;
2576 REG_PidFlt *pPidFlt = PPIDFLT0(pid_no);
2577
2578 pid_data = TSP32_IdrR(pPidFlt);
2579
2580 HALNSK2_DBG(NSK2_DBGLV_INFO,"pid_data = %x\n",pid_data);
2581
2582 FltPid = (pid_data & 0x1fff);
2583 TS_SRC = ((pid_data>>13) & 0x7);
2584 dscmb_key_en = ((pid_data>>16) & 0x1);
2585 prim = ((pid_data>>17) & 0x1);
2586 pid_pair = ((pid_data>>18) & 0xf);
2587
2588 if(dscmb_key_en)
2589 {
2590 HALNSK2_DBG(NSK2_DBGLV_INFO,"(%d) = (FltPid=%x, TS_SRC=%d, prim=%d, pid_pair=%d\n",pid_no,FltPid,TS_SRC,prim,pid_pair);
2591 }
2592 }
2593
HAL_NSK2_ReadTSPDstInfo(MS_U32 pid_no)2594 void HAL_NSK2_ReadTSPDstInfo(MS_U32 pid_no)
2595 {
2596 MS_U32 pid_data;
2597 REG_PidFlt *pPidFlt = PPIDFLT1(pid_no);
2598
2599 pid_data = TSP32_IdrR(pPidFlt);
2600
2601 HALNSK2_DBG(NSK2_DBGLV_INFO,"dst_data = %x\n",pid_data);
2602 }
2603
HAL_NSK2_AllTSPPidFilter(void)2604 void HAL_NSK2_AllTSPPidFilter(void)
2605 {
2606 MS_U32 i;
2607 for(i=0;i<0x100;i++)
2608 {
2609 HAL_NSK2_ReadTSPInfo(i);
2610 }
2611
2612 for(i=0;i<0x100;i++)
2613 {
2614 HAL_NSK2_ReadTSPDstInfo(i);
2615 }
2616 }
2617
HAL_NSK2_ChangePidFilter(MS_U32 pid_no,MS_U32 Data)2618 void HAL_NSK2_ChangePidFilter(MS_U32 pid_no, MS_U32 Data)
2619 {
2620 REG_PidFlt *pPidFlt = PPIDFLT0(pid_no);
2621 TSP32_IdrW(pPidFlt,Data);
2622 }
2623
2624
2625
HAL_NSK2_ReadSwitchFromNSK2(void)2626 MS_U32 HAL_NSK2_ReadSwitchFromNSK2(void)
2627 {
2628
2629 #if 0
2630 2. N2_KteValid=1. NI bank offset 13 bit[3].
2631 3. N2_KteDest=0. NI bank offset 13 bit[2:0].
2632 4. Read the NSK bank offset 0xfc40-0xfc48 to read the NSK driven switch value. (see NSK-ICD-253 page21).
2633 In the read 96 bits, you can find:
2634 Bit[55] AU
2635 Bit[54] BU
2636 Bit[53] DU
2637 Bit[52] EU
2638 Bit[51] AL
2639 Bit[50] BL
2640 Bit[49] DL
2641 Bit[48] EL
2642 Bit[47:44] LocalSelectD
2643 Bit[43:40] LocalSelectS
2644 Bit[39:36] ESA select
2645 Bit[35:33] ESA subselect
2646 Please print out these fields and send the log to me.
2647 #endif
2648
2649 #ifdef ReadSwitchInfoNSK2
2650 MS_U32 NI13 = NI_REG(13);
2651 HALNSK2_DBG(0,"NI13 = %x\n",NI13);
2652
2653 MS_U32 NSK2Debug[3];
2654 NSK2Debug[0] = HAL_NSK2_ReadReg(0xFC40);
2655 NSK2Debug[1] = HAL_NSK2_ReadReg(0xFC44);
2656 NSK2Debug[2] = HAL_NSK2_ReadReg(0xFC48);
2657
2658 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"NSK2Debug = (%x,%x,%x)\n",NSK2Debug[0],NSK2Debug[1],NSK2Debug[2]);
2659 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"AU=%x,BU=%x,DU=%x,EU=%x \n",(NSK2Debug[1]>>23)&0x1,(NSK2Debug[1]>>22)&0x1,(NSK2Debug[1]>>21)&0x1,(NSK2Debug[1]>>20)&0x1);
2660 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"AL=%x,BL=%x,DL=%x,EL=%x \n",(NSK2Debug[1]>>19)&0x1,(NSK2Debug[1]>>18)&0x1,(NSK2Debug[1]>>17)&0x1,(NSK2Debug[1]>>16)&0x1);
2661 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"LocalSelectD = %x, LocalSelectS = %x\n",(NSK2Debug[1]>>12)&0xf,(NSK2Debug[1]>>8)&0xf);
2662 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"ESA select = %x, ESA subselect = %x\n",(NSK2Debug[1]>>4)&0xf,(NSK2Debug[1]>>0)&0xf);
2663 #endif
2664 return TRUE;
2665 }
2666
HAL_NSK2_GetSRAlignBit(void)2667 MS_U32 HAL_NSK2_GetSRAlignBit(void)
2668 {
2669 return 16;
2670 }
2671
2672
HAL_NSK2_RSA_SetSecureRange(MS_U32 u32SecSet,MS_U32 u32SecStart,MS_U32 u32SecEnd,MS_BOOL bEnable)2673 MS_BOOL HAL_NSK2_RSA_SetSecureRange(MS_U32 u32SecSet, MS_U32 u32SecStart, MS_U32 u32SecEnd, MS_BOOL bEnable)
2674 {
2675 if(u32SecSet > REG_RSA_SECRANGE_SET || u32SecEnd <= u32SecStart)
2676 return FALSE;
2677
2678 *(volatile MS_U32*) (_gBasicAddr + REG_RSA_SECRANGE_START(u32SecSet)) = ( u32SecStart & RSA_SECRANGE_MASK);
2679
2680 if (TRUE == bEnable)
2681 {
2682 *(volatile MS_U32*) (_gBasicAddr + REG_RSA_SECRANGE_END(u32SecSet)) = REG_RSA_SECRANGE_ENABLE & ( u32SecEnd & RSA_SECRANGE_MASK);
2683 }
2684 else
2685 {
2686 *(volatile MS_U32*) (_gBasicAddr + REG_RSA_SECRANGE_END(u32SecSet)) = (~REG_RSA_SECRANGE_ENABLE) | ( u32SecEnd & RSA_SECRANGE_MASK);
2687 }
2688
2689 return TRUE;
2690 }
2691
2692 /**
2693 * @brief Configure CA secure range mask
2694 */
HAL_NSK2_RSA_SetSR_Mask(MS_U32 u32DramSize)2695 void HAL_NSK2_RSA_SetSR_Mask(MS_U32 u32DramSize)
2696 {
2697 MS_U32 u32Mask = 0x00000000;
2698
2699 if (0 != ((u32DramSize >> 16) >> 8))
2700 {
2701 u32Mask = (((u32DramSize >> 16) >> 8) - 1) & 0xFF;
2702
2703 *(volatile MS_U32*) (_gBasicAddr + REG_RSA_SECRANGE_MASK) = u32Mask;
2704 }
2705 }
2706 //=====================================
2707 //====== NSK2.1 new functions ======
2708 //=====================================
2709
2710
HAL_NSK2_ReadAllOTP(void)2711 void HAL_NSK2_ReadAllOTP(void)
2712 {
2713 MS_U32 u32RetValue, addr;
2714
2715 for( addr=0 ; addr<0x4000; addr+=4)
2716 {
2717 HAL_NSK2_OTP_Get(addr, 31, 0, &u32RetValue);
2718 //if( (addr&0xf) == 0)
2719 // printf("\n");
2720
2721 if(u32RetValue != 0)
2722 {
2723 printf("addr = %x, value = %x \n",addr, u32RetValue);
2724 }
2725 }
2726 }
2727
HAL_NSK2_ReadKTEResp(void)2728 MS_U32 HAL_NSK2_ReadKTEResp(void)
2729 {
2730 StatusCheck(HAL_NSK2_CheckBusy());
2731
2732 MS_U32 u32KTEResp;
2733 u32KTEResp = NI_REG(REG_NI_NSK2_KTE_RESP);
2734
2735 HALNSK2_DBG(NSK2_DBGLV_INFO,"KTE_RESP = %x\n",u32KTEResp);
2736
2737 return u32KTEResp;
2738 }
2739
HAL_NSK2_GetPubOTP(MS_U8 * pPubOTP)2740 MS_BOOL HAL_NSK2_GetPubOTP(MS_U8 *pPubOTP)
2741 {
2742 #if 0
2743 Table 7 Public OTP Bits
2744 Bit Name Description
2745 127:64 U_OTP_v_pubOtpUniqueID1 OTP unique ID.
2746 This field is unique chip data that can be shared with other non-NDS modules.
2747 63:48 U_OTP_v_PubOtpGP General purpose OTP field.
2748 47:40 U_OTP_v_PubOtpMinConfVer OTPpublic minimum configuration version.
2749 39:36 U_OTP_v_PubOtpRsaIndex OTP public RSA index
2750 35:32 U_OTP_v_PubOtpBID OTP public BlackBox ID
2751 31:16 U_OTP_v_PubOtpVID OTP public version ID
2752 15:0 U_OTP_v_PubOtpOID OTP public owner ID
2753 #endif
2754
2755 //U_OTP_v_pubOtpUniqueID1 0x3DA8 63 0
2756 //U_OTP_v_PubOtpGP 0x3B08 15 0
2757 //U_OTP_v_PubOtpMinConfVer 0x3B14 7 0
2758 //U_OTP_v_PubOtpRsaIndex 0x3B10 3 0
2759 //U_OTP_v_PubOtpBID 0x3B0C 3 0
2760 //U_OTP_v_PubOtpVID 0x3B04 15 0
2761 //U_OTP_v_PubOtpOID 0x3B00 15 0
2762
2763 MS_U8 *pRunPubOTP = (MS_U8 *)pPubOTP;
2764 MS_U32 ReadValue,ReadValue2;
2765
2766 HAL_NSK2_OTP_Get(0x3B00, 15, 0, &ReadValue);
2767 printf("U_OTP_v_PubOtpOID = %x\n",ReadValue);
2768 memcpy(pRunPubOTP,&ReadValue,2);
2769 pRunPubOTP += 2;
2770
2771 HAL_NSK2_OTP_Get(0x3B04, 15, 0, &ReadValue);
2772 printf("U_OTP_v_PubOtpVID = %x\n",ReadValue);
2773 memcpy(pRunPubOTP,&ReadValue,2);
2774 pRunPubOTP += 2;
2775
2776 HAL_NSK2_OTP_Get(0x3B0C, 3, 0, &ReadValue);
2777 printf("U_OTP_v_PubOtpBID = %x\n",ReadValue);
2778 HAL_NSK2_OTP_Get(0x3B10, 3, 0, &ReadValue2);
2779 printf("U_OTP_v_PubOtpRsaIndex = %x\n",ReadValue2);
2780 *pRunPubOTP = (MS_U8)(ReadValue&0xF) + (MS_U8)((ReadValue2&0xF)<<4);
2781 pRunPubOTP ++;
2782
2783 HAL_NSK2_OTP_Get(0x3B14, 7, 0, &ReadValue);
2784 printf("U_OTP_v_PubOtpMinConfVer = %x\n",ReadValue);
2785 memcpy(pRunPubOTP,&ReadValue,1);
2786 pRunPubOTP ++;
2787
2788 HAL_NSK2_OTP_Get(0x3B08, 15, 0, &ReadValue);
2789 printf("U_OTP_v_PubOtpGP = %x\n",ReadValue);
2790 memcpy(pRunPubOTP,&ReadValue,2);
2791 pRunPubOTP += 2;
2792
2793 HAL_NSK2_OTP_Get(0x3DA8, 31, 0, &ReadValue);
2794 printf("U_OTP_v_pubOtpUniqueID1 = %x\n",ReadValue);
2795 memcpy(pRunPubOTP,&ReadValue,4);
2796 pRunPubOTP += 4;
2797
2798 HAL_NSK2_OTP_Get(0x3DAC, 31, 0, &ReadValue);
2799 memcpy(pRunPubOTP,&ReadValue,4);
2800 pRunPubOTP += 4;
2801
2802 return TRUE;
2803 }
2804
HAL_NSK21_InvalidCmChannel(MS_U16 PidSlot)2805 MS_U32 HAL_NSK21_InvalidCmChannel(MS_U16 PidSlot)
2806 {
2807 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s PidSlot = %x\n", __FUNCTION__,PidSlot);
2808
2809 MS_U32 u32PidSlot = 0;
2810 StatusCheck(HAL_NSK2_CheckBusy());
2811
2812 u32PidSlot = (((MS_U32)PidSlot<<NI_WriteTKey_PidNo_Shift)&NI_WriteTransportKey_PidNo);
2813 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_InvalidateCmChannel | u32PidSlot);
2814
2815 return TRUE;
2816 }
2817
2818 typedef enum
2819 {
2820 NSK21_DVBCSA2 = 0,
2821 NSK21_DVBCSA2_CONF,
2822 NSK21_DVBCSA3,
2823 NSK21_CPCM_LSA_MDI_CBC,
2824 NSK21_CPCM_LSA_MDI_RCBC,
2825 NSK21_CPCM_LSA_MDD_CBC, //5
2826 NSK21_CPCM_LSA_MDD_RCBC,
2827 NSK21_SYNAMEDIA_AES,
2828 NSK21_AES_ECB_CLR,
2829 NSK21_CIPLUS_AES,
2830 NSK21_SCTE41_DES, //10
2831 NSK21_SCTE52_DES,
2832 NSK21_TDES_ECB_CLR,
2833 NSK21_MULTI2_TS,
2834 NSK21_TDES_ECB_CTS,
2835 NSK21_DES_ECB_CTS, //15
2836 NSK21_IDSA_AES,
2837 }NSK21_CMChAlgo_e;
2838
HAL_NSK21_CfgCmChannel(MS_U16 PidSlot,MS_U16 LocalDAlgo,MS_U16 ESAAlgo,MS_U16 LocalSAlgo,MS_U16 SysKeyIndex)2839 MS_U32 HAL_NSK21_CfgCmChannel(MS_U16 PidSlot, MS_U16 LocalDAlgo, MS_U16 ESAAlgo, MS_U16 LocalSAlgo, MS_U16 SysKeyIndex)
2840 {
2841
2842 #define Algoffset 100
2843 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_CfgCmChannel PidSlot = %x, LocalDAlgo = %x, ESAAlgo = %x, LocalSAlgo = %x, SysKeyIndex = %x\n",PidSlot, LocalDAlgo, ESAAlgo, LocalSAlgo, SysKeyIndex);
2844 StatusCheck(HAL_NSK2_CheckBusy());
2845 MS_U32 algorithms = 0, u32PidSlot = 0;
2846
2847 if(LocalDAlgo < Algoffset)
2848 LocalDAlgo = 0;
2849 else
2850 LocalDAlgo -= Algoffset;
2851
2852 if(ESAAlgo < Algoffset)
2853 ESAAlgo = 0;
2854 else
2855 ESAAlgo -= Algoffset;
2856
2857 if(LocalSAlgo < Algoffset)
2858 LocalSAlgo = 0;
2859 else
2860 LocalSAlgo -= Algoffset;
2861
2862 #if 0 //tmp solution...
2863 algorithms = ((LocalDAlgo - 100) & NI_KIW_LSAD_ALGO_MASK) +
2864 (((ESAAlgo - 100) << NI_KIW_ESA_ALGO_SHIFT) & NI_KIW_ESA_ALGO_MASK) +
2865 (((LocalSAlgo - 100) << NI_KIW_LSAS_ALGO_SHIFT) & NI_KIW_LSAS_ALGO_MASK) ;
2866 #else
2867 algorithms = (LocalDAlgo & NI_KIW_LSAD_ALGO_MASK) +
2868 ((ESAAlgo << NI_KIW_ESA_ALGO_SHIFT) & NI_KIW_ESA_ALGO_MASK) +
2869 ((LocalSAlgo << NI_KIW_LSAS_ALGO_SHIFT) & NI_KIW_LSAS_ALGO_MASK) ;
2870 #endif
2871
2872 HALNSK2_DBG(NSK2_DBGLV_INFO,"algorithms = %x\n",algorithms);
2873 NI_REG(REG_NI_DSCMB_ALGO) = algorithms;
2874
2875 u32PidSlot = (((MS_U32)PidSlot<<NI_WriteTKey_PidNo_Shift)&NI_WriteTransportKey_PidNo);
2876 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_ConfigureCmChannel | u32PidSlot);
2877 MsOS_DelayTaskUs(1);
2878 HALNSK2_DBG(NSK2_DBGLV_INFO,"REG_NI_DSCMB_ALGO = %x\n",NI_REG(REG_NI_DSCMB_ALGO));
2879
2880 return TRUE;
2881 }
2882
HAL_NSK21_WriteTransportKey(MS_U8 SCB,MS_U8 ForceSCB,void * pLocalDIV1,void * pLocalDIV2,void * pESAIV1,void * pESAIV2,void * pLocalSIV1,void * pLocalSIV2,MS_U16 PidSlot)2883 MS_U32 HAL_NSK21_WriteTransportKey(MS_U8 SCB, MS_U8 ForceSCB, void *pLocalDIV1, void *pLocalDIV2,
2884 void *pESAIV1, void *pESAIV2, void *pLocalSIV1, void *pLocalSIV2, MS_U16 PidSlot )
2885 {
2886 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK21_WriteTransportKey PidSlot = %x, SCB = %x, ForceSCB = %x\n", PidSlot, SCB, ForceSCB);
2887
2888 MS_U32 data,data2;
2889 //check NULL pointer or not....
2890
2891 StatusCheck(HAL_NSK2_CheckBusy());
2892
2893 data = NI_REG(REG_NI_KTE_STATUS);
2894 if( ( data & NI_KTE_DEST_MASK ) == 0 )
2895 {
2896
2897 ForceSCB = HAL_NSK2_SCBTransToHW(ForceSCB);
2898
2899 HALNSK2_DBG(NSK2_DBGLV_INFO,"PidSlot: %x\n", PidSlot);
2900 data2 = (((MS_U32)PidSlot<<NI_WriteTKey_PidNo_Shift)&NI_WriteTransportKey_PidNo) +
2901 (((MS_U32)SCB<<NI_WriteTKey_SCB_Shift) & NI_WriteTKey_SCB_MASK)
2902 + ( ( (MS_U32)ForceSCB<<NI_WriteTKey_FSCB_Shift) & NI_WriteTKey_FSCB_MASK) ;
2903
2904 #if 1
2905 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteTransportKey | data2 | NI_OTP_ACK_NSK2 | NI_ERR_INVALID_SLOT);
2906 #else
2907 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteTransportKey | data2);
2908 #endif
2909 HALNSK2_DBG(NSK2_DBGLV_INFO,"NI 6 = %x\n", NI_REG(REG_NI_COMMAND));
2910
2911 StatusCheck(HAL_NSK2_KIW_BusyPolling());
2912 }
2913 else
2914 {
2915 HALNSK2_DBG(NSK2_DBGLV_ERR,"WriteTransportKey abnormal ignored: KteDest not zero\n");
2916 return HAL_NSK2_ReadKTEResp();
2917 }
2918
2919 return HAL_NSK2_ReadKTEResp();
2920 }
2921
HAL_NSK21_WriteM2MKey(MS_U32 M2MAlgo)2922 MS_U32 HAL_NSK21_WriteM2MKey(MS_U32 M2MAlgo)
2923 {
2924 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s M2MAlgo = %x\n",__FUNCTION__,M2MAlgo);
2925
2926 MS_U32 algorithms;
2927
2928 StatusCheck(HAL_NSK2_CheckBusy());
2929
2930 algorithms = (M2MAlgo & NI_KIW_LSAD_ALGO_MASK) +
2931 ((M2MAlgo << NI_KIW_LSAS_ALGO_SHIFT) & NI_KIW_LSAS_ALGO_MASK) ;
2932
2933 HALNSK2_DBG(NSK2_DBGLV_INFO,"algorithms = %x\n",algorithms);
2934 NI_REG(REG_NI_DSCMB_ALGO) = algorithms;
2935 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteM2MKey);
2936
2937 MsOS_DelayTaskUs(1);
2938
2939 return HAL_NSK2_ReadKTEResp();
2940 }
2941
HAL_NSK21_ModifyGenIn(MS_U32 MaskVal,MS_U32 XorVal)2942 MS_U32 HAL_NSK21_ModifyGenIn(MS_U32 MaskVal,MS_U32 XorVal)
2943 {
2944 MS_U32 GenIn = 0, WriteGenIn = 0;
2945
2946 StatusCheck(HAL_NSK2_CheckBusy());
2947
2948 GenIn = NI_REG(REG_NI_NSK2_REG_GENIN);
2949
2950 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s GenIn = %x\n",__FUNCTION__,GenIn);
2951
2952 GenIn = (GenIn&MaskVal);
2953
2954 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s GenIn = %x, XorVal = %x\n",__FUNCTION__,GenIn,XorVal);
2955
2956 WriteGenIn = GenIn^XorVal;
2957 printf("WriteGenIn = %x\n",WriteGenIn);
2958
2959 #ifdef TestGenIn
2960 NI_REG(REG_NI_NSK21_GENIN) = WriteGenIn;
2961 MsOS_DelayTaskUs(10);
2962 #else
2963
2964 //NI_REG(REG_NI_NSK21_GENIN) = ( (WriteGenIn & BMASK(9:0)) | (WriteGenIn & __BIT(13)) );
2965 NI_REG(REG_NI_NSK21_GENIN) = WriteGenIn;
2966
2967 NI_REG(REG_NI_NSK21_CONCURR_PROT_EN) = ((WriteGenIn>>10) & BMASK(1:0));
2968 NI_REG(REG_NI_NSK21_CONCURR_SET) = ((WriteGenIn>>12) & BMASK(0:0));
2969 NI_REG(REG_NI_NSK21_GEN_SHOT) = ((WriteGenIn>>14) & BMASK(3:0));
2970
2971 MsOS_DelayTaskUs(10);
2972
2973 HALNSK2_DBG(NSK2_DBGLV_INFO,"CONCURR_PROT_EN = %x, CONCURR_SET = %x, GEN_SHOT = %x\n", NI_REG(REG_NI_NSK21_CONCURR_PROT_EN), NI_REG(REG_NI_NSK21_CONCURR_SET), NI_REG(REG_NI_NSK21_GEN_SHOT));
2974 #endif
2975 GenIn = NI_REG(REG_NI_NSK2_REG_GENIN);
2976
2977 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s GenIn = %x\n",__FUNCTION__,GenIn);
2978
2979 if(GenIn == WriteGenIn)
2980 return TRUE;
2981 else
2982 return FALSE;
2983
2984 }
2985
HAL_NSK21_GetGenIn(void)2986 MS_U32 HAL_NSK21_GetGenIn(void)
2987 {
2988 return NI_REG(REG_NI_NSK2_REG_GENIN);
2989 }
2990
HAL_NSK21_ReadNIReg(MS_U32 offset)2991 MS_U32 HAL_NSK21_ReadNIReg(MS_U32 offset)
2992 {
2993 return NI_REG(offset);
2994 }
2995
HAL_NSK21_WriteNIReg(MS_U32 offset,MS_U32 Value)2996 void HAL_NSK21_WriteNIReg(MS_U32 offset, MS_U32 Value)
2997 {
2998 NI_REG(offset) = Value;
2999 }
3000
HAL_NSK21_WriteJTagKey(MS_U32 OverrideOid,MS_U32 Select)3001 MS_U32 HAL_NSK21_WriteJTagKey(MS_U32 OverrideOid, MS_U32 Select)
3002 {
3003 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s OverrideOid = %x, Select = %x\n",__FUNCTION__,OverrideOid,Select);
3004
3005 MS_U32 functionality = 0, OID = 0;
3006
3007 StatusCheck(HAL_NSK2_CheckBusy());
3008
3009 if(OverrideOid>1) //invalid OverrideOid
3010 {
3011 HALNSK2_DBG(NSK2_DBGLV_ERR,"invalid OverrideOid\n");
3012 return FALSE;
3013 }
3014
3015 OID = (OverrideOid << NI_KIW_OID_SHIFT) & NI_KIW_OID_MASK ;
3016 #if 0
3017 functionality = (Select << NI_WriteTKey_PidNo_Shift) & NI_WriteTransportKey_PidNo ;
3018 #else
3019 functionality = 0; //N21_EJTAG_PWD
3020 #endif
3021
3022 HALNSK2_DBG(NSK2_DBGLV_INFO,"functionality = %x\n",functionality);
3023 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteJTAGKey | functionality | OID);
3024
3025 MsOS_DelayTaskUs(1);
3026
3027 return HAL_NSK2_ReadKTEResp();
3028 }
3029
HAL_NSK21_IncrementNvCounter(void)3030 MS_U32 HAL_NSK21_IncrementNvCounter(void)
3031 {
3032 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n",__FUNCTION__);
3033
3034 StatusCheck(HAL_NSK2_CheckBusy());
3035
3036 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_IncrementNvCounter);
3037 MsOS_DelayTaskUs(1);
3038
3039 return HAL_NSK2_ReadKTEResp();
3040 }
3041
HAL_NSK2_WriteOtpKey(void)3042 MS_U32 HAL_NSK2_WriteOtpKey(void)
3043 {
3044 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n",__FUNCTION__);
3045 StatusCheck(HAL_NSK2_CheckBusy());
3046
3047 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteOTPKey);
3048 MsOS_DelayTask(10);
3049
3050 return HAL_NSK2_ReadKTEResp();
3051 }
3052
HAL_NSK2_ReadPWD_Status(void)3053 MS_U32 HAL_NSK2_ReadPWD_Status(void)
3054 {
3055 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n",__FUNCTION__);
3056 StatusCheck(HAL_NSK2_CheckBusy());
3057 MS_U32 RegPwd;
3058
3059 RegPwd = NI_REG(REG_NI_NSK2_PWD_ON);
3060
3061 if(RegPwd & N2_JTAGPWD0_ON)
3062 {
3063 printf("JTAG PWD0 ON \n");
3064 }
3065
3066 if(RegPwd & N2_JTAGPWD1_ON)
3067 {
3068 printf("JTAG PWD1 ON \n");
3069 }
3070
3071 if(RegPwd & N2_SCANPWD_ON)
3072 {
3073 printf("SCAN PWD ON \n");
3074 }
3075
3076 if(RegPwd & N2_MBISTPWD_ON)
3077 {
3078 printf("MBIST PWD ON \n");
3079 }
3080
3081 if(RegPwd & N2_M2MKEY_ON)
3082 {
3083 printf("M2M KEY ON \n");
3084 }
3085
3086 if(RegPwd & N2_SCPUKEY0_ON)
3087 {
3088 printf("SCPU KEY0 ON \n");
3089 }
3090
3091 if(RegPwd & N2_SCPUKEY1_ON)
3092 {
3093 printf("SCPU KEY1 ON \n");
3094 }
3095
3096 if(RegPwd & N2_RNGVALUE0_ON)
3097 {
3098 printf("RNG VALUE0 ON \n");
3099 }
3100
3101 if(RegPwd & N2_RNGVALUE1_ON)
3102 {
3103 printf("RNG VALUE1 ON \n");
3104 }
3105
3106 return TRUE;
3107 }
3108
HAL_NSK2_CtrlClk(MS_BOOL Enable)3109 MS_U32 HAL_NSK2_CtrlClk(MS_BOOL Enable)
3110 {
3111 if(Enable)
3112 {
3113 printf("enable NSK clock\n");
3114 NI_REG(REG_NI_NSK2_CTRL) |= (NI_NSK2_CLK_ENABLE | NI_NSK2_RESET_DISABLE);
3115 HAL_NSK2_ColdReset();
3116 }
3117 else
3118 {
3119 printf("disable NSK clock\n");
3120 NI_REG(REG_NI_NSK2_CTRL) &= ~(NI_NSK2_CLK_ENABLE | NI_NSK2_RESET_DISABLE);
3121 _gReset = FALSE;
3122 _gCheckBusyFlag = FALSE;
3123 }
3124
3125 MsOS_DelayTask(1);
3126
3127
3128 printf("REG_NI_NSK2_CTRL = %x\n",NI_REG(REG_NI_NSK2_CTRL));
3129 return TRUE;
3130 }
3131
HAL_NSK2_ReadClkStatus(void)3132 MS_U32 HAL_NSK2_ReadClkStatus(void)
3133 {
3134 MS_U32 status;
3135 MS_U32 rom[4];
3136
3137 status = (NI_REG(REG_NI_KTE_STATUS)& NI_SLOW_CLOCK_DETECT);
3138
3139 printf("REG_NI_KTE_STATUS = %x\n",NI_REG(REG_NI_KTE_STATUS));
3140 printf("NI_SLOW_CLOCK_DETECT = %x\n", (status>>5));
3141
3142 if(status)
3143 {
3144 printf("no clock for NSK\n");
3145 }
3146 else
3147 {
3148 printf("clock is alive for NSK\n");
3149 }
3150
3151 printf("read NSK ROM value\n");
3152 HAL_NSK2_ReadData32(0x8000, 4, &rom[0]);
3153
3154 printf("%x, %x, %x, %x,\n",rom[0],rom[1],rom[2],rom[3]);
3155
3156 return TRUE;
3157 }
3158
3159 //<MStar Software>
3160