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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file drvDscmb.h 98 /// @brief Descrambler (Dscmb) Driver Interface 99 /// @author MStar Semiconductor,Inc. 100 /// @attention 101 //////////////////////////////////////////////////////////////////////////////////////////////////// 102 103 #ifndef __HAL_DSCMB_H__ 104 #define __HAL_DSCMB_H__ 105 106 #define DSCMB2_DBGLV_EMERG 0 //Used for emergency messages, usually those that precede a crash. 107 #define DSCMB2_DBGLV_ALERT 1 //A situation requiring immediate action. 108 #define DSCMB2_DBGLV_CRIT 2 //Critical conditions, often related to serious hardware or software failures. 109 #define DSCMB2_DBGLV_ERR 3 //Used to report error conditions; device drivers often use KERN_ERR to report hardware difficulties. 110 #define DSCMB2_DBGLV_WARNING 4 //Warnings about problematic situations that do not, in themselves, create serious problems with the system. 111 #define DSCMB2_DBGLV_NOTICE 5 //Situations that are normal, but still worthy of note. A number of security-related conditions are reported at this level. 112 #define DSCMB2_DBGLV_INFO 6 //Informational messages. Many drivers print information about the hardware they find at startup time at this level. 113 #define DSCMB2_DBGLV_DEBUG 7 //Used for debugging messages. 114 #define DSCMB2_DBGLV_ARRAY 8 //Uesd for array data. 115 116 117 #define NDS_IMPL // tag for reconstructure the code 118 119 #define HAL_DSCMB_FLT_NULL 0xFFFFFFFFUL 120 #define PID_SLOT_INDEX_NULL 0x7FUL 121 122 //HAL_DSCMB_KTE_GetStatus(), for debug usage 123 #define DSCMB_PIDIDX_EN 0x80000000UL 124 #define DSCMB_KTE_VALID 0x40000000UL 125 #define DSCMB_KTE_DUAL_EN 0x10000000UL 126 #define DSCMB_KTE_LSAS_EN 0x00000001UL 127 #define DSCMB_KTE_ESA_EN 0x00000100UL 128 #define DSCMB_KTE_LSAD_EN 0x00010000UL 129 #define DSCMB_KTE_IV_EN 0x01000000UL 130 131 #define HAL_DSCMB_RIV_MAX 16UL //max number of RIV slot 132 133 #define HAL_DSCMB_KTE_MAX 128UL // 0 ~ 127 and 127 is reserved for NULL key 134 #define HAL_DSCMB_KTE_ID_NULL 127UL 135 #define HAL_DSCMB_PIDIDX_MAX 192UL 136 #define HAL_DSCMB_PIDFLT_NUM 192UL 137 #define HAL_DSCMB_TSIF_MAX 4UL 138 #define HAL_DSCMB_TSID_MAX 4UL 139 #define HAL_DSCMB_ENG_MAX 1UL 140 #define REG_DSCMB_PATH_CNT HAL_DSCMB_TSID_MAX 141 142 #define HAL_DSCMB_ENG_NUM 1UL 143 144 #define HAL_DSCMB_KEY_TYPE_CLEAR 0UL 145 #define HAL_DSCMB_KEY_TYPE_EVEN 2UL 146 #define HAL_DSCMB_KEY_TYPE_ODD 3UL 147 148 #define HAL_DSCMB_KEYLEN_MAX 16UL 149 #define HAL_DSCMB_MULTI2_SYSKEY_MAX 32UL 150 151 #define HAL_DSCMB_ES_STATICKEY_MAX 16UL 152 153 #define HAL_DSCMB_SPSPVR_ENG_NUM 1UL //only one spspvr filter in dscmb(32 filter pid) 154 #define HAL_DSCMB_SPSPVR_FLT_NUM 32UL 155 //#define HAL_DSCMB_SPSPVR_BUF_NUM 1 156 157 #define DSCMB_CAPVR_PIDTABLE_NUM (2UL) 158 #define DSCMB_CAPVR_PIDFLT_MAX (HAL_DSCMB_SPSPVR_FLT_NUM*DSCMB_CAPVR_PIDTABLE_NUM) 159 160 #define DEFAULT_CAVID (0x0FUL) 161 162 #define DSCMB_CWKL (0UL) 163 #define DSCMB_PVRKL (1UL) 164 165 #define DSCMB_KL_DST_CLASS_CPU (0x80UL) 166 #define DSCMB_KL_DST_CLASS_TSIO (0x800UL) 167 #define DSCMB_KL_DST_CLASS_KT (0x8000UL) 168 #define DSCMB_KL_DST_CLASS_DMA (0x800000UL) 169 #define DSCMB_KL_DST_CLASS_SPSSPD (0x880000UL) 170 #define DSCMB_KL_DST_CLASS_PVT (0x80000000UL) 171 172 //Tmp define here, need to put drvDSCMB.h in the future 173 #define E_DSCMB_KL_DST_DMA_CSSK 0x00900000UL 174 175 typedef enum 176 { 177 E_HAL_DSCMB_CAVID1 = 0x0001, 178 E_HAL_DSCMB_CAVID2 = 0x0002, 179 E_HAL_DSCMB_CAVID3 = 0x0003, 180 E_HAL_DSCMB_CAVID4 = 0x0004, 181 E_HAL_DSCMB_CAVID5 = 0x0005, 182 E_HAL_DSCMB_CAVID6 = 0x0006, 183 E_HAL_DSCMB_CAVID7 = 0x0007, 184 E_HAL_DSCMB_CAVID8 = 0x0008, 185 E_HAL_DSCMB_CAVIDF = 0x000F, 186 } HAL_DSCMB_CAVID; 187 188 typedef enum 189 { 190 E_HAL_DSCMB_MAIN_ALGO_AES = 0, 191 E_HAL_DSCMB_MAIN_ALGO_CSA2 = 1, 192 E_HAL_DSCMB_MAIN_ALGO_DES = 2, 193 E_HAL_DSCMB_MAIN_ALGO_TDES = 3, 194 E_HAL_DSCMB_MAIN_ALGO_MULTI2 = 4, 195 E_HAL_DSCMB_MAIN_ALGO_CSA2_CONF =5, 196 E_HAL_DSCMB_MAIN_ALGO_CSA3 = 6, 197 E_HAL_DSCMB_MAIN_ALGO_ASA = 7, 198 E_HAL_DSCMB_MAIN_ALGO_TCSA3 = 8, 199 E_HAL_DSCMB_MAIN_ALGO_DEFAULT = 0xF, 200 E_HAL_DSCMB_MAIN_ALGO_NUM, 201 } HAL_DSCMB_MainAlgo_Type; 202 203 typedef enum 204 { 205 E_HAL_DSCMB_SUB_ALGO_MDI_CBC = 0, 206 E_HAL_DSCMB_SUB_ALGO_MDI_RCBC = 1, 207 E_HAL_DSCMB_SUB_ALGO_MDD_CBC = 2 , 208 E_HAL_DSCMB_SUB_ALGO_MDD_RCBC = 3, 209 E_HAL_DSCMB_SUB_ALGO_LEADING_CLEAR = 4, 210 E_HAL_DSCMB_SUB_ALGO_ECB = 5, 211 E_HAL_DSCMB_SUB_ALGO_CBC = 6, 212 E_HAL_DSCMB_SUB_ALGO_CTR = 7, 213 E_HAL_DSCMB_SUB_ALGO_OFB = 8, 214 E_HAL_DSCMB_SUB_ALGO_AESVAR = 9 , 215 E_HAL_DSCMB_SUB_ALGO_DEFAULT = 0xF, 216 E_HAL_DSCMB_SUB_ALGO_NUM, 217 } HAL_DSCMB_SubAlgo_Type; 218 219 220 typedef enum 221 { 222 E_HAL_DSCMB_RESSB_ALGO_CLR = 0, 223 E_HAL_DSCMB_RESSB_ALGO_CTS = 1, 224 E_HAL_DSCMB_RESSB_ALGO_SCTE52 = 2, 225 E_HAL_DSCMB_RESSB_ALGO_XORIV1 = 3, 226 E_HAL_DSCMB_RESSB_ALGO_OC_M = 4, 227 E_HAL_DSCMB_RESSB_ALGO_XORIV2 = 5, 228 E_HAL_DSCMB_RESSB_ALGO_CTR = 6, 229 E_HAL_DSCMB_RESSB_ALGO_DEFAULT = 0x7, 230 E_HAL_DSCMB_RESSB_ALGO_NUM, 231 } HAL_DSCMB_ResSBAlgo_Type; 232 233 234 typedef enum 235 { 236 E_HAL_DSCMB_ENG_LSAD = 0 , 237 E_HAL_DSCMB_ENG_ESA = 1 , 238 E_HAL_DSCMB_ENG_LSAS = 2 , 239 E_HAL_DSCMB_ENG_SWITCH = 3 , 240 E_HAL_DSCMB_ENG_IV_LSAD = 4, 241 E_HAL_DSCMB_ENG_IV_ESA = 5 , 242 E_HAL_DSCMB_ENG_IV_LSAS = 6 , 243 E_HAL_DSCMB_ENG_NUM, 244 } HAL_DSCMB_KTE_WriteType; 245 246 247 // descrambler key ladder 248 typedef enum 249 { 250 E_HAL_DSCMB_KEY_CLEAR = 0, 251 E_HAL_DSCMB_KEY_UNDEFINE = 1, 252 E_HAL_DSCMB_KEY_EVEN = 2, 253 E_HAL_DSCMB_KEY_ODD = 3, 254 } HAL_DSCMB_KeyType; 255 256 typedef enum 257 { 258 E_HAL_DSCMB_FSCB_UNCHG = 0, 259 E_HAL_DSCMB_FSCB_B00 = 1, 260 E_HAL_DSCMB_FSCB_B10 = 2, 261 E_HAL_DSCMB_FSCB_B11 = 3, 262 } HAL_DSCMB_FSCB; 263 264 265 typedef enum 266 { 267 E_HAL_DSCMB_SCBFIX_UNCHG = 0, 268 E_HAL_DSCMB_SCBFIX_USESCB = 1, 269 E_HAL_DSCMB_SCBFIX_CLEAR = 2, 270 271 E_HAL_DSCMB_SCBFIX_ODD2EVEN = 4, 272 E_HAL_DSCMB_SCBFIX_EVEN2ODD = 5, 273 274 E_HAL_DSCMB_SCBFIX_ODD2CLEAR = 6, 275 E_HAL_DSCMB_SCBFIX_EVEN2CLEAR = 7, 276 277 } HAL_DSCMB_SCBFix; 278 279 280 typedef enum 281 { 282 E_HAL_DSCMB_SCBFIX_LSAD = 0, 283 E_HAL_DSCMB_SCBFIX_ESA = 1, 284 E_HAL_DSCMB_SCBFIX_LSAS = 2, 285 E_HAL_DSCMB_SCBFIX_DMXU = 3, 286 E_HAL_DSCMB_SCBFIX_DMXL = 4, 287 } HAL_DSCMB_SCBFix_EngSel; 288 289 290 291 typedef enum 292 { 293 E_HAL_DSCMB_CIPHER_OUTPUT_SPS0 = 0 , 294 E_HAL_DSCMB_CIPHER_OUTPUT_SPS1 = 1 , 295 E_HAL_DSCMB_CIPHER_OUTPUT_SPS2 = 2 , 296 E_HAL_DSCMB_CIPHER_OUTPUT_SPS3 = 3 , 297 E_HAL_DSCMB_CIPHER_OUTPUT_CLR0 = 4 , 298 E_HAL_DSCMB_CIPHER_OUTPUT_CLR1 = 5 , 299 E_HAL_DSCMB_CIPHER_OUTPUT_CLR2 = 6 , 300 E_HAL_DSCMB_CIPHER_OUTPUT_CLR3 = 7 , 301 E_HAL_DSCMB_CIPHER_OUTPUT_CLR4 = 8 , 302 E_HAL_DSCMB_CIPHER_OUTPUT_CLR5 = 9 , 303 E_HAL_DSCMB_CIPHER_OUTPUT_TSO0 = 10 , 304 E_HAL_DSCMB_CIPHER_OUTPUT_TSO1 = 11 , 305 306 } HAL_DSCMB_OutPut_Eng_Sel; 307 308 309 typedef enum 310 { 311 E_HAL_DSCMB_PARSER_CNT = 0, 312 E_HAL_DSCMB_PARSER_EVENT = 1, 313 E_HAL_DSCMB_PARSER_SCB = 2, 314 E_HAL_DSCMB_PARSER_BADPKT = 3, 315 E_HAL_DSCMB_PARSER_2NDHIT = 4, 316 E_HAL_DSCMB_PARSER_ESA = 5, 317 E_HAL_DSCMB_PARSER_LSA = 6, 318 E_HAL_DSCMB_PARSER_INFO = 7, 319 } HAL_DSCMB_PktParser_Mode; 320 321 322 //--------------------------- 323 // KL enumerate 324 //--------------------------- 325 typedef enum 326 { 327 E_HAL_DSCMB_KL_DST_KT = 0x0, 328 E_HAL_DSCMB_KL_DST_DMA = 0x1, 329 E_HAL_DSCMB_KL_DST_CSSK = 0x1, 330 E_HAL_DSCMB_KL_DST_ACPU = 0x4, 331 E_HAL_DSCMB_KL_DST_SCPU = 0x5, 332 E_HAL_DSCMB_KL_DST_PRI0 = 0x8, 333 E_HAL_DSCMB_KL_DST_PRI1 = 0x9, 334 E_HAL_DSCMB_KL_DST_PRI2 = 0xA, 335 E_HAL_DSCMB_KL_DST_PRI3 = 0xB, 336 337 } HAL_DSCMB_KL_Dst; 338 339 typedef enum 340 { 341 E_HAL_DSCMB_KL_DSTDMA_NA = 0x0 , 342 E_HAL_DSCMB_KL_DSTDMA_SK0 = 0x0 , 343 E_HAL_DSCMB_KL_DSTDMA_SK1 = 0x1 , 344 E_HAL_DSCMB_KL_DSTDMA_SK2 = 0x2 , 345 E_HAL_DSCMB_KL_DSTDMA_SK3 = 0x3 , 346 347 E_HAL_DSCMB_KL_DSTDMA_SPS0 = 0xf , 348 E_HAL_DSCMB_KL_DSTDMA_SPS1 = 0xf , 349 E_HAL_DSCMB_KL_DSTDMA_SPS2 = 0xf , 350 E_HAL_DSCMB_KL_DSTDMA_SPS3 = 0xf , 351 352 E_HAL_DSCMB_KL_DSTDMA_SPD0 = 0xf , //PVR 353 E_HAL_DSCMB_KL_DSTDMA_SPD1 = 0xf , //PVR 354 E_HAL_DSCMB_KL_DSTDMA_SPD2 = 0xf , //PVR 355 E_HAL_DSCMB_KL_DSTDMA_SPD3 = 0xf , //PVR 356 E_HAL_DSCMB_KL_DSTDMA_SPD4 = 0xf , //PVR 357 E_HAL_DSCMB_KL_DSTDMA_SPD5 = 0xf , //PVR 358 E_HAL_DSCMB_KL_DSTDMA_CSSK = 0xf , //CW 359 } HAL_DSCMB_KL_DstDma; 360 361 typedef enum 362 { 363 E_HAL_DSCMB_KL_DST_SP_NA = 0x0 , 364 E_HAL_DSCMB_KL_DST_SP_SPS0 = 0x4 , 365 E_HAL_DSCMB_KL_DST_SP_SPS1 = 0x5 , 366 E_HAL_DSCMB_KL_DST_SP_SPS2 = 0x6 , 367 E_HAL_DSCMB_KL_DST_SP_SPS3 = 0x7 , 368 E_HAL_DSCMB_KL_DST_SP_SPD0 = 0xC , 369 E_HAL_DSCMB_KL_DST_SP_SPD1 = 0xD , 370 E_HAL_DSCMB_KL_DST_SP_SPD2 = 0x8 , 371 E_HAL_DSCMB_KL_DST_SP_SPD3 = 0x9 , 372 E_HAL_DSCMB_KL_DST_SP_SPD4 = 0xA , 373 E_HAL_DSCMB_KL_DST_SP_SPD5 = 0xB , 374 } HAL_DSCMB_KL_DstSP; 375 376 typedef enum 377 { 378 E_HAL_DSCMB_KL_DSTKT_LSAD = 0x0 , 379 E_HAL_DSCMB_KL_DSTKT_ESA = 0x1 , 380 E_HAL_DSCMB_KL_DSTKT_LSAS = 0x2 , 381 } HAL_DSCMB_KL_DstKT; 382 383 384 typedef enum 385 { 386 E_HAL_DSCMB_KL_SRC_ACPU = 0, 387 E_HAL_DSCMB_KL_SRC_SK1 = 1, 388 E_HAL_DSCMB_KL_SRC_SK2 = 2, 389 E_HAL_DSCMB_KL_SRC_SK3 = 3, 390 E_HAL_DSCMB_KL_SRC_SK4 = 4, 391 E_HAL_DSCMB_KL_SRC_SK5 = 5, 392 E_HAL_DSCMB_KL_SRC_SK6 = 6, 393 E_HAL_DSCMB_KL_SRC_SK7 = 7, 394 E_HAL_DSCMB_KL_SRC_SK8 = 8, 395 E_HAL_DSCMB_KL_SRC_SK9 = 9, 396 E_HAL_DSCMB_KL_SRC_SK10 = 10, 397 E_HAL_DSCMB_KL_SRC_SK11 = 11, 398 E_HAL_DSCMB_KL_SRC_SK12 = 12, 399 E_HAL_DSCMB_KL_SRC_SK13 = 13, 400 E_HAL_DSCMB_KL_SRC_SK14 = 14, 401 E_HAL_DSCMB_KL_SRC_SK15 = 15, 402 403 } HAL_DSCMB_KL_Src; 404 405 typedef enum 406 { 407 E_HAL_DSCMB_KL_TYPE_0 = 0x0, 408 E_HAL_DSCMB_KL_TYPE_1 = 0x1, 409 E_HAL_DSCMB_KL_TYPE_2 = 0x2, 410 E_HAL_DSCMB_KL_TYPE_3 = 0x3, 411 E_HAL_DSCMB_KL_TYPE_4 = 0x4, 412 E_HAL_DSCMB_KL_TYPE_5 = 0x5, 413 E_HAL_DSCMB_KL_TYPE_1_KPR =0x9, 414 E_HAL_DSCMB_KL_TYPE_1_2 =0xA, 415 E_HAL_DSCMB_KL_TYPE_1_3 =0xB, 416 E_HAL_DSCMB_KL_TYPE_5_SMI =0xD, 417 E_HAL_DSCMB_KL_TYPE_LUT =0xF, 418 E_HAL_DSCMB_KL_TYPE_INVALID, 419 } HAL_DSCMB_KL_Type; 420 421 422 typedef enum 423 { 424 E_HAL_DSCMB_KL_ALGO_TDES = 0, 425 E_HAL_DSCMB_KL_ALGO_AES = 1, 426 } HAL_DSCMB_KL_Algo; 427 428 typedef struct 429 { 430 MS_U32 u32LUT; //LUT3 fill in 512 bytes table, each has 9 bits to describe 431 MS_U32 u32M; 432 MS_U32 u32BC; 433 } DSCMB_KL_TA_LUT3; 434 435 typedef enum 436 { 437 E_HAL_DSCMB_KL_ERR_MSG_KDF, 438 E_HAL_DSCMB_KL_ERR_MSG_KL, 439 E_HAL_DSCMB_KL_ERR_MSG_AES, 440 E_HAL_DSCMB_KL_ERR_MSG_TDES, 441 E_HAL_DSCMB_KL_ERR_MSG_LSA, 442 E_HAL_DSCMB_KL_ERR_MSG_ESA, 443 E_HAL_DSCMB_KL_ERR_MSG_DMA, 444 E_HAL_DSCMB_KL_ERR_MSG_NONCE, 445 E_HAL_DSCMB_KL_ERR_MSG_UACPU, 446 E_HAL_DSCMB_KL_ERR_MSG_SEP, 447 E_HAL_DSCMB_KL_ERR_MSG_LUT, 448 E_HAL_DSCMB_KL_ERR_MSG_TYPE, 449 E_HAL_DSCMB_KL_ERR_MSG_PRV, 450 E_HAL_DSCMB_KL_ERR_MSG_HK, 451 E_HAL_DSCMB_KL_ERR_MSG_DACPU, 452 E_HAL_DSCMB_KL_ERR_MSG_BADRK, 453 E_HAL_DSCMB_KL_ERR_MSG_ILUT, 454 E_HAL_DSCMB_KL_ERR_MSG_RSV1, 455 E_HAL_DSCMB_KL_ERR_MSG_KLTYPE, 456 E_HAL_DSCMB_KL_ERR_MSG_ZERO, 457 E_HAL_DSCMB_KL_ERR_MSG_RSV2, 458 E_HAL_DSCMB_KL_ERR_MSG_RSV3, 459 E_HAL_DSCMB_KL_ERR_MSG_KCV, 460 E_HAL_DSCMB_KL_ERR_MSG_BADIK, 461 462 }HAL_DSCMB_KL_Err_Msg; 463 464 465 //--------------------------- 466 // enumerate 467 //--------------------------- 468 //ts_if 469 typedef enum 470 { 471 E_HAL_DSCMB_TSIF0 = 0, 472 E_HAL_DSCMB_TSIF1 = 1, 473 E_HAL_DSCMB_TSIF2 = 2, 474 E_HAL_DSCMB_TSIF3 = 3, 475 E_HAL_DSCMB_TSIF_NUM, 476 } HAL_DSCMB_TSIF; 477 478 //pktDmx 479 typedef enum 480 { 481 E_HAL_DSCMB_TSID0 = 0, 482 E_HAL_DSCMB_TSID1 = 1, 483 E_HAL_DSCMB_TSID2 = 2, 484 E_HAL_DSCMB_TSID3 = 3, 485 E_HAL_DSCMB_TSID_NUM, 486 } HAL_DSCMB_TSID; 487 488 typedef enum 489 { 490 E_HAL_DSCMB_CHANNEL0 = 0, 491 E_HAL_DSCMB_CHANNEL_NUM, 492 } HAL_DSCMB_CHANNEL; 493 494 typedef enum 495 { 496 E_HAL_DSCMB_SPSPVR_NUM, 497 } HAL_DSCMB_SPSPVR; 498 499 500 typedef struct 501 { 502 //for read: 503 MS_U32 ClrSlotIndex : 7; //bit[6:0] clr slot index 504 MS_U32 PktViewDbgInfo : 1; //bit[7] 505 MS_U32 OddSlotIndex : 7; //bit[14:8] odd slot index 506 MS_U32 PidSlotEn : 1; //bit[15] 507 MS_U32 EvenSlotIndex : 7; //bit[22:16] even slot index 508 MS_U32 DualSloEn : 1; //bit[23] dualpath_en 509 MS_U32 ClrSloEn : 1; //bit[24] clr slot enable 510 MS_U32 OddSloEn : 1; //bit[25] odd slot enable 511 MS_U32 EvenSloEn : 1; //bit[26] even slot enable 512 MS_U32 CA_VID : 5; //bit[31:27] cavid 513 } PidSlotMapRead_t; 514 515 516 typedef struct 517 { 518 519 MS_U32 ForceSCB : 2; //bit[1:0] 520 MS_U32 NDS_AES_MODE_PI : 1; 521 MS_U32 NDS_AES_MODE_EN : 1; 522 MS_U32 Reg2_reserve_4_7 : 4; 523 MS_U32 IuputSrc : 8; 524 MS_U32 LowDest : 8; 525 MS_U32 UppDest : 8; 526 527 MS_U32 ESA_Decrypt : 1; 528 MS_U32 Reg3_reserve_1_11 : 11; 529 MS_U32 ESA_SB : 3; 530 MS_U32 Reg3_reserve_15 : 1; 531 MS_U32 ESA_RES : 3; 532 MS_U32 Reg3_reserve_19 : 1; 533 MS_U32 ESA_SubAlgo : 4; 534 MS_U32 ESA_MainAlgo : 4; 535 MS_U32 Reg3_reserve_28_31 : 4; 536 537 MS_U32 LSAS_Decrypt : 1; 538 MS_U32 Reg4_reserve_1_11 : 11; 539 MS_U32 LSAS_SB : 3; 540 MS_U32 Reg4_reserve_15 : 1; 541 MS_U32 LSAS_RES : 3; 542 MS_U32 Reg4_reserve_19 : 1; 543 MS_U32 LSAS_SubAlgo : 4; 544 MS_U32 LSAS_MainAlgo : 4; 545 MS_U32 Reg4_reserve_28_31 : 4; 546 547 MS_U32 LSAD_Decrypt : 1; 548 MS_U32 Reg5_reserve_1_11 : 11; 549 MS_U32 LSAD_SB : 3; 550 MS_U32 Reg5_reserve_15 : 1; 551 MS_U32 LSAD_RES : 3; 552 MS_U32 Reg5_reserve_19 : 1; 553 MS_U32 LSAD_SubAlgo : 4; 554 MS_U32 LSAD_MainAlgo : 4; 555 MS_U32 Reg5_reserve_28_31 : 4; 556 557 MS_U32 Low_Switch : 4; 558 MS_U32 Upp_Switch : 4; 559 MS_U32 DVBCSA_Var : 5; 560 MS_U32 Reg6_reserve_13_14 : 2; 561 MS_U32 ModifyXrc : 1; 562 MS_U32 Permutation : 3; 563 MS_U32 CAVid : 5; 564 MS_U32 RegCnt : 8; 565 566 } SwitchReg_Map_t; 567 568 typedef struct 569 { 570 #define ErrStatusMak 0x1FFFFFFF 571 MS_U32 Key_KDF_KeyForbidden : 1; 572 MS_U32 Key_KL_KeyForbidden : 1; 573 MS_U32 Key_AES_KeyForbidden : 1; 574 MS_U32 Key_TDES_KeyForbidden : 1; 575 MS_U32 Key_LSA_KeyForbidden : 1; 576 MS_U32 Key_ESA_KeyForbidden : 1; 577 MS_U32 Key_DMA_KeyForbidden : 1; 578 MS_U32 Key_HMAC_KeyForbidden : 1; 579 MS_U32 Key_ACPU_KeyForbidden : 1; 580 MS_U32 Key_SEP_KeyForbidden : 1; 581 MS_U32 Key_LUT_KeyForbidden : 1; 582 MS_U32 Key_Type_KeyForbidden : 1; 583 MS_U32 Key_PrivateKey_KeyForbidden : 1; 584 MS_U32 Key_SW_KeyForbidden : 1; 585 MS_U32 Key_Reserve : 1; 586 MS_U32 Key_BadRootKey : 1; 587 588 MS_U32 KL_LUT_NotInit : 1; 589 MS_U32 KL_LUT_GenWithoutSWReset : 1; 590 MS_U32 KL_NotSupportKLType : 1; 591 MS_U32 KL_ZeroOrder : 1; 592 MS_U32 KL_Reserve : 2; 593 MS_U32 KL_LUT0_Err : 1; 594 MS_U32 KL_BadInternalKey : 1; 595 596 MS_U32 KeyBus_Resp : 5; 597 #define KeyBusRespMsk 0x1F 598 #define KeyBusRespOK 0x0 599 #define KeyBusNoSlot 0x1F 600 #define KeyBusNotAllowToWriteKey 0x19 601 #define KeyBusAllOneOrZeroKey 0x10 602 603 MS_U32 KeyBus_Done : 1; 604 605 MS_U32 Biss_AllowWriteKey : 1; 606 MS_U32 Biss_WriteKeyError : 1; 607 608 }KL_RegErrFlag_t; 609 610 611 #if 1 //put here temp, when sps/spd read, and want to open api, put these to drvDSCMB.h 612 typedef struct 613 { 614 MS_U32 pPvrBuf0; ///< DMX PVR buffer 0 starting address 615 MS_U32 pPvrBuf1; ///< DMX PVR buffer 1 starting address 616 MS_U32 u32PvrBufSize0; ///< DMX PVR buffer 0 size 617 MS_U32 u32PvrBufSize1; ///< DMX PVR buffer 1 size 618 MS_U32 u32ChannelEngId; 619 MS_BOOL bEncrypt; 620 } DSCMB_SPSPVR_Info; 621 622 623 typedef enum 624 { 625 E_DSCMB_SPSPVR_ENG0 = 0 , 626 E_DSCMB_SPSPVR_ENG1 = 1 , 627 E_DSCMB_SPSPVR_ENG2 = 2 , 628 E_DSCMB_SPSPVR_ENG3 = 3 , 629 E_DSCMB_SPSPVR_ENG_NUM, 630 } DSCMB_SPSPVR_ENG; 631 632 #endif 633 634 typedef enum 635 { 636 // descrambler engine 637 E_HAL_DSCMB_CAP_ENGINE_NUM, 638 // descrambler slot 639 E_HAL_DSCMB_CAP_FLT_NUM, 640 // descrambler type supported 641 E_HAL_DSCMB_CAP_SUPPORT_ALGORITHM, 642 // descrambler mapping, start tsp pid filter 643 E_HAL_DSCMB_CAP_PIDFILTER_MAP_START, 644 // descrambler mapping, end tsp pid filter 645 E_HAL_DSCMB_CAP_PIDFILTER_MAP_END, 646 // share key slot max number 647 E_HAL_DSCMB_CAP_SHARE_KEY_SLOT_NUM, 648 // share key slot max number 649 E_HAL_DSCMB_CAP_SHARE_KEY_SLOT_MAX_NUM, 650 // share key region number 651 E_HAL_DSCMB_CAP_SHARE_KEY_REGION_NUM, 652 // share key region start 653 E_HAL_DSCMB_CAP_SHARE_KEY_REGION_START, 654 // share key region end 655 E_HAL_DSCMB_CAP_SHARE_KEY_REGION_END, 656 } HAL_DSCMB_Query_Type; 657 658 659 //-------------------------------------------------------------------------- 660 // function Declaration 661 //-------------------------------------------------------------------------- 662 MS_BOOL HAL_DSCMB_SetBank(MS_VIRT u32Bank); 663 MS_BOOL HAL_DSCMB_GetBank(MS_VIRT * u32Bank); 664 MS_BOOL HAL_DSCMB_Init(void); 665 MS_BOOL HAL_DSCMB_OTPEnDSCMB(void); 666 MS_BOOL HAL_DSCMB_SetCAVid(MS_U32 u32CAVid); 667 MS_U32 HAL_DSCMB_GetCAVid(void); 668 MS_BOOL HAL_DSCMB_GetCap(MS_U32 u32EngId, HAL_DSCMB_Query_Type eQueryType, void* pInData, void* pOutData); 669 670 void HAL_DSCMB_ReadPidSlotMap(MS_U32 u32FltId,PidSlotMapRead_t *pReadData); 671 MS_BOOL HAL_DSCMB_CC_Respin(MS_U32 u32CHNum, MS_U32 u32Tsid, MS_BOOL bEnable); 672 673 void HAL_DSCMB_SetDBGLevel(MS_U32 u32Level); 674 675 676 ////////////////////////////////////// 677 ////// //// 678 ////// PidSlotMap Control function /// 679 ////// //// 680 ////////////////////////////////////// 681 MS_BOOL HAL_DSCMB_PidIdx_SetCAVid(MS_U32 u32fltid , MS_U32 u32CAVid ); 682 MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 683 MS_BOOL HAL_DSCMB_PidIdx_SetSlotKeyIdx(MS_U32 u32FltId,DSCMB_Key_Type key, MS_U32 keyIdx); 684 MS_BOOL HAL_DSCMB_PidIdx_ClearSlotKeyIdx(MS_U32 u32FltId,DSCMB_Key_Type key); 685 MS_BOOL HAL_DSCMB_PidIdx_EnableSlot(MS_U32 u32FltId); 686 MS_BOOL HAL_DSCMB_PidIdx_DisableSlot(MS_U32 u32FltId); 687 MS_BOOL HAL_DSCMB_PidIdx_DualPath(MS_U32 u32fltid , MS_BOOL bDual ); 688 MS_BOOL HAL_DSCMB_PidIdx_Enable(MS_U32 u32fltid , MS_BOOL bEnable); 689 MS_BOOL HAL_DSCMB_PidIdx_SetSecure(MS_U32 u32fltid , MS_BOOL bSecure); 690 691 692 //////////////////////////////////////////// 693 ////// //// 694 ////// Slot Control function (Key & Switch) /// 695 ////// //// 696 ///////////////////////////////////////////// 697 698 // Key-specific FSCB 699 #define ENABLE_KEY_FSCB 700 #ifdef ENABLE_KEY_FSCB 701 void HAL_DSCMB_KTE_Clear_KeyFSCB(MS_U32 u32fltid); 702 void HAL_DSCMB_KTE_Copy_KeyFSCB(MS_U32 u32fltid_Src, MS_U32 u32fltid_Dst); 703 MS_BOOL HAL_DSCMB_KTE_Write_KeyFSCB(MS_U32 u32FltId, MS_U32 u32KteSel, DSCMB_Key_Type eKeyType, HAL_DSCMB_FSCB eForceSCB); 704 #endif 705 706 MS_BOOL HAL_DSCMB_KTE_Read_Switch(MS_U32 u32fltid, DSCMB_Key_Type type, MS_U32 u32CAVid, MS_U32 *u32data); 707 MS_BOOL HAL_DSCMB_KTE_Write_Key(MS_U32 u32fltid, DSCMB_Key_Type type,DSCMB_Eng_Type wtype, MS_U32 u32CAVid, MS_U8* u8key); 708 MS_BOOL HAL_DSCMB_KTE_Write_RIV(MS_U32 u32FltId, DSCMB_Key_Type eType, MS_U32 u32CAVid, MS_U8* u8key, MS_U32 u32RIVIdx); 709 MS_BOOL HAL_DSCMB_KTE_Write_IV(MS_U32 u32FltId, DSCMB_Key_Type eType, MS_U32 u32CAVid, MS_U8* u8key ); 710 MS_BOOL HAL_DSCMB_KTE_Write_IV_Ex(MS_U32 u32FltId, DSCMB_Key_Type eType, DSCMB_Eng_Type wType, MS_U32 u32CAVid, MS_U8* u8key ); 711 MS_BOOL HAL_DSCMB_KTE_Key_Ctrl (MS_U32 u32fltid, DSCMB_Key_Type type, DSCMB_Eng_Type wtype, MS_U32 u32CAVid, MS_BOOL bEnable ); 712 MS_BOOL HAL_DSCMB_KTE_Key_Ctrl_Ex(MS_U32 u32FltId, DSCMB_Key_Type eType, DSCMB_Eng_Type wType, MS_U32 u32CAVid, MS_BOOL bEnable, MS_BOOL bIsKL); 713 MS_BOOL HAL_DSCMB_KTE_IV_Ctrl(MS_U32 u32FltId, DSCMB_Key_Type eType, MS_U32 u32CAVid, MS_BOOL bEnable ); 714 MS_BOOL HAL_DSCMB_KTE_IV_Ctrl_Ex(MS_U32 u32FltId, DSCMB_Key_Type eType, DSCMB_Eng_Type wType, MS_U32 u32CAVid, MS_BOOL bEnable ); 715 716 MS_BOOL HAL_DSCMB_KTE_Write_Algo(MS_U32 u32fltid,DSCMB_Key_Type eKeyType,DSCMB_Eng_Type eEngType , MS_U32 u32CAVid, 717 DSCMB_MainAlgo_Type eAlgoType, DSCMB_SubAlgo_Type eSubAlgo, 718 DSCMB_ResSBAlgo_Type eRes, DSCMB_ResSBAlgo_Type eSB , 719 MS_BOOL bDecrypt ); 720 MS_BOOL HAL_DSCMB_KTE_Write_Switch(MS_U32 u32fltid, DSCMB_Key_Type eKeyType, MS_U32 u32CAVid, MS_U32 UppSwitch, MS_U32 LowSwitch); 721 MS_BOOL HAL_DSCMB_KTE_Write_Permu(MS_U32 u32fltid ,DSCMB_Key_Type eKeyType, MS_U32 u32CAVid, MS_U32 u32per); 722 MS_BOOL HAL_DSCMB_KTE_Write_SBOX(MS_U32 u32fltid ,DSCMB_Key_Type eKeyType, MS_U32 u32CAVid, MS_U32 u32Sbox, MS_BOOL bCSA2Mode); 723 MS_BOOL HAL_DSCMB_KTE_GetStatus(MS_U32 u32fltid ,DSCMB_Key_Type eKeyType, MS_U32 *KeyStatus); 724 MS_BOOL HAL_DSCMB_KTE_Write_SrcDst(MS_U32 u32fltid ,DSCMB_Key_Type eKeyType, MS_U32 u32CAVid, MS_U32 Src, MS_U32 UppDst, MS_U32 LowDst); 725 MS_BOOL HAL_DSCMB_KTE_Write_FSCB(MS_U32 u32FltId ,DSCMB_Key_Type eKeyType, MS_U32 u32CAVid, DSCMB_FSCB eForceSCB); 726 MS_BOOL HAL_DSCMB_KTE_Write_PacketSwitch(MS_U32 u32FltId ,DSCMB_Key_Type eKeyType, MS_U32 u32CAVid, DSCMB_Eng_Type eUppSwitch, DSCMB_Eng_Type eLowSwitch); 727 728 // Set Multi2 syskey // 729 MS_BOOL HAL_DSCMB_KTE_Write_MULTI2_SysKey(MS_U8* Key , MS_U32 u32Len); 730 MS_BOOL HAL_DSCMB_KTE_Write_MULTI2_Round(MS_U32 u32Round) ; 731 732 ///////////////////////////////////////////// 733 ////// //// 734 ////// Cipher Channel function //// 735 ////// //// 736 ///////////////////////////////////////////// 737 738 MS_BOOL HAL_DSCMB_Cipher_DualPath(MS_U32 u32CHNum, MS_BOOL bEnable); 739 MS_BOOL HAL_DSCMB_Cipher_TCSA3(MS_U32 u32CHNum, MS_BOOL bEnable); 740 741 MS_BOOL HAL_DSCMB_Cipher_Set_SCBFix(MS_U32 EngId ,MS_U32 u32tsif ,HAL_DSCMB_SCBFix_EngSel eEngSel , 742 HAL_DSCMB_SCBFix eSCBFix); 743 744 MS_U32 HAL_DSCMB_Cipher_Output_Ctrl(HAL_DSCMB_OutPut_Eng_Sel EngId, MS_U32 u32ChlSel , MS_BOOL bEnable , MS_BOOL bEncrypt , 745 MS_U32 u32TsId , MS_U32 u32CaVid) ; 746 747 MS_BOOL HAL_DSCMB_Cipher_ES_SetStaticKey(MS_U32 u32EngId, MS_U8 *pu8StaticKey, MS_U32 u32KeyLen); 748 749 MS_U32 HAL_DSCMB_PktParser_Ctrl( MS_U32 u32Eng, MS_U32 u32tsif, MS_BOOL bRst, MS_U32 u32Range , 750 HAL_DSCMB_PktParser_Mode u32viewer, MS_BOOL bEnable ); 751 752 // SPS PVR Functions // 753 // SPS only support AES ECB alogorithm // 754 MS_BOOL HAL_DSCMB_SPSPVR_Reset( MS_U32 EngId); 755 MS_BOOL HAL_DSCMB_SPSPVR_SetPid( MS_U32 EngId , MS_U32 u32FltId , MS_U32 U32Pid , MS_BOOL bBuf0, MS_BOOL bBuf1 ); 756 MS_BOOL HAL_DSCMB_SPSPVR_GetWPtr( MS_U32 EngId , MS_U32 *pu32WPtr0, MS_U32 *pu32WPtr1 ); 757 MS_BOOL HAL_DSCMB_SPSPVR_SetBuffer(MS_U32 EngId,MS_U32 BufSel,MS_U32 u32Buf0,MS_U32 u32Size0,MS_U32 u32Buf1 , MS_U32 u32Size1 ); 758 MS_BOOL HAL_DSCMB_SPSPVR_Stop( MS_U32 EngId); 759 MS_BOOL HAL_DSCMB_SPSPVR_Start( MS_U32 EngId); 760 761 // TSP control 762 void HAL_DSCMB_SetTSPCADst(MS_U32 fltId, MS_U32 u32UpDst, MS_U32 u32LowDst); 763 void HAL_DSCMB_SetTSPPidSlotMap(MS_U32 u32FltId, MS_U32 u32PidSlotMapNo); 764 void HAL_DSCMB_PidFlt_EnableKey(MS_U32 fltId, MS_BOOL bEnable); 765 void HAL_DSCMB_Get_TsidInput(MS_U32 u32FltId, MS_U32 *u32Tsid); 766 void HAL_DSCMB_ConnectPath(MS_U32 u32Idx ,MS_BOOL bEnable); 767 void HAL_DSCMB_SetTSPCAVid(MS_U32 u32Tsid, MS_U32 CAVid); 768 void HAL_DSCMB_PidFlt_2ndPid(MS_U32 u32FltId, MS_BOOL bEnable); 769 void HAL_DSCMB_PidFlt_PIDPair(MS_U32 u32FltId, MS_U32 u32PPNo, MS_BOOL bEnable); 770 MS_BOOL HAL_DSCMB_ClearPidPairStatus(MS_U32 u32TsSrc, MS_U32 u32PidPairNum); 771 MS_BOOL HAL_DSCMB_PidFlt_SetPidPair(MS_U32 u32FltIdPri, MS_U32 u32FltIdSec); 772 MS_BOOL HAL_DSCMB_PidFlt_ClearPidPair(MS_U32 u32FltIdPri, MS_U32 u32FltIdSec); 773 MS_U32 HAL_DSCMB_PidFlt_GetPid(MS_U32 u32FltId); 774 775 // New 776 MS_U32 HAL_DSCMB_FltSrc2TSIF(DSCMB_TSIF ePidFltSrc); 777 MS_U32 HAL_DSCMB_FltSrc2PktDmx(DSCMB_TSIF ePidFltSrc); 778 MS_BOOL HAL_DSCMB_SPD_Enable(MS_U32 tsif); 779 MS_BOOL HAL_DSCMB_SPD_Disable(MS_U32 tsif); 780 MS_BOOL HAL_DSCMB_SPD_Reset(MS_U32 tsif); 781 void HAL_DSCMB_PrintSwitchSetup(MS_U32 u32FltId, DSCMB_Key_Type type, MS_U32 u32CAVid); 782 void HAL_DSCMB_PktParser_PrintEvent(MS_U32 event); 783 MS_U32 HAL_DSCMB_GetProgId(DSCMB_CAPVR_MODE eCaMode); 784 MS_U32 HAL_DSCMB_GetChannlId(DSCMB_TSIF ePidFltSrc); 785 MS_BOOL HAL_DSCMB_Cipher_SPS_Enable(HAL_DSCMB_OutPut_Eng_Sel EngId, MS_BOOL bEncrypt); 786 MS_BOOL HAL_DSCMB_PES_Enable(MS_U32 u32CHNum, MS_U32 u32Tsid, MS_BOOL bEnable); 787 788 789 // Key Ladder Functions // 790 MS_BOOL HAL_DSCMB_KL_Start( DSCMB_KL_SelEng eKLEng ); 791 MS_BOOL HAL_DSCMB_KL_Reset(DSCMB_KL_SelEng eKLEng) ; 792 MS_BOOL HAL_DSCMB_KL_KeyProp(DSCMB_KL_SelEng eKLEng, MS_U32 u32CAVid, MS_U32 u32KeyUsg, MS_U32 u32KeyEtpy); 793 #ifdef ENABLE_KEY_FSCB 794 MS_BOOL HAL_DSCMB_KL_KeyBus_Ex(DSCMB_KL_SelEng eKLEng, MS_U32 u32FltId, MS_U32 u32Field, DSCMB_Key_Type eKeyType, DSCMB_KLDst eDst, HAL_DSCMB_FSCB eFSCB); 795 #endif 796 MS_BOOL HAL_DSCMB_KL_KeyBus(DSCMB_KL_SelEng eKLEng, MS_U32 u32FltId, MS_U32 u32Field, DSCMB_Key_Type eKeyType, DSCMB_KLDst eDst); 797 MS_BOOL HAL_DSCMB_KL_Ctrl(DSCMB_KL_SelEng eKLEng, DSCMB_KLEng eAlgo, DSCMB_KLType eType, DSCMB_KLSrc eSrc, DSCMB_KLDst eDst); 798 MS_BOOL HAL_DSCMB_KL_GetACPUOut(DSCMB_KL_SelEng eKLEng, MS_U8 *pu8Key, MS_U32 u32Size); 799 MS_BOOL HAL_DSCMB_KL_ACPURootKey(DSCMB_KL_SelEng eKLEng, MS_U8 *pu8Key); 800 MS_BOOL HAL_DSCMB_KL_Input(DSCMB_KL_SelEng eKLEng, MS_U32 u32In, MS_U8 *pu8Key); 801 MS_BOOL HAL_DSCMB_KL_ErrStatus(DSCMB_KL_SelEng eKLEng); 802 MS_BOOL HAL_DSCMB_KL_ErrMsg(DSCMB_KL_SelEng eKLEng, MS_U32 *pu32ErrMsg); 803 MS_BOOL HAL_DSCMB_KL_KDF_Busy(DSCMB_KL_SelEng eKLEng, MS_BOOL *pbBusy); 804 MS_BOOL HAL_DSCMB_KL_TCSA3_CHSel(MS_U32 u32Ch); 805 MS_BOOL HAL_DSCMB_KL_TCSA3_Start(void); 806 MS_BOOL HAL_DSCMB_KL_TCSA3_ActCode(MS_U8 *pu8Code, MS_U32 u32Size); 807 808 MS_BOOL HAL_DSCMB_KL_TA_LUT3(DSCMB_KL_SelEng eKLEng, DSCMB_KL_TA_LUT3 *LUT3Tab); 809 MS_BOOL HAL_DSCMB_KL_TA_EncCW(DSCMB_KL_SelEng eKLEng, MS_U8 *pu8EncCW); 810 MS_BOOL HAL_DSCMB_KL_TA_EN(DSCMB_KL_SelEng eKLEng, MS_BOOL bTAEn); 811 812 MS_BOOL HAL_DSCMB_KL_ETSI_Nonce(DSCMB_KL_SelEng eKLEng, MS_U8 *pu8Nonce); 813 MS_BOOL HAL_DSCMB_KL_ETSI_Response(DSCMB_KL_SelEng eKLEng, MS_U8 *pu8Response); 814 void HAL_DSCMB_KL_KDF_Disable( DSCMB_KL_SelEng eKLEng); 815 void HAL_DSCMB_KL_KDF_Enable( DSCMB_KL_SelEng eKLEng, KDF_TYPE eKDFType, MS_U16 u16AppId, KDF_HW_KEY_SEL eHWKeyId); 816 817 MS_BOOL HAL_DSCMB_KL_SP_KeyCtrl(DSCMB_KL_SelEng eKLEng, DSCMB_KLDst eDst); 818 MS_BOOL HAL_DSCMB_KL_SP_SetIV(DSCMB_KL_SelEng eKLEng, MS_U8 *pu8IV); 819 MS_BOOL HAL_DSCMB_KL_SP_Start(DSCMB_KL_SelEng eKLEng); 820 821 #endif 822