1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halPVR.h 20 // @brief PVR HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_PVR_H__ 24 #define __HAL_PVR_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM 4 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 //VQ define 36 #define VQ_NUM 4 37 #define VQ_PACKET_UNIT_LEN 208 38 39 #define TSP_TSIF0 0x00 40 #define TSP_TSIF1 0x01 41 #define TSP_TSIF2 0x02 42 #define TSP_TSIF3 0x03 43 44 //FQ define 45 #define TSP_FQ_NUM 4 46 47 //u32Cmd of MApi_DMX_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config, MS_U32 u32DataNum, void *pData); 48 #define HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK 0x00000001 //[u32Config] 1:disable cc check on fw, 0: enable cc check on fw; [u32DataNum,*pData] do not use 49 //######################################################################### 50 //#### Software Capability Macro Start 51 //######################################################################### 52 53 #define TSP_CA_RESERVED_FLT_NUM 1 54 #define TSP_RECFLT_NUM 1 55 #define TSP_PIDFLT_REC_NUM (TSP_PIDFLT_NUM - TSP_PCRFLT_NUM) // 0~189 (0 for CA) 56 // 193 for Err 57 // 192 for REC 58 // 191 for PCR1 59 // 190 for PCR0 60 61 #if HW_PCRFLT_ENABLE 62 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 63 #else 64 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + TSP_RECFLT_NUM) 65 #endif 66 67 //######################################################################### 68 //#### Software Capability Macro End 69 //######################################################################### 70 71 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 72 #define TSP_CAFLT_START_ID 0 73 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) // 1 74 75 // section FLT ID 76 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID // 1 77 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID // 1 78 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 79 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 80 81 // PID 82 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID // 1 83 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 84 85 // PCR 86 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID // 192 87 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 88 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) // 196 89 90 // REC 91 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID // 196 92 93 //-------------------------------------------------------------------------------------------------- 94 // Driver Compiler Option 95 //-------------------------------------------------------------------------------------------------- 96 97 98 //-------------------------------------------------------------------------------------------------- 99 // PVR Hardware Abstraction Layer 100 //-------------------------------------------------------------------------------------------------- 101 102 // HW characteristic 103 104 typedef enum _PVRENG_SEQ 105 { 106 E_TSP_PVR_PVRENG_START = 0, 107 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 108 E_TSP_PVR_PVRENG_1, 109 E_TSP_PVR_PVRENG_2, 110 E_TSP_PVR_PVRENG_3, 111 E_TSP_PVR_PVRENG_END, 112 E_TSP_PVR_ENG_INVALID, 113 } PVRENG_SEQ; 114 115 typedef enum _FILEENG_SEQ 116 { 117 E_FILEENG_TSIF0 = TSP_TSIF0, 118 E_FILEENG_TSIF1 = TSP_TSIF1, 119 E_FILEENG_TSIF2 = TSP_TSIF2, 120 E_FILEENG_TSIF3 = TSP_TSIF3, 121 E_FILEENG_INVALID, 122 123 } FILEENG_SEQ; 124 125 #if 1 // Destination type 126 typedef enum _TSP_DST_SEQ 127 { 128 E_TSP_DST_FIFO_VIDEO, 129 E_TSP_DST_FIFO_VIDEO3D, 130 E_TSP_DST_FIFO_AUDIO, 131 E_TSP_DST_FIFO_AUDIO2, 132 E_TSP_DST_FIFO_AUDIO3, 133 E_TSP_DST_SEC, 134 E_TSP_DST_PVR_PVR0, 135 E_TSP_DST_PVR_PVR1, 136 E_TSP_DST_PVR_PVR2, 137 E_TSP_DST_PVR_PVR3, 138 E_TSP_DST_PVR_PVRCB, //Not support 139 E_TSP_DST_PVR_RASP0, //Not support 140 E_TSP_DST_PVR_RASP1, //Not support 141 E_TSP_DST_TSO_TSO0, 142 E_TSP_DST_TSO_TSO1, //Not support 143 E_TSP_DST_FIFO_AUDIO4, 144 E_TSP_DST_FIFO_VIDEO3, //Not support 145 E_TSP_DST_FIFO_VIDEO4, //Not support 146 E_TSP_DST_INVALID, 147 } TSP_DST_SEQ; 148 #else 149 #define TSP_FltType MS_U32 150 /// TS stream fifo type (Exclusive usage) 151 #define E_TSP_FLT_FIFO_MASK 0x000000FF 152 #define E_TSP_FLT_FIFO_VIDEO 0x00000001 153 #define E_TSP_FLT_FIFO_AUDIO 0x00000002 154 #define E_TSP_FLT_FIFO_AUDIO2 0x00000004 155 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000008 156 #endif 157 158 typedef enum _TSP_SRC_SEQ{ 159 E_TSP_SRC_PKTDMX0, 160 E_TSP_SRC_PKTDMX1, 161 E_TSP_SRC_PKTDMX2, 162 E_TSP_SRC_PKTDMX3, 163 E_TSP_SRC_PKTDMX4, //not used 164 E_TSP_SRC_PKTDMX5, //not used 165 E_TSP_SRC_MMFI0, 166 E_TSP_SRC_MMFI1, 167 168 E_TSP_SRC_INVALID, 169 } TSP_SRC_SEQ; 170 171 typedef enum _TSIF_CFG 172 { 173 // @NOTE should be Exclusive usage 174 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 175 E_TSP_TSIF_CFG_EN = 0x0001, 176 E_TSP_TSIF_CFG_PARA = 0x0002, 177 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 178 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 179 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 180 E_TSP_TSIF_CFG_3WIRE = 0x0010 181 } TSP_TSIF_CFG; 182 183 // for stream input source 184 typedef enum _HAL_TS_PAD 185 { 186 E_TSP_TS_PAD_EXT0, 187 E_TSP_TS_PAD_EXT1, 188 E_TSP_TS_PAD_EXT2, 189 E_TSP_TS_PAD_EXT3, // 4/3 wired serial mode 190 E_TSP_TS_PAD_EXT4, // 4/3 wired serial mode 191 E_TSP_TS_PAD_EXT5, // 4/3 wired serial mode 192 E_TSP_TS_PAD_EXT6, // 3 wired serial mode 193 E_TSP_TS_PAD_INTER0, 194 E_TSP_TS_PAD_INTER1, 195 E_TSP_TS_PAD_TSOUT0, 196 E_TSP_TS_PAD_TSOUT1, //not support, 197 E_TSP_TS_PAD_TSIOOUT0, 198 E_TSP_TS_PAD_INVALID, 199 } TSP_TS_PAD; 200 201 // for ts pad mode 202 typedef enum _HAL_TS_PAD_MUX_MODE 203 { 204 E_TSP_TS_PAD_MUX_PARALLEL, // in 205 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, // in 206 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, // in 207 E_TSP_TS_PAD_MUX_TSO, // out 208 E_TSP_TS_PAD_MUX_S2P, // out 209 E_TSP_TS_PAD_MUX_S2P1, // out 210 E_TSP_TS_PAD_MUX_DEMOD, // out 211 212 E_TSP_TS_PAD_MUX_INVALID 213 } TSP_TS_PAD_MUX_MODE; 214 215 216 // for pkt converter mode 217 typedef enum _HAL_TS_PKT_CONVERTER_MODE 218 { 219 E_TSP_PKT_CONVERTER_188Mode = 0, 220 E_TSP_PKT_CONVERTER_CIMode = 1, 221 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 222 E_TSP_PKT_CONVERTER_ATSMode = 3, 223 E_TSP_PKT_CONVERTER_MxLMode = 4, 224 E_TSP_PKT_CONVERTER_NagraDongleMode = 5, 225 E_TSP_PKT_CONVERTER_Invalid, 226 } TSP_TS_PKT_CONVERTER_MODE; 227 228 typedef enum _HAL_TS_MXL_PKT_MODE 229 { 230 E_TSP_TS_MXL_PKT_192 = 4, 231 E_TSP_TS_MXL_PKT_196 = 8, 232 E_TSP_TS_MXL_PKT_200 = 12, 233 E_TSP_TS_MXL_PKT_INVALID, 234 } TSP_TS_MXL_PKT_MODE; 235 236 typedef enum _HAL_TSP_CLK_TYPE 237 { 238 E_TSP_HAL_TSP_CLK, 239 E_TSP_HAL_STC_CLK, 240 E_TSP_HAL_INVALID 241 } EN_TSP_HAL_CLK_TYPE; 242 243 typedef struct _HAL_TSP_CLK_STATUS 244 { 245 MS_BOOL bEnable; 246 MS_BOOL bInvert; 247 MS_U8 u8ClkSrc; 248 } ST_TSP_HAL_CLK_STATUS; 249 250 typedef enum _PCR_SRC 251 { 252 /* register setting for kaiser pcr 253 0: tsif0 254 1: tsif1 255 2: tsif2 256 3: tsif3 257 4: tsif4 258 5: tsif5 259 6: un-used 260 7: un-used 261 8: pkt merge 0 262 9: pkt merge 1 263 a: MM file in 1 264 b: MM file in 2 265 */ 266 E_TSP_PCR_SRC_TSIF0 = 0, 267 E_TSP_PCR_SRC_TSIF1, 268 E_TSP_PCR_SRC_TSIF2, 269 E_TSP_PCR_SRC_TSIF3, 270 E_TSP_PCR_SRC_TSIF4, 271 E_TSP_PCR_SRC_TSIF5, 272 E_TSP_PCR_SRC_PKT_MERGE0 = 8, 273 E_TSP_PCR_SRC_PKT_MERGE1, 274 E_TSP_PCR_SRC_MMFI0, 275 E_TSP_PCR_SRC_MMFI1, 276 E_TSP_PCR_SRC_INVALID, 277 } TSP_PCR_SRC; 278 279 typedef enum _HAL_TSP_TSIF // for HW TSIF 280 { 281 E_TSP_HAL_TSIF_0 , 282 E_TSP_HAL_TSIF_1 , 283 E_TSP_HAL_TSIF_2 , 284 E_TSP_HAL_TSIF_3 , 285 E_TSP_HAL_TSIF_TSP_MAX , 286 E_TSP_HAL_TSIF_CB , //not support 287 E_TSP_HAL_TSIF_TSO0 , 288 E_TSP_HAL_TSIF_TSO1 , //not support 289 E_TSP_HAL_TSIF_RASP0 , //not support 290 E_TSP_HAL_TSIF_RASP1 , //not support 291 E_TSP_HAL_TSIF_EMMFLT , 292 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 293 E_TSP_HAL_TSIF_PVR0 , 294 E_TSP_HAL_TSIF_PVR1 , 295 E_TSP_HAL_TSIF_PVR2 , 296 E_TSP_HAL_TSIF_PVR3 , 297 E_TSP_HAL_TSIF_INVALID , 298 } TSP_HAL_TSIF; 299 300 301 typedef enum _TSP_HAL_FileState 302 { 303 /// Command Queue is Idle 304 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 305 /// Command Queue is Busy 306 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 307 /// Command Queue is Paused. 308 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 309 310 E_TSP_HAL_FILE_STATE_INVALID, 311 }TSP_HAL_FileState; 312 313 typedef enum 314 { 315 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 316 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 317 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 318 319 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 320 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 321 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 322 323 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 324 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 325 326 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 327 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 328 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 329 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 330 331 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 332 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 333 334 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 335 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 336 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 337 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 338 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 339 340 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 341 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 342 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 343 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 344 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 345 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 346 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 347 348 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 349 350 //27 is reserved, and can not be used 351 352 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 353 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 354 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 355 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 356 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 357 358 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 359 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 360 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 361 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 362 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 363 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 364 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 365 E_TSP_HAL_CAP_FIQ_NUM = 40, 366 E_TSP_HAL_CAP_TYPE_NULL, 367 } TSP_HAL_CAP_TYPE; 368 369 // @F_TODO remove unused enum member 370 typedef enum 371 { 372 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PCRFLT_END_ID - TSP_PIDFLT_START_ID), 373 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), 374 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), 375 376 E_TSP_HAL_CAP_VAL_RECENG_NUM = 4, 377 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, 378 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, 379 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, 380 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 381 382 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 4, //MMFI0 filters 383 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 4, //MMFI1 filters 384 385 E_TSP_HAL_CAP_VAL_TSIF_NUM = 4, 386 E_TSP_HAL_CAP_VAL_DEMOD_NUM = 4, //internal demod // [ToDo] STC number... by MM problem Jason-YH.Sun 387 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 3, 388 E_TSP_HAL_CAP_VAL_VQ_NUM = 4, 389 390 E_TSP_HAL_CAP_VAL_CAFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), //@NOTE: flt number for descrypt purpose 391 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 392 393 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 394 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 395 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 396 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 397 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 398 399 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 400 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 401 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 402 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 403 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 404 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 405 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 406 407 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 408 409 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 4, 410 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 4, 411 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 412 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 413 414 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x4000, 415 416 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 417 } TSP_HAL_CAP_VAL; 418 419 /// TSP TEI Remove Error Packet Infomation 420 typedef enum 421 { 422 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 423 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT ///< TEI Remoce Video Packet 424 425 }TSP_HAL_TEI_RmPktType; 426 427 // TSP TimeStamp Clk Select 428 typedef enum 429 { 430 E_TSP_HAL_TIMESTAMP_CLK_90K = 0, 431 E_TSP_HAL_TIMESTAMP_CLK_27M = 1, 432 E_TSP_HAL_TIMESTAMP_CLK_INVALID = 2 433 434 } TSP_HAL_TimeStamp_Clk; 435 436 /// TSP Packet Converter Input Mode 437 typedef enum 438 { 439 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 440 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 441 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 442 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 443 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 444 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 445 E_TSP_HAL_PKT_MODE_MXL_200, ///< MXL mode (200 bytes) 446 E_TSP_HAL_PKT_MODE_ND, ///< Nagra Dongle mode (192 bytes) 447 448 E_TSP_HAL_PKT_MODE_INVALID 449 }TSP_HAL_PKT_MODE; 450 451 //---------------------------------- 452 /// DMX debug table information structure 453 //---------------------------------- 454 455 typedef enum 456 { 457 E_TSP_HAL_FLOW_LIVE0, 458 E_TSP_HAL_FLOW_LIVE1, 459 E_TSP_HAL_FLOW_LIVE2, 460 E_TSP_HAL_FLOW_LIVE3, 461 E_TSP_HAL_FLOW_FILE0, 462 E_TSP_HAL_FLOW_FILE1, 463 E_TSP_HAL_FLOW_FILE2, 464 E_TSP_HAL_FLOW_FILE3, 465 E_TSP_HAL_FLOW_MMFI0, 466 E_TSP_HAL_FLOW_MMFI1, 467 468 E_TSP_HAL_FLOW_INVALID, 469 470 } TSP_HAL_FLOW; 471 472 typedef enum 473 { 474 E_TSP_HAL_GATING_PATH0 = 0, 475 E_TSP_HAL_GATING_PATH1, 476 E_TSP_HAL_GATING_PATH2, 477 E_TSP_HAL_GATING_PATH3, 478 E_TSP_HAL_GATING_PATH4, 479 E_TSP_HAL_GATING_PATH5, 480 E_TSP_HAL_GATING_TSP_ENG, 481 E_TSP_HAL_GATING_FIQ, 482 E_TSP_HAL_GATING_PVR1, 483 E_TSP_HAL_GATING_PVR2, 484 E_TSP_HAL_GATING_PVR3, 485 E_TSP_HAL_GATING_PVR4, 486 487 E_TSP_HAL_MIU_CLK_GATING_PATH0 = 17, 488 E_TSP_HAL_MIU_CLK_GATING_PATH1, 489 E_TSP_HAL_MIU_CLK_GATING_PATH2, 490 E_TSP_HAL_MIU_CLK_GATING_PATH3, 491 E_TSP_HAL_MIU_CLK_GATING_PATH4, 492 E_TSP_HAL_MIU_CLK_GATING_PATH5, 493 E_TSP_HAL_MIU_CLK_GATING_TSP_ENG, 494 E_TSP_HAL_MIU_CLK_GATING_FIQ, 495 E_TSP_HAL_MIU_CLK_GATING_PVR1, 496 E_TSP_HAL_MIU_CLK_GATING_PVR2, 497 E_TSP_HAL_MIU_CLK_GATING_PVR3, 498 E_TSP_HAL_MIU_CLK_GATING_PVR4, 499 E_TSP_HAL_MIU_CLK_GATING_MMFI0, 500 E_TSP_HAL_MIU_CLK_GATING_MMFI1, 501 502 E_TSP_HAL_GATING_FIQ0 = 31, 503 E_TSP_HAL_GATING_FIQ1, 504 E_TSP_HAL_GATING_FIQ2, 505 E_TSP_HAL_GATING_FIQ3, 506 E_TSP_HAL_GATING_FIQ4, 507 E_TSP_HAL_GATING_FIQ5, 508 509 E_TSP_HAL_MIU_CLK_GATING_FIQ0, 510 E_TSP_HAL_MIU_CLK_GATING_FIQ1, 511 E_TSP_HAL_MIU_CLK_GATING_FIQ2, 512 E_TSP_HAL_MIU_CLK_GATING_FIQ3, 513 E_TSP_HAL_MIU_CLK_GATING_FIQ4, 514 E_TSP_HAL_MIU_CLK_GATING_FIQ5, 515 516 E_TSP_HAL_GATING_INVALID, 517 518 } TSP_HAL_GATING; 519 520 typedef enum 521 { 522 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER0 = 0, 523 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER1, 524 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER2, 525 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER3, 526 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER4, 527 E_TSP_HAL_RESET_CTRL_PKT_CONVERTER5, 528 529 E_TSP_HAL_RESET_CTRL_FIQ0 = 8, 530 E_TSP_HAL_RESET_CTRL_FIQ1, 531 E_TSP_HAL_RESET_CTRL_FIQ2, 532 E_TSP_HAL_RESET_CTRL_FIQ3, 533 E_TSP_HAL_RESET_CTRL_FIQ4, 534 E_TSP_HAL_RESET_CTRL_FIQ5, 535 536 E_TSP_HAL_RESET_CTRL_VQ_TX0 = 16, 537 E_TSP_HAL_RESET_CTRL_VQ_TX1, 538 E_TSP_HAL_RESET_CTRL_VQ_TX2, 539 E_TSP_HAL_RESET_CTRL_VQ_TX3, 540 E_TSP_HAL_RESET_CTRL_VQ_TX4, 541 E_TSP_HAL_RESET_CTRL_VQ_TX5, 542 E_TSP_HAL_RESET_CTRL_VQ_RX, 543 E_TSP_HAL_RESET_CTRL_VQ_TOP, 544 E_TSP_HAL_RESET_CTRL_PKT_DEMUX0, 545 E_TSP_HAL_RESET_CTRL_PKT_DEMUX1, 546 E_TSP_HAL_RESET_CTRL_PKT_DEMUX2, 547 E_TSP_HAL_RESET_CTRL_PKT_DEMUX3, 548 E_TSP_HAL_RESET_CTRL_PKT_DEMUX4, 549 E_TSP_HAL_RESET_CTRL_PKT_DEMUX5, 550 551 E_TSP_HAL_RESET_CTRL_PVR1 = 32, 552 E_TSP_HAL_RESET_CTRL_PVR2, 553 E_TSP_HAL_RESET_CTRL_PVR3, 554 E_TSP_HAL_RESET_CTRL_PVR4, 555 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR1, 556 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR2, 557 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR3, 558 E_TSP_HAL_RESET_CTRL_TIMESTAMP_SEL_PVR4, 559 E_TSP_HAL_RESET_CTRL_SP_D0, 560 E_TSP_HAL_RESET_CTRL_SP_D1, 561 E_TSP_HAL_RESET_CTRL_SP_D2, 562 E_TSP_HAL_RESET_CTRL_SP_D3, 563 E_TSP_HAL_RESET_CTRL_SP_D4, 564 E_TSP_HAL_RESET_CTRL_SP_D5, 565 566 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT0 = 48, 567 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT1, 568 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT2, 569 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT3, 570 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT4, 571 E_TSP_HAL_RESET_CTRL_FILTER_NULL_PKT5, 572 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_0, 573 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_1, 574 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_2, 575 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_3, 576 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_4, 577 E_TSP_HAL_RESET_CTRL_DIRECTV_130_188_5, 578 579 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER0 = 64, 580 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER1, 581 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER2, 582 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER3, 583 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER4, 584 E_TSP_HAL_RESET_CTRL_SRC_ID_PARSER5, 585 E_TSP_HAL_RESET_CTRL_PCRFLT_0, 586 E_TSP_HAL_RESET_CTRL_PCRFLT_1, 587 E_TSP_HAL_RESET_CTRL_PCRFLT_2, 588 E_TSP_HAL_RESET_CTRL_PCRFLT_3, 589 E_TSP_HAL_RESET_CTRL_PCRFLT_4, 590 E_TSP_HAL_RESET_CTRL_PCRFLT_5, 591 592 E_TSP_HAL_RESET_PATH0 = 80, 593 E_TSP_HAL_RESET_PATH1, 594 E_TSP_HAL_RESET_PATH2, 595 E_TSP_HAL_RESET_PATH3, 596 E_TSP_HAL_RESET_PATH4, 597 E_TSP_HAL_RESET_PATH5, 598 E_TSP_HAL_RESET_OTV, 599 E_TSP_HAL_RESET_DEBUG_TABLE, 600 E_TSP_HAL_RESET_DMA_ENG, 601 E_TSP_HAL_RESET_SEC_CMP, 602 E_TSP_HAL_RESET_SECFLT_REG, 603 E_TSP_HAL_RESET_SEC, 604 E_TSP_HAL_RESET_PID_TABLE, 605 606 E_TSP_HAL_RESET_CTRL_INVALID, 607 608 } TSP_HAL_RESET_CTRL; 609 610 611 //-------------------------------------------------------------------------------------------------- 612 // PVR HAL API 613 //-------------------------------------------------------------------------------------------------- 614 // Static Register Mapping for external access 615 #define REG_PIDFLT_BASE0 (0x00240000UL) 616 #define REG_PIDFLT_BASE1 (0x00241000UL) 617 #define REG_SECFLT_BASE (0x00221000UL) 618 #define REG_SECBUF_BASE (0x00221024UL) 619 #define REG_CTRL_BASE (0x00210200UL) 620 621 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 622 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 623 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 624 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 625 //#define _REGSynth ((REG_Synth*)(REG_SYNTH_BASE )) 626 627 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 628 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 629 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE+(_fltid>>5)*0x1000))->Flt[_fltid&(0x1F)])) 630 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE+(_bufid>>5)*0x1000))->Buf[_bufid&(0x1F)])) 631 632 //#define TSIF2PKTDMX(_tsif) (((_tsif)<2)?(_tsif):((_tsif > 3)?(_tsif+2):(_tsif+1))) 633 634 //#define PKTDMX2TSIF(_pktdmx) ((_pktdmx)>2)?(((_pktdmx)==2)?(_pktdmx-1):(_pktdmx)):(((_pktdmx)==5)?(_pktdmx-2):(_pktdmx-1)) 635 636 637 638 //******************** PIDFLT DEFINE START ********************// 639 // PID 640 #define TSP_PIDFLT_PID_MASK 0x00001FFF 641 #define TSP_PIDFLT_PID_SHFT 0 642 643 // Continuous counter 644 #define TSP_PIDFLT_CC_MASK 0xFF000000 645 #define TSP_PIDFLT_CC_SHFT 24 646 647 // PIDFLT SRC 648 typedef enum _TSP_PIDFLT_SRC 649 { 650 E_TSP_PIDFLT_LIVE0, 651 E_TSP_PIDFLT_LIVE1, 652 E_TSP_PIDFLT_LIVE2, 653 E_TSP_PIDFLT_LIVE3, 654 E_TSP_PIDFLT_FILE0, 655 E_TSP_PIDFLT_FILE1, 656 E_TSP_PIDFLT_FILE2, 657 E_TSP_PIDFLT_FILE3, 658 E_TSP_PIDFLT_INVALID, 659 } TSP_PIDFLT_SRC; 660 661 #define TSP_PIDFLT_IN_MASK 0x0000E000 662 #define TSP_PIDFLT_TSIF_SHFT 13 663 #define TSP_PIDFLT_TSIF0 0x00 664 #define TSP_PIDFLT_TSIF1 0x01 665 #define TSP_PIDFLT_TSIF2 0x02 666 #define TSP_PIDFLT_TSIF3 0x03 667 #define TSP_PIDFLT_TSIF_MAX 0x04 668 669 // Section filter Id (0~63) 670 #define TSP_PIDFLT_SECFLT_MASK 0x000000FF // [21:16] secflt id 671 #define TSP_PIDFLT_SECFLT_SHFT 0 672 673 // AF/Sec/Video/V3D/Audio/AudioB/AudioC/AudioD/PVR1/PVR2/PVR3/PVR4 674 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 675 #define TSP_PIDFLT_OUT_MASK 0x009FFF00 676 #define TSP_PIDFLT_OUT_SHFT 8 677 #define TSP_PIDFLT_OUT_NONE 0x00000000 678 #define TSP_PIDFLT_OUT_SECAF 0x00000100 679 #define TSP_PIDFLT_OUT_SECFLT 0x00000200 680 #define TSP_PIDFLT_OUT_VFIFO 0x00000400 681 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000800 682 #define TSP_PIDFLT_OUT_AFIFO 0x00001000 683 #define TSP_PIDFLT_OUT_AFIFO2 0x00002000 684 #define TSP_PIDFLT_OUT_VFIFO3 0x00004000 685 #define TSP_PIDFLT_OUT_AFIFO3 0x00080000 686 #define TSP_PIDFLT_OUT_AFIFO4 0x00100000 687 #define TSP_PIDFLT_OUT_VFIFO4 0x00800000 688 689 690 // SRC ID 691 #define TSP_PIDFLT_SRCID_MASK 0xF0000000 692 #define TSP_PIDFLT_SRCID_SHIFT 28 693 694 695 696 #define TSP_PIDFLT_PVRFLT_MASK 0x00078000 697 #define TSP_PIDFLT_PVRFLT_SHFT 15 698 //enable LUT 699 #define TSP_PIDFLT_OUT_LUT 0x00400000 700 701 #define TSP_PIDFLT_OUT_PVR1 0x00008000 702 #define TSP_PIDFLT_OUT_PVR2 0x00010000 703 #define TSP_PIDFLT_OUT_PVR3 0x00020000 704 #define TSP_PIDFLT_OUT_PVR4 0x00040000 705 706 707 #define TSP_PIDFLT_PKTPUSH_PASS_MASK 0x00200000 708 #define TSP_PIDFLT_PKTPUSH_PASS_SHFT 21 709 #define TSP_PID_FLT_PKTPUSH_PASS 0x00200000 710 711 #define TSP_PIDFLT_TSOFLT_MASK 0x00400000 712 #define TSP_PIDFLT_TSOFLT_SHFT 22 713 #define TSP_PID_FLT_OUT_TSO0 0x00400000 714 715 //******************** PIDFLT DEFINE END ********************// 716 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 717 MS_U32 TSP32_IdrR(TSP32 *preg); 718 719 //=========================TSIF================================ 720 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 721 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable); 722 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 723 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 724 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 725 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 726 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 727 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 728 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 729 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 730 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 731 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 732 MS_BOOL HAL_TSP_GET_TSIF_FileEnStatus(MS_U32 u32FileEn); 733 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 734 735 //=========================TSP================================ 736 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn); 737 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 738 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn); 739 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 740 void HAL_TSP_Reset(MS_BOOL bEn); 741 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn); 742 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus); 743 void HAL_TSP_Power(MS_BOOL bEn); 744 void HAL_TSP_CPU(MS_BOOL bEn); 745 void HAL_TSP_ResetCPU(MS_BOOL bReset); 746 void HAL_TSP_HwPatch(void); 747 void HAL_TSP_RestoreFltState(void); 748 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 749 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn); 750 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 751 void HAL_TSP_PktBuf_Reset(MS_U32 pktBufId, MS_BOOL bEn); 752 void HAL_TSP_SaveFltState(void); 753 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 754 void HAL_TSP_FIFOPBFltFullSel(MS_U32 u32FIFOFullLevel); 755 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 756 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 757 void HAL_TSP_Bank1137_Write(MS_U32 u32Offset,MS_U16 u16Value); 758 759 //=========================TSO================================ 760 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 761 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 762 763 //=========================Filein================================ 764 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 765 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 766 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 767 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 768 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 769 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 770 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 771 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 772 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 773 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 774 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 775 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 776 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 777 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 778 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk); 779 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 780 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 781 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass);// for PS mode A/V fifo pull back 782 783 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 784 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 785 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 786 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 787 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 788 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 789 /* 790 // Only used by [HW test code] 791 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 792 */ 793 794 //=========================PCR FLT================================ 795 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 796 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId); 797 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 798 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 799 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc);//[Jason] 800 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 801 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 802 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 803 804 //=========================STC================================ 805 void HAL_TSP_STC_Init(void); 806 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 807 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 808 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 809 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 810 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 811 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); 812 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); 813 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable); 814 815 //=========================FIFO================================ 816 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 817 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 818 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 819 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType); 820 void HAL_TSP_FIFO_ClearAll (void); 821 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 822 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 823 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 824 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 825 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 826 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 827 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 828 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 829 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 830 831 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 832 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 833 void HAL_TSP_PS_SRC(MS_U32 tsIf); 834 void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 835 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType); // read A/V fifo data 836 MS_U16 HAL_TSP_FIFO_ReadPkt(void); // 837 void HAL_TSP_FIFO_ReadEn(MS_BOOL bEn); // 838 void HAL_TSP_FIFO_Connect(MS_BOOL bEn); // 839 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 840 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn); 841 842 //=========================VQ================================ 843 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 844 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 845 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 846 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 847 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn); 848 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 849 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 850 851 //=========================Pid Flt================================ 852 //void HAL_TSP_PidFlt_SetFltOut(MS_U32 pPidFlt, MS_U32 u32FltOu); 853 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 854 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 855 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 856 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 857 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 858 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 859 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn); 860 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 861 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 862 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 863 864 //=========================SecFlt================================ 865 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 866 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 867 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 868 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 869 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 870 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 871 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 872 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 873 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 874 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFlt, MS_U32 u32ReqCount); 875 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 876 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFlt); 877 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 878 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 879 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 880 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 881 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 882 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 883 884 //=========================Sec Buf================================ 885 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 886 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 887 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 888 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 889 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 890 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 891 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 892 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 893 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 894 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 895 896 //=========================PVR================================ 897 void HAL_PVR_SetBank(MS_U32 u32BankAddr); 898 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 899 void HAL_PVR_Exit(MS_U32 u32PVREng); 900 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 901 /* 902 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 903 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 904 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 905 */ 906 void HAL_PVR_FlushData(MS_U32 u32PVREng); 907 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 908 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 909 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 910 void HAL_PVR_Start(MS_U32 u32PVREng); 911 void HAL_PVR_Stop(MS_U32 u32PVREng); 912 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 913 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 914 void HAL_PVR_RecNull(MS_BOOL bSet); 915 void HAL_PVR_SetPidflt(MS_U32 u32PVREng, MS_U16 u16Fltid, MS_U16 u16Pid); 916 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 917 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 918 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 919 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 920 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 921 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 922 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 923 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 924 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 925 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 926 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable); 927 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime); 928 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 929 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 930 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 931 /* 932 void HAL_TSP_PVR_SPSConfig(MS_U8 u8Eng, MS_BOOL CTR_mode); 933 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode); 934 */ 935 936 //=========================RASP================================ 937 MS_U32 HAL_RASP_Set_Source(MS_U32 u32RASPEng, MS_U32 pktDmxId); 938 MS_U32 HAL_RASP_Get_Source(MS_U32 u32RASPEng, TSP_SRC_SEQ *eSrc); 939 940 //=========================FQ================================ 941 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc); 942 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng); 943 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull); 944 945 //=========================HCMD================================ 946 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 947 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 948 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 949 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 950 MS_BOOL HAL_TSP_HCMD_Alive(void); 951 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 952 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 953 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 954 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 955 956 //=========================INT================================ 957 void HAL_TSP_INT_Enable(MS_U32 u32Mask); 958 void HAL_TSP_INT_Disable(MS_U32 u32Mask); 959 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask); 960 MS_U32 HAL_TSP_INT_GetHW(void); 961 void HAL_TSP_INT_ClrSW(void); 962 MS_U32 HAL_TSP_INT_GetSW(void); 963 964 //=========================Mapping================================ 965 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 966 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 967 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 968 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 969 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 970 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 971 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 972 MS_U32 HAL_TSP_PVRRASPEngMapping(MS_U32 u32Eng); 973 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 974 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 975 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 976 977 //========================DSCMB Functions=================================== 978 extern MS_BOOL HAL_DSCMB_GetBank(MS_U32 *u32Bank); 979 extern MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 980 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 981 982 //========================MOBF Functions===================================== 983 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 984 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 985 986 //========================Protection range=================================== 987 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 988 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 989 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 990 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 991 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 992 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 993 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 994 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 995 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 996 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 997 998 //========================Debug table============================= 999 void HAL_TSP_FltNullPkt_En(MS_BOOL bEn); 1000 1001 // @TODO Renaming Load and Get 1002 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 1003 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 1004 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_BOOL bLock); 1005 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif); 1006 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 1007 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 1008 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 1009 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 1010 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 1011 1012 // @TODO Implement Drop and Dis Hal 1013 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId); 1014 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn); 1015 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload); 1016 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop); 1017 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 1018 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 1019 1020 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 1021 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 1022 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void); 1023 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif); 1024 1025 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); 1026 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 1027 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); 1028 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); 1029 1030 //========================MergeStream Functions============================= 1031 void HAL_TSP_PktConverter_Init(void); 1032 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 1033 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet); 1034 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet); 1035 /* 1036 void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen); 1037 */ 1038 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 1039 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId); 1040 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 1041 1042 //==========================TSIO ============================================ 1043 void HAL_TSP_Privilege_Enable(MS_BOOL bEnable); 1044 1045 void HAL_TSP_Module_Reset(TSP_HAL_RESET_CTRL ePath, MS_U32 u32Idx, MS_BOOL bEn); 1046 void HAL_TSP_CLK_GATING(TSP_HAL_GATING ePath, MS_U32 u32eng, MS_BOOL bEn); 1047 1048 void HAL_TSP_PidFlt_SetLutEn(MS_U32 fltId, MS_BOOL bEn); 1049 1050 #endif // #ifndef __HAL_PVR_H__ 1051