1 //<MStar Software>
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halCA.c
97 // @brief CA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include "string.h"
104 #endif
105
106 #include "MsCommon.h"
107 #include "regCA.h"
108 #include "drvCA.h"
109 #include "halCA.h"
110
111 #include <drvSYS.h>
112
113 // #undef MS_DEBUG_MSG
114 // #define MS_DEBUG_MSG(x) x
115
116 //--------------------------------------------------------------------------------------------------
117 // Driver Compiler Option
118 //--------------------------------------------------------------------------------------------------
119
120
121 //--------------------------------------------------------------------------------------------------
122 // CA Hardware Abstraction Layer
123 //--------------------------------------------------------------------------------------------------
124 static MS_VIRT _u32REGBase = 0;
125 static MS_VIRT _u32REGPMBase = 0;
126 static MS_VIRT _u32REG_OTP_Base = 0;
127 static MS_VIRT _u32REG_RSA_Base = 0;
128
129 #define REG16(addr) (*(volatile unsigned short *)(_u32REGBase + (addr)))
130 #define REG16_WRITE(addr, value, mask) do { REG16(addr) = (REG16(addr) & ~(mask)) | ((value) & (mask)); } while(0)
131
132 #define REG32(addr) (*(volatile unsigned *)(_u32REGBase + (addr)))
133 #define REG32_WRITE(addr, value, mask) do { REG32(addr) = (REG32(addr) & ~(mask)) | ((value) & (mask)); } while(0)
134
135 #define REG32_PM(addr) (*(volatile unsigned *)(_u32REGPMBase + (addr)))
136 #define REG16_PM(addr) (*(volatile unsigned short *)(_u32REGPMBase + (addr)))
137
138 #ifdef CA_NO_PRINTF
139 #define HAL_CA_DEBUG(fmt, args...)
140 #else
141 #define HAL_CA_DEBUG(fmt, args...) do{ \
142 printf("[%s][%d]"fmt"\n", __FUNCTION__, __LINE__, ## args);}\
143 while(0)
144 #endif
bitmask(unsigned hi,unsigned lo)145 static unsigned bitmask(unsigned hi, unsigned lo)
146 {
147 unsigned x, s = hi - lo + 1;
148 // printf("hi=%d lo=%d size=%d\n", hi, lo, s);
149
150 if(s >= sizeof(unsigned) * 8)
151 x = (unsigned)-1;
152 else
153 x = (1U << s) - 1;
154 return x << lo;
155 }
156
157 struct {
158 MS_U32 u32Addr;
159 MS_U32 u32Hi;
160 MS_U32 u32Lo;
161 } _HAL_CA_OTP_Addr[] = {
162 //Parse from otp mapping
163 [U_OTP_CA_reserved0] = {0x003500, 255, 0},
164 [U_OTP_CA_reserved1] = {0x003520, 255, 0},
165 [U_OTP_CA_reserved2] = {0x003540, 255, 0},
166 [U_OTP_CA_reserved3] = {0x003560, 255, 0},
167 [U_OTP_CA_reserved4] = {0x003580, 255, 0},
168 [U_OTP_CA_reserved5] = {0x0035A0, 255, 0},
169 [U_OTP_CA_reserved6] = {0x0035C0, 255, 0},
170 [U_OTP_CA_reserved7] = {0x0035E0, 255, 0},
171 [U_OTP_CA_reserved8] = {0x003600, 255, 0},
172 [U_OTP_CA_reserved9] = {0x003620, 255, 0},
173 [U_OTP_CA_reserved10] = {0x003640, 255, 0},
174 [U_OTP_CA_reserved11] = {0x003660, 255, 0},
175 [U_OTP_CA_reserved12] = {0x003680, 255, 0},
176 [U_OTP_CA_reserved13] = {0x0036A0, 255, 0},
177 [U_OTP_CA_reserved14] = {0x0036C0, 255, 0},
178 [U_OTP_CA_reserved15] = {0x0036E0, 255, 0},
179 [U_OTP_Chip_Extension_ID] = {0x003700, 127, 0},
180 [U_OTP_PVConfiguration] = {0x003710, 23, 0},
181 [U_OTP_EncryptLoader_Key_sel] = {0x003710, 27, 24},
182 [U_OTP_EncryptLoader_KL_level] = {0x003710, 29, 28},
183 [U_OTP_SW_Reserved0] = {0x003710, 31, 30},
184 [U_OTP_EncryptLoader_ForceEnc] = {0x003714, 1, 0},
185 [U_OTP_SW_Reserved1] = {0x003714, 31, 2},
186 [U_OTP_SW_Reserved2] = {0x003724, 31, 0},
187 [U_OTP_Versioning] = {0x003728, 511, 0},
188 [U_OTP_Preenablement_0] = {0x003768, 31, 0},
189 [U_OTP_Preenablement_1] = {0x00376C, 31, 0},
190 [U_OTP_Preenablement_2] = {0x003770, 31, 0},
191 [U_OTP_Preenablement_3] = {0x003774, 31, 0},
192 [U_OTP_Preenablement_4] = {0x003778, 31, 0},
193 [U_OTP_Preenablement_5] = {0x00377C, 31, 0},
194 [U_OTP_Preenablement_6] = {0x003780, 31, 0},
195 [U_OTP_Preenablement_7] = {0x003784, 31, 0},
196 [U_OTP_CAdata_0] = {0x003788, 31, 0},
197 [U_OTP_CAdata_1] = {0x00378C, 31, 0},
198 [U_OTP_CAdata_2] = {0x003790, 31, 0},
199 [U_OTP_CAdata_3] = {0x003794, 31, 0},
200 [U_OTP_CAdata_4] = {0x003798, 31, 0},
201 [U_OTP_CAdata_5] = {0x00379C, 31, 0},
202 [U_OTP_CAdata_6] = {0x0037A0, 31, 0},
203 [U_OTP_CAdata_7] = {0x0037A4, 31, 0},
204 [U_OTP_CAdata_8] = {0x0037A8, 31, 0},
205 [U_OTP_CAdata_9] = {0x0037AC, 31, 0},
206 [U_OTP_CAdata_10] = {0x0037B0, 31, 0},
207 [U_OTP_CAdata_11] = {0x0037B4, 31, 0},
208 [U_OTP_CAdata_12] = {0x0037B8, 31, 0},
209 [U_OTP_CAdata_13] = {0x0037BC, 31, 0},
210 [U_OTP_CAdata_14] = {0x0037C0, 31, 0},
211 [U_OTP_CAdata_15] = {0x0037C4, 31, 0},
212 [U_OTP_CAdata_16] = {0x0037C8, 31, 0},
213 [U_OTP_CAdata_17] = {0x0037CC, 31, 0},
214 [U_OTP_CAdata_18] = {0x0037D0, 31, 0},
215 [U_OTP_CAdata_19] = {0x0037D4, 31, 0},
216 [U_OTP_CAdata_20] = {0x0037D8, 31, 0},
217 [U_OTP_CAdata_21] = {0x0037DC, 31, 0},
218 [U_OTP_CAdata_22] = {0x0037E0, 31, 0},
219 [U_OTP_CAdata_23] = {0x0037E4, 31, 0},
220 [U_OTP_CAdata_24] = {0x0037E8, 31, 0},
221 [U_OTP_CAdata_25] = {0x0037EC, 31, 0},
222 [U_OTP_CAdata_26] = {0x0037F0, 31, 0},
223 [U_OTP_CAdata_27] = {0x0037F4, 31, 0},
224 [U_OTP_CAdata_28] = {0x0037F8, 31, 0},
225 [U_OTP_CAdata_29] = {0x0037FC, 31, 0},
226 [U_OTP_CAdata_30] = {0x003800, 31, 0},
227 [U_OTP_CAdata_31] = {0x003804, 31, 0},
228 [U_OTP_CAdata_32] = {0x003808, 31, 0},
229 [U_OTP_CAdata_33] = {0x00380C, 31, 0},
230 [U_OTP_CAdata_34] = {0x003810, 31, 0},
231 [U_OTP_CAdata_35] = {0x003814, 31, 0},
232 [U_OTP_CAdata_36] = {0x003818, 31, 0},
233 [U_OTP_CAdata_37] = {0x00381C, 31, 0},
234 [U_OTP_forbid_SCPU2DRAM] = {0x003820, 3, 0},
235 [U_OTP_forbid_SCPUQMEM_to_DRAM] = {0x003820, 7, 4},
236 [U_OTP_forbid_CryptoDMA_keyslot_QMEM] = {0x003820, 11, 8},
237 [U_OTP_forbid_SCPU2UART] = {0x003820, 15, 12},
238 [U_OTP_IXSC_config1] = {0x003820, 19, 16},
239 [U_OTP_IXSC_config2] = {0x003820, 23, 20},
240 [U_OTP_IXSC_config3] = {0x003820, 27, 24},
241 [U_OTP_IXSC_config4] = {0x003820, 31, 28},
242 [U_OTP_LockWord_Preenablement_0_W] = {0x003824, 1, 0},
243 [U_OTP_LockWord_Preenablement_1_W] = {0x003824, 3, 2},
244 [U_OTP_LockWord_Preenablement_2_W] = {0x003824, 5, 4},
245 [U_OTP_LockWord_Preenablement_3_W] = {0x003824, 7, 6},
246 [U_OTP_LockWord_Preenablement_4_W] = {0x003824, 9, 8},
247 [U_OTP_LockWord_Preenablement_5_W] = {0x003824, 11, 10},
248 [U_OTP_LockWord_Preenablement_6_W] = {0x003824, 13, 12},
249 [U_OTP_LockWord_Preenablement_7_W] = {0x003824, 15, 14},
250 [U_OTP_Test_Switch] = {0x003824, 23, 16},
251 [U_OTP_IXSC_Reserved0] = {0x003824, 31, 24},
252 [U_OTP_NOCS3_00] = {0x003828, 383, 0},
253 [U_OTP_NOCS3_01] = {0x003858, 383, 0},
254 [U_OTP_NOCS3_02] = {0x003888, 127, 0},
255 [U_OTP_NOCS3_03] = {0x003898, 127, 0},
256 [U_OTP_MSID] = {0x0038A8, 31, 0},
257 [U_OTP_CFG_STB_CA_SN] = {0x0038AC, 31, 0},
258 [U_OTP_HASH0_VER_REF] = {0x0038c8, 31, 0},
259 [U_OTP_HASH1_VER_REF] = {0x0038cc, 31, 0},
260 [U_OTP_HASH2_VER_REF] = {0x0038d0, 31, 0},
261 [U_OTP_RSA_0] = {0x0039B0, 2047, 0},
262 [U_OTP_RSA_1] = {0x003628, 2047, 0},
263 [U_OTP_RSA_0_integrity_chk] = {0x003AB0, 1, 0},
264 [U_OTP_RSA_1_integrity_chk] = {0x003AB0, 3, 2},
265 [U_OTP_ena_ACPUUseHWRSAKey] = {0x003AB0, 7, 4},
266 [U_OTP_forbid_ACPUReadRSAKey0] = {0x003AB0, 10, 8},
267 [U_OTP_forbid_ACPUReadRSAKey1] = {0x003AB0, 13, 11},
268 [U_OTP_forbid_ACPUWrite_Versioning] = {0x003AB0, 15, 14},
269 [U_OTP_forbid_ACPURead_Versioning] = {0x003AB0, 17, 16},
270 [U_OTP_RSA_Reserved0] = {0x003AB0, 31, 18},
271 [U_OTP_RSA_0_CRC] = {0x003AB4, 15, 0},
272 [U_OTP_RSA_1_CRC] = {0x003AB4, 31, 16},
273 [U_OTP_PGMask0] = {0x003AB8, 31, 0},
274 [U_OTP_PGMask1] = {0x003ABC, 31, 0},
275 [U_OTP_PGMask2] = {0x003AC0, 31, 0},
276 [U_OTP_PGMask3] = {0x003AC4, 31, 0},
277 [U_OTP_PGMask4] = {0x003AC8, 31, 0},
278 [U_OTP_PGMask5] = {0x003ACC, 31, 0},
279 [U_OTP_PGMask6] = {0x003AD0, 31, 0},
280 [U_OTP_PGMask7] = {0x003AD4, 31, 0},
281 [U_OTP_PGMask8] = {0x003AD8, 31, 0},
282 [U_OTP_PGMask9] = {0x003ADC, 31, 0},
283 [U_OTP_PGMask10] = {0x003AE0, 31, 0},
284 [U_OTP_PGMask11] = {0x003AE4, 31, 0},
285 [U_OTP_PGMask12] = {0x003AE8, 31, 0},
286 [U_OTP_PGMask13] = {0x003AEC, 31, 0},
287 [U_OTP_PGMask14] = {0x003AF0, 31, 0},
288 [U_OTP_PGMask15] = {0x003AF4, 31, 0},
289 [U_OTP_PGMask16] = {0x003AF8, 31, 0},
290 [U_OTP_PGMask17] = {0x003AFC, 31, 0},
291 [U_OTP_v_PubOtpOID] = {0x003B00, 15, 0},
292 [U_OTP_NDS_Reserved0] = {0x003B00, 31, 16},
293 [U_OTP_v_PubOtpVID] = {0x003B04, 15, 0},
294 [U_OTP_NDS_Reserved1] = {0x003B04, 31, 16},
295 [U_OTP_v_PubOtpGP] = {0x003B08, 15, 0},
296 [U_OTP_LockWord_GP_group_W] = {0x003B08, 31, 16},
297 [U_OTP_v_PubOtpBID] = {0x003B0C, 3, 0},
298 [U_OTP_NDS_Reserved2] = {0x003B0C, 31, 4},
299 [U_OTP_v_PubOtpRsaIndex] = {0x003B10, 3, 0},
300 [U_OTP_NDS_Reserved3] = {0x003B10, 31, 4},
301 [U_OTP_v_PubOtpMinConfVer] = {0x003B14, 7, 0},
302 [U_OTP_NDS_Reserved4] = {0x003B14, 31, 8},
303 [U_OTP_VenderConstSel] = {0x003B18, 2, 0},
304 [U_OTP_NDS_Reserved5] = {0x003B18, 31, 3},
305 [U_OTP_LockWord_NDS_Key1] = {0x003B1C, 2, 0},
306 [U_OTP_LockWord_NDS_Key2] = {0x003B1C, 5, 3},
307 [U_OTP_LockWord_NDS_Key3] = {0x003B1C, 8, 6},
308 [U_OTP_LockWord_NDS_Key4] = {0x003B1C, 11, 9},
309 [U_OTP_LockWord_NDS_Key5] = {0x003B1C, 14, 12},
310 [U_OTP_LockWord_NDS_Key6] = {0x003B1C, 17, 15},
311 [U_OTP_LockWord_NDS_Key7] = {0x003B1C, 20, 18},
312 [U_OTP_LockWord_NDS_Key8] = {0x003B1C, 23, 21},
313 [U_OTP_NDSKeyValid] = {0x003B1C, 31, 24},
314 [U_OTP_forbid_NSK_wr_sck] = {0x003B20, 7, 0},
315 [U_OTP_UseCheckSum] = {0x003B20, 15, 8},
316 [U_OTP_allow_NDSKey_BlankChk] = {0x003B20, 17, 16},
317 [U_OTP_allow_ProgFail_RuinNDSKey] = {0x003B20, 19, 18},
318 [U_OTP_allow_NDSReadKeyWait200ms] = {0x003B20, 21, 20},
319 [U_OTP_allow_ReadErrorRstOtp] = {0x003B20, 23, 22},
320 [U_OTP_allow_illegalNDSFlagChk] = {0x003B20, 27, 24},
321 [U_OTP_allow_Rst_NDS_SCFlag_ParityFail] = {0x003B20, 31, 28},
322 [U_OTP_ena_ACPUUseNSK2] = {0x003B24, 3, 0},
323 [U_OTP_ena_DBUSUseNSK2] = {0x003B24, 7, 4},
324 [U_OTP_ena_ForceOneMilSec] = {0x003B24, 11, 8},
325 [U_OTP_allow_SCCheck] = {0x003B24, 15, 12},
326 [U_OTP_ena_TestRCFreq] = {0x003B24, 19, 16},
327 [U_OTP_ena_SWRN] = {0x003B24, 23, 20},
328 [U_OTP_ena_NSKSeedPRNG] = {0x003B24, 27, 24},
329 [U_OTP_OTPWritePWDProtect] = {0x003B24, 31, 28},
330 [U_OTP_NDS_keysel] = {0x003B28, 5, 0},
331 [U_OTP_allow_NSK2_PWD_Mode] = {0x003B28, 7, 6},
332 [U_OTP_ena_EMMFilter] = {0x003B28, 11, 8},
333 [U_OTP_ena_TestGenIN] = {0x003B28, 15, 12},
334 [U_OTP_RCFreq_map] = {0x003B28, 20, 16},
335 [U_OTP_NDS_Reserved6] = {0x003B28, 31, 21},
336 [U_OTP_allow_SkipBadNVBit] = {0x003B2C, 1, 0},
337 [U_OTP_allow_NDSSC_ReadFail_BadPkt] = {0x003B2C, 3, 2},
338 [U_OTP_allow_RANDOM_keybus] = {0x003B2C, 5, 4},
339 [U_OTP_allow_RANDOM_byteacc] = {0x003B2C, 7, 6},
340 [U_OTP_allow_NDS_Rd55AA] = {0x003B2C, 9, 8},
341 [U_OTP_allow_NDS_Parity_chk] = {0x003B2C, 11, 10},
342 [U_OTP_allow_NDS_KeyRd55AA] = {0x003B2C, 13, 12},
343 [U_OTP_forbid_OTPBuiltInTest] = {0x003B2C, 15, 14},
344 [U_OTP_forbid_Kilo_ProgRepair] = {0x003B2C, 17, 16},
345 [U_OTP_NDS_Reserved7] = {0x003B2C, 31, 18},
346 [U_OTP_NVCOUNT] = {0x003B30, 1023, 0},
347 [U_OTP_NDS_SecretKey1] = {0x003BB0, 127, 0},
348 [U_OTP_NDS_SecretKey2] = {0x003BC0, 127, 0},
349 [U_OTP_NDS_SecretKey3] = {0x003BD0, 127, 0},
350 [U_OTP_NDS_SecretKey4] = {0x003BE0, 127, 0},
351 [U_OTP_NDS_SecretKey5] = {0x003BF0, 127, 0},
352 [U_OTP_NDS_SecretKey6] = {0x003C00, 127, 0},
353 [U_OTP_NDS_SecretKey7] = {0x003C10, 127, 0},
354 [U_OTP_NDS_SecretKey8] = {0x003C20, 127, 0},
355 [U_OTP_NDSKey1Chksum] = {0x003C30, 7, 0},
356 [U_OTP_NDSKey1Tag] = {0x003C30, 15, 8},
357 [U_OTP_NDSKey2Chksum] = {0x003C30, 23, 16},
358 [U_OTP_NDSKey2Tag] = {0x003C30, 31, 24},
359 [U_OTP_NDSKey3Chksum] = {0x003C34, 7, 0},
360 [U_OTP_NDSKey3Tag] = {0x003C34, 15, 8},
361 [U_OTP_NDSKey4Chksum] = {0x003C34, 23, 16},
362 [U_OTP_NDSKey4Tag] = {0x003C34, 31, 24},
363 [U_OTP_NDSKey5Chksum] = {0x003C38, 7, 0},
364 [U_OTP_NDSKey5Tag] = {0x003C38, 15, 8},
365 [U_OTP_NDSKey6Chksum] = {0x003C38, 23, 16},
366 [U_OTP_NDSKey6Tag] = {0x003C38, 31, 24},
367 [U_OTP_NDSKey7Chksum] = {0x003C3C, 7, 0},
368 [U_OTP_NDSKey7Tag] = {0x003C3C, 15, 8},
369 [U_OTP_NDSKey8Chksum] = {0x003C3C, 23, 16},
370 [U_OTP_NDSKey8Tag] = {0x003C3C, 31, 24},
371 [U_OTP_NDS_Key1_CRC] = {0x003C40, 15, 0},
372 [U_OTP_NDS_Key2_CRC] = {0x003C40, 31, 16},
373 [U_OTP_NDS_Key3_CRC] = {0x003C44, 15, 0},
374 [U_OTP_NDS_Key4_CRC] = {0x003C44, 31, 16},
375 [U_OTP_NDS_Key5_CRC] = {0x003C48, 15, 0},
376 [U_OTP_NDS_Key6_CRC] = {0x003C48, 31, 16},
377 [U_OTP_NDS_Key7_CRC] = {0x003C4C, 15, 0},
378 [U_OTP_NDS_Key8_CRC] = {0x003C4C, 31, 16},
379 [U_OTP_NDS_ESCK_Key1_obfuscation] = {0x003C50, 1, 0},
380 [U_OTP_NDS_Key1_integrity_chk] = {0x003C50, 3, 2},
381 [U_OTP_NDS_ESCK_Key2_obfuscation] = {0x003C50, 5, 4},
382 [U_OTP_NDS_Key2_integrity_chk] = {0x003C50, 7, 6},
383 [U_OTP_NDS_ESCK_Key3_obfuscation] = {0x003C50, 9, 8},
384 [U_OTP_NDS_Key3_integrity_chk] = {0x003C50, 11, 10},
385 [U_OTP_NDS_ESCK_Key4_obfuscation] = {0x003C50, 13, 12},
386 [U_OTP_NDS_Key4_integrity_chk] = {0x003C50, 15, 14},
387 [U_OTP_NDS_ESCK_Key5_obfuscation] = {0x003C50, 17, 16},
388 [U_OTP_NDS_Key5_integrity_chk] = {0x003C50, 19, 18},
389 [U_OTP_NDS_ESCK_Key6_obfuscation] = {0x003C50, 21, 20},
390 [U_OTP_NDS_Key6_integrity_chk] = {0x003C50, 23, 22},
391 [U_OTP_NDS_ESCK_Key7_obfuscation] = {0x003C50, 25, 24},
392 [U_OTP_NDS_Key7_integrity_chk] = {0x003C50, 27, 26},
393 [U_OTP_NDS_ESCK_Key8_obfuscation] = {0x003C50, 29, 28},
394 [U_OTP_NDS_Key8_integrity_chk] = {0x003C50, 31, 30},
395 [U_OTP_EJTAG_MODE_Parity_bit] = {0x003C54, 0, 0},
396 [U_OTP_I2C_MODE_Parity_bit] = {0x003C54, 1, 1},
397 [U_OTP_SCAN_MODE_Parity_bit] = {0x003C54, 2, 2},
398 [U_OTP_VenderConstSel_Parity_bit] = {0x003C54, 3, 3},
399 [U_OTP_v_PubOtpRsaIndex_Parity_bit] = {0x003C54, 4, 4},
400 [U_OTP_NDS_ESCK_Key1_obfuscation_Parity_bit] = {0x003C54, 5, 5},
401 [U_OTP_NDS_ESCK_Key2_obfuscation_Parity_bit] = {0x003C54, 6, 6},
402 [U_OTP_NDS_ESCK_Key3_obfuscation_Parity_bit] = {0x003C54, 7, 7},
403 [U_OTP_NDS_ESCK_Key4_obfuscation_Parity_bit] = {0x003C54, 8, 8},
404 [U_OTP_NDS_ESCK_Key5_obfuscation_Parity_bit] = {0x003C54, 9, 9},
405 [U_OTP_NDS_ESCK_Key6_obfuscation_Parity_bit] = {0x003C54, 10, 10},
406 [U_OTP_NDS_ESCK_Key7_obfuscation_Parity_bit] = {0x003C54, 11, 11},
407 [U_OTP_NDS_ESCK_Key8_obfuscation_Parity_bit] = {0x003C54, 12, 12},
408 [U_OTP_allow_ReadErrorRstOtp_Parity_bit] = {0x003C54, 13, 13},
409 [U_OTP_ena_ACPUUseNSK2_Parity_bit] = {0x003C54, 14, 14},
410 [U_OTP_BootMode_Parity_bit] = {0x003C54, 15, 15},
411 [U_OTP_ena_ACPU2KT_Parity_bit] = {0x003C54, 16, 16},
412 [U_OTP_ena_EMMFilter_Parity_bit] = {0x003C54, 17, 17},
413 [U_OTP_allow_NDS_Rd55AA_Parity_bit] = {0x003C54, 18, 18},
414 [U_OTP_forbid_OTPBuiltInTest_Parity_bit] = {0x003C54, 19, 19},
415 [U_OTP_allow_NSK_RNG_ROSC_Parity_bit] = {0x003C54, 20, 20},
416 [U_OTP_SecretAreaEnable_Parity_bit] = {0x003C54, 21, 21},
417 [U_OTP_forbid_SW_SPSD_Key_Parity_bit] = {0x003C54, 22, 22},
418 [U_OTP_allow_OTP_BgCRC_Parity_bit] = {0x003C54, 23, 23},
419 [U_OTP_forbid_USBSlaveMode_Parity_bit] = {0x003C54, 24, 24},
420 [U_OTP_OTPWritePWDProtect_Parity_bit] = {0x003C54, 25, 25},
421 [U_OTP_ena_NSK2_Parity_bit] = {0x003C54, 26, 26},
422 [U_OTP_NDS_Reserved8] = {0x003C54, 31, 27},
423 [U_OTP_ena_ESAAlgo_invalidate] = {0x003C58, 3, 0},
424 [U_OTP_ena_LocalAlgo_Invalidate] = {0x003C58, 7, 4},
425 [U_OTP_ContentProtEn] = {0x003C58, 11, 8},
426 [U_OTP_concurrency_configuration] = {0x003C58, 13, 12},
427 [U_OTP_allow_NSK_RNG_ROSC] = {0x003C58, 15, 14},
428 [U_OTP_nds_fc_disable] = {0x003C58, 16, 16},
429 [U_OTP_NDS_CPNR0_sel] = {0x003C58, 17, 17},
430 [U_OTP_NDS_CPNR_off] = {0x003C58, 18, 18},
431 [U_OTP_NDS_Reserved9] = {0x003C58, 31, 19},
432 [U_OTP_PM51_ST_ADDR] = {0x003C5C, 11, 0},
433 [U_OTP_PM51_ED_ADDR] = {0x003C5C, 23, 12},
434 [U_OTP_forbid_PM51ReadOTP] = {0x003C5C, 25, 24},
435 [U_OTP_forbid_PM51WriteOTP] = {0x003C5C, 27, 26},
436 [U_OTP_allow_PM51] = {0x003C5C, 29, 28},
437 [U_OTP_PM51_SW_R2] = {0x003C5C, 31, 30},
438 [U_OTP_forbid_CLK_SEED_TEST] = {0x003C60, 0, 0},
439 [U_OTP_MOBF_TOP_use_DES] = {0x003C60, 1, 1},
440 [U_OTP_OBFUSCATEVideoStream] = {0x003C60, 3, 2},
441 [U_OTP_forbid_EJTAG_Pinshare] = {0x003C60, 5, 4},
442 [U_OTP_allow_clear_sram] = {0x003C60, 6, 6},
443 [U_OTP_forbid_dft_md_sram] = {0x003C60, 7, 7},
444 [U_OTP_LINK_ISOEN2GPIO4] = {0x003C60, 8, 8},
445 [U_OTP_PM_SLEEP_WR_PROT_EN] = {0x003C60, 9, 9},
446 [U_OTP_PWR_HW_RST_MODE_EN] = {0x003C60, 10, 10},
447 [U_OTP_ISOC_TST_DIG_EN_GATE] = {0x003C60, 11, 11},
448 [U_OTP_OTHERS_Reserved0] = {0x003C60, 15, 12},
449 [U_OTP_Rsv_Feature] = {0x003C60, 31, 16},
450 [U_OTP_forbid_CA_MCM] = {0x003C64, 2, 0},
451 [U_OTP_forbid_DIAMOND_PMU] = {0x003C64, 5, 3},
452 [U_OTP_allow_force_dual_core] = {0x003C64, 6, 6},
453 [U_OTP_disable_jpi] = {0x003C64, 7, 7},
454 [U_OTP_forbid_DIG_PMU] = {0x003C64, 10, 8},
455 [U_OTP_forbid_WHOLECHIP_alive_when_NOCORE_alive] = {0x003C64, 13, 11},
456 [U_OTP_OTHERS_Reserved2] = {0x003C64, 15, 14},
457 [U_OTP_allow_CORE0_always_alive] = {0x003C64, 18, 16},
458 [U_OTP_allow_NONCORE0_default_reset] = {0x003C64, 21, 19},
459 [U_OTP_pwrgd_int_en] = {0x003C64, 22, 22},
460 [U_OTP_OTHERS_Reserved3] = {0x003C64, 31, 23},
461 [U_OTP_LOGICBIST_SCAN_OUT_CRC32] = {0x003C68, 31, 0},
462 [U_OTP_OTHERS_Reserved4] = {0x003C6C, 31, 0},
463 [U_OTP_RC_OPTION] = {0x003C70, 7, 0},
464 [U_OTP_RC_OPTION_EN] = {0x003C70, 8, 8},
465 [U_OTP_GCR_TRVBG] = {0x003C70, 14, 9},
466 [U_OTP_OTHERS_Reserved5] = {0x003C70, 15, 15},
467 [U_OTP_TEST_Status_TE] = {0x003C70, 23, 16},
468 [U_OTP_TEST_Status] = {0x003C70, 31, 24},
469 [U_OTP_ena_PVRNS2S] = {0x003C74, 3, 0},
470 [U_OTP_ena_PVRS2NS] = {0x003C74, 7, 4},
471 [U_OTP_ena_PlayBackRec0] = {0x003C74, 11, 8},
472 [U_OTP_ena_PlayBackRec1] = {0x003C74, 15, 12},
473 [U_OTP_ena_PlayBackRec2] = {0x003C74, 19, 16},
474 [U_OTP_ena_PlayBackRec3] = {0x003C74, 23, 20},
475 [U_OTP_ena_PlayBackRec4] = {0x003C74, 27, 24},
476 [U_OTP_ena_PlayBackRec5] = {0x003C74, 31, 28},
477 [U_OTP_ena_PVR_secure_protect_0] = {0x003C78, 3, 0},
478 [U_OTP_ena_PVR_secure_protect_1] = {0x003C78, 7, 4},
479 [U_OTP_ena_VQ_secure_protect_0] = {0x003C78, 11, 8},
480 [U_OTP_TSP_Reserved0] = {0x003C78, 15, 12},
481 [U_OTP_dis_TSO] = {0x003C78, 19, 16},
482 [U_OTP_ena_TS2TSO_0] = {0x003C78, 23, 20},
483 [U_OTP_ena_TS2TSO_1] = {0x003C78, 27, 24},
484 [U_OTP_ena_TSO_SecRange] = {0x003C78, 31, 28},
485 [U_OTP_CAVIDEnforcedTS0] = {0x003C7C, 5, 0},
486 [U_OTP_CAVIDEnforcedTS1] = {0x003C7C, 11, 6},
487 [U_OTP_CAVIDEnforcedTS2] = {0x003C7C, 17, 12},
488 [U_OTP_CAVIDEnforcedTS3] = {0x003C7C, 23, 18},
489 [U_OTP_CAVIDEnforcedTS4] = {0x003C7C, 29, 24},
490 [U_OTP_TSP_Reserved1] = {0x003C7C, 31, 30},
491 [U_OTP_CAVIDEnforcedTS5] = {0x003C80, 5, 0},
492 [U_OTP_ForbidAVtoSec] = {0x003C80, 6, 6},
493 [U_OTP_TSP_Reserved2] = {0x003C80, 7, 7},
494 [U_OTP_dis_clear_stream_to_PVR] = {0x003C80, 11, 8},
495 [U_OTP_forbid_SW_SPSD_Key] = {0x003C80, 13, 12},
496 [U_OTP_forbid_KL_SPSD_Key] = {0x003C80, 15, 14},
497 [U_OTP_allow_TSPCPUCodeProt] = {0x003C80, 17, 16},
498 [U_OTP_TSP_Reserved3] = {0x003C80, 31, 18},
499 [U_OTP_ena_KeyLadder_0_lock] = {0x003C84, 3, 0},
500 [U_OTP_ena_KeyLadder_1_lock] = {0x003C84, 7, 4},
501 [U_OTP_ena_NSK2_lock] = {0x003C84, 11, 8},
502 [U_OTP_ena_CERT_IP_lock] = {0x003C84, 15, 12},
503 [U_OTP_ena_DMA_lock] = {0x003C84, 19, 16},
504 [U_OTP_ena_SCPU_lock] = {0x003C84, 23, 20},
505 [U_OTP_Dlock_Reserved0] = {0x003C84, 31, 24},
506 [U_OTP_ena_ACPU2KT_lock] = {0x003C88, 3, 0},
507 [U_OTP_ena_NSK2KT_lock] = {0x003C88, 7, 4},
508 [U_OTP_ena_KL2KT_lock] = {0x003C88, 11, 8},
509 [U_OTP_ena_SCPU2KT_lock] = {0x003C88, 15, 12},
510 [U_OTP_ena_ACPU2DMA_lock] = {0x003C88, 19, 16},
511 [U_OTP_ena_DMA_DESBasedCipher_lock] = {0x003C88, 23, 20},
512 [U_OTP_Dlock_Reserved1] = {0x003C88, 31, 24},
513 [U_OTP_ena_LSACPCM_lock] = {0x003C8C, 3, 0},
514 [U_OTP_ena_AESBasedCipher_lock] = {0x003C8C, 7, 4},
515 [U_OTP_ena_DESBasedCipher_lock] = {0x003C8C, 11, 8},
516 [U_OTP_ena_3DESBasedCipher_lock] = {0x003C8C, 15, 12},
517 [U_OTP_ena_Multi2BasedCipher_lock] = {0x003C8C, 19, 16},
518 [U_OTP_ena_DVBCSA2ConfCipher_lock] = {0x003C8C, 23, 20},
519 [U_OTP_ena_DVBCSA2Cipher_lock] = {0x003C8C, 27, 24},
520 [U_OTP_ena_DVBCSA3BasedCipher_lock] = {0x003C8C, 31, 28},
521 [U_OTP_dis_kl0_hostkey_lock] = {0x003C90, 3, 0},
522 [U_OTP_dis_kl1_hostkey_lock] = {0x003C90, 7, 4},
523 [U_OTP_NDSKeyValid_lock] = {0x003C90, 11, 8},
524 [U_OTP_RC_OPTION_lock] = {0x003C90, 15, 12},
525 [U_OTP_Dlock_Reserved2] = {0x003C90, 31, 16},
526 [U_OTP_Dlock_Reserved3] = {0x003C94, 31, 0},
527 [U_OTP_LockWord_CA_reserved0_W] = {0x003C98, 1, 0},
528 [U_OTP_LockWord_CA_reserved1_W] = {0x003C98, 3, 2},
529 [U_OTP_LockWord_CA_reserved2_W] = {0x003C98, 5, 4},
530 [U_OTP_LockWord_CA_reserved3_W] = {0x003C98, 7, 6},
531 [U_OTP_LockWord_CA_reserved4_W] = {0x003C98, 9, 8},
532 [U_OTP_LockWord_CA_reserved5_W] = {0x003C98, 11, 10},
533 [U_OTP_LockWord_CA_reserved6_W] = {0x003C98, 13, 12},
534 [U_OTP_LockWord_CA_reserved7_W] = {0x003C98, 15, 14},
535 [U_OTP_LockWord_CA_reserved8_W] = {0x003C98, 17, 16},
536 [U_OTP_LockWord_CA_reserved9_W] = {0x003C98, 19, 18},
537 [U_OTP_LockWord_CA_reserved10_W] = {0x003C98, 21, 20},
538 [U_OTP_LockWord_CA_reserved11_W] = {0x003C98, 23, 22},
539 [U_OTP_LockWord_CA_reserved12_W] = {0x003C98, 25, 24},
540 [U_OTP_LockWord_CA_reserved13_W] = {0x003C98, 27, 26},
541 [U_OTP_LockWord_CA_reserved14_W] = {0x003C98, 29, 28},
542 [U_OTP_LockWord_CA_reserved15_W] = {0x003C98, 31, 30},
543 [U_OTP_LockWord_RSA_0_W] = {0x003C9C, 1, 0},
544 [U_OTP_LockWord_RSA_1_W] = {0x003C9C, 3, 2},
545 [U_OTP_LockWord_RSA_CTRL_W] = {0x003C9C, 5, 4},
546 [U_OTP_LockWord_IXSC_Config_W] = {0x003C9C, 7, 6},
547 [U_OTP_LockWord_v_PubOtpOID_W] = {0x003C9C, 9, 8},
548 [U_OTP_LockWord_v_PubOtpVID_W] = {0x003C9C, 11, 10},
549 [U_OTP_LockWord_v_PubOtpBID_W] = {0x003C9C, 13, 12},
550 [U_OTP_LockWord_v_PubOtpRsaIndex_W] = {0x003C9C, 15, 14},
551 [U_OTP_LockWord_v_PubOtpMinConfVer_W] = {0x003C9C, 17, 16},
552 [U_OTP_LockWord_VenderConstSel_W] = {0x003C9C, 19, 18},
553 [U_OTP_LockWord_NDS_info_W] = {0x003C9C, 21, 20},
554 [U_OTP_LockWord_PM51_W] = {0x003C9C, 23, 22},
555 [U_OTP_LockWord_OTHERS_W] = {0x003C9C, 25, 24},
556 [U_OTP_LockWord_Reserved0] = {0x003C9C, 31, 26},
557 [U_OTP_LockWord_NOCS3_MEM0_W] = {0x003CA0, 1, 0},
558 [U_OTP_LockWord_NOCS3_MEM1_W] = {0x003CA0, 3, 2},
559 [U_OTP_LockWord_NOCS3_MEM2_W] = {0x003CA0, 5, 4},
560 [U_OTP_LockWord_NOCS3_MEM3_W] = {0x003CA0, 7, 6},
561 [U_OTP_LockWord_MSID_W] = {0x003CA0, 9, 8},
562 [U_OTP_LockWord_CFG_STB_CA_SN_W] = {0x003CA0, 11, 10},
563 [U_OTP_LockWord_TSP_W] = {0x003CA0, 13, 12},
564 [U_OTP_LockWord_PGMask_W] = {0x003CA0, 15, 14},
565 [U_OTP_LockWord_ClkDet_Para_W] = {0x003CA0, 17, 16},
566 [U_OTP_LockWord_OTP_CTRL_W] = {0x003CA0, 19, 18},
567 [U_OTP_LockWord_CPU_bank_W] = {0x003CA0, 21, 20},
568 [U_OTP_LockWord_trimming_W] = {0x003CA0, 23, 22},
569 [U_OTP_LockWord_BOND0_W] = {0x003CA0, 25, 24},
570 [U_OTP_LockWord_BOND_Reserved_W] = {0x003CA0, 27, 26},
571 [U_OTP_LockWord_Reserved1] = {0x003CA0, 31, 28},
572 [U_OTP_LockWord_LOT_INFO_W] = {0x003CA4, 1, 0},
573 [U_OTP_LockWord_CA_Enable_W] = {0x003CA4, 3, 2},
574 [U_OTP_LockWord_KL_bank_W] = {0x003CA4, 5, 4},
575 [U_OTP_LockWord_KT_bank_W] = {0x003CA4, 7, 6},
576 [U_OTP_LockWord_DMA_bank_W] = {0x003CA4, 9, 8},
577 [U_OTP_LockWord_TSCE_W] = {0x003CA4, 11, 10},
578 [U_OTP_LockWord_HDCP_KEY_W] = {0x003CA4, 13, 12},
579 [U_OTP_LockWord_Multi2SysKey_W] = {0x003CA4, 15, 14},
580 [U_OTP_LockWord_CAV_Key1_W] = {0x003CA4, 17, 16},
581 [U_OTP_LockWord_CAV_Key2_W] = {0x003CA4, 19, 18},
582 [U_OTP_LockWord_CAV_Key3_W] = {0x003CA4, 21, 20},
583 [U_OTP_LockWord_CAV_Key4_W] = {0x003CA4, 23, 22},
584 [U_OTP_LockWord_CAV_Key5_W] = {0x003CA4, 25, 24},
585 [U_OTP_LockWord_CAV_Key6_W] = {0x003CA4, 27, 26},
586 [U_OTP_LockWord_CAV_Key7_W] = {0x003CA4, 29, 28},
587 [U_OTP_LockWord_CAV_Key8_W] = {0x003CA4, 31, 30},
588 [U_OTP_LockWord_CAVID_W] = {0x003CA8, 1, 0},
589 [U_OTP_LockWord_CAV_KP1_W] = {0x003CA8, 3, 2},
590 [U_OTP_LockWord_CAV_KP2_W] = {0x003CA8, 5, 4},
591 [U_OTP_LockWord_CAV_KP3_W] = {0x003CA8, 7, 6},
592 [U_OTP_LockWord_CAV_KP4_W] = {0x003CA8, 9, 8},
593 [U_OTP_LockWord_CAV_KP5_W] = {0x003CA8, 11, 10},
594 [U_OTP_LockWord_CAV_KP6_W] = {0x003CA8, 13, 12},
595 [U_OTP_LockWord_CAV_KP7_W] = {0x003CA8, 15, 14},
596 [U_OTP_LockWord_CAV_KP8_W] = {0x003CA8, 17, 16},
597 [U_OTP_LockWord_CAV_KP9_W] = {0x003CA8, 19, 18},
598 [U_OTP_LockWord_CAV_KP10_W] = {0x003CA8, 21, 20},
599 [U_OTP_LockWord_CAV_KP11_W] = {0x003CA8, 23, 22},
600 [U_OTP_LockWord_CAV_KP12_W] = {0x003CA8, 25, 24},
601 [U_OTP_LockWord_CAV_KP13_W] = {0x003CA8, 27, 26},
602 [U_OTP_LockWord_CAV_KP14_W] = {0x003CA8, 29, 28},
603 [U_OTP_LockWord_CAV_KP15_W] = {0x003CA8, 31, 30},
604 [U_OTP_LockWord_PubOTPUniqueID1_W] = {0x003CAC, 1, 0},
605 [U_OTP_LockWord_PubOTPUniqueID2_W] = {0x003CAC, 3, 2},
606 [U_OTP_LockWord_PubOTPUniqueID3_W] = {0x003CAC, 5, 4},
607 [U_OTP_LockWord_PubOTPUniqueID4_W] = {0x003CAC, 7, 6},
608 [U_OTP_LockWord_AES_MOD_MASK_W] = {0x003CAC, 9, 8},
609 [U_OTP_LockWord_ACPU_Property_W] = {0x003CAC, 11, 10},
610 [U_OTP_LockWord_SCPU_Property_W] = {0x003CAC, 13, 12},
611 [U_OTP_LockWord_CA_PWD_W] = {0x003CAC, 15, 14},
612 [U_OTP_LockWord_CA_PWD_CTRL_W] = {0x003CAC, 17, 16},
613 [U_OTP_LockWord_VtrackData_W] = {0x003CAC, 19, 18},
614 [U_OTP_LockWord_FAKE_W] = {0x003CAC, 21, 20},
615 [U_OTP_LockWord_SW0_W] = {0x003CAC, 23, 22},
616 [U_OTP_LockWord_Reserved2] = {0x003CAC, 31, 26},
617 [U_OTP_LockWord_0000_0511_W] = {0x003CB0, 1, 0},
618 [U_OTP_LockWord_0512_1023_W] = {0x003CB0, 3, 2},
619 [U_OTP_LockWord_1024_1535_W] = {0x003CB0, 5, 4},
620 [U_OTP_LockWord_1536_2047_W] = {0x003CB0, 7, 6},
621 [U_OTP_LockWord_2048_2559_W] = {0x003CB0, 9, 8},
622 [U_OTP_LockWord_2560_3071_W] = {0x003CB0, 11, 10},
623 [U_OTP_LockWord_3072_3391_W] = {0x003CB0, 13, 12},
624 [U_OTP_LockWord_Chip_Extension_ID] = {0x003CB0, 15, 14},
625 [U_OTP_LockWord_Reserved3] = {0x003CB0, 31, 16},
626 [U_OTP_LockWord_CAV_Key1_R] = {0x003CB4, 1, 0},
627 [U_OTP_LockWord_CAV_Key2_R] = {0x003CB4, 3, 2},
628 [U_OTP_LockWord_CAV_Key3_R] = {0x003CB4, 5, 4},
629 [U_OTP_LockWord_CAV_Key4_R] = {0x003CB4, 7, 6},
630 [U_OTP_LockWord_CAV_Key5_R] = {0x003CB4, 9, 8},
631 [U_OTP_LockWord_CAV_Key6_R] = {0x003CB4, 11, 10},
632 [U_OTP_LockWord_CAV_Key7_R] = {0x003CB4, 13, 12},
633 [U_OTP_LockWord_CAV_Key8_R] = {0x003CB4, 15, 14},
634 [U_OTP_LockWord_RSA_0_R] = {0x003CB4, 17, 16},
635 [U_OTP_LockWord_RSA_1_R] = {0x003CB4, 19, 18},
636 [U_OTP_LockWord_HDCP_KEY_R] = {0x003CB4, 21, 20},
637 [U_OTP_LockWord_Multi2SysKey_R] = {0x003CB4, 23, 22},
638 [U_OTP_LockWord_AES_MOD_MASK_R] = {0x003CB4, 25, 24},
639 [U_OTP_LockWord_VtrackData_R] = {0x003CB4, 27, 26},
640 [U_OTP_LockWord_CA_PWD_R] = {0x003CB4, 29, 28},
641 [U_OTP_LockWord_Reserved4] = {0x003CB4, 31, 30},
642 [U_OTP_ClkDet_Para] = {0x003CB8, 63, 0},
643 [U_OTP_forbid_ACPUWriteOTP] = {0x003CC0, 1, 0},
644 [U_OTP_forbid_ACPUReadOTP] = {0x003CC0, 3, 2},
645 [U_OTP_forbid_SCPUWriteOTP] = {0x003CC0, 5, 4},
646 [U_OTP_forbid_SCPUReadOTP] = {0x003CC0, 7, 6},
647 [U_OTP_forbid_DBBUSWriteOTP] = {0x003CC0, 9, 8},
648 [U_OTP_forbid_DBBUSReadOTP] = {0x003CC0, 11, 10},
649 [U_OTP_allow_RANDOM] = {0x003CC0, 13, 12},
650 [U_OTP_allow_NOISE_Rd] = {0x003CC0, 15, 14},
651 [U_OTP_allow_OTP_BgCRC] = {0x003CC0, 17, 16},
652 [U_OTP_allow_SKIP_0] = {0x003CC0, 19, 18},
653 [U_OTP_allow_SKIP_1] = {0x003CC0, 21, 20},
654 [U_OTP_allow_Mask_AES] = {0x003CC0, 23, 22},
655 [U_OTP_ena_Mstar_Wrapper] = {0x003CC0, 25, 24},
656 [U_OTP_CTRL_Reserved0] = {0x003CC0, 31, 26},
657 [U_OTP_allow_XOR_ROMCODE] = {0x003CC4, 6, 0},
658 [U_OTP_allow_XOR_FIX] = {0x003CC4, 7, 7},
659 [U_OTP_allow_PWD_OTP_prog] = {0x003CC4, 9, 8},
660 [U_OTP_CTRL_Reserved1] = {0x003CC4, 31, 10},
661 [U_OTP_SBoot] = {0x003CC8, 3, 0},
662 [U_OTP_SecretAreaEnable] = {0x003CC8, 7, 4},
663 [U_OTP_forbid_TestInOut] = {0x003CC8, 9, 8},
664 [U_OTP_allow_FlashProtect] = {0x003CC8, 11, 10},
665 [U_OTP_PERSO_done] = {0x003CC8, 13, 12},
666 [U_OTP_CERT_PERSO_done] = {0x003CC8, 15, 14},
667 [U_OTP_DBUG_Reserved0] = {0x003CC8, 31, 16},
668 [U_OTP_SCAN_MODE] = {0x003CCC, 8, 0},
669 [U_OTP_DBUG_Reserved1] = {0x003CCC, 9, 9},
670 [U_OTP_MBIST_MODE] = {0x003CCC, 15, 10},
671 [U_OTP_I2C_MODE] = {0x003CCC, 21, 16},
672 [U_OTP_DBUG_Reserved2] = {0x003CCC, 25, 22},
673 [U_OTP_EJTAG_MODE] = {0x003CCC, 31, 26},
674 [U_OTP_RMA_MODE] = {0x003CD0, 5, 0},
675 [U_OTP_LicRework] = {0x003CD0, 7, 6},
676 [U_OTP_forbid_USBSlaveMode] = {0x003CD0, 11, 8},
677 [U_OTP_allow_DRAM_MOBF] = {0x003CD0, 13, 12},
678 [U_OTP_allow_DRAMOBF_4ROUND] = {0x003CD0, 15, 14},
679 [U_OTP_ena_DRAMOBF_NS_MASK_ADDR] = {0x003CD0, 17, 16},
680 [U_OTP_forbid_clk_otp_sel] = {0x003CD0, 20, 18},
681 [U_OTP_forbid_acpu_access_sec_bridge] = {0x003CD0, 23, 21},
682 [U_OTP_forbid_dbbus_access_sec_bridge] = {0x003CD0, 26, 24},
683 [U_OTP_XPM_State] = {0x003CD0, 29, 27},
684 [U_OTP_DBUG_Reserved3] = {0x003CD0, 31, 30},
685 [U_OTP_DeactiveDRAMBoot] = {0x003CD4, 3, 0},
686 [U_OTP_ACPU_Reserved0] = {0x003CD4, 7, 4},
687 [U_OTP_BootMode] = {0x003CD4, 13, 8},
688 [U_OTP_forbid_BCKGND_CHK] = {0x003CD4, 15, 14},
689 [U_OTP_SCPUBootMode] = {0x003CD4, 21, 16},
690 [U_OTP_ACPU_Reserved1] = {0x003CD4, 23, 22},
691 [U_OTP_PM_MCU_RST_MOD] = {0x003CD4, 26, 24},
692 [U_OTP_boot_host_sel] = {0x003CD4, 29, 27},
693 [U_OTP_ACPU_Reserved2] = {0x003CD4, 31, 30},
694 [U_OTP_ACPU_Reserved3] = {0x003CD8, 11, 0},
695 [U_OTP_PostMskAreaRangeU] = {0x003CD8, 23, 12},
696 [U_OTP_ACPUasHost] = {0x003CD8, 26, 24},
697 [U_OTP_BONDING] = {0x003CD8, 28, 27},
698 [U_OTP_NON_BLANK] = {0x003CD8, 29, 29},
699 [U_OTP_ACPU_Reserved4] = {0x003CD8, 31, 30},
700 [U_OTP_PE_LOT_INFO] = {0x003CDC, 47, 0},
701 [U_OTP_BootDevice] = {0x003CDC, 55, 48},
702 [U_OTP_MAX_RDNTBLK] = {0x003CDC, 61, 56},
703 [U_OTP_forbid_STR] = {0x003CDC, 63, 62},
704 [U_OTP_Bootcode_project] = {0x003CE4, 7, 0},
705 [U_OTP_Bootcode_subversion] = {0x003CE4, 15, 8},
706 [U_OTP_Bootcode_version] = {0x003CE4, 31, 16},
707 [U_OTP_Analog_Usage] = {0x003CE8, 63, 0},
708 [U_OTP_Analog_Usage2] = {0x003CF0, 95, 0},
709 [U_OTP_trim_dac] = {0x003CFC, 125, 0},
710 [U_OTP_Trim_Reserved0] = {0x003CFC, 127, 126},
711 [U_OTP_BOND0] = {0x003D0C, 95, 0},
712 [U_OTP_BOND_Reserved] = {0x003D18, 95, 0},
713 [U_OTP_ena_KeyLadder_0] = {0x003D24, 3, 0},
714 [U_OTP_ena_KeyLadder_1] = {0x003D24, 7, 4},
715 [U_OTP_ena_NSK2] = {0x003D24, 11, 8},
716 [U_OTP_ena_CERT_IP] = {0x003D24, 13, 12},
717 [U_OTP_ena_DMA] = {0x003D24, 15, 14},
718 [U_OTP_ena_SCPU] = {0x003D24, 19, 16},
719 [U_OTP_CA_EN_Reserved0] = {0x003D24, 31, 20},
720 [U_OTP_allow_IXSC] = {0x003D28, 3, 0},
721 [U_OTP_forbid_IXSC] = {0x003D28, 7, 4},
722 [U_OTP_forbid_PAVOSC] = {0x003D28, 9, 8},
723 [U_OTP_cfDeactiveFuse] = {0x003D28, 10, 10},
724 [U_OTP_SOC_UID_SEL] = {0x003D28, 12, 11},
725 [U_OTP_CA_EN_Reserved2] = {0x003D28, 31, 13},
726 [U_OTP_dis_kl0_hostkey] = {0x003D2C, 1, 0},
727 [U_OTP_dis_kl1_hostkey] = {0x003D2C, 3, 2},
728 [U_OTP_dis_kl0_hostkey_property] = {0x003D2C, 5, 4},
729 [U_OTP_dis_kl1_hostkey_property] = {0x003D2C, 7, 6},
730 [U_OTP_kl_protect0_mode] = {0x003D2C, 9, 8},
731 [U_OTP_kl_protect1_mode] = {0x003D2C, 11, 10},
732 [U_OTP_kl_protect2_mode] = {0x003D2C, 13, 12},
733 [U_OTP_kl_protect3_mode] = {0x003D2C, 15, 14},
734 [U_OTP_dis_kl_protect0] = {0x003D2C, 17, 16},
735 [U_OTP_dis_kl_protect1] = {0x003D2C, 19, 18},
736 [U_OTP_dis_kl_protect2] = {0x003D2C, 21, 20},
737 [U_OTP_dis_kl_protect3] = {0x003D2C, 23, 22},
738 [U_OTP_dis_kl_protect4] = {0x003D2C, 25, 24},
739 [U_OTP_kl_TA_LUT0_mode] = {0x003D2C, 27, 26},
740 [U_OTP_kl_TA_LUT1_mode] = {0x003D2C, 29, 28},
741 [U_OTP_ena_kl_StopClkChk] = {0x003D2C, 31, 30},
742 [U_OTP_KDF_secret_mask] = {0x003D30, 127, 0},
743 [U_OTP_IMLB_ROTATION] = {0x003D40, 15, 0},
744 [U_OTP_IrdetoTweakedCSAv3] = {0x003D40, 17, 16},
745 [U_OTP_allow_SPSSPDKeyShuffle] = {0x003D40, 21, 18},
746 [U_OTP_kl_BISS_MODE] = {0x003D40, 23, 22},
747 [U_OTP_ena_kl_xor_func] = {0x003D40, 25, 24},
748 [U_OTP_KL_Reserved2] = {0x003D40, 31, 26},
749 [U_OTP_ena_ACPU2KT] = {0x003D44, 3, 0},
750 [U_OTP_ena_NSK2KT] = {0x003D44, 7, 4},
751 [U_OTP_ena_KL2KT] = {0x003D44, 11, 8},
752 [U_OTP_ena_SCPU2KT] = {0x003D44, 15, 12},
753 [U_OTP_ena_ACPUWrNSKKey2KT] = {0x003D44, 19, 16},
754 [U_OTP_ena_ACPUWrCFBKey2KT] = {0x003D44, 23, 20},
755 [U_OTP_ena_NSKCW2CryptoDMA] = {0x003D44, 27, 24},
756 [U_OTP_ena_ACPU2LSA] = {0x003D44, 31, 28},
757 [U_OTP_BISS_MODE] = {0x003D48, 3, 0},
758 [U_OTP_BISS_SUBMODE] = {0x003D48, 5, 4},
759 [U_OTP_KT_Reserved0] = {0x003D48, 31, 6},
760 [U_OTP_ena_ACPU2DMA] = {0x003D4C, 3, 0},
761 [U_OTP_ena_DMA_DESBasedCipher] = {0x003D4C, 7, 4},
762 [U_OTP_ena_AESMAC_MaxRate] = {0x003D4C, 9, 8},
763 [U_OTP_allow_DMAtDES2KeyEQChk] = {0x003D4C, 12, 10},
764 [U_OTP_DMA_Reserved0] = {0x003D4C, 13, 13},
765 [U_OTP_ena_DMA_ClearKeySlot ] = {0x003D4C, 15, 14},
766 [U_OTP_dis_DMA_mask_engine] = {0x003D4C, 17, 16},
767 [U_OTP_DMA_Reserved1] = {0x003D4C, 31, 18},
768 [U_OTP_ena_LSACPCM] = {0x003D50, 3, 0},
769 [U_OTP_ena_AESBasedCipher] = {0x003D50, 7, 4},
770 [U_OTP_ena_DESBasedCipher] = {0x003D50, 11, 8},
771 [U_OTP_ena_3DESBasedCipher] = {0x003D50, 15, 12},
772 [U_OTP_ena_Multi2BasedCipher] = {0x003D50, 19, 16},
773 [U_OTP_ena_DVBCSA2ConfCipher] = {0x003D50, 23, 20},
774 [U_OTP_ena_DVBCSA2Cipher] = {0x003D50, 27, 24},
775 [U_OTP_ena_DVBCSA3BasedCipher] = {0x003D50, 31, 28},
776 [U_OTP_Ch_SwitchComb] = {0x003D54, 63, 0},
777 [U_OTP_ena_LSAD_MDI] = {0x003D5C, 3, 0},
778 [U_OTP_ena_LSAD_MDD] = {0x003D5C, 7, 4},
779 [U_OTP_ena_LSAD_CIPLUS_AES] = {0x003D5C, 11, 8},
780 [U_OTP_ena_LSAD_AES_ECB_CLEAR] = {0x003D5C, 15, 12},
781 [U_OTP_ena_LSAD_SCTE41_SCTE52_DES] = {0x003D5C, 19, 16},
782 [U_OTP_TSCE_Reserved0] = {0x003D5C, 31, 20},
783 [U_OTP_ena_ESA_CIPLUS_AES] = {0x003D60, 3, 0},
784 [U_OTP_ena_ESA_CIPLUS_DES] = {0x003D60, 7, 4},
785 [U_OTP_ena_ESA_SCTE52_DES] = {0x003D60, 11, 8},
786 [U_OTP_ena_ESA_tDES_CBC_CLEAR] = {0x003D60, 15, 12},
787 [U_OTP_TSCE_Reserved1] = {0x003D60, 31, 16},
788 [U_OTP_ena_LSAS_MDI] = {0x003D64, 3, 0},
789 [U_OTP_ena_LSAS_MDD] = {0x003D64, 7, 4},
790 [U_OTP_ena_LSAS_CIPLUS_AES] = {0x003D64, 11, 8},
791 [U_OTP_ena_LSAS_AES_ECB_CLEAR] = {0x003D64, 15, 12},
792 [U_OTP_ena_LSAS_SCTE41_SCTE52_DES] = {0x003D64, 19, 16},
793 [U_OTP_TSCE_Reserved2] = {0x003D64, 31, 20},
794 [U_OTP_ena_DRMAreaEncrypt] = {0x003D68, 3, 0},
795 [U_OTP_ena_ReviewFailPkt] = {0x003D68, 7, 4},
796 [U_OTP_dis_NonSecRangeEncrypt] = {0x003D68, 11, 8},
797 [U_OTP_TSCE_Reserved3] = {0x003D68, 31, 12},
798 [U_OTP_ena_CA_PVR_secure_protect_0] = {0x003D6C, 3, 0},
799 [U_OTP_ena_CA_PVR_secure_protect_1] = {0x003D6C, 7, 4},
800 [U_OTP_ena_CA_PVR_secure_protect_2] = {0x003D6C, 11, 8},
801 [U_OTP_ena_CA_PVR_secure_protect_3] = {0x003D6C, 15, 12},
802 [U_OTP_ena_LowerPathRec] = {0x003D6C, 19, 16},
803 [U_OTP_ena_SWMulti2SysKey] = {0x003D6C, 23, 20},
804 [U_OTP_TSCE_Reserved4] = {0x003D6C, 31, 24},
805 [U_OTP_HDCP_KEY] = {0x003D70, 55, 0},
806 [U_OTP_HDCP_Reserved0] = {0x003D70, 7, 0},
807 [U_OTP_Multi2SysKey] = {0x003D78, 255, 0},
808 [U_OTP_AES_MOD_MASK] = {0x003D98, 127, 0},
809 [U_OTP_v_pubOtpUniqueID1] = {0x003DA8, 63, 0},
810 [U_OTP_v_pubOtpUniqueID2] = {0x003DB0, 63, 0},
811 [U_OTP_v_pubOtpUniqueID3] = {0x003DB8, 63, 0},
812 [U_OTP_v_pubOtpUniqueID4] = {0x003DC0, 63, 0},
813 [U_OTP_CAV_ESCK_KeyValid] = {0x003DC8, 7, 0},
814 [U_OTP_CAV_Reserved0] = {0x003DC8, 15, 8},
815 [U_OTP_CAV_SCK_KeyValid] = {0x003DC8, 31, 16},
816 [U_OTP_CAV_Reserved1] = {0x003DCC, 31, 0},
817 [U_OTP_CAV_Key1_SCK_mapping] = {0x003DD0, 15, 0},
818 [U_OTP_CAV_Key1_integrity_chk] = {0x003DD0, 17, 16},
819 [U_OTP_CAV_Key1_allow_ChkNum] = {0x003DD0, 19, 18},
820 [U_OTP_CAV_Key1_obfuscation] = {0x003DD0, 21, 20},
821 [U_OTP_CAV_Key1_IdSel] = {0x003DD0, 23, 22},
822 [U_OTP_CAV_Key1_KeySel] = {0x003DD0, 29, 24},
823 [U_OTP_CAV_Key1_reserved] = {0x003DD0, 31, 30},
824 [U_OTP_CAV_Key1_ChkNum_Gold] = {0x003DD4, 31, 0},
825 [U_OTP_CAV_Key2_SCK_mapping] = {0x003DD8, 15, 0},
826 [U_OTP_CAV_Key2_integrity_chk] = {0x003DD8, 17, 16},
827 [U_OTP_CAV_Key2_allow_ChkNum] = {0x003DD8, 19, 18},
828 [U_OTP_CAV_Key2_obfuscation] = {0x003DD8, 21, 20},
829 [U_OTP_CAV_Key2_IdSel] = {0x003DD8, 23, 22},
830 [U_OTP_CAV_Key2_KeySel] = {0x003DD8, 29, 24},
831 [U_OTP_CAV_Key2_reserved] = {0x003DD8, 31, 30},
832 [U_OTP_CAV_Key2_ChkNum_Gold] = {0x003DDC, 31, 0},
833 [U_OTP_CAV_Key3_SCK_mapping] = {0x003DE0, 15, 0},
834 [U_OTP_CAV_Key3_integrity_chk] = {0x003DE0, 17, 16},
835 [U_OTP_CAV_Key3_allow_ChkNum] = {0x003DE0, 19, 18},
836 [U_OTP_CAV_Key3_obfuscation] = {0x003DE0, 21, 20},
837 [U_OTP_CAV_Key3_IdSel] = {0x003DE0, 23, 22},
838 [U_OTP_CAV_Key3_KeySel] = {0x003DE0, 29, 24},
839 [U_OTP_CAV_Key3_reserved] = {0x003DE0, 31, 30},
840 [U_OTP_CAV_Key3_ChkNum_Gold] = {0x003DE4, 31, 0},
841 [U_OTP_CAV_Key4_SCK_mapping] = {0x003DE8, 15, 0},
842 [U_OTP_CAV_Key4_integrity_chk] = {0x003DE8, 17, 16},
843 [U_OTP_CAV_Key4_allow_ChkNum] = {0x003DE8, 19, 18},
844 [U_OTP_CAV_Key4_obfuscation] = {0x003DE8, 21, 20},
845 [U_OTP_CAV_Key4_IdSel] = {0x003DE8, 23, 22},
846 [U_OTP_CAV_Key4_KeySel] = {0x003DE8, 29, 24},
847 [U_OTP_CAV_Key4_reserved] = {0x003DE8, 31, 30},
848 [U_OTP_CAV_Key4_ChkNum_Gold] = {0x003DEC, 31, 0},
849 [U_OTP_CAV_Key5_SCK_mapping] = {0x003DF0, 15, 0},
850 [U_OTP_CAV_Key5_integrity_chk] = {0x003DF0, 17, 16},
851 [U_OTP_CAV_Key5_allow_ChkNum] = {0x003DF0, 19, 18},
852 [U_OTP_CAV_Key5_obfuscation] = {0x003DF0, 21, 20},
853 [U_OTP_CAV_Key5_IdSel] = {0x003DF0, 23, 22},
854 [U_OTP_CAV_Key5_KeySel] = {0x003DF0, 29, 24},
855 [U_OTP_CAV_Key5_reserved] = {0x003DF0, 31, 30},
856 [U_OTP_CAV_Key5_ChkNum_Gold] = {0x003DF4, 31, 0},
857 [U_OTP_CAV_Key6_SCK_mapping] = {0x003DF8, 15, 0},
858 [U_OTP_CAV_Key6_integrity_chk] = {0x003DF8, 17, 16},
859 [U_OTP_CAV_Key6_allow_ChkNum] = {0x003DF8, 19, 18},
860 [U_OTP_CAV_Key6_obfuscation] = {0x003DF8, 21, 20},
861 [U_OTP_CAV_Key6_IdSel] = {0x003DF8, 23, 22},
862 [U_OTP_CAV_Key6_KeySel] = {0x003DF8, 29, 24},
863 [U_OTP_CAV_Key6_reserved] = {0x003DF8, 31, 30},
864 [U_OTP_CAV_Key6_ChkNum_Gold] = {0x003DFC, 31, 0},
865 [U_OTP_CAV_Key7_SCK_mapping] = {0x003E00, 15, 0},
866 [U_OTP_CAV_Key7_integrity_chk] = {0x003E00, 17, 16},
867 [U_OTP_CAV_Key7_allow_ChkNum] = {0x003E00, 19, 18},
868 [U_OTP_CAV_Key7_obfuscation] = {0x003E00, 21, 20},
869 [U_OTP_CAV_Key7_IdSel] = {0x003E00, 23, 22},
870 [U_OTP_CAV_Key7_KeySel] = {0x003E00, 29, 24},
871 [U_OTP_CAV_Key7_reserved] = {0x003E00, 31, 30},
872 [U_OTP_CAV_Key7_ChkNum_Gold] = {0x003E04, 31, 0},
873 [U_OTP_CAV_Key8_SCK_mapping] = {0x003E08, 15, 0},
874 [U_OTP_CAV_Key8_integrity_chk] = {0x003E08, 17, 16},
875 [U_OTP_CAV_Key8_allow_ChkNum] = {0x003E08, 19, 18},
876 [U_OTP_CAV_Key8_obfuscation] = {0x003E08, 21, 20},
877 [U_OTP_CAV_Key8_IdSel] = {0x003E08, 23, 22},
878 [U_OTP_CAV_Key8_KeySel] = {0x003E08, 29, 24},
879 [U_OTP_CAV_Key8_reserved] = {0x003E08, 31, 30},
880 [U_OTP_CAV_Key8_ChkNum_Gold] = {0x003E0C, 31, 0},
881 [U_OTP_ACPU_Property] = {0x003E10, 127, 0},
882 [U_OTP_SCPU_Property] = {0x003E20, 127, 0},
883 [U_OTP_CAV_Key1_Property] = {0x003E30, 127, 0},
884 [U_OTP_CAV_Key2_Property] = {0x003E40, 127, 0},
885 [U_OTP_CAV_Key3_Property] = {0x003E50, 127, 0},
886 [U_OTP_CAV_Key4_Property] = {0x003E60, 127, 0},
887 [U_OTP_CAV_Key5_Property] = {0x003E70, 127, 0},
888 [U_OTP_CAV_Key6_Property] = {0x003E80, 127, 0},
889 [U_OTP_CAV_Key7_Property] = {0x003E90, 127, 0},
890 [U_OTP_CAV_Key8_Property] = {0x003EA0, 127, 0},
891 [U_OTP_CAV_Key9_Property] = {0x003EB0, 127, 0},
892 [U_OTP_CAV_Key10_Property] = {0x003EC0, 127, 0},
893 [U_OTP_CAV_Key11_Property] = {0x003ED0, 127, 0},
894 [U_OTP_CAV_Key12_Property] = {0x003EE0, 127, 0},
895 [U_OTP_CAV_Key13_Property] = {0x003EF0, 127, 0},
896 [U_OTP_CAV_Key14_Property] = {0x003F00, 127, 0},
897 [U_OTP_CAV_Key15_Property] = {0x003F10, 127, 0},
898 [U_OTP_CAV_SecretKey1] = {0x003F20, 127, 0},
899 [U_OTP_CAV_SecretKey2] = {0x003F30, 127, 0},
900 [U_OTP_CAV_SecretKey3] = {0x003F40, 127, 0},
901 [U_OTP_CAV_SecretKey4] = {0x003F50, 127, 0},
902 [U_OTP_CAV_SecretKey5] = {0x003F60, 127, 0},
903 [U_OTP_CAV_SecretKey6] = {0x003F70, 127, 0},
904 [U_OTP_CAV_SecretKey7] = {0x003F80, 127, 0},
905 [U_OTP_CAV_SecretKey8] = {0x003F90, 127, 0},
906 [U_OTP_CA_PWD_integrity_chk] = {0x003FA0, 1, 0},
907 [U_OTP_Multi2SysKey_integrity_chk] = {0x003FA0, 3, 2},
908 [U_OTP_CA_PWD_Reserved0] = {0x003FA0, 7, 4},
909 [U_OTP_I2C_PWD_obfuscation] = {0x003FA0, 9, 8},
910 [U_OTP_EJTAG_PWD_obfuscation] = {0x003FA0, 11, 10},
911 [U_OTP_SCAN_PWD_obfuscation] = {0x003FA0, 13, 12},
912 [U_OTP_MBIST_PWD_obfuscation] = {0x003FA0, 15, 14},
913 [U_OTP_Multi2SysKey_CRC] = {0x003FA0, 31, 16},
914 [U_OTP_I2C_PWD_CRC] = {0x003FA4, 15, 0},
915 [U_OTP_EJTAG_PWD_CRC] = {0x003FA4, 31, 16},
916 [U_OTP_SCAN_PWD_CRC] = {0x003FA8, 15, 0},
917 [U_OTP_MBIST_PWD_CRC] = {0x003FA8, 31, 16},
918 [U_OTP_CA_PWD_Keysel] = {0x003FAC, 5, 0},
919 [U_OTP_ena_TP_PWD] = {0x003FAC, 7, 6},
920 [U_OTP_ena_KDF_I2C_PWD] = {0x003FAC, 9, 8},
921 [U_OTP_ena_KDF_EJTAG_PWD] = {0x003FAC, 11, 10},
922 [U_OTP_ena_KDF_SCAN_PWD] = {0x003FAC, 13, 12},
923 [U_OTP_ena_KDF_MBIST_PWD] = {0x003FAC, 15, 14},
924 [U_OTP_I2C_TP_ID] = {0x003FAC, 19, 16},
925 [U_OTP_EJTAG_TP_ID] = {0x003FAC, 23, 20},
926 [U_OTP_SCAN_TP_ID] = {0x003FAC, 27, 24},
927 [U_OTP_MBIST_TP_ID] = {0x003FAC, 31, 28},
928 [U_OTP_I2C_PWD] = {0x003FB0, 127, 0},
929 [U_OTP_EJTAG_PWD] = {0x003FC0, 127, 0},
930 [U_OTP_SCAN_PWD] = {0x003FD0, 127, 0},
931 [U_OTP_MBIST_PWD] = {0x003FE0, 127, 0},
932 [U_OTP_VtrackID] = {0x003FF0, 31, 0},
933 [U_OTP_VtrackKey] = {0x003FF4, 31, 0},
934 [U_OTP_VtrackID_select] = {0x003FF8, 0, 0},
935 [U_OTP_VtrackKey_select] = {0x003FF8, 1, 1},
936 [U_OTP_Vtrack_Reserved0] = {0x003FF8, 31, 2},
937 [U_OTP_FAKE] = {0x003FFC, 23, 0},
938 [U_OTP_allow_CPU_rst_release] = {0x003FFC, 31, 24},
939
940 };
941
942
943 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value);
944 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value);
945
946 //--------------------------------------------------------------------------------------------------
947 // Macro of bit operations
948 //--------------------------------------------------------------------------------------------------
949
950 //--------------------------------------------------------------------------------------------------
951 // Inline Function
952 //--------------------------------------------------------------------------------------------------
HAL_CA_SetBank(MS_U32 u32RegAddr)953 void HAL_CA_SetBank(MS_U32 u32RegAddr)
954 {
955 _u32REGBase = u32RegAddr;
956 _u32REGPMBase = u32RegAddr - 0x200000UL;
957 _u32REG_OTP_Base = u32RegAddr + REG_OTP_BASE;
958 _u32REG_RSA_Base = u32RegAddr + REG_RSA_BASE;
959 }
960
HAL_CA_Init(void)961 MS_BOOL HAL_CA_Init(void)
962 {
963 return TRUE;
964 }
965
HAL_CA_BGC_ISR(void)966 void HAL_CA_BGC_ISR(void)
967 {
968 MS_U32 u32Excp = REG32(BGC_RESP_FAIL);
969 // MS_U32 u32SecID = u32Excp & BGC_RESP_SECID;
970
971 if((u32Excp & BGC_RESP_RESET_AV) == BGC_RESP_RESET_AV)
972 {
973 //AV reset
974 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset AV.");
975 }
976
977 if((u32Excp & BGC_RESP_RESET_ACPU) == BGC_RESP_RESET_ACPU)
978 {
979 //ACPU reset
980 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset ACPU.");
981 }
982
983 if((u32Excp & BGC_RESP_RESET_SCPU) == BGC_RESP_RESET_SCPU)
984 {
985 //SCPU reset
986 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset SCPU.");
987 }
988
989 if((u32Excp & BGC_RESP_RESET_SYSTEM) == BGC_RESP_RESET_SYSTEM)
990 {
991 //If error is reset system, run reset system(only in keres)
992 //System reset
993 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset system.");
994 // REG32_PM(REG_TOP_SW_RST) = ((REG32_PM(REG_TOP_SW_RST) & ~REG_TOP_SW_RST_MSK) | REG_TOP_SW_RST_PASSWD);
995 }
996
997
998 }
999
HAL_CA_BGC_DisableINT(void)1000 void HAL_CA_BGC_DisableINT(void)
1001 {
1002 REG32(REG_INTR_CPUINIT_HST3) = REG32(REG_INTR_CPUINIT_HST3) & (~REG_HST3TO2_INT);
1003 }
1004
HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr,MS_U32 u32FwSize)1005 MS_BOOL HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr, MS_U32 u32FwSize)
1006 {
1007 if(u32FwSize > 0x2000)
1008 { //max size is 8K
1009 return FALSE;
1010 }
1011
1012 if((REG32(REG_ONEWAY_42) & SEC51_SW_RST) == 0x0)//bit0, reset sec51
1013 {
1014 return TRUE;//already enable sec51
1015 }
1016
1017 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1018 REG32(REG_BDMA_CTRL) = 0x0; //disable
1019 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51
1020 REG32(REG_BDMA_SRC_ADDR_L) = u32FwAddr & 0xFFFF;
1021 REG32(REG_BDMA_SRC_ADDR_H) = (u32FwAddr >> 16) & 0xFFFF;
1022 REG32(REG_BDMA_DST_ADDR_L) = 0x0;
1023 REG32(REG_BDMA_DST_ADDR_H) = 0x0;
1024 REG32(REG_BDMA_SIZE_L) = u32FwSize & 0xFFFF; //size
1025 REG32(REG_BDMA_SIZE_H) = 0x0;
1026 REG32(REG_BDMA_CTRL) = 0x1; // triger bdma
1027 while((REG32(REG_BDMA_CTRL) & 0x1) != 0); //wait bdma done
1028
1029 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1030
1031 REG32(REG_ONEWAY_42) = REG32(REG_ONEWAY_42) & (~SEC51_SW_RST);//bit 0, release sec51
1032
1033 REG32(REG_ONEWAY_52) = REG32(REG_ONEWAY_52) | SEC51_SW_LOCK;//bit 0, oneway lock sec51
1034
1035 //enable MIU cross bar
1036 REG32(REG_MIU_CROSSBAR_CTRL) = REG32(REG_MIU_CROSSBAR_CTRL) | REG_MIU_CROSSBAR_EN;
1037 return TRUE;
1038 }
1039
HAL_CA_BGC_Ctrl(MS_U32 u32Cmd,MS_U32 u32Data)1040 MS_BOOL HAL_CA_BGC_Ctrl(MS_U32 u32Cmd, MS_U32 u32Data)
1041 {
1042 MS_U16 u16Cmd = ((u32Data << BGC_CMD_SEC_DATA_SHT) & BGC_CMD_SEC_DATA) |
1043 ((u32Cmd << BGC_CMD_SEC_TYPE_SHT) & BGC_CMD_SEC_TYPE);
1044
1045 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1046
1047 REG32(BGC_CMD_CTRL) = u16Cmd;
1048 REG32(BGC_CMD_CTRL) = u16Cmd | BGC_CMD_SEC_GO;
1049 // printf("[BGC Cmd]:%04X\n", u16Cmd);
1050
1051 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1052 // printf("[BGC Cmd]:after write:%04X\n", REG32(BGC_CMD_CTRL));
1053
1054 if((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_STATUS) == BGC_CMD_SEC_STATUS)
1055 {
1056 return FALSE;
1057 }
1058 return TRUE;
1059 }
1060
HAL_CA_BGC_SetSec(MS_U32 u32SecId,const CA_BGC_SEC_CFG * pstSecCfg)1061 MS_BOOL HAL_CA_BGC_SetSec(MS_U32 u32SecId, const CA_BGC_SEC_CFG* pstSecCfg)
1062 {
1063 MS_U32 i = 0;
1064 MS_U32 u32Fail = 0;
1065
1066 if(u32SecId >= BGC_SEC_MAX )
1067 {
1068 return FALSE;
1069 }
1070
1071 //set section id
1072 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1073 {
1074 u32Fail = 1;
1075 goto BGC_CONFIG_FAIL;
1076 }
1077
1078 //set BGC mode
1079 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_MODE, pstSecCfg->u32BGCMode == 1 ? BGC_SEC_MODE_STATIC : BGC_SEC_MODE_DYNAMIC) == FALSE)
1080 {
1081 u32Fail = 2;
1082 goto BGC_CONFIG_FAIL;
1083 }
1084
1085 //set protect address and input cmd length
1086 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1087 {
1088 u32Fail = 3;
1089 goto BGC_CONFIG_FAIL;
1090 }
1091
1092 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x000000FF)>>0) == FALSE) |
1093 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x0000FF00)>>8) == FALSE) |
1094 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x00FF0000)>>16) == FALSE) |
1095 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0xFF000000)>>24) == FALSE))
1096 {
1097 u32Fail = 4;
1098 goto BGC_CONFIG_FAIL;
1099 }
1100
1101 //set protect size and input cmd length
1102 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1103 {
1104 u32Fail = 5;
1105 goto BGC_CONFIG_FAIL;
1106 }
1107 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x000000FF)>>0) == FALSE) |
1108 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x0000FF00)>>8) == FALSE) |
1109 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x00FF0000)>>16) == FALSE) |
1110 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0xFF000000)>>24) == FALSE))
1111 {
1112 u32Fail = 6;
1113 goto BGC_CONFIG_FAIL;
1114 }
1115
1116 //set interval bwteen two BGC check and input cmd length
1117 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x2) == FALSE)
1118 {
1119 u32Fail = 7;
1120 goto BGC_CONFIG_FAIL;
1121 }
1122 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0x00FF)>>0) == FALSE) |
1123 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0xFF00)>>8) == FALSE))
1124 {
1125 u32Fail = 8;
1126 goto BGC_CONFIG_FAIL;
1127 }
1128
1129
1130 //set golden and incput golden length
1131 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x20) == FALSE)
1132 {
1133 u32Fail = 9;
1134 goto BGC_CONFIG_FAIL;
1135 }
1136
1137 for(i = 0 ; i < 0x20 ; i ++)
1138 {
1139 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_GOLDEN, pstSecCfg->u8Golden[i]) == FALSE)
1140 {
1141 u32Fail = 10;
1142 goto BGC_CONFIG_FAIL;
1143 }
1144 }
1145
1146 //set password and incput length
1147 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1148 {
1149 u32Fail = 11;
1150 goto BGC_CONFIG_FAIL;
1151 }
1152
1153 for(i = 0 ; i < 0x4 ; i ++)
1154 {
1155 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SET_PASSWD, pstSecCfg->u8ResetPassword[i]) == FALSE)
1156 {
1157 u32Fail = 12;
1158 goto BGC_CONFIG_FAIL;
1159 }
1160 }
1161
1162 //set algorithm to sha256
1163 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ALGO, BGC_SEC_ALGO_SHA256) == FALSE)
1164 {
1165 u32Fail = 13;
1166 goto BGC_CONFIG_FAIL;
1167 }
1168
1169 //set the reset mode if BGC check fail
1170 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_MODE, BGC_SEC_RESET_INTERRUPT | BGC_SEC_RESET_SYSTEM) == FALSE)
1171 {
1172 u32Fail = 14;
1173 goto BGC_CONFIG_FAIL;
1174 }
1175
1176 //enable section id
1177 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ENABLE, TRUE) == FALSE)
1178 {
1179 u32Fail = 15;
1180 goto BGC_CONFIG_FAIL;
1181 }
1182
1183 return TRUE;
1184
1185 BGC_CONFIG_FAIL:
1186 HAL_CA_DEBUG("BGC config fail:%08X\n", u32Fail);
1187 return FALSE;
1188 }
1189
HAL_CA_BGC_ResetSec(MS_U32 u32SecId,const MS_U8 * pu8RstPSWD)1190 MS_BOOL HAL_CA_BGC_ResetSec(MS_U32 u32SecId, const MS_U8* pu8RstPSWD)
1191 {
1192 MS_U32 i = 0;
1193 MS_U32 u32Fail = 0;
1194
1195 if((u32SecId >= BGC_SEC_MAX) || (pu8RstPSWD == NULL))
1196 {
1197 return FALSE;
1198 }
1199
1200 //check bgc mode, if mode = 1, return fail
1201 //set section id
1202 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1203 {
1204 u32Fail = 1;
1205 goto BGC_RESET_FAIL;
1206 }
1207
1208 //set reset password and incput length
1209 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1210 {
1211 u32Fail = 2;
1212 goto BGC_RESET_FAIL;
1213 }
1214
1215 for(i = 0 ; i < 0x4 ; i ++)
1216 {
1217 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_PASSWD, pu8RstPSWD[i]) == FALSE)
1218 {
1219 u32Fail = 3;
1220 goto BGC_RESET_FAIL;
1221 }
1222 }
1223 return TRUE;
1224
1225 BGC_RESET_FAIL:
1226 HAL_CA_DEBUG("BGC reset fail:%08X\n", u32Fail);
1227 return FALSE;
1228
1229 }
1230
HAL_CA_OTP_IsBlank(MS_U32 addr)1231 MS_BOOL HAL_CA_OTP_IsBlank(MS_U32 addr)
1232 {
1233 MS_U32 value;
1234
1235 if(addr >= CA_OTP_SIZE)
1236 return 0;
1237
1238 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1239
1240 return value == 0;
1241 }
1242
1243
_HAL_CA_OTP_Read_Real(MS_U32 addr,MS_BOOL bXor)1244 MS_U32 _HAL_CA_OTP_Read_Real(MS_U32 addr, MS_BOOL bXor)
1245 {
1246 MS_U32 value;
1247
1248 if(addr >= CA_OTP_SIZE)
1249 return 0;
1250
1251 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1252
1253 return value;
1254 }
1255
1256
HAL_CA_OTP_Read(MS_U32 addr)1257 MS_U32 HAL_CA_OTP_Read(MS_U32 addr)
1258 {
1259 return _HAL_CA_OTP_Read_Real(addr, FALSE);
1260 }
1261
1262
_HAL_CA_OTP_Write_Real(MS_U32 addr,MS_U8 value)1263 MS_BOOL _HAL_CA_OTP_Write_Real(MS_U32 addr, MS_U8 value)
1264 {
1265 MS_DEBUG_MSG(printf("[_HAL_CA_OTP_Write_Real] addr=0x%04lx value=0x%02lx\n", addr, (MS_U32)value);)
1266 #if 0
1267 printf("[_HAL_CA_OTP_Write_Real] NO REAL WRITE!!!\n");
1268 #else
1269 *(volatile MS_U8 *)(_u32REG_OTP_Base + addr) = value;
1270 #endif
1271
1272 MS_U32 v;
1273 v = REG32(REG_OTP_CTRL_PV) & REG_OTP_CTRL_PG_VERIFY_FAIL_FLAG;
1274 if(v == 0) {
1275 return TRUE;
1276 }
1277
1278 HAL_CA_DEBUG("[_HAL_CA_OTP_Write_Real] PV fail (0x%08x)\n", v);
1279 return FALSE;
1280 }
1281
HAL_CA_OTP_Write(MS_U32 addr,MS_U32 value)1282 MS_BOOL HAL_CA_OTP_Write(MS_U32 addr, MS_U32 value)
1283 {
1284 int i;
1285 if(addr >= CA_OTP_SIZE)
1286 return FALSE;
1287
1288 if(addr % 4 != 0)
1289 return FALSE;
1290
1291 REG32(REG_OTP_CTRL_0) = REG_OTP_CTRL_0_VALUE;
1292
1293 MS_U32 orig = _HAL_CA_OTP_Read_Real(addr, TRUE);
1294 MS_U32 write = value & (orig ^ value); // only write the bit from 0 to 1
1295
1296 if(write == 0)
1297 return TRUE;
1298
1299 for(i = 0; i < 4; i++) {
1300 if(_HAL_CA_OTP_Write_Real(addr + i, (value >> (i * 8)) & 0xff) == FALSE)
1301 return FALSE;
1302 }
1303
1304 MS_U32 result = _HAL_CA_OTP_Read_Real(addr, TRUE);
1305 if((result & value) == value) // only check the bit 1
1306 {
1307 return TRUE;
1308 }
1309
1310 return FALSE;
1311 }
1312
_HAL_CA_OTP_GetConfig(MS_U32 u32Idx,MS_U32 * pu32Value)1313 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value)
1314 {
1315 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1316 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1317 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1318 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1319
1320 if(pu32Value == NULL)
1321 return FALSE;
1322
1323 if(u32Len > 32)
1324 return FALSE;
1325
1326 *pu32Value = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1327
1328 return TRUE;
1329 }
1330
_HAL_CA_OTP_SetConfig(MS_U32 u32Idx,MS_U32 u32Value)1331 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value)
1332 {
1333 //printf("[_HAL_CA_OTP_SetConfig] u32Idx=%ld u32Value=0x%08lx\n", u32Idx, u32Value);
1334
1335 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1336 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1337 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1338 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1339
1340 if(u32Len > 32)
1341 return FALSE;
1342
1343 u32Value = (u32Value << u32Shift) & u32Mask;
1344
1345 return HAL_CA_OTP_Write(u32Addr, u32Value);
1346 }
1347
HAL_CA_OTP_EnableSecureBoot(void)1348 MS_BOOL HAL_CA_OTP_EnableSecureBoot(void)
1349 {
1350 return _HAL_CA_OTP_SetConfig(U_OTP_SBoot, 0xf);
1351 }
1352
HAL_CA_OTP_IsSecureBootEnabled(void)1353 MS_BOOL HAL_CA_OTP_IsSecureBootEnabled(void)
1354 {
1355 MS_U32 u32Value = 0;
1356 MS_BOOL ret = FALSE;
1357
1358 ret = _HAL_CA_OTP_GetConfig(U_OTP_SBoot, &u32Value);
1359
1360 if (ret == FALSE)
1361 {
1362 return FALSE;
1363 }
1364 return u32Value != 0;
1365 }
1366
1367
HAL_CA_OTP_SetBlockLock(MS_U32 u32Start,MS_U32 u32End,CA_LOCK_TYPE eLockType)1368 MS_BOOL HAL_CA_OTP_SetBlockLock(MS_U32 u32Start, MS_U32 u32End, CA_LOCK_TYPE eLockType)
1369 {
1370 //Not support
1371 MS_DEBUG_MSG(printf("[%s][%d] do not support\n", __FUNCTION__, __LINE__));
1372 return FALSE;
1373 }
1374
HAL_CA_OTP_GetBlockLock(MS_U32 * pu32Start,MS_U32 * pu32End,CA_LOCK_TYPE * peLockType)1375 MS_BOOL HAL_CA_OTP_GetBlockLock(MS_U32 *pu32Start, MS_U32 *pu32End, CA_LOCK_TYPE *peLockType)
1376 {
1377 //Not support
1378 MS_DEBUG_MSG(printf("[%s][%d] do not support\n", __FUNCTION__, __LINE__));
1379 return FALSE;
1380 }
1381
1382
1383 //=======================================================
1384 // RSA bank for Secure Range
1385 //=======================================================
1386
HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet,MS_U32 u32SecStart,MS_U32 u32SecEnd)1387 MS_BOOL HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet, MS_U32 u32SecStart, MS_U32 u32SecEnd)
1388 {
1389 if(u32SecSet > REG_RSA_SEC_RANGE_SET || u32SecEnd <= u32SecStart)
1390 return FALSE;
1391
1392 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_START(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecStart & REG_RSA_SEC_RANGE_MASK);
1393 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_END(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecEnd & REG_RSA_SEC_RANGE_MASK);
1394
1395 return TRUE;
1396 }
1397
HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)1398 MS_BOOL HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)
1399 {
1400 switch(eLock)
1401 {
1402 // Boot Area
1403 case E_BOOT_LockWord_W0000_0511_Addr:
1404 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0000_0511_W, 0x3);
1405 case E_BOOT_LockWord_W0512_1023_Addr:
1406 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0512_1023_W, 0x3);
1407 case E_BOOT_LockWord_W1024_1535_Addr:
1408 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1024_1535_W, 0x3);
1409 case E_BOOT_LockWord_W1536_2047_Addr:
1410 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1536_2047_W, 0x3);
1411 case E_BOOT_LockWord_W2048_2559_Addr:
1412 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2048_2559_W, 0x3);
1413 case E_BOOT_LockWord_W2560_3071_Addr:
1414 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2560_3071_W, 0x3);
1415 case E_BOOT_LockWord_W3072_3391_Addr:
1416 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_3072_3391_W, 0x3);
1417
1418 // IDs
1419 case E_LockWord_v_PubOtpOID:
1420 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpOID_W, 0x3);
1421 case E_LockWord_v_PubOtpVID:
1422 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpVID_W, 0x3);
1423 case E_LockWord_v_pubOtpUniqueID1:
1424 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, 0x3);
1425 case E_LockWord_v_pubOtpUniqueID2:
1426 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, 0x3);
1427 case E_LockWord_v_pubOtpUniqueID3:
1428 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, 0x3);
1429 case E_LockWord_v_pubOtpUniqueID4:
1430 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, 0x3);
1431 default:
1432 return FALSE;
1433 }
1434 }
1435
HAL_CA_Locked(CA_OTP_LOCK eLock)1436 MS_BOOL HAL_CA_Locked(CA_OTP_LOCK eLock)
1437 {
1438 MS_U32 u32Value = 0;
1439 MS_BOOL ret = FALSE;
1440 switch(eLock)
1441 {
1442 // Boot Area
1443 case E_BOOT_LockWord_W0000_0511_Addr:
1444 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0000_0511_W, &u32Value);
1445 break;
1446 case E_BOOT_LockWord_W0512_1023_Addr:
1447 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0512_1023_W, &u32Value);
1448 break;
1449 case E_BOOT_LockWord_W1024_1535_Addr:
1450 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1024_1535_W, &u32Value);
1451 break;
1452 case E_BOOT_LockWord_W1536_2047_Addr:
1453 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1536_2047_W, &u32Value);
1454 break;
1455 case E_BOOT_LockWord_W2048_2559_Addr:
1456 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2048_2559_W, &u32Value);
1457 break;
1458 case E_BOOT_LockWord_W2560_3071_Addr:
1459 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2560_3071_W, &u32Value);
1460 break;
1461 case E_BOOT_LockWord_W3072_3391_Addr:
1462 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_3072_3391_W, &u32Value);
1463 break;
1464
1465 // IDs
1466 case E_LockWord_v_PubOtpOID:
1467 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpOID_W, &u32Value);
1468 break;
1469 case E_LockWord_v_PubOtpVID:
1470 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpVID_W, &u32Value);
1471 break;
1472 case E_LockWord_v_pubOtpUniqueID1:
1473 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, &u32Value);
1474 break;
1475 case E_LockWord_v_pubOtpUniqueID2:
1476 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, &u32Value);
1477 break;
1478 case E_LockWord_v_pubOtpUniqueID3:
1479 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, &u32Value);
1480 break;
1481 case E_LockWord_v_pubOtpUniqueID4:
1482 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, &u32Value);
1483 break;
1484 default:
1485 ret = FALSE;
1486 }
1487
1488 if(ret == FALSE)
1489 return FALSE;
1490
1491 if(u32Value == 0x01) // 0x01 : unlock, xx : locked
1492 return FALSE;
1493
1494 return TRUE;
1495 }
1496
HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)1497 MS_BOOL HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)
1498 {
1499 return _HAL_CA_OTP_SetConfig(U_OTP_MSID, u32Value);
1500 }
1501
HAL_CA_OTP_GetRSAextID(void)1502 MS_U32 HAL_CA_OTP_GetRSAextID(void)
1503 {
1504
1505 MS_U32 u32Value = 0;
1506 MS_BOOL ret = FALSE;
1507
1508 ret = _HAL_CA_OTP_GetConfig(U_OTP_MSID, &u32Value);
1509
1510 if (ret == FALSE)
1511 {
1512 return FALSE;
1513 }
1514 return u32Value;
1515 }
1516
1517
HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH1_REF_VER,MS_U32 u32HASH2_REF_VER)1518 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH1_REF_VER, MS_U32 u32HASH2_REF_VER)
1519 {
1520 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH0_VER_REF, u32HASH0_REF_VER) == FALSE)
1521 {
1522 return FALSE;
1523 }
1524
1525 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH1_VER_REF, u32HASH1_REF_VER) == FALSE)
1526 {
1527 return FALSE;
1528 }
1529
1530 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH2_VER_REF, u32HASH2_REF_VER) == FALSE)
1531 {
1532 return FALSE;
1533 }
1534
1535 return TRUE;
1536 }
1537
HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH1_REF_VER,MS_U32 * pu32HASH2_REF_VER)1538 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH1_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1539 {
1540 MS_U32 u32Value = 0;
1541
1542 if(pu32HASH0_REF_VER != NULL)
1543 {
1544 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH0_VER_REF, &u32Value) == FALSE)
1545 {
1546 return FALSE;
1547 }
1548
1549 *pu32HASH0_REF_VER = (u32Value);
1550 }
1551
1552 if(pu32HASH1_REF_VER != NULL)
1553 {
1554 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH1_VER_REF, &u32Value) == FALSE)
1555 {
1556 return FALSE;
1557 }
1558 *pu32HASH1_REF_VER = (u32Value);
1559 }
1560
1561 if(pu32HASH2_REF_VER != NULL)
1562 {
1563 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH2_VER_REF, &u32Value) == FALSE)
1564 {
1565 return FALSE;
1566 }
1567
1568 *pu32HASH2_REF_VER = (u32Value);
1569 }
1570
1571 return TRUE;
1572 }
1573
HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)1574 MS_BOOL HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)
1575 {
1576 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(0, u32HASH1_REF_VER, 0) == FALSE)
1577 {
1578 return FALSE;
1579 }
1580
1581 return TRUE;
1582 }
1583
HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 * pu32HASH1_REF_VER)1584 MS_BOOL HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 *pu32HASH1_REF_VER)
1585 {
1586 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(NULL, pu32HASH1_REF_VER, NULL) == FALSE)
1587 {
1588 return FALSE;
1589 }
1590
1591 return TRUE;
1592 }
1593
1594
HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH2_REF_VER)1595 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH2_REF_VER)
1596 {
1597 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(u32HASH0_REF_VER, 0, u32HASH2_REF_VER) == FALSE)
1598 {
1599 return FALSE;
1600 }
1601
1602 return TRUE;
1603 }
1604
HAL_CA_OTP_GetHASH_REF_VER(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH2_REF_VER)1605 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1606 {
1607 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(pu32HASH0_REF_VER, NULL, pu32HASH2_REF_VER) == FALSE)
1608 {
1609 return FALSE;
1610 }
1611
1612 return TRUE;
1613 }
1614
1615
HAL_CA_MaxDeviceIdSize(void)1616 MS_U32 HAL_CA_MaxDeviceIdSize(void)
1617 {
1618 return MAX_DEVICEID_SIZE;
1619 }
1620
HAL_CA_OTP_SetDeviceId(const MS_U8 * pu8Did,MS_U32 u32Size)1621 MS_BOOL HAL_CA_OTP_SetDeviceId(const MS_U8 *pu8Did, MS_U32 u32Size)
1622 {
1623 MS_U32 did[8] = {0};
1624 MS_U32 i, u32Addr;
1625 MS_U32 Did_Size = 2;
1626 MS_U8 *p = (MS_U8 *)did;
1627
1628 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1629 {
1630 p[i] = pu8Did[i];
1631 }
1632
1633 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1634 for(i = 0; i < Did_Size; i++)
1635 {
1636 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1637 {
1638 return FALSE;
1639 }
1640 u32Addr += 4;
1641 }
1642 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1643 for(i = Did_Size; i < (2*Did_Size); i++)
1644 {
1645 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1646 {
1647 return FALSE;
1648 }
1649 u32Addr += 4;
1650 }
1651 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1652 for(i = (2*Did_Size); i < (3*Did_Size); i++)
1653 {
1654 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1655 {
1656 return FALSE;
1657 }
1658 u32Addr += 4;
1659 }
1660 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1661 for(i = (3*Did_Size); i < (4*Did_Size); i++)
1662 {
1663 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1664 {
1665 return FALSE;
1666 }
1667 u32Addr += 4;
1668 }
1669
1670 return TRUE;
1671 }
1672
HAL_CA_OTP_GetDeviceId(MS_U8 * pu8Did,MS_U32 u32Size)1673 MS_BOOL HAL_CA_OTP_GetDeviceId(MS_U8 *pu8Did, MS_U32 u32Size)
1674 {
1675 MS_U32 did[8] = {0};
1676 MS_U32 Did_Size = 2;
1677 MS_U32 i, u32Addr;
1678 MS_U8 *p = (MS_U8 *)did;
1679
1680 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1681 for(i = 0; i < Did_Size; i++)
1682 {
1683 did[i] = HAL_CA_OTP_Read(u32Addr);
1684 u32Addr += 4;
1685 }
1686 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1687 for(i = Did_Size; i < (2*Did_Size) ; i++)
1688 {
1689 did[i] = HAL_CA_OTP_Read(u32Addr);
1690 u32Addr += 4;
1691 }
1692 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1693 for(i = (2*Did_Size) ; i < (3*Did_Size) ; i++)
1694 {
1695 did[i] = HAL_CA_OTP_Read(u32Addr);
1696 u32Addr += 4;
1697 }
1698 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1699 for(i = (3*Did_Size); i < (4*Did_Size) ; i++)
1700 {
1701 did[i] = HAL_CA_OTP_Read(u32Addr);
1702 u32Addr += 4;
1703 }
1704
1705 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1706 {
1707 pu8Did[i] = p[i];
1708 }
1709
1710 return TRUE;
1711 }
1712
HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE eMode)1713 MS_BOOL HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE eMode)
1714 {
1715 MS_U32 idx = 0;
1716 MS_U32 v = 0;
1717
1718 switch(eDebugPort)
1719 {
1720 case E_CA_DEBUG_PORT_I2C:
1721 idx = U_OTP_I2C_MODE;
1722 break;
1723 case E_CA_DEBUG_PORT_JTAG:
1724 idx = U_OTP_EJTAG_MODE;
1725 break;
1726 case E_CA_DEBUG_PORT_SCAN:
1727 idx = U_OTP_SCAN_MODE;
1728 break;
1729 default:
1730 return FALSE;
1731 }
1732
1733 switch(eMode)
1734 {
1735 case E_CA_DEBUG_PORT_OPEN:
1736 return TRUE;
1737 case E_CA_DEBUG_PORT_PASSWD:
1738 v = 0x7;
1739 break;
1740 case E_CA_DEBUG_PORT_CLOSE:
1741 v = 0x3f;
1742 break;
1743 default:
1744 return FALSE;
1745 }
1746
1747 return _HAL_CA_OTP_SetConfig(idx, v);
1748
1749 }
1750
1751
HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE * eMode)1752 MS_BOOL HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE *eMode)
1753 {
1754 MS_U32 v = 0;
1755 MS_BOOL ret = FALSE;
1756
1757 if(eMode == NULL)
1758 {
1759 return FALSE;
1760 }
1761
1762 switch(eDebugPort)
1763 {
1764 case E_CA_DEBUG_PORT_I2C:
1765 ret = _HAL_CA_OTP_GetConfig(U_OTP_I2C_MODE, &v);
1766 break;
1767 case E_CA_DEBUG_PORT_JTAG:
1768 ret = _HAL_CA_OTP_GetConfig(U_OTP_EJTAG_MODE, &v);
1769 break;
1770 case E_CA_DEBUG_PORT_SCAN:
1771 ret = _HAL_CA_OTP_GetConfig(U_OTP_SCAN_MODE, &v);
1772 break;
1773 default:
1774 return FALSE;
1775 }
1776
1777 if (ret == FALSE)
1778 {
1779 return FALSE;
1780 }
1781
1782 if(v & 0x38)
1783 {
1784 *eMode = E_CA_DEBUG_PORT_CLOSE;
1785 }
1786 else if(v)
1787 {
1788 *eMode = E_CA_DEBUG_PORT_PASSWD;
1789 }
1790 else
1791 {
1792 *eMode = E_CA_DEBUG_PORT_OPEN;
1793 }
1794
1795 return TRUE;
1796 }
1797
1798
1799 // This function is created to used for another hal driver: NSK2
HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)1800 MS_BOOL HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)
1801 {
1802 return _HAL_CA_OTP_GetConfig(u32Idx, pu32Value);
1803 }
1804
HAL_CA_OTP_EnableSecureCWMode(void)1805 MS_BOOL HAL_CA_OTP_EnableSecureCWMode(void)
1806 {
1807 return _HAL_CA_OTP_SetConfig(U_OTP_ena_ACPU2KT, 0xF);
1808 }
1809
HAL_CA_OTP_IsSecureCWMode(void)1810 MS_BOOL HAL_CA_OTP_IsSecureCWMode(void)
1811 {
1812 MS_U32 u32Value = 0;
1813 MS_BOOL ret = FALSE;
1814
1815 ret = _HAL_CA_OTP_GetConfig(U_OTP_ena_ACPU2KT, &u32Value);
1816
1817 if (ret == FALSE)
1818 {
1819 return FALSE;
1820 }
1821
1822 if(u32Value == 1)
1823 {
1824 return FALSE;
1825 }
1826 else
1827 {
1828 return TRUE;
1829 }
1830 }
1831
_HAL_CA_Random(void)1832 MS_U16 _HAL_CA_Random(void)
1833 {
1834 MS_U32 n;
1835
1836 do{
1837 n = REG32(REG_RNG_TRNG);
1838 if( n & REG_RNG_TRNG_VALID_MASK) //check valid
1839 {
1840 n &= REG_RNG_TRNG_OUT_MASK; // get random number
1841 REG32(REG_RNG_TRNG) = REG_RNG_TRNG_ACK; //ack
1842 break;
1843 }
1844 }while(1);
1845
1846 return n;
1847 }
1848
1849
HAL_CA_Random(void)1850 MS_U32 HAL_CA_Random(void)
1851 {
1852 MS_U32 u32Val = 0;
1853
1854 u32Val += _HAL_CA_Random()<<16;
1855 u32Val += _HAL_CA_Random();
1856
1857 return u32Val;
1858
1859 }
1860
HAL_CA_OTP_ReadCAVendor(void)1861 MS_U32 HAL_CA_OTP_ReadCAVendor(void)
1862 {
1863 MS_U32 u32CAV_Key_VendorID[CA_SCK_NUM] = {0}; // Store all VendorID
1864 MS_U32 u32CAV_Key_VendorID_Hi = 24; //High bit of VendorID in Key property
1865 MS_U32 u32CAV_Key_VendorID_Lo = 20; //Low bit of VendorID in Key property
1866
1867 MS_U32 u32CAV1_VendorID = 0;
1868 MS_U32 u32CAV2_VendorID = 0;
1869 MS_U32 u32CAV_Vendor = 0;
1870 MS_U32 u32CAV_Vendor_Shift = 16;
1871 MS_U32 u32CAV_Vendor_Num = 0; // Calculate how many different VendorID
1872
1873 MS_U32 u32Idx = 0;
1874 MS_U32 u32Addr = 0;
1875 MS_U32 u32Shift = 0;
1876 MS_U32 u32Len = 0;
1877 MS_U32 u32Mask = 0;
1878
1879 // Read VendorID of U_OTP_CAV_Keyn_Property
1880 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1881 {
1882 u32Addr = _HAL_CA_OTP_Addr[u32Idx + U_OTP_CAV_Key1_Property].u32Addr;
1883 u32Shift = u32CAV_Key_VendorID_Lo;
1884 u32Len = u32CAV_Key_VendorID_Hi - u32CAV_Key_VendorID_Lo + 1;
1885 u32Mask = bitmask(u32CAV_Key_VendorID_Hi, u32CAV_Key_VendorID_Lo);
1886
1887 u32CAV_Key_VendorID[u32Idx] = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1888 }
1889
1890 // Assign VendorID
1891 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1892 {
1893 // First non NULL VendorID assign to u32CAV1_VendorID
1894 if( (0 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1895 {
1896 u32CAV1_VendorID = u32CAV_Key_VendorID[u32Idx];
1897 u32CAV_Vendor_Num++;
1898 }
1899 // Second non NULL and not u32CAV1_VendorID VendorID assign to u32CAV2_VendorID
1900 else if( (1 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1901 {
1902 if(u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx])
1903 {
1904 u32CAV2_VendorID = u32CAV_Key_VendorID[u32Idx];
1905 u32CAV_Vendor_Num++;
1906 }
1907 }
1908 // If third non NULL, not u32CAV1_VendorID and not u32CAV2_VendorID VendorID
1909 else if( (2 <= u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1910 {
1911 if( (u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx]) && (u32CAV2_VendorID != u32CAV_Key_VendorID[u32Idx]) )
1912 {
1913 u32CAV1_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1914 u32CAV2_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1915 u32CAV_Vendor_Num++;
1916 }
1917
1918 }
1919 }
1920
1921 // Transform VendorID to Vendor code
1922 switch(u32CAV1_VendorID)
1923 {
1924 case CA_OTP_VENDOR_ID_NULL:
1925 break;
1926 case CA_OTP_VENDOR_ID_NDS:
1927 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS;
1928 break;
1929 case CA_OTP_VENDOR_ID_NAGRA:
1930 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA;
1931 break;
1932 case CA_OTP_VENDOR_ID_VIACCESS:
1933 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS;
1934 break;
1935 case CA_OTP_VENDOR_ID_IRDETO:
1936 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO;
1937 break;
1938 case CA_OTP_VENDOR_ID_VERIMATRIX:
1939 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX;
1940 break;
1941 case CA_OTP_VENDOR_ID_SMI:
1942 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI;
1943 break;
1944 case CA_OTP_VENDOR_ID_CONAX:
1945 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX;
1946 break;
1947 case CA_OTP_VENDOR_ID_LATENS:
1948 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS;
1949 break;
1950 case CA_OTP_VENDOR_ID_ECHOSTAR:
1951 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR;
1952 break;
1953 default:
1954 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW;
1955 }
1956
1957 switch(u32CAV2_VendorID)
1958 {
1959 case CA_OTP_VENDOR_ID_NULL:
1960 break;
1961 case CA_OTP_VENDOR_ID_NDS:
1962 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS << u32CAV_Vendor_Shift;
1963 break;
1964 case CA_OTP_VENDOR_ID_NAGRA:
1965 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA << u32CAV_Vendor_Shift;
1966 break;
1967 case CA_OTP_VENDOR_ID_VIACCESS:
1968 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS << u32CAV_Vendor_Shift;
1969 break;
1970 case CA_OTP_VENDOR_ID_IRDETO:
1971 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO << u32CAV_Vendor_Shift;
1972 break;
1973 case CA_OTP_VENDOR_ID_VERIMATRIX:
1974 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX << u32CAV_Vendor_Shift;
1975 break;
1976 case CA_OTP_VENDOR_ID_SMI:
1977 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI << u32CAV_Vendor_Shift;
1978 break;
1979 case CA_OTP_VENDOR_ID_CONAX:
1980 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX << u32CAV_Vendor_Shift;
1981 break;
1982 case CA_OTP_VENDOR_ID_LATENS:
1983 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS << u32CAV_Vendor_Shift;
1984 break;
1985 case CA_OTP_VENDOR_ID_ECHOSTAR:
1986 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR << u32CAV_Vendor_Shift;
1987 break;
1988 default:
1989 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW << u32CAV_Vendor_Shift;
1990 }
1991
1992 return u32CAV_Vendor;
1993 }
1994
1995
HAL_CA_STR_SetBank(MS_U32 u32Bank)1996 void HAL_CA_STR_SetBank(MS_U32 u32Bank)
1997 {
1998 _u32REGPMBase = u32Bank;
1999
2000 return;
2001 }
2002
HAL_CA_STR_EnableKey(void)2003 void HAL_CA_STR_EnableKey(void)
2004 {
2005 MS_U16 u16Tmp = 0;
2006 u16Tmp = REG16_PM(REG_STR_KEY);
2007 u16Tmp |= REG_STR_DMA_KEY_VALID;
2008 REG16_PM(REG_STR_KEY) = u16Tmp;
2009
2010 return;
2011 }
2012
HAL_CA_STR_SetMAC(MS_U8 * pu8STRMAC,MS_U32 u32STRMACSize)2013 void HAL_CA_STR_SetMAC(MS_U8* pu8STRMAC, MS_U32 u32STRMACSize)
2014 {
2015 MS_U8 i = 0;
2016
2017 for(i = 0; i < (u32STRMACSize/2); i++) {
2018 REG16_PM(REG_STR_AUTH_RESULT + i*4) = (pu8STRMAC[i*2 + 1]<<8 |pu8STRMAC[i*2]);
2019 }
2020
2021 return;
2022 }
2023
HAL_CA_STR_SetParamAddr(MS_U8 * pu8BAddr)2024 void HAL_CA_STR_SetParamAddr(MS_U8 *pu8BAddr)
2025 {
2026 MS_U16 u16Tmp = 0;
2027
2028 u16Tmp = ((MS_VIRT)pu8BAddr & 0x0000FFFF);
2029 REG16_PM(REG_STR_PTR) = u16Tmp;
2030
2031 u16Tmp = ((MS_VIRT)pu8BAddr & 0xFFFF0000)>>16;
2032 REG16_PM(REG_STR_PTR + 4) = u16Tmp;
2033
2034 return;
2035 }
2036
HAL_CA_STR_EnableWarmBoot(void)2037 void HAL_CA_STR_EnableWarmBoot(void)
2038 {
2039 //Oneway
2040 REG16_PM(REG_WARM_BOOT_IND) = REG_WARM_BOOT_IND_MAGIC;
2041
2042 return;
2043 }
HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel,const MS_U8 * pu8SecretKey,MS_U32 u32Size)2044 MS_BOOL HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel, const MS_U8 *pu8SecretKey, MS_U32 u32Size)
2045 {
2046
2047 MS_U32 secret_key[4] = {0};
2048 MS_U32 i, j, u32Addr;
2049 MS_U8 *p = (MS_U8 *)secret_key;
2050 switch(eKeySel)
2051 {
2052 case E_CA_SECRET_KEY1:
2053 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2054 break;
2055 case E_CA_SECRET_KEY2:
2056 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2057 break;
2058 case E_CA_SECRET_KEY3:
2059 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2060 break;
2061 case E_CA_SECRET_KEY4:
2062 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2063 break;
2064 case E_CA_SECRET_KEY5:
2065 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2066 break;
2067 case E_CA_SECRET_KEY6:
2068 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2069 break;
2070 case E_CA_SECRET_KEY7:
2071 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2072 break;
2073 case E_CA_SECRET_KEY8:
2074 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2075 break;
2076 default:
2077 return FALSE;
2078 }
2079
2080 if(sizeof(secret_key)>u32Size)
2081 {
2082 j = u32Size;
2083 }
2084 else
2085 {
2086 j=sizeof(secret_key);
2087 }
2088 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2089 {
2090 p[i] = pu8SecretKey[(j-1)-i]; // Array reverse, for user easy viewing
2091 }
2092
2093 for(i = 0; i < 4; i++)
2094 {
2095 if(HAL_CA_OTP_Write(u32Addr,secret_key[i]) == FALSE)
2096 {
2097 return FALSE;
2098 }
2099 u32Addr += 4;
2100 }
2101 return TRUE;
2102 }
2103
HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel,MS_U8 * pu8SecretKey,MS_U32 u32Size)2104 MS_BOOL HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel, MS_U8 *pu8SecretKey, MS_U32 u32Size)
2105 {
2106 MS_U32 secret_key[4] = {0};
2107 MS_U32 i, j, u32Addr;
2108 MS_U8 *p = (MS_U8 *)secret_key;
2109
2110 switch(eKeySel)
2111 {
2112 case E_CA_SECRET_KEY1:
2113 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2114 break;
2115 case E_CA_SECRET_KEY2:
2116 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2117 break;
2118 case E_CA_SECRET_KEY3:
2119 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2120 break;
2121 case E_CA_SECRET_KEY4:
2122 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2123 break;
2124 case E_CA_SECRET_KEY5:
2125 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2126 break;
2127 case E_CA_SECRET_KEY6:
2128 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2129 break;
2130 case E_CA_SECRET_KEY7:
2131 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2132 break;
2133 case E_CA_SECRET_KEY8:
2134 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2135 break;
2136 default:
2137 return FALSE;
2138 }
2139 for(i = 0; i < 4; i++)
2140 {
2141 secret_key[i] = HAL_CA_OTP_Read(u32Addr);
2142 u32Addr += 4;
2143 }
2144
2145 if(sizeof(secret_key)>u32Size)
2146 {
2147 j = u32Size;
2148 }
2149 else
2150 {
2151 j=sizeof(secret_key);
2152 }
2153
2154 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2155 {
2156 pu8SecretKey[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2157 }
2158
2159 return TRUE;
2160 }
2161
HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel,const MS_U8 * pu8RSAKey,MS_U32 u32Size)2162 MS_BOOL HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel, const MS_U8 *pu8RSAKey, MS_U32 u32Size)
2163 {
2164 MS_U32 RSA_key[64] = {0};
2165 MS_U32 i, u32Addr;
2166 MS_U8 *p = (MS_U8 *)RSA_key;
2167
2168 switch(eKeySel)
2169 {
2170 case E_CA_RSA_KEY0:
2171 return FALSE;
2172 case E_CA_RSA_KEY1:
2173 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2174 break;
2175 default:
2176 return FALSE;
2177 }
2178
2179 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2180 {
2181 p[i] = pu8RSAKey[i];
2182 }
2183 for(i = 0; i < 64; i++)
2184 {
2185 if(HAL_CA_OTP_Write(u32Addr,RSA_key[i]) == FALSE)
2186 {
2187 return FALSE;
2188 }
2189 u32Addr += 4;
2190 }
2191
2192 return TRUE;
2193 }
HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel,MS_U8 * pu8RSAKey,MS_U32 u32Size)2194 MS_BOOL HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel, MS_U8 *pu8RSAKey, MS_U32 u32Size)
2195 {
2196 MS_U32 RSA_key[64] = {0};
2197 MS_U32 i, u32Addr;
2198 MS_U8 *p = (MS_U8 *)RSA_key;
2199
2200 switch(eKeySel)
2201 {
2202 case E_CA_RSA_KEY0:
2203 return FALSE;
2204 break;
2205 case E_CA_RSA_KEY1:
2206 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2207 break;
2208 default:
2209 return FALSE;
2210 }
2211 for(i = 0; i < 64; i++)
2212 {
2213 RSA_key[i] = HAL_CA_OTP_Read(u32Addr);
2214 u32Addr += 4;
2215 }
2216 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2217 {
2218 pu8RSAKey[i] = p[i];
2219 }
2220
2221 return TRUE;
2222 }
2223
2224
HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort,const MS_U8 * pu8Password,MS_U32 u32Size)2225 MS_BOOL HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort, const MS_U8 *pu8Password, MS_U32 u32Size)
2226 {
2227
2228 MS_U32 pwd[4] = {0};
2229 MS_U32 i, j, u32Addr;
2230 MS_U8 *p = (MS_U8 *)pwd;
2231
2232 switch(eDebugPort)
2233 {
2234 case E_CA_DEBUG_PORT_I2C:
2235 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2236 break;
2237 case E_CA_DEBUG_PORT_JTAG:
2238 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2239 break;
2240 case E_CA_DEBUG_PORT_SCAN:
2241 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2242 break;
2243 default:
2244 return FALSE;
2245 }
2246 if(sizeof(pwd)>u32Size)
2247 {
2248 j = u32Size;
2249 }
2250 else
2251 {
2252 j=sizeof(pwd);
2253 }
2254
2255 for(i = 0; i < sizeof(pwd) && i < u32Size; i++)
2256 {
2257 p[i] = pu8Password[(j-1)-i]; // Array reverse, for user easy viewing
2258 }
2259
2260
2261 for(i = 0; i < 4; i++)
2262 {
2263 if(HAL_CA_OTP_Write(u32Addr,pwd[i]) == FALSE)
2264 {
2265 return FALSE;
2266 }
2267 u32Addr += 4;
2268 }
2269
2270 return TRUE;
2271 }
2272
HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort,MS_U8 * pu8Password,MS_U32 u32Size)2273 MS_BOOL HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort, MS_U8 *pu8Password, MS_U32 u32Size)
2274 {
2275 MS_U32 pwd[4] = {0};
2276 MS_U32 i, j, u32Addr;
2277 MS_U8 *p = (MS_U8 *)pwd;
2278
2279 switch(eDebugPort)
2280 {
2281 case E_CA_DEBUG_PORT_I2C:
2282 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2283 break;
2284 case E_CA_DEBUG_PORT_JTAG:
2285 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2286 break;
2287 case E_CA_DEBUG_PORT_SCAN:
2288 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2289 break;
2290 default:
2291 return FALSE;
2292 }
2293 for(i = 0; i < 4; i++)
2294 {
2295 pwd[i] = HAL_CA_OTP_Read(u32Addr);
2296 u32Addr += 4;
2297 }
2298 if(sizeof(pwd)>u32Size)
2299 {
2300 j = u32Size;
2301 }
2302 else
2303 {
2304 j=sizeof(pwd);
2305 }
2306 for(i = 0; i < sizeof(pwd) &&i < u32Size; i++)
2307 {
2308 pu8Password[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2309 }
2310 return TRUE;
2311 }
2312
HAL_CA_MaxReservedSize(void)2313 MS_U32 HAL_CA_MaxReservedSize(void)
2314 {
2315 HAL_CA_DEBUG("Not Implement\n");
2316 return FALSE;
2317 }
2318
HAL_CA_OTP_WriteReserved(const MS_U8 * pu8RData,MS_U32 u32Size)2319 MS_BOOL HAL_CA_OTP_WriteReserved(const MS_U8 *pu8RData, MS_U32 u32Size)
2320 {
2321 HAL_CA_DEBUG("Not Implement\n");
2322 return FALSE;
2323 }
2324
HAL_CA_OTP_ReadReserved(MS_U8 * pu8RData,MS_U32 u32Size)2325 MS_BOOL HAL_CA_OTP_ReadReserved(MS_U8 *pu8RData, MS_U32 u32Size)
2326 {
2327 HAL_CA_DEBUG("Not Implement\n");
2328 return FALSE;
2329 }
2330