1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halPVR.h 20 // @brief PVR HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_PVR_H__ 24 #define __HAL_PVR_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM 4 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 // PVR buffer define 36 #define PVR_NON_OVERWRITE (MS_U64)0xDEADBEEFDEADBEEFLL 37 // If the PVR buffer in non-OverWrite state, the first 8 bytes of the PVR buffer must be the PVR_NON_OVERWRITE value 38 39 //VQ define 40 #define VQ_NUM 4 41 #define VQ_PACKET_UNIT_LEN 208 42 43 #define TSP_TSIF0 0x00 44 #define TSP_TSIF1 0x01 45 #define TSP_TSIF2 0x02 46 #define TSP_TSIF3 0x03 47 48 //FQ define 49 #define TSP_FQ_NUM 4 50 51 //u32Cmd of MApi_DMX_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config, MS_U32 u32DataNum, void *pData); 52 #define HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK 0x00000001 //[u32Config] 1:disable cc check on fw, 0: enable cc check on fw; [u32DataNum,*pData] do not use 53 54 //######################################################################### 55 //#### Software Capability Macro Start 56 //######################################################################### 57 58 #define TSP_CA_RESERVED_FLT_NUM 1 59 #define TSP_RECFLT_NUM 1 60 #define TSP_PIDFLT_REC_NUM TSP_PIDFLT_NUM // 0~191 (0 for CA) 61 // 197 for Err 62 // 196 for REC 63 // 195 for PCR3 64 // 194 for PCR2 65 // 193 for PCR1 66 // 192 for PCR0 67 68 #if HW_PCRFLT_ENABLE 69 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 70 #else 71 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + TSP_RECFLT_NUM) 72 #endif 73 74 //######################################################################### 75 //#### Software Capability Macro End 76 //######################################################################### 77 78 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 79 #define TSP_CAFLT_START_ID 0 80 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) // 1 81 82 // section FLT ID 83 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID // 1 84 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID // 1 85 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 86 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 87 88 // PID 89 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID // 1 90 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM) // 192 91 92 // PCR 93 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID // 192 94 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 95 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) // 196 96 97 // REC 98 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID // 196 99 100 //-------------------------------------------------------------------------------------------------- 101 // Driver Compiler Option 102 //-------------------------------------------------------------------------------------------------- 103 104 105 //-------------------------------------------------------------------------------------------------- 106 // PVR Hardware Abstraction Layer 107 //-------------------------------------------------------------------------------------------------- 108 109 // HW characteristic 110 111 typedef enum _PVRENG_SEQ 112 { 113 E_TSP_PVR_PVRENG_START = 0, 114 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 115 E_TSP_PVR_PVRENG_1, 116 E_TSP_PVR_PVRENG_2, 117 E_TSP_PVR_PVRENG_3, 118 E_TSP_PVR_PVRENG_END, 119 E_TSP_PVR_ENG_INVALID, 120 } PVRENG_SEQ; 121 122 typedef enum _FILEENG_SEQ 123 { 124 E_FILEENG_TSIF0 = TSP_TSIF0, 125 E_FILEENG_TSIF1 = TSP_TSIF1, 126 E_FILEENG_TSIF2 = TSP_TSIF2, 127 E_FILEENG_TSIF3 = TSP_TSIF3, 128 E_FILEENG_INVALID, 129 130 } FILEENG_SEQ; 131 132 #if 1 // Destination type 133 typedef enum _TSP_DST_SEQ 134 { 135 E_TSP_DST_FIFO_VIDEO, 136 E_TSP_DST_FIFO_VIDEO3D, 137 E_TSP_DST_FIFO_AUDIO, 138 E_TSP_DST_FIFO_AUDIO2, 139 E_TSP_DST_FIFO_AUDIO3, 140 E_TSP_DST_SEC, 141 E_TSP_DST_PVR_PVR0, 142 E_TSP_DST_PVR_PVR1, 143 E_TSP_DST_PVR_PVR2, 144 E_TSP_DST_PVR_PVR3, 145 E_TSP_DST_PVR_PVRCB, //Not support 146 E_TSP_DST_PVR_RASP0, //Not support 147 E_TSP_DST_PVR_RASP1, //Not support 148 E_TSP_DST_TSO_TSO0, 149 E_TSP_DST_TSO_TSO1, //Not support 150 E_TSP_DST_FIFO_AUDIO4, 151 E_TSP_DST_FIFO_VIDEO3, 152 E_TSP_DST_FIFO_VIDEO4, 153 E_TSP_DST_INVALID, 154 } TSP_DST_SEQ; 155 #else 156 #define TSP_FltType MS_U32 157 /// TS stream fifo type (Exclusive usage) 158 #define E_TSP_FLT_FIFO_MASK 0x000000FF 159 #define E_TSP_FLT_FIFO_VIDEO 0x00000001 160 #define E_TSP_FLT_FIFO_AUDIO 0x00000002 161 #define E_TSP_FLT_FIFO_AUDIO2 0x00000004 162 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000008 163 #endif 164 165 typedef enum _TSP_SRC_SEQ{ 166 E_TSP_SRC_PKTDMX0, 167 E_TSP_SRC_PKTDMX1, 168 E_TSP_SRC_PKTDMX2, 169 E_TSP_SRC_PKTDMX3, 170 E_TSP_SRC_PKTDMX4, //not used 171 E_TSP_SRC_PKTDMX5, //not used 172 E_TSP_SRC_MMFI0, 173 E_TSP_SRC_MMFI1, 174 175 E_TSP_SRC_INVALID, 176 } TSP_SRC_SEQ; 177 178 typedef enum _TSIF_CFG 179 { 180 // @NOTE should be Exclusive usage 181 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 182 E_TSP_TSIF_CFG_EN = 0x0001, 183 E_TSP_TSIF_CFG_PARA = 0x0002, 184 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 185 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 186 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 187 E_TSP_TSIF_CFG_3WIRE = 0x0010 188 } TSP_TSIF_CFG; 189 190 // for stream input source 191 typedef enum _HAL_TS_PAD 192 { 193 E_TSP_TS_PAD_EXT0, 194 E_TSP_TS_PAD_EXT1, 195 E_TSP_TS_PAD_EXT2, 196 E_TSP_TS_PAD_EXT3, // 4/3 wired serial mode 197 E_TSP_TS_PAD_EXT4, // 4/3 wired serial mode 198 E_TSP_TS_PAD_EXT5, // 4/3 wired serial mode 199 E_TSP_TS_PAD_EXT6, // 3 wired serial mode 200 E_TSP_TS_PAD_INTER0, // not support, 201 E_TSP_TS_PAD_INTER1, // not support, 202 E_TSP_TS_PAD_TSOUT0, 203 E_TSP_TS_PAD_TSOUT1, //not support, 204 E_TSP_TS_PAD_TSIOOUT0, 205 E_TSP_TS_PAD_INVALID, 206 } TSP_TS_PAD; 207 208 // for ts pad mode 209 typedef enum _HAL_TS_PAD_MUX_MODE 210 { 211 E_TSP_TS_PAD_MUX_PARALLEL, // in 212 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, // in 213 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, // in 214 E_TSP_TS_PAD_MUX_TSO, // out 215 E_TSP_TS_PAD_MUX_S2P, // out 216 E_TSP_TS_PAD_MUX_S2P1, // out 217 E_TSP_TS_PAD_MUX_DEMOD, // out 218 219 E_TSP_TS_PAD_MUX_INVALID 220 } TSP_TS_PAD_MUX_MODE; 221 222 223 // for pkt converter mode 224 typedef enum _HAL_TS_PKT_CONVERTER_MODE 225 { 226 E_TSP_PKT_CONVERTER_188Mode = 0, 227 E_TSP_PKT_CONVERTER_CIMode = 1, 228 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 229 E_TSP_PKT_CONVERTER_ATSMode = 3, 230 E_TSP_PKT_CONVERTER_MxLMode = 4, 231 E_TSP_PKT_CONVERTER_NagraDongleMode = 5, 232 E_TSP_PKT_CONVERTER_Invalid, 233 } TSP_TS_PKT_CONVERTER_MODE; 234 235 typedef enum _HAL_TS_MXL_PKT_MODE 236 { 237 E_TSP_TS_MXL_PKT_192 = 4, 238 E_TSP_TS_MXL_PKT_196 = 8, 239 E_TSP_TS_MXL_PKT_200 = 12, 240 E_TSP_TS_MXL_PKT_INVALID, 241 } TSP_TS_MXL_PKT_MODE; 242 243 typedef enum _HAL_TSP_CLK_TYPE 244 { 245 E_TSP_HAL_TSP_CLK, 246 E_TSP_HAL_STC_CLK, 247 E_TSP_HAL_INVALID 248 } EN_TSP_HAL_CLK_TYPE; 249 250 typedef struct _HAL_TSP_CLK_STATUS 251 { 252 MS_BOOL bEnable; 253 MS_BOOL bInvert; 254 MS_U8 u8ClkSrc; 255 } ST_TSP_HAL_CLK_STATUS; 256 257 typedef enum _PCR_SRC 258 { 259 /* register setting for kaiser pcr 260 0: tsif0 261 1: tsif1 262 2: tsif2 263 3: tsif3 264 4: tsif4 265 5: tsif5 266 6: un-used 267 7: un-used 268 8: pkt merge 0 269 9: pkt merge 1 270 a: MM file in 1 271 b: MM file in 2 272 */ 273 E_TSP_PCR_SRC_TSIF0 = 0, 274 E_TSP_PCR_SRC_TSIF1, 275 E_TSP_PCR_SRC_TSIF2, 276 E_TSP_PCR_SRC_TSIF3, 277 E_TSP_PCR_SRC_TSIF4, 278 E_TSP_PCR_SRC_TSIF5, 279 E_TSP_PCR_SRC_PKT_MERGE0 = 8, 280 E_TSP_PCR_SRC_PKT_MERGE1, 281 E_TSP_PCR_SRC_MMFI0, 282 E_TSP_PCR_SRC_MMFI1, 283 E_TSP_PCR_SRC_INVALID, 284 } TSP_PCR_SRC; 285 286 typedef enum _HAL_TSP_TSIF // for HW TSIF 287 { 288 E_TSP_HAL_TSIF_0 , 289 E_TSP_HAL_TSIF_1 , 290 E_TSP_HAL_TSIF_2 , 291 E_TSP_HAL_TSIF_3 , 292 E_TSP_HAL_TSIF_TSP_MAX , 293 E_TSP_HAL_TSIF_CB , //not support 294 E_TSP_HAL_TSIF_TSO0 , 295 E_TSP_HAL_TSIF_TSO1 , //not support 296 E_TSP_HAL_TSIF_RASP0 , //not support 297 E_TSP_HAL_TSIF_RASP1 , //not support 298 E_TSP_HAL_TSIF_EMMFLT , 299 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 300 E_TSP_HAL_TSIF_PVR0 , 301 E_TSP_HAL_TSIF_PVR1 , 302 E_TSP_HAL_TSIF_PVR2 , 303 E_TSP_HAL_TSIF_PVR3 , 304 E_TSP_HAL_TSIF_INVALID , 305 } TSP_HAL_TSIF; 306 307 308 typedef enum _TSP_HAL_FileState 309 { 310 /// Command Queue is Idle 311 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 312 /// Command Queue is Busy 313 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 314 /// Command Queue is Paused. 315 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 316 317 E_TSP_HAL_FILE_STATE_INVALID, 318 }TSP_HAL_FileState; 319 320 typedef enum 321 { 322 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 323 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 324 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 325 326 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 327 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 328 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 329 330 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 331 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 332 333 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 334 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 335 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 336 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 337 338 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 339 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 340 341 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 342 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 343 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 344 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 345 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 346 347 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 348 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 349 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 350 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 351 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 352 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 353 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 354 355 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 356 357 //27 is reserved, and can not be used 358 359 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 360 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 361 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 362 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 363 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 364 365 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 366 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 367 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 368 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 369 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 370 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 371 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 372 E_TSP_HAL_CAP_FIQ_NUM = 40, 373 E_TSP_HAL_CAP_TYPE_NULL, 374 } TSP_HAL_CAP_TYPE; 375 376 // @F_TODO remove unused enum member 377 typedef enum 378 { 379 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PCRFLT_END_ID - TSP_PIDFLT_START_ID), 380 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), 381 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), 382 383 E_TSP_HAL_CAP_VAL_RECENG_NUM = 4, 384 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, 385 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, 386 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, 387 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 388 389 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 4, //MMFI0 filters 390 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 4, //MMFI1 filters 391 392 E_TSP_HAL_CAP_VAL_TSIF_NUM = 4, 393 E_TSP_HAL_CAP_VAL_DEMOD_NUM = 4, //internal demod // [ToDo] STC number... by MM problem Jason-YH.Sun 394 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 3, 395 E_TSP_HAL_CAP_VAL_VQ_NUM = 4, 396 397 E_TSP_HAL_CAP_VAL_CAFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), //@NOTE: flt number for descrypt purpose 398 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 399 400 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 401 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 402 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 403 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 404 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 405 406 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 407 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 408 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 409 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 410 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 411 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 412 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 413 414 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 415 416 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 4, 417 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 4, 418 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 419 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 420 421 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x4000, 422 423 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 424 } TSP_HAL_CAP_VAL; 425 426 /// TSP TEI Remove Error Packet Infomation 427 typedef enum 428 { 429 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 430 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT ///< TEI Remoce Video Packet 431 432 }TSP_HAL_TEI_RmPktType; 433 434 /// TSP Packet Converter Input Mode 435 typedef enum 436 { 437 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 438 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 439 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 440 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 441 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 442 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 443 E_TSP_HAL_PKT_MODE_MXL_200, ///< MXL mode (200 bytes) 444 E_TSP_HAL_PKT_MODE_ND, ///< Nagra Dongle mode (192 bytes) 445 446 }TSP_HAL_PKT_MODE; 447 448 // TSP TimeStamp Clk Select 449 typedef enum 450 { 451 E_TSP_HAL_TIMESTAMP_CLK_90K = 0, 452 E_TSP_HAL_TIMESTAMP_CLK_27M = 1, 453 E_TSP_HAL_TIMESTAMP_CLK_INVALID = 2 454 455 } TSP_HAL_TimeStamp_Clk; 456 457 //---------------------------------- 458 /// DMX debug table information structure 459 //---------------------------------- 460 461 typedef enum 462 { 463 E_TSP_HAL_FLOW_LIVE0, 464 E_TSP_HAL_FLOW_LIVE1, 465 E_TSP_HAL_FLOW_LIVE2, 466 E_TSP_HAL_FLOW_LIVE3, 467 E_TSP_HAL_FLOW_FILE0, 468 E_TSP_HAL_FLOW_FILE1, 469 E_TSP_HAL_FLOW_FILE2, 470 E_TSP_HAL_FLOW_FILE3, 471 E_TSP_HAL_FLOW_MMFI0, 472 E_TSP_HAL_FLOW_MMFI1, 473 474 E_TSP_HAL_FLOW_INVALID, 475 476 } TSP_HAL_FLOW; 477 478 479 //-------------------------------------------------------------------------------------------------- 480 // PVR HAL API 481 //-------------------------------------------------------------------------------------------------- 482 // Static Register Mapping for external access 483 #define REG_PIDFLT_BASE0 (0x00240000UL) 484 #define REG_PIDFLT_BASE1 (0x00241000UL) 485 #define REG_SECFLT_BASE (0x00221000UL) 486 #define REG_SECBUF_BASE (0x00221024UL) 487 #define REG_CTRL_BASE (0x00210200UL) 488 489 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 490 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 491 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 492 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 493 //#define _REGSynth ((REG_Synth*)(REG_SYNTH_BASE )) 494 495 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 496 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 497 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE+(_fltid>>5)*0x1000))->Flt[_fltid&(0x1F)])) 498 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE+(_bufid>>5)*0x1000))->Buf[_bufid&(0x1F)])) 499 500 //#define TSIF2PKTDMX(_tsif) (((_tsif)<2)?(_tsif):((_tsif > 3)?(_tsif+2):(_tsif+1))) 501 502 //#define PKTDMX2TSIF(_pktdmx) ((_pktdmx)>2)?(((_pktdmx)==2)?(_pktdmx-1):(_pktdmx)):(((_pktdmx)==5)?(_pktdmx-2):(_pktdmx-1)) 503 504 505 506 //******************** PIDFLT DEFINE START ********************// 507 // PID 508 #define TSP_PIDFLT_PID_MASK 0x00001FFF 509 #define TSP_PIDFLT_PID_SHFT 0 510 511 // Continuous counter 512 #define TSP_PIDFLT_CC_MASK 0xFF000000 513 #define TSP_PIDFLT_CC_SHFT 24 514 515 // PIDFLT SRC 516 typedef enum _TSP_PIDFLT_SRC 517 { 518 E_TSP_PIDFLT_LIVE0, 519 E_TSP_PIDFLT_LIVE1, 520 E_TSP_PIDFLT_LIVE2, 521 E_TSP_PIDFLT_LIVE3, 522 E_TSP_PIDFLT_FILE0, 523 E_TSP_PIDFLT_FILE1, 524 E_TSP_PIDFLT_FILE2, 525 E_TSP_PIDFLT_FILE3, 526 E_TSP_PIDFLT_INVALID, 527 } TSP_PIDFLT_SRC; 528 529 #define TSP_PIDFLT_IN_MASK 0x0000E000 530 #define TSP_PIDFLT_TSIF_SHFT 13 531 #define TSP_PIDFLT_TSIF0 0x00 532 #define TSP_PIDFLT_TSIF1 0x01 533 #define TSP_PIDFLT_TSIF2 0x02 534 #define TSP_PIDFLT_TSIF3 0x03 535 #define TSP_PIDFLT_TSIF_MAX 0x04 536 537 // Section filter Id (0~63) 538 #define TSP_PIDFLT_SECFLT_MASK 0x000000FF // [21:16] secflt id 539 #define TSP_PIDFLT_SECFLT_SHFT 0 540 541 // AF/Sec/Video/V3D/V3/V4/Audio/AudioB/AudioC/AudioD/PVR1/PVR2/PVR3/PVR4 542 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 543 #define TSP_PIDFLT_OUT_MASK 0x009FFF00 544 #define TSP_PIDFLT_OUT_SHFT 8 545 #define TSP_PIDFLT_OUT_NONE 0x00000000 546 #define TSP_PIDFLT_OUT_SECAF 0x00000100 547 #define TSP_PIDFLT_OUT_SECFLT 0x00000200 548 #define TSP_PIDFLT_OUT_VFIFO 0x00000400 549 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000800 550 #define TSP_PIDFLT_OUT_AFIFO 0x00001000 551 #define TSP_PIDFLT_OUT_AFIFO2 0x00002000 552 #define TSP_PIDFLT_OUT_VFIFO3 0x00004000 553 #define TSP_PIDFLT_OUT_AFIFO3 0x00080000 554 #define TSP_PIDFLT_OUT_AFIFO4 0x00100000 555 #define TSP_PIDFLT_OUT_VFIFO4 0x00800000 556 557 558 // SRC ID 559 #define TSP_PIDFLT_SRCID_MASK 0xF0000000 560 #define TSP_PIDFLT_SRCID_SHIFT 28 561 562 563 564 #define TSP_PIDFLT_PVRFLT_MASK 0x00078000 565 #define TSP_PIDFLT_PVRFLT_SHFT 15 566 #define TSP_PIDFLT_OUT_PVR1 0x00008000 567 #define TSP_PIDFLT_OUT_PVR2 0x00010000 568 #define TSP_PIDFLT_OUT_PVR3 0x00020000 569 #define TSP_PIDFLT_OUT_PVR4 0x00040000 570 571 572 #define TSP_PIDFLT_PKTPUSH_PASS_MASK 0x00200000 573 #define TSP_PIDFLT_PKTPUSH_PASS_SHFT 21 574 #define TSP_PID_FLT_PKTPUSH_PASS 0x00200000 575 576 #define TSP_PIDFLT_TSOFLT_MASK 0x00400000 577 #define TSP_PIDFLT_TSOFLT_SHFT 22 578 #define TSP_PID_FLT_OUT_TSO0 0x00400000 579 580 //******************** PIDFLT DEFINE END ********************// 581 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 582 MS_U32 TSP32_IdrR(TSP32 *preg); 583 584 //=========================TSIF================================ 585 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 586 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable); 587 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 588 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 589 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 590 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 591 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 592 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 593 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 594 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 595 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 596 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 597 MS_BOOL HAL_TSP_GET_TSIF_FileEnStatus(MS_U32 u32FileEn); 598 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 599 600 //=========================TSP================================ 601 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn); 602 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 603 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn); 604 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 605 void HAL_TSP_Reset(MS_BOOL bEn); 606 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn); 607 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus); 608 void HAL_TSP_Power(MS_BOOL bEn); 609 void HAL_TSP_CPU(MS_BOOL bEn); 610 void HAL_TSP_ResetCPU(MS_BOOL bReset); 611 void HAL_TSP_HwPatch(void); 612 void HAL_TSP_RestoreFltState(void); 613 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 614 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn); 615 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 616 void HAL_TSP_PktBuf_Reset(MS_U32 pktBufId, MS_BOOL bEn); 617 void HAL_TSP_SaveFltState(void); 618 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 619 void HAL_TSP_FIFOPBFltFullSel(MS_U32 u32FIFOFullLevel); 620 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 621 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 622 void HAL_TSP_Bank1137_Write(MS_U32 u32Offset,MS_U16 u16Value); 623 624 //=========================TSO================================ 625 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 626 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 627 628 //=========================Filein================================ 629 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 630 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 631 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 632 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 633 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 634 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 635 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 636 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 637 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 638 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 639 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 640 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 641 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 642 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 643 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk); 644 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 645 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 646 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bBypass);// for PS mode A/V fifo pull back 647 648 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 649 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 650 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 651 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 652 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 653 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 654 /* 655 // Only used by [HW test code] 656 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 657 */ 658 659 //=========================PCR FLT================================ 660 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 661 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId); 662 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 663 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 664 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc);//[Jason] 665 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 666 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 667 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 668 669 //=========================STC================================ 670 void HAL_TSP_STC_Init(void); 671 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 672 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 673 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 674 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 675 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 676 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); 677 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); 678 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable); 679 680 //=========================FIFO================================ 681 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 682 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 683 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 684 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType); 685 void HAL_TSP_FIFO_ClearAll (void); 686 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 687 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 688 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 689 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 690 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 691 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 692 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 693 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 694 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 695 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 696 void HAL_TSP_PS_SRC(MS_U32 tsIf); 697 void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 698 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType); // read A/V fifo data 699 MS_U16 HAL_TSP_FIFO_ReadPkt(void); // 700 void HAL_TSP_FIFO_ReadEn(MS_BOOL bEn); // 701 void HAL_TSP_FIFO_Connect(MS_BOOL bEn); // 702 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 703 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn); 704 705 //=========================VQ================================ 706 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 707 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 708 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 709 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 710 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn); 711 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 712 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 713 714 //=========================Pid Flt================================ 715 //void HAL_TSP_PidFlt_SetFltOut(MS_U32 pPidFlt, MS_U32 u32FltOu); 716 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 717 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 718 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 719 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 720 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 721 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 722 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn); 723 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 724 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 725 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 726 727 //=========================SecFlt================================ 728 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 729 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 730 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 731 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 732 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 733 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 734 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 735 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 736 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 737 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFlt, MS_U32 u32ReqCount); 738 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 739 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFlt); 740 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 741 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 742 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 743 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 744 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 745 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 746 747 //=========================Sec Buf================================ 748 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 749 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 750 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 751 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 752 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 753 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 754 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 755 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 756 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 757 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 758 759 //=========================PVR================================ 760 void HAL_PVR_SetBank(MS_U32 u32BankAddr); 761 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 762 void HAL_PVR_Exit(MS_U32 u32PVREng); 763 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 764 /* 765 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 766 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 767 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 768 */ 769 void HAL_PVR_FlushData(MS_U32 u32PVREng); 770 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 771 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 772 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 773 void HAL_PVR_Start(MS_U32 u32PVREng); 774 void HAL_PVR_Stop(MS_U32 u32PVREng); 775 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 776 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 777 void HAL_PVR_RecNull(MS_BOOL bSet); 778 void HAL_PVR_SetPidflt(MS_U32 u32PVREng, MS_U16 u16Fltid, MS_U16 u16Pid); 779 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 780 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 781 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 782 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 783 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 784 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 785 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 786 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 787 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 788 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 789 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable); 790 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime); 791 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 792 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 793 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 794 /* 795 void HAL_TSP_PVR_SPSConfig(MS_U8 u8Eng, MS_BOOL CTR_mode); 796 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode); 797 */ 798 799 //=========================RASP================================ 800 MS_U32 HAL_RASP_Set_Source(MS_U32 u32RASPEng, MS_U32 pktDmxId); 801 MS_U32 HAL_RASP_Get_Source(MS_U32 u32RASPEng, TSP_SRC_SEQ *eSrc); 802 803 //=========================FQ================================ 804 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc); 805 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng); 806 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull); 807 808 //=========================HCMD================================ 809 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 810 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 811 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 812 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 813 MS_BOOL HAL_TSP_HCMD_Alive(void); 814 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 815 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 816 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 817 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 818 819 //=========================INT================================ 820 void HAL_TSP_INT_Enable(MS_U32 u32Mask); 821 void HAL_TSP_INT_Disable(MS_U32 u32Mask); 822 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask); 823 MS_U32 HAL_TSP_INT_GetHW(void); 824 void HAL_TSP_INT_ClrSW(void); 825 MS_U32 HAL_TSP_INT_GetSW(void); 826 827 //=========================Mapping================================ 828 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 829 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 830 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 831 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 832 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 833 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 834 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 835 MS_U32 HAL_TSP_PVRRASPEngMapping(MS_U32 u32Eng); 836 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 837 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 838 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 839 840 //========================DSCMB Functions=================================== 841 extern MS_BOOL HAL_DSCMB_GetBank(MS_U32 *u32Bank); 842 extern MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 843 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 844 845 //========================MOBF Functions===================================== 846 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 847 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 848 849 //========================Protection range=================================== 850 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 851 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 852 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 853 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 854 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 855 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 856 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 857 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 858 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 859 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 860 861 //========================Debug table============================= 862 863 // @TODO Renaming Load and Get 864 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 865 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 866 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_BOOL bLock); 867 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif); 868 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 869 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 870 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 871 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 872 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 873 874 // @TODO Implement Drop and Dis Hal 875 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId); 876 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn); 877 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload); 878 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop); 879 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 880 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 881 882 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 883 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 884 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void); 885 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif); 886 887 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); 888 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 889 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); 890 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); 891 892 //========================MergeStream Functions============================= 893 void HAL_TSP_PktConverter_Init(void); 894 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 895 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet); 896 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet); 897 /* 898 void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen); 899 */ 900 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 901 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId); 902 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 903 904 //==========================TSIO ============================================ 905 void HAL_TSP_Privilege_Enable(MS_BOOL bEnable); 906 907 #endif // #ifndef __HAL_PVR_H__ 908