1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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92 ////////////////////////////////////////////////////////////////////////////////
93 #define _HAL_NSK2_C
94
95 ////////////////////////////////////////////////////////////////////////////////
96 /// @file halEMMflt.c
97 /// @author MStar Semiconductor Inc.
98 /// @brief
99 ////////////////////////////////////////////////////////////////////////////////
100
101 ////////////////////////////////////////////////////////////////////////////////
102 // Header Files
103 ////////////////////////////////////////////////////////////////////////////////
104 #ifdef MSOS_TYPE_LINUX_KERNEL
105 #include <linux/string.h>
106 #else
107 #include "string.h"
108 #endif
109
110 #include "MsCommon.h"
111 #include "MsTypes.h"
112 #include "drvSYS.h"
113
114 #include "halNSK2.h"
115 #include "regNSK2.h"
116 #include "MsOS.h"
117
118 #include "regTSP.h" // todo
119 #include "halTSP.h" // todo
120 #include "drvDSCMB.h"
121 #include "halDSCMB.h" // todo
122
123 #include "drvNSK2Type.h"
124 #include "drvCA.h"
125
126 #include "nsk_282.h"
127
128 ////////////////////////////////////////////////////////////////////////////////
129 // Define & data type
130 ///////////////////////////////////////////////////////////////////////////////
131
132 //#define SlowClockTest
133
134 #define POLLING_CNT 100
135
136 #ifdef SlowClockTest
137 #define BUSYCHECK_CNT 0x1000000
138 #else
139 #define BUSYCHECK_CNT 100
140 #endif
141
142 static MS_U32 _gBasicAddr = 0;
143 static MS_U32 _gNSK2_Addr = 0;
144 static MS_U32 _gOTP_Addr = 0;
145 static MS_U32 _gOTP_CTRL_Addr = 0;
146 static MS_U32 _gNI_Addr = 0;
147 static MS_U32 _gRSA_Addr = 0;
148 static MS_U32 _gKeyTable_Addr = 0;
149 static MS_U32 _gNDSJTagPwd_Addr = 0;
150 static MS_U32 _gCipherCH0_Addr = 0;
151 static MS_U32 _gCryptoDMA_Addr = 0;
152
153 static MS_U32 _g32NSK2HalDbgLv = NSK2_DBGLV_DEBUG;
154
155 #define HALNSK2_DBG(lv, x, args...) if (lv <= _g32NSK2HalDbgLv ) \
156 {printf(x, ##args);}
157
158 //bank 0x1700
159 #define OTP_REG(addr) (*((volatile MS_U32*)(_gOTP_Addr + addr )))
160
161 //bank 0x1a13
162 #define OTP_CTRL_REG(addr) (*((volatile MS_U32*)(_gOTP_CTRL_Addr + (addr<<2) )))
163
164 //bank 0x1620
165 #define NI_REG(addr) (*((volatile MS_U32*)(_gNI_Addr + (addr<<2) )))
166
167 //bank 1630
168 #define RSA_REG(addr) (*((volatile MS_U32*)(_gRSA_Addr + (addr<<2) )))
169
170 //bank 1626
171 #define KeyTable_REG(addr) (*((volatile MS_U32*)(_gKeyTable_Addr + (addr<<2) )))
172
173 //bank xxxxxx
174 #define NDSJTagPwd_REG(addr) (*((volatile MS_U16*)(_gNDSJTagPwd_Addr + (addr<<2) )))
175
176 //bank 1621
177 #define CMCHANNEL0_REG(addr) (*((volatile MS_U32*)(_gCipherCH0_Addr + (addr<<2) )))
178
179
180 //#define FPGAMode
181 //#define NSK2SelfTest
182
183 //#define TestGenIn
184 //#define ReadSwitchInfoNSK2
185
186
187 #define StatusCheck(status) do { if(status == FALSE) \
188 { \
189 printf("status error %s, %d\n",__FUNCTION__,__LINE__); \
190 return status; \
191 } \
192 } while(0);
193
194 #define NSK2HDI_CMCHANNEL_WITH_ALL_PARITY ( NSK2HDI_CMCHANNEL_CLEAR_PARITY | NSK2HDI_CMCHANNEL_EVEN_PARITY | NSK2HDI_CMCHANNEL_EVEN_CLEAR_PARITY | NSK2HDI_CMCHANNEL_ODD_PARITY | \
195 NSK2HDI_CMCHANNEL_ODD_CLEAR_PARITY | NSK2HDI_CMCHANNEL_ODD_EVEN_PARITY | NSK2HDI_CMCHANNEL_ODD_EVEN_CLEAR_PARITY )
196
197 #define CMCHANNEL_NSK_All_CAPABILITY (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG)
198
199 ////////////////////////////////////////////////////////////////////////////////
200 // Local variable
201 ////////////////////////////////////////////////////////////////////////////////
202
203 static MS_BOOL _gReset = FALSE;
204 static MS_BOOL _gCheckBusyFlag = FALSE;
205 static MS_U32 dead_polling_cnt = 1;
206
207 static cmchannel_group_capability_descriptor_t cm_capb =
208 {
209 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_CAPABILITY_DESC_TAG,
210 .descriptor_length = sizeof(cmchannel_group_capability_descriptor_t) - 2,
211 .number_of_channels[3] = 40,
212 .switch_combination_bitmap[0] = 0xff,
213 .user_context[0] = 'M',
214 .user_context[1] = 'S',
215 .user_context[2] = 't',
216 .user_context[3] = 'a',
217 .user_context[4] = 'r',
218 .user_context[5] = 0x00,
219 .user_context[6] = 0x00,
220 .user_context[7] = 0x00,
221 };
222
223 static cmchannel_group_algorithm_record_descriptor_t cm_algo[] =
224 {
225
226 //-------------------------------LSA---------------------------------------//
227 {
228 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
229 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
230 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
231 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_CBC,
232 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
233 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
234 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
235 },
236
237 {
238 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
239 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
240 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
241 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_RCBC,
242 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
243 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
244 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
245 },
246
247 {
248 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
249 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
250 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
251 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_CBC,
252 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
253 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
254 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
255 },
256
257 {
258 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
259 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
260 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
261 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_RCBC,
262 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
263 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
264 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
265 },
266
267 {
268 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
269 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
270 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
271 .algorithm = NSK2HDI_SPROFILE_SYNAMEDIA_AES,
272 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
273 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
274 },
275
276 {
277 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
278 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
279 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
280 .algorithm = NSK2HDI_SPROFILE_AES_ECB_CLEARTAIL,
281 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
282 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
283 },
284
285 {
286 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
287 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
288 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
289 .algorithm = NSK2HDI_SPROFILE_CIPLUS_AES,
290 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
291 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
292 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
293 },
294
295 {
296 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
297 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
298 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
299 .algorithm = NSK2HDI_SPROFILE_SCTE41_DES,
300 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
301 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
302 },
303
304 {
305 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
306 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
307 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
308 .algorithm = NSK2HDI_SPROFILE_SCTE52_DES,
309 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
310 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
311 .capability = CMCHANNEL_NSK_All_CAPABILITY,
312 },
313
314 {
315 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
316 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
317 .algorithm_type = NSK2HDI_CMCHANNEL_LSA_ALGORITHM_TYPE,
318 .algorithm = NSK2HDI_SPROFILE_TDES_ECB_CLEARTAIL,
319 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
320 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
321 },
322
323
324 //-------------------------------LSA---------------------------------------//
325 //10
326
327
328
329 //-------------------------------ESA---------------------------------------//
330 {
331 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
332 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
333 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
334 .algorithm = NSK2HDI_SPROFILE_DVB_CSA2,
335 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
336 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
337 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
338 },
339
340
341 {
342 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
343 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
344 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
345 .algorithm = NSK2HDI_SPROFILE_DVB_CSA_CONFORMANCE,
346 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
347 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
348 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
349 },
350
351 {
352 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
353 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
354 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
355 .algorithm = NSK2HDI_SPROFILE_DVB_CSA3,
356 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
357 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
358 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
359 },
360
361
362 {
363 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
364 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
365 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
366 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_CBC,
367 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
368 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
369 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
370 },
371
372 {
373 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
374 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
375 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
376 .algorithm = NSK2HDI_SPROFILE_SYNAMEDIA_AES,
377 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
378 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
379 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
380 },
381
382 {
383 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
384 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
385 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
386 .algorithm = NSK2HDI_SPROFILE_AES_ECB_CLEARTAIL,
387 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
388 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
389 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
390 },
391
392
393 {
394 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
395 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
396 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
397 .algorithm = NSK2HDI_SPROFILE_CIPLUS_AES,
398 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
399 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
400 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
401 },
402
403 {
404 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
405 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
406 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
407 .algorithm = NSK2HDI_SPROFILE_SCTE41_DES,
408 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
409 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
410 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
411 },
412
413 {
414 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
415 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
416 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
417 .algorithm = NSK2HDI_SPROFILE_SCTE52_DES,
418 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
419 .capability = CMCHANNEL_NSK_All_CAPABILITY,
420 },
421
422 {
423 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
424 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
425 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
426 .algorithm = NSK2HDI_SPROFILE_TDES_ECB_CLEARTAIL,
427 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
428 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
429 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
430 },
431
432
433 {
434 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
435 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
436 .algorithm_type = NSK2HDI_CMCHANNEL_ESA_ALGORITHM_TYPE,
437 .algorithm = NSK2HDI_SPROFILE_MULTI2_TS,
438 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
439 //.capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV2_CONFIGURE_CAPABILITY_FLAG),
440 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
441 },
442 //-------------------------------ESA---------------------------------------//
443 //24
444
445 //-------------------------------LDA---------------------------------------//
446 {
447 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
448 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
449 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
450 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_CBC,
451 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
452 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
453 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
454 },
455
456 {
457 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
458 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
459 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
460 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDI_RCBC,
461 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
462 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
463 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
464 },
465
466 {
467 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
468 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
469 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
470 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_CBC,
471 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
472 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
473 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
474 },
475
476 {
477 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
478 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
479 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
480 .algorithm = NSK2HDI_SPROFILE_CPCM_LSA_MDD_RCBC,
481 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
482 //.capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
483 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
484 },
485
486 {
487 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
488 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
489 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
490 .algorithm = NSK2HDI_SPROFILE_SYNAMEDIA_AES,
491 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
492 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
493 },
494
495 {
496 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
497 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
498 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
499 .algorithm = NSK2HDI_SPROFILE_AES_ECB_CLEARTAIL,
500 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
501 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG,
502 },
503
504 {
505 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
506 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
507 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
508 .algorithm = NSK2HDI_SPROFILE_CIPLUS_AES,
509 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
510 //.capability = CMCHANNEL_NSK_All_CAPABILITY,
511 .capability = (NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV1_CONFIGURE_CAPABILITY_FLAG | NSK2HDI_CMCHANNEL_IV_WRITEKEY_CAPABILITY_FLAG),
512 },
513
514 {
515 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
516 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
517 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
518 .algorithm = NSK2HDI_SPROFILE_SCTE41_DES,
519 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
520 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
521 },
522
523 {
524 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
525 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
526 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
527 .algorithm = NSK2HDI_SPROFILE_SCTE52_DES,
528 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
529 .capability = CMCHANNEL_NSK_All_CAPABILITY,
530 },
531
532 {
533 .descriptor_tag = NSK2HDI_CMCHANNELGROUP_ALGORITHM_RECORD_DESC_TAG,
534 .descriptor_length = sizeof(cmchannel_group_algorithm_record_descriptor_t) - 2,
535 .algorithm_type = NSK2HDI_CMCHANNEL_LDA_ALGORITHM_TYPE,
536 .algorithm = NSK2HDI_SPROFILE_TDES_ECB_CLEARTAIL,
537 .parity_combination_bitmap = NSK2HDI_CMCHANNEL_WITH_ALL_PARITY,
538 .capability = NSK2HDI_CMCHANNEL_NSK_CAPABILITY_FLAG ,
539 },
540
541 //-------------------------------LDA---------------------------------------//
542 //34
543
544 };
545
546 static M2MChGr_Capa_Desc_t m2m_capa_desc = {
547 .descriptor_tag = NSK2HDI_M2MCHANNELGROUP_CAPABILITY_DESC_TAG,
548 .descriptor_length = sizeof(M2MChGr_Capa_Desc_t) - 2,
549 .number_of_channels[3] = 0x1,
550 .user_context[0] = 0x4e,
551 .user_context[1] = 0x44,
552 .user_context[2] = 0x53,
553 .user_context[3] = 0x5f,
554 .user_context[4] = 0x44,
555 .user_context[5] = 0x52,
556 .user_context[6] = 0x4d,
557 .user_context[7] = 0x00,
558 };
559
560 static M2MChGr_AlgoRecord_Desc_t m2m_algo[] =
561 {
562 {
563 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
564 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
565 .algorithm = NSK2HDI_SPROFILE_M2M_DES_ECB_CLR_CLR,
566 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
567 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
568 },
569
570 {
571 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
572 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
573 .algorithm = NSK2HDI_SPROFILE_M2M_DES_CBC_SCTE52_IV1,
574 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
575 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
576 },
577
578 {
579 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
580 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
581 .algorithm = NSK2HDI_SPROFILE_M2M_DES_CBC_SCTE52_IV2,
582 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
583 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
584 },
585
586 {
587 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
588 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
589 .algorithm = NSK2HDI_SPROFILE_M2M_DES_CBC_CLR_CLR,
590 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
591 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
592 },
593
594 {
595 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
596 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
597 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_ECB_CLR_CLR,
598 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
599 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
600 },
601
602 {
603 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
604 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
605 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_CBC_SCTE52_IV1,
606 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
607 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
608 },
609
610 {
611 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
612 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
613 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_CBC_SCTE52_IV2,
614 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
615 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
616 },
617
618 {
619 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
620 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
621 .algorithm = NSK2HDI_SPROFILE_M2M_TDES_CBC_CLR_CLR,
622 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
623 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
624 },
625
626 {
627 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
628 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
629 .algorithm = NSK2HDI_SPROFILE_M2M_AES_ECB_CLR_CLR,
630 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
631 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
632 },
633
634 {
635 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
636 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
637 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_CTS_IV1,
638 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
639 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
640 },
641
642 {
643 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
644 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
645 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_CTS_CLR,
646 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
647 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
648 },
649
650 {
651 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
652 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
653 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_SCTE52_IV1,
654 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
655 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
656 },
657
658 {
659 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
660 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
661 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_SCTE52_CLR,
662 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
663 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
664 },
665
666 {
667 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
668 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
669 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CBC_CLR_CLR,
670 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
671 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
672 },
673
674 {
675 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
676 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
677 .algorithm = NSK2HDI_SPROFILE_M2M_RC4_64,
678 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
679 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
680 },
681
682 {
683 .descriptor_tag = NSK2HDI_M2MCHANNEL_OPERATION_DESC_TAG,
684 .descriptor_length = sizeof(M2MChGr_AlgoRecord_Desc_t) - 2,
685 .algorithm = NSK2HDI_SPROFILE_M2M_AES_CTR,
686 .capability[0] = (MS_U8)(NSK2HDI_M2MCHANNELGROUP_NSK_CAPABILITY_FLAG>>24),
687 .capability[3] = NSK2HDI_M2MCHANNELGROUP_NON_NSK_CAPABILITY_FLAG,
688 },
689 };
690
691
692 static DMA_Capa_Desc_t dma_capa_desc = {
693 .descriptor_tag = NSK2HDI_DMA_CAPABILITY_DESC_TAG,
694 .descriptor_length = sizeof(DMA_Capa_Desc_t) - 2,
695 .maximum_data_size[0] = 0,
696 .maximum_data_size[1] = 0,
697 .maximum_data_size[2] = 0,
698 .maximum_data_size[3] = 1,
699 .minimum_data_size[0] = 0x01,
700 .data_size_granularity[0] = 0x4,
701 .data_alignment[0] = 0x4,
702 .capability[0] = NSK2HDI_DMA_CONTIGUOUS_MEMORY_TYPE,
703 };
704 ////////////////////////////////////////////////////////////////////////////////
705 // Global variable
706 ////////////////////////////////////////////////////////////////////////////////
707
708
709
710 ////////////////////////////////////////////////////////////////////////////////
711 // Extern Function
712 ////////////////////////////////////////////////////////////////////////////////
713
714 extern MS_U32 TSP32_IdrR(TSP32 *preg);
715 extern void TSP32_IdrW(TSP32 *preg, MS_U32 value);
716 extern int ChkForNskTest(volatile unsigned int *OtpMemBase, volatile unsigned int *RSABase,
717 volatile unsigned int *NIBase, volatile unsigned int *CCh0Base);
718 extern int HW_CompareKTvalid(unsigned int pid_no, unsigned int scb, unsigned int compare, volatile unsigned int *KTBase);
719 extern void acpu_w_pidslotmap (unsigned char indx, unsigned char wmux, unsigned char wdata, volatile unsigned int *KTBase);
720 extern void acpu_r_keyslot (unsigned char key_indx, unsigned char key_field, volatile unsigned int *KTBase);
721
722
723 ////////////////////////////////////////////////////////////////////////////////
724 // Function Declaration
725 ////////////////////////////////////////////////////////////////////////////////
726
727 ////////////////////////////////////////////////////////////////////////////////
728 // Local Function
729 ////////////////////////////////////////////////////////////////////////////////
730
731
HAL_NSK2_ReadReg(MS_U32 u32RegAddr)732 static MS_U32 HAL_NSK2_ReadReg(MS_U32 u32RegAddr)
733 {
734 if(_gReset == FALSE)
735 return 0;
736 MS_U32 u32reg;
737 MS_U32 u32Data;
738 u32reg = u32RegAddr + _gNSK2_Addr;
739 u32Data = (*(volatile MS_U32*)(u32reg));
740
741 HALNSK2_DBG(NSK2_DBGLV_ARRAY, "read NSK2 %x = %x\n",u32RegAddr,u32Data);
742
743 return u32Data;
744 }
745
HAL_NSK2_WriteReg(MS_U32 u32RegAddr,MS_U32 u32Data)746 static void HAL_NSK2_WriteReg(MS_U32 u32RegAddr,MS_U32 u32Data)
747 {
748 if(_gReset == FALSE)
749 return ;
750 MS_U32 u32reg;
751 u32reg = u32RegAddr + _gNSK2_Addr;
752 (*(volatile MS_U32*)(u32reg)) = u32Data;
753
754 HALNSK2_DBG(NSK2_DBGLV_ARRAY, "write NSK2 %x = %x\n",u32RegAddr,u32Data);
755 }
756
HAL_NSK2_KIW_BusyPolling(void)757 static MS_U32 HAL_NSK2_KIW_BusyPolling(void)
758 {
759 MS_U32 xiu_rdata;
760 MS_U32 cnt = 0;
761
762 xiu_rdata = NI_REG(REG_NI_STATUS);
763 while( (xiu_rdata & NI_KIW_BUSY) && (cnt < POLLING_CNT) )
764 {
765 xiu_rdata = NI_REG(REG_NI_STATUS);
766 HALNSK2_DBG(NSK2_DBGLV_INFO," read NI (STATUS = %x)\n",xiu_rdata);
767
768 cnt ++;
769 MsOS_DelayTask(1);
770 }
771
772 if(cnt >= POLLING_CNT)
773 {
774 HALNSK2_DBG(NSK2_DBGLV_ERR,"KIW_BusyPolling TimeOut\n");
775 return FALSE;
776 }
777 else
778 {
779 return TRUE;
780 }
781 }
782
HAL_NSK2_CheckBusy(void)783 static MS_U32 HAL_NSK2_CheckBusy(void)
784 {
785 //printf("_gCheckBusyFlag = %x\n",_gCheckBusyFlag);
786 if(_gCheckBusyFlag == TRUE)
787 {
788 MS_U32 cnt = 0;
789
790 #ifdef SlowClockTest
791 while( (cnt < BUSYCHECK_CNT) && (HAL_NSK2_ReadReg(REG_NSK2_ACPU_WARNING) & NSK2_ACPU_BUSY) )
792 {
793 cnt ++;
794 //MsOS_DelayTaskUs(1);
795 }
796 #else
797 while( (cnt < BUSYCHECK_CNT) && (HAL_NSK2_ReadReg(REG_NSK2_ACPU_WARNING) & NSK2_ACPU_BUSY) )
798 {
799 cnt ++;
800 MsOS_DelayTask(1);
801 }
802 #endif
803
804 if(cnt == BUSYCHECK_CNT)
805 {
806 HALNSK2_DBG(NSK2_DBGLV_ERR, "NSK2 is still busy\n");
807 return FALSE;
808 }
809 }
810 else
811 {
812 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NSK2 does't check busy\n");
813 }
814 return TRUE;
815 }
816
817
HAL_NSK2_DeadPolling(void)818 static void HAL_NSK2_DeadPolling(void)
819 {
820 #if 0
821 MS_U32 polling_cnt = dead_polling_cnt;
822 while(polling_cnt){
823 MsOS_DelayTask(10);
824 HALNSK2_DBG(NSK2_DBGLV_ERR, "Error, Dead Polling\n");
825 polling_cnt --;
826 }
827
828 //read ACPU Error....
829 HALNSK2_DBG(NSK2_DBGLV_INFO,"ACPU Error = %x\n", HAL_NSK2_ReadReg(REG_NSK2_ACPU_ERROR));
830 #endif
831 }
832
833
HAL_NSK2_OTP_Get(MS_U32 Addr,MS_U8 Msb,MS_U8 Lsb,MS_U32 * pValue)834 void HAL_NSK2_OTP_Get(MS_U32 Addr, MS_U8 Msb, MS_U8 Lsb, MS_U32 *pValue)
835 {
836 MS_U32 u32Data;
837
838 u32Data = OTP_REG(Addr);
839
840 //read back first....
841 //HALNSK2_DBG(NSK2_DBGLV_DEBUG, "read OTP %x = %x\n",Addr,u32Data);
842
843 //write value next
844
845 if( (Msb == 31) && (Lsb == 0) )
846 {
847 *pValue = u32Data;
848 }
849 else
850 {
851 *pValue = ((u32Data & BMASK(Msb:Lsb) ) >> Lsb);
852 }
853
854 }
855
856 ////////////////////////////////////////////////////////////////////////////////
857 // Global Function
858 ////////////////////////////////////////////////////////////////////////////////
859
HAL_NSK2_Init(void)860 MS_U32 HAL_NSK2_Init(void)
861 {
862 #if 0
863 MS_U32 u32Data;
864 {
865 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
866 MsOS_DelayTaskUs(1);
867
868 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
869 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA 0x1 = %x\n",u32Data);
870 }
871 #endif
872
873
874 //self test....
875 #ifdef NSK2SelfTest
876 NI_REG(REG_NI_NSK2_FREERUN) |= NI_NSK2_FREERUN_ENABLE;
877
878
879 MsOS_DelayTaskUs(1);
880 u32Data = NI_REG(REG_NI_NSK2_FREERUN);
881 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI 0x1 = %x\n",u32Data);
882 #endif
883
884
885 //set OTP timing...
886 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CC<<1)))) = 0xd;
887 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CD<<1)))) = 0x17;
888 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CE<<1)))) = 0x01;
889 MsOS_DelayTask(1);
890 (*((volatile MS_U8*)(_gBasicAddr + (0x1A27CE<<1)))) = 0x00;
891
892 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"finish NSK2.1 init\n");
893
894 return TRUE;
895 }
896
HAL_NSK2_Exit(void)897 MS_U32 HAL_NSK2_Exit(void)
898 {
899 NI_REG(REG_NI_NSK2_CTRL) &= (~NI_NSK2_RESET_DISABLE);
900 return TRUE;
901 }
902
HAL_NSK2_UnlockOTPCtrl(void)903 MS_U32 HAL_NSK2_UnlockOTPCtrl(void)
904 {
905 HALNSK2_DBG(NSK2_DBGLV_INFO, "OTP control to unlock NDS secret key\n");
906 OTP_CTRL_REG(0x10) = 0x99885a5a;
907 OTP_CTRL_REG(0x11) = 0x00114433;
908 OTP_CTRL_REG(0x12) = 0x23456789;
909 OTP_CTRL_REG(0x13) = 0xabcdef01;
910
911 return TRUE;
912 }
913
HAL_NSK2_ColdReset(void)914 MS_U32 HAL_NSK2_ColdReset(void)
915 {
916 MS_U32 u32Data;
917
918 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "%s \n",__FUNCTION__);
919
920 {
921 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
922 MsOS_DelayTaskUs(1);
923
924 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
925 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA 0x1 = %x\n",u32Data);
926 }
927
928 u32Data = NI_REG(REG_NI_NSK2_CTRL);
929
930 NI_REG(REG_NI_NSK2_CTRL) = (u32Data & (~NI_NSK2_RESET_DISABLE));
931 MsOS_DelayTaskUs(1);
932
933 u32Data &= (~NI_N2ROM_PD);
934 //u32Data &= (~NI_N2ROM_PD);
935
936 //bit 0 set to 1...
937 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_TS2NSK_ENABLE | NI_NSK2_CLK_ENABLE | NI_NSK2_RESET_DISABLE;
938
939 //MsOS_DelayTaskUs(1);
940
941 u32Data = NI_REG(REG_NI_NSK2_CTRL);
942 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI 0x0 = %x\n",u32Data);
943
944 _gReset = TRUE;
945 _gCheckBusyFlag = TRUE;
946
947 HAL_NSK2_EnableInt();
948 return TRUE;
949 }
950
951
HAL_NSK2_EndSubtest(void)952 MS_U32 HAL_NSK2_EndSubtest(void)
953 {
954 MS_U32 u32Data;
955
956 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "%s \n",__FUNCTION__);
957
958 HAL_NSK2_DisableInt();
959
960 u32Data = NI_REG(REG_NI_NSK2_CTRL);
961 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "REG_NI_NSK2_CTRL = %x \n",u32Data);
962
963 if(u32Data & NI_NSK2_RESET_DISABLE)
964 {
965
966 NI_REG(REG_NI_NSK2_CTRL) = (u32Data & (~NI_NSK2_RESET_DISABLE));
967 //NI_REG(REG_NI_NSK2_CTRL) = 0;
968 //printf("wait here\n");
969 //while(1);
970 MsOS_DelayTaskUs(1);
971 }
972
973 _gReset = FALSE;
974 _gCheckBusyFlag = FALSE;
975 return TRUE;
976 }
977
978
HAL_NSK2_SetBase(MS_U32 u32Base)979 void HAL_NSK2_SetBase(MS_U32 u32Base)
980 {
981 HALNSK2_DBG(NSK2_DBGLV_INFO, "u32Base = %x\n",u32Base);
982
983 _gBasicAddr = u32Base;
984
985 _gOTP_Addr = _gBasicAddr + REG_OTP_BASE;
986 _gRSA_Addr = _gBasicAddr + REG_RSA_BASE;
987 _gOTP_CTRL_Addr = _gBasicAddr + REG_OTP_CTRL_BASE;
988 _gNSK2_Addr = _gBasicAddr + REG_NSK2_BASE;
989
990 _gNI_Addr = _gBasicAddr + REG_NI_BASE;
991
992 _gKeyTable_Addr = _gBasicAddr + REG_KEY_TABLE_BASE;
993 _gNDSJTagPwd_Addr= _gBasicAddr + REG_JTAG_PWD_BASE;
994 _gCipherCH0_Addr = _gBasicAddr + REG_CIPHER_CH0_BASE;
995 _gCryptoDMA_Addr = _gBasicAddr + REG_CRYPTO_DMA_BASE;
996 HALNSK2_DBG(NSK2_DBGLV_INFO, "%s _gNSK2_Addr : %x\n", __FUNCTION__, _gNSK2_Addr);
997
998 //OTP_CTRL_REG(0x3A) = 0x0;
999 }
1000
1001
1002
1003
1004 //compare the contect of a buffer in the NSK2's memory map to an expected value.
HAL_NSK2_CompareMem(MS_U32 reserved,MS_U32 StartAddr,MS_U32 CompareLens,MS_U32 CompareSim,MS_U32 ExpectResult,void * pGolden)1005 MS_U32 HAL_NSK2_CompareMem(MS_U32 reserved, MS_U32 StartAddr, MS_U32 CompareLens,
1006 MS_U32 CompareSim, MS_U32 ExpectResult, void *pGolden)
1007 {
1008 MS_U32 u32ReadData, u32GoldenData;
1009 MS_U32 u32Addr = StartAddr;
1010 MS_U32 *pGoldenData = (MS_U32 *)pGolden;
1011 MS_U32 u32CompLens = CompareLens;
1012 MS_U32 status = TRUE;
1013 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s \n",__FUNCTION__);
1014 //check lengths
1015 if(u32CompLens == 0)
1016 {
1017 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s CompareLens = %x\n",__FUNCTION__,u32CompLens);
1018 }
1019
1020 do
1021 {
1022 HAL_NSK2_CheckBusy();
1023
1024 u32ReadData = HAL_NSK2_ReadReg(u32Addr);
1025 u32GoldenData = *pGoldenData;
1026
1027 if(u32ReadData != u32GoldenData)
1028 {
1029 HALNSK2_DBG(NSK2_DBGLV_ERR,"%s, Addr = %x, u32ReadData = %x, u32GoldenData = %x\n",__FUNCTION__,u32Addr, u32ReadData, u32GoldenData);
1030 HAL_NSK2_DeadPolling();
1031 //return FALSE;
1032 status = FALSE;
1033 }
1034 else
1035 {
1036 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Data Correct, Addr = %x, u32GoldenData = %x\n",u32Addr, u32GoldenData);
1037 }
1038
1039 pGoldenData ++;
1040 u32Addr += 4;
1041 u32CompLens --; //32 bit bus
1042
1043 } while(u32CompLens > 0);
1044
1045 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s, successful = %x\n",__FUNCTION__,StartAddr);
1046 return status;
1047 }
1048
HAL_NSK2_Compare(MS_U32 StartAddr,MS_U32 CompareLens,MS_U32 CompareSim,MS_U32 Mask,MS_U32 ExpectResult)1049 MS_U32 HAL_NSK2_Compare(MS_U32 StartAddr, MS_U32 CompareLens, MS_U32 CompareSim,
1050 MS_U32 Mask, MS_U32 ExpectResult)
1051 {
1052
1053 MS_U32 u32ReadData, u32GoldenData = ExpectResult;
1054 MS_U32 u32Addr = StartAddr;
1055
1056 StatusCheck(HAL_NSK2_CheckBusy());
1057
1058 u32ReadData = HAL_NSK2_ReadReg(u32Addr);
1059 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Mask = %x\n",Mask);
1060 u32ReadData &= Mask;
1061
1062 if(u32ReadData != u32GoldenData)
1063 {
1064 HALNSK2_DBG(NSK2_DBGLV_ERR,"%s fail, Addr = %x, u32ReadData = %x, u32GoldenData = %x\n",__FUNCTION__,u32Addr, u32ReadData, u32GoldenData);
1065 HAL_NSK2_DeadPolling();
1066 return FALSE;
1067 }
1068 else
1069 {
1070 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"compare data correct, Addr = %x, u32GoldenData = %x\n",u32Addr,u32GoldenData);
1071 }
1072
1073 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"%s, successful\n",__FUNCTION__);
1074 return TRUE;
1075 }
1076
HAL_NSK2_WriteMem(MS_U32 reserved,MS_U32 StartAddr,MS_U32 WriteLens,void * pWriteData)1077 MS_U32 HAL_NSK2_WriteMem(MS_U32 reserved, MS_U32 StartAddr, MS_U32 WriteLens,
1078 void *pWriteData)
1079 {
1080
1081 MS_U32 *pWriteD = (MS_U32 *)pWriteData;
1082 MS_U32 u32Data;
1083 while(WriteLens > 0)
1084 {
1085 StatusCheck(HAL_NSK2_CheckBusy());
1086
1087 u32Data = *pWriteD ;
1088
1089 HAL_NSK2_WriteReg(StartAddr,u32Data);
1090 HALNSK2_DBG(NSK2_DBGLV_ARRAY,"WriteMem (Addr,Data) = (%x,%x)\n",StartAddr,u32Data);
1091
1092 WriteLens --;
1093 StartAddr += 4;
1094 pWriteD ++;
1095 }
1096
1097 StatusCheck(HAL_NSK2_CheckBusy());
1098 return TRUE;
1099 }
1100
HAL_NSK2_WriteSFR(MS_U32 StartAddr,MS_U32 Data)1101 MS_U32 HAL_NSK2_WriteSFR(MS_U32 StartAddr, MS_U32 Data)
1102 {
1103 StatusCheck(HAL_NSK2_CheckBusy());
1104 HALNSK2_DBG(NSK2_DBGLV_ARRAY,"WriteSFR (Addr,Data) = (%x,%x)\n",StartAddr,Data);
1105 HAL_NSK2_WriteReg(StartAddr,Data);
1106 StatusCheck(HAL_NSK2_CheckBusy());
1107 return TRUE;
1108 }
1109
HAL_NSK2_NSKBasicInitializationComplete(void)1110 MS_U32 HAL_NSK2_NSKBasicInitializationComplete(void)
1111 {
1112 //$display($time,"NS NSKBasicInitializationComplete ");
1113 //xiu_w_ni(16'h6,4'b0001,32'h0000000F);
1114
1115 MS_U32 data;
1116 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_NSKBasicInitializationComplete\n");
1117 StatusCheck(HAL_NSK2_CheckBusy());
1118
1119 data = NI_REG(REG_NI_COMMAND);
1120 //NI_REG(REG_NI_COMMAND) = (data | NI_NSKBIComplete | NI_COMMAND_START);
1121 NI_REG(REG_NI_COMMAND) = (NI_NSKBIComplete | NI_COMMAND_START);
1122
1123 MsOS_DelayTaskUs(1);
1124 //NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_NopNop);
1125 NI_REG(REG_NI_NSK2_CLK_CSA) = NSK2_EN_CSA_VAR;
1126
1127
1128 return TRUE;
1129 }
1130
HAL_NSK2_SCBTransToHW(MS_U8 ForceSCB)1131 MS_U8 HAL_NSK2_SCBTransToHW(MS_U8 ForceSCB)
1132 {
1133 MS_U8 NewForceSCB = 0;
1134
1135 NewForceSCB = ForceSCB;
1136 if(ForceSCB == 0)
1137 {
1138 NewForceSCB = 1;
1139 }
1140 else if(ForceSCB == 1)
1141 {
1142 NewForceSCB = 0;
1143 }
1144
1145 return NewForceSCB;
1146 }
1147
1148
HAL_NSK2_WriteESA(MS_U8 ESASelect,MS_U8 ESASubSelect,MS_U8 pid_no)1149 MS_U32 HAL_NSK2_WriteESA(MS_U8 ESASelect, MS_U8 ESASubSelect, MS_U8 pid_no)
1150 {
1151 #if 0
1152 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteESA pid_no = %x, ESASelect = %x, ESASubSelect = %x\n",pid_no, ESASelect, ESASubSelect);
1153 //scb = 2'b00; pid_no = 1; ESAselect = 4'h0; ESAsubselect =4'h0;
1154 //wdata = {10'b0,ESAselect[3:0],ESAsubselect[2:0],3'b0,pid_no[12:0]};
1155 //xiu_w_ni(16'h7,4'b1111,wdata[31:0]);
1156 //xiu_w_ni(16'h6,4'b1111,32'h00000003);
1157 //xiu_rdata = 32'h8; while(xiu_rdata[3]===1'b1)begin xiu_r_ni(16'hc); end
1158 StatusCheck(HAL_NSK2_CheckBusy());
1159
1160 MS_U32 data;
1161
1162 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteESA pid_no = %x\n",pid_no);
1163 data = (((MS_U32)ESASelect<<NI_WriteESA_ESASel_Shift) & NI_WriteESA_ESASel_MASK) +
1164 (((MS_U32)ESASubSelect<<NI_WriteESA_ESASubSel_Shift) & NI_WriteESA_ESASubSel_MASK) +
1165 ((MS_U32)pid_no & NI_WriteESA_PidNo);
1166
1167
1168 HALNSK2_DBG(NSK2_DBGLV_INFO," write NI (REG_NI_PARAMETERS = %x)\n",data);
1169 NI_REG(REG_NI_PARAMETERS) = data;
1170 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteESA);
1171
1172 StatusCheck(HAL_NSK2_KIW_BusyPolling());
1173 #endif
1174 return TRUE;
1175 }
1176
HAL_NSK2_WriteTransportKey(MS_U8 SCB,MS_U8 ForceSCB,void * pLabel,MS_U8 pid_no)1177 MS_U32 HAL_NSK2_WriteTransportKey(MS_U8 SCB, MS_U8 ForceSCB, void *pLabel, MS_U8 pid_no)
1178 {
1179 #if 0
1180 //$display($time,"NS WriteTransportKey 0134 00 01 IV__0");
1181 //wait_nsk_busy;
1182 //xiu_r_ni(16'hd);
1183 //if((xiu_rdata & 7)==0) begin
1184 // scb = 2'b00; fscb = 2'b00; pid_no = 1;
1185 // wdata = {12'b0,fscb[1:0],scb[1:0],3'b0,pid_no[12:0]};
1186 // xiu_w_ni(16'h7,4'b1111,wdata[31:0]);
1187 // xiu_w_ni(16'hb,4'b1111,32'h00000000);
1188 // xiu_w_ni(16'ha,4'b1111,32'h00000000);
1189 // xiu_w_ni(16'h9,4'b1111,32'h00000000);
1190 // xiu_w_ni(16'h8,4'b1111,32'h00000000);
1191 // xiu_w_ni(16'h6,4'b1111,32'h00000005);
1192 // xiu_rdata = 32'h8; while(xiu_rdata[3]===1'b1)begin xiu_r_ni(16'hc); end
1193 //end
1194 //else $display("WriteTransportKey abnormal ignored: KteDest not zero");
1195 #define N 0xfffffff0
1196 #define N1 0xfffffff1
1197 #define N2 0xfffffff2
1198
1199 MS_U32 data = 0;
1200 MS_U32 data2 = 0;
1201 MS_U32 pIV[4] = {0,0,0,0};
1202
1203 MS_U32* pIV_copy = (MS_U32*)pLabel;
1204
1205 if((pLabel != NULL) && (pLabel != (MS_U32*)N) && (pLabel != (MS_U32*)N1) && (pLabel != (MS_U32*)N2))
1206 {
1207 memcpy(pIV,pIV_copy,16);
1208 }
1209
1210 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteTransportKey pid_no = %x, SCB = %x, ForceSCB = %x\n",pid_no, SCB, ForceSCB);
1211 StatusCheck(HAL_NSK2_CheckBusy());
1212
1213 data = NI_REG(REG_NI_KTE_STATUS);
1214 if( ( data & NI_KTE_DEST_MASK ) == 0 )
1215 {
1216
1217 ForceSCB = HAL_NSK2_SCBTransToHW(ForceSCB);
1218
1219 HALNSK2_DBG(NSK2_DBGLV_INFO,"pid_no: %x\n", pid_no);
1220 data2 = pid_no + ( ( (MS_U32)SCB<<NI_WriteTKey_SCB_Shift) & NI_WriteTKey_SCB_MASK)
1221 + ( ( (MS_U32)ForceSCB<<NI_WriteTKey_FSCB_Shift) & NI_WriteTKey_FSCB_MASK) ;
1222
1223
1224 NI_REG(REG_NI_PARAMETERS) = data2;
1225 NI_REG(REG_NI_IV_127_96) = pIV[0];
1226 NI_REG(REG_NI_IV_95_64) = pIV[1];
1227 NI_REG(REG_NI_IV_63_31) = pIV[2];
1228 NI_REG(REG_NI_IV_31_00) = pIV[3];
1229 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteTransportKey);
1230
1231 HALNSK2_DBG(NSK2_DBGLV_INFO,"NI 7 : %x, NI 6 = %x\n", NI_REG(REG_NI_PARAMETERS) , NI_REG(REG_NI_COMMAND));
1232
1233 StatusCheck(HAL_NSK2_KIW_BusyPolling());
1234 }
1235 else
1236 {
1237 HALNSK2_DBG(NSK2_DBGLV_ERR,"WriteTransportKey abnormal ignored: KteDest not zero\n");
1238 return FALSE;
1239 }
1240
1241 HAL_NSK2_ReadSwitchFromNSK2();
1242 #endif
1243 return TRUE;
1244 }
1245
HAL_NSK2_wait_kte_valid(void)1246 MS_U32 HAL_NSK2_wait_kte_valid(void)
1247 {
1248 MS_U32 xiu_rdata = HAL_NSK2_ReadReg(REG_NSK2_KTE_VALID);
1249 MS_U32 cnt = 0;
1250 while( ( (xiu_rdata & NSK2_KTE_VALID_TRUE) == 0 ) && (cnt < POLLING_CNT) )
1251 {
1252 xiu_rdata = HAL_NSK2_ReadReg(REG_NSK2_KTE_VALID);
1253 HALNSK2_DBG(NSK2_DBGLV_INFO,"xiu_rdata = %x\n",xiu_rdata);
1254 cnt ++;
1255 MsOS_DelayTask(1);
1256 }
1257
1258 if(cnt == POLLING_CNT)
1259 {
1260 HALNSK2_DBG(NSK2_DBGLV_ERR,"HAL_NSK2_wait_kte_valid time out\n");
1261 return FALSE;
1262 }
1263
1264 return TRUE;
1265 }
1266
HAL_NSK2_CompareKTE(MS_U32 reserved_1,MS_U32 reserved_2,void * pLabel)1267 MS_U32 HAL_NSK2_CompareKTE(MS_U32 reserved_1, MS_U32 reserved_2, void *pLabel)
1268 {
1269
1270 #ifdef FPGAMode
1271 MS_U32 data;
1272 MS_U32 *pKTEGolden = (MS_U32 *)pLabel;
1273 MS_U32 KTE_Index = REG_KT_KEYS_START_FPGA;
1274 MS_U32 status = TRUE;
1275
1276 StatusCheck(HAL_NSK2_CheckBusy());
1277 //StatusCheck(HAL_NSK2_wait_kte_valid());
1278 data = NI_REG(REG_NI_NSK2_KTE_VALID_FPGA);
1279 HALNSK2_DBG(NSK2_DBGLV_INFO,"NSK2_KTE_VALID_FPGA = %x\n",data);
1280
1281 for(KTE_Index = REG_KT_KEYS_END_FPGA; KTE_Index<=REG_KT_KEYS_START_FPGA; KTE_Index--)
1282 {
1283 data = NI_REG(KTE_Index);
1284
1285 if(data != *pKTEGolden)
1286 {
1287 HALNSK2_DBG(NSK2_DBGLV_ERR," %x, (%x , %x)\n",KTE_Index,data,*pKTEGolden);
1288 status = FALSE;
1289 }
1290
1291 pKTEGolden ++;
1292 }
1293
1294 return status;
1295
1296 #else
1297
1298 #endif
1299
1300 return TRUE;
1301 }
1302
HAL_NSK2_CompareOut(MS_U32 reserved_1,MS_U32 reserved_2,MS_U32 HighDWord,MS_U32 LowDWord)1303 MS_U32 HAL_NSK2_CompareOut(MS_U32 reserved_1, MS_U32 reserved_2, MS_U32 HighDWord, MS_U32 LowDWord)
1304 {
1305
1306 //wait_nsk_busy;
1307 //$display($time,"NS CompareOut 1 1 0000001555400000");
1308 //xiu_r_ni(16'd24); genout = xiu_rdata; genout = genout << 32;
1309 //xiu_r_ni(16'd23); genout = genout | {6'b0,xiu_rdata[31:0]};
1310 //$display("CompareOut read PS",genout[37:0]);
1311 // if(genout!==38'h0000001555400000)begin
1312 //$display("CompareOut Expected=38'h0000001555400000 Read=38'hPS",genout[37:0]);
1313 // nsk2_GeneralOut_test_fail = 1;
1314 // #2000;
1315 //$finish;
1316 //end
1317
1318
1319 MS_U32 high_data,low_data;
1320 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_CompareOut HighDWord = %x, LowDWord = %x\n",HighDWord, LowDWord);
1321 StatusCheck(HAL_NSK2_CheckBusy());
1322 low_data = NI_REG(REG_NI_COMPARE_GENOUT_L);
1323 high_data = (NI_REG(REG_NI_COMPARE_GENOUT_H)&NI_GENOUT_H_MASK);
1324 HALNSK2_DBG(NSK2_DBGLV_INFO,"NI 24 = %x , 23 = %x\n",high_data,low_data);
1325
1326 if( (HighDWord != high_data) || (LowDWord!= low_data) )
1327 {
1328 HAL_NSK2_DeadPolling();
1329 return FALSE;
1330 }
1331 else
1332 {
1333 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_CompareOut successfully\n");
1334 }
1335
1336 return TRUE;
1337 }
1338
HAL_NSK2_SetRNG(MS_U32 reserved_1,MS_U32 RNG_Value)1339 MS_U32 HAL_NSK2_SetRNG(MS_U32 reserved_1,MS_U32 RNG_Value)
1340 {
1341
1342 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_SetRNG = %x\n",RNG_Value);
1343 NI_REG(REG_NI_SW_SET_RNG) = (RNG_Value&NI_SW_RNG_MASK);
1344 return TRUE;
1345 }
1346
HAL_NSK2_WriteM2MKey(void * pIV,MS_U8 SubAlgo)1347 MS_U32 HAL_NSK2_WriteM2MKey(void *pIV, MS_U8 SubAlgo)
1348 {
1349 #if 0
1350 //wait_nsk_busy;
1351 //WriteM2MKey IV__1 0
1352 //$display($time,"NS WriteM2MKey IV__1 0");
1353 //wdata = {12'b0,4'h0,16'b0};
1354 //xiu_w_ni(16'h7,4'b1111,wdata[31:0]);
1355 //xiu_w_ni(16'hb,4'b1111,32'h00010203);
1356 //xiu_w_ni(16'ha,4'b1111,32'h04050607);
1357 //xiu_w_ni(16'h9,4'b1111,32'h08090a0b);
1358 //xiu_w_ni(16'h8,4'b1111,32'h0c0d0e0f);
1359 //xiu_w_ni(16'h6,4'b1111,32'h00000007);
1360 //xiu_rdata = 32'h8; while(xiu_rdata[3]===1'b1)begin xiu_r_ni(16'hc); end
1361
1362 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_WriteM2MKey, SubAlgo = %x \n", SubAlgo);
1363 HAL_NSK2_CheckBusy();
1364
1365 MS_U32 wdata = 0;
1366 MS_U32 pWIV[4];
1367
1368 memset(pWIV, 0x0, 4*4);
1369 if(pIV != NULL)
1370 {
1371 memcpy(pWIV,pIV,4*4);
1372 }
1373
1374
1375 wdata = ( ((MS_U32)SubAlgo << NI_WriteM2MKey_Shift) & NI_WriteM2MKey_MASK); //write sub algorithm....[19:16]
1376 NI_REG(REG_NI_PARAMETERS) = wdata;
1377
1378 NI_REG(REG_NI_IV_127_96) = pWIV[0];
1379 NI_REG(REG_NI_IV_95_64) = pWIV[1];
1380 NI_REG(REG_NI_IV_63_31) = pWIV[2];
1381 NI_REG(REG_NI_IV_31_00) = pWIV[3];
1382
1383 HALNSK2_DBG(NSK2_DBGLV_INFO,"pwIV = (%x, %x, %x, %x)\n",pWIV[0],pWIV[1],pWIV[2],pWIV[3]);
1384 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteM2MKey); //write M2M key and start...
1385 #endif
1386 return TRUE;
1387 }
1388
HAL_NSK2_WriteSCPUKey(void)1389 MS_U32 HAL_NSK2_WriteSCPUKey(void)
1390 {
1391 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n", __FUNCTION__);
1392 StatusCheck(HAL_NSK2_CheckBusy());
1393 NI_REG(REG_NI_COMMAND) = (NI_WriteSCPUKey | NI_COMMAND_START);
1394 MsOS_DelayTaskUs(1);
1395
1396 return HAL_NSK2_ReadKTEResp();
1397 }
1398
1399 static MS_U32 KeyNum = 0;
HAL_NSK2_WriteReservedKey(void)1400 MS_U32 HAL_NSK2_WriteReservedKey(void)
1401 {
1402 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n", __FUNCTION__);
1403 StatusCheck(HAL_NSK2_CheckBusy());
1404 NI_REG(REG_NI_COMMAND) = (NI_WriteReservedKey | NI_COMMAND_START);
1405 MsOS_DelayTaskUs(1);
1406
1407 HALNSK2_DBG(NSK2_DBGLV_INFO,"write key = %x, %x\n", NI_REG(REG_NI_COMPARE_GENOUT_L), NI_REG(REG_NI_COMPARE_GENOUT_H));
1408 KeyNum = NI_REG(REG_NI_COMPARE_GENOUT_L)>>17;
1409
1410 return HAL_NSK2_ReadKTEResp();
1411 }
1412
HAL_NSK2_GetReserveKeyNum(void)1413 MS_U32 HAL_NSK2_GetReserveKeyNum(void)
1414 {
1415 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s KeyNum = %x\n", __FUNCTION__,KeyNum);
1416 return KeyNum;
1417 }
1418
HAL_NSK2_DriveKteAck(void)1419 MS_U32 HAL_NSK2_DriveKteAck(void)
1420 {
1421 //DriveKteAck
1422 //$display($time,"NS DriveKteAck");
1423 //xiu_w_ni(16'h6,4'b1111,32'h0000000B);
1424
1425 StatusCheck(HAL_NSK2_CheckBusy());
1426 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n", __FUNCTION__);
1427
1428 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_DriveAck);
1429 MsOS_DelayTaskUs(1);
1430 StatusCheck(HAL_NSK2_CheckBusy());
1431 return TRUE;
1432 }
1433
HAL_NSK2_SetJTagPswd(void)1434 MS_U32 HAL_NSK2_SetJTagPswd(void)
1435 {
1436
1437 #if 0
1438 #define JTagPwd0Addr 0x64
1439 #define InputPwd0Addr 0x4
1440 MS_U32 JTagPwd0[4];
1441
1442 NDSJTagPwd_REG(3) = 0x0;
1443 NDSJTagPwd_REG(2) = 0x0;
1444 NDSJTagPwd_REG(1) = 0x0;
1445 NDSJTagPwd_REG(0) = 0x1;
1446
1447 NDSJTagPwd_REG(0x14) = 0x1;
1448
1449 JTagPwd0[0] = KeyTable_REG(JTagPwd0Addr);
1450 JTagPwd0[1] = KeyTable_REG((JTagPwd0Addr+1));
1451 JTagPwd0[2] = KeyTable_REG((JTagPwd0Addr+2));
1452 JTagPwd0[3] = KeyTable_REG((JTagPwd0Addr+3));
1453
1454 HALNSK2_DBG(0,"JTagPwd0 = %x, %x, %x, %x\n",JTagPwd0[0],JTagPwd0[1],JTagPwd0[2],JTagPwd0[3]);
1455
1456 NDSJTagPwd_REG((InputPwd0Addr+7)) = (MS_U16) ((JTagPwd0[3]>>16)&0xffff);
1457 NDSJTagPwd_REG((InputPwd0Addr+6)) = (MS_U16) (JTagPwd0[3]&0xffff);
1458 NDSJTagPwd_REG((InputPwd0Addr+5)) = (MS_U16) ((JTagPwd0[2]>>16)&0xffff);
1459 NDSJTagPwd_REG((InputPwd0Addr+4)) = (MS_U16) (JTagPwd0[2]&0xffff);
1460 NDSJTagPwd_REG((InputPwd0Addr+3)) = (MS_U16) ((JTagPwd0[1]>>16)&0xffff);
1461 NDSJTagPwd_REG((InputPwd0Addr+2)) = (MS_U16) (JTagPwd0[1]&0xffff);
1462 NDSJTagPwd_REG((InputPwd0Addr+1)) = (MS_U16) ((JTagPwd0[0]>>16)&0xffff);
1463 NDSJTagPwd_REG((InputPwd0Addr+0)) = (MS_U16) (JTagPwd0[0]&0xffff);
1464
1465 NDSJTagPwd_REG(0x14) = 0x7;
1466 #else
1467 MS_U32 jtag_status;
1468 jtag_status = KeyTable_REG(88);
1469 //88 bit 0 and 1 = 1
1470
1471 HALNSK2_DBG(NSK2_DBGLV_INFO,"KeyTable 88 jtag_status = %x\n",jtag_status);
1472 #endif
1473
1474 return TRUE;
1475 }
1476
1477 //MS_BOOL HAL_CA_OTP_GetCfg(MS_U32 u32Idx, MS_U32 *pu32Value);
1478
HAL_NSK2_CheckPubOTPConfig(void * pCheck)1479 MS_BOOL HAL_NSK2_CheckPubOTPConfig(void *pCheck)
1480 {
1481 #if 0
1482 OTP bits OTP name function
1483 [127:64] V_PubOtpUniqueID Unique ID, 0x3da8~0x3daf
1484 [63:48] V_PubOtpGP General Purpose Field (bit-by-bit lock),3b08~3b09
1485 [47:40] V_PubOtpMinConfVer Minimum Configuration Version,3b14
1486 [39:36] V_PubOtpRSAIndex RSA Index, 3b10
1487 [35:32] V_PubOtpBID BlackBox ID, 0x3b0c
1488 [31:16] V_PubOtpVID Version ID, 0x3b04
1489 [15:0] V_PubOtpOID Owner ID, 0x3b00
1490 #endif
1491
1492 MS_U32 *pDataArray;
1493 MS_U32 OTP_PubOtpOID,OTP_PubOtpVID,OTP_PubOtpBID,OTP_PubOtpRsaIndex,OTP_PubOtpMinConfVer ;
1494 MS_U32 OTP_PubOtpGP,OTP_PubOtpUniqueID[2];
1495
1496 MS_U32 CHK_PubOtpOID,CHK_PubOtpVID,CHK_PubOtpBID,CHK_PubOtpRsaIndex,CHK_PubOtpMinConfVer ;
1497 MS_U32 CHK_PubOtpGP,CHK_PubOtpUniqueID[2];
1498
1499 MS_BOOL status = TRUE;
1500 if(pCheck == NULL)
1501 {
1502 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, pCheck = NULL\n",__LINE__,__FUNCTION__);
1503 return FALSE;
1504 }
1505 pDataArray = (MS_U32 *)pCheck;
1506
1507 HAL_NSK2_OTP_Get(0x3da8,31,0, &OTP_PubOtpUniqueID[0]);
1508 HAL_NSK2_OTP_Get(0x3dac,31,0, &OTP_PubOtpUniqueID[1]);
1509
1510 CHK_PubOtpUniqueID[1] = pDataArray[0];
1511 CHK_PubOtpUniqueID[0] = pDataArray[1];
1512
1513 HALNSK2_DBG(NSK2_DBGLV_INFO,"uniqueID = (%x%x, %x%x)\n",CHK_PubOtpUniqueID[1],CHK_PubOtpUniqueID[0],OTP_PubOtpUniqueID[1],OTP_PubOtpUniqueID[0]);
1514
1515 if( (CHK_PubOtpUniqueID[1] != OTP_PubOtpUniqueID[1]) || (CHK_PubOtpUniqueID[0] != OTP_PubOtpUniqueID[0]))
1516 {
1517 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, UniqueID WRONG\n",__LINE__,__FUNCTION__);
1518 status = FALSE;
1519 }
1520
1521 HAL_NSK2_OTP_Get(0x3b08,15,0, &OTP_PubOtpGP);
1522 CHK_PubOtpGP = (pDataArray[2]>>16)&0xffff;
1523
1524 if(OTP_PubOtpGP != CHK_PubOtpGP)
1525 {
1526 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpGP WRONG\n",__LINE__,__FUNCTION__);
1527 HALNSK2_DBG(NSK2_DBGLV_ERR,"OtpGP = (%x, %x)\n",CHK_PubOtpGP,OTP_PubOtpGP);
1528 status = FALSE;
1529 }
1530
1531 HAL_NSK2_OTP_Get(0x3b14,7,0, &OTP_PubOtpMinConfVer);
1532 CHK_PubOtpMinConfVer = (pDataArray[2]>>8)&0xff;
1533
1534 if(OTP_PubOtpMinConfVer != CHK_PubOtpMinConfVer)
1535 {
1536 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpMinConfVer WRONG\n",__LINE__,__FUNCTION__);
1537 HALNSK2_DBG(NSK2_DBGLV_ERR,"OtpMinConfVer = (%x, %x)\n",CHK_PubOtpMinConfVer,OTP_PubOtpMinConfVer);
1538 status = FALSE;
1539 }
1540
1541 HAL_NSK2_OTP_Get(0x3b10,3,0, &OTP_PubOtpRsaIndex);
1542 CHK_PubOtpRsaIndex = (pDataArray[2]>>4)&0xf;
1543
1544 if(OTP_PubOtpRsaIndex != CHK_PubOtpRsaIndex)
1545 {
1546 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpRsaIndex WRONG\n",__LINE__,__FUNCTION__);
1547 HALNSK2_DBG(NSK2_DBGLV_ERR,"OtpRsaIndex = (%x, %x)\n",CHK_PubOtpRsaIndex,OTP_PubOtpRsaIndex);
1548 status = FALSE;
1549 }
1550
1551 HAL_NSK2_OTP_Get(0x3b0C,3,0, &OTP_PubOtpBID);
1552 CHK_PubOtpBID = (pDataArray[2])&0xf;
1553
1554 if(OTP_PubOtpBID != CHK_PubOtpBID)
1555 {
1556 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpBID WRONG\n",__LINE__,__FUNCTION__);
1557 HALNSK2_DBG(NSK2_DBGLV_ERR,"OtpBID = (%x, %x)\n",CHK_PubOtpBID,OTP_PubOtpBID);
1558 status = FALSE;
1559 }
1560
1561 HAL_NSK2_OTP_Get(0x3b04,15,0, &OTP_PubOtpVID);
1562 CHK_PubOtpVID = (pDataArray[3]>>16)&0xffff;
1563
1564 if(OTP_PubOtpVID != CHK_PubOtpVID)
1565 {
1566 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpVID WRONG\n",__LINE__,__FUNCTION__);
1567 HALNSK2_DBG(NSK2_DBGLV_ERR,"OtpVID = (%x, %x)\n",CHK_PubOtpVID,CHK_PubOtpVID);
1568 status = FALSE;
1569 }
1570
1571 HAL_NSK2_OTP_Get(0x3b00,15,0, &OTP_PubOtpOID);
1572 CHK_PubOtpOID = (pDataArray[3])&0xffff;
1573
1574 if(OTP_PubOtpOID != CHK_PubOtpOID)
1575 {
1576 HALNSK2_DBG(NSK2_DBGLV_ERR,"%d, %s, PubOtpOID WRONG\n",__LINE__,__FUNCTION__);
1577 HALNSK2_DBG(NSK2_DBGLV_ERR,"OtpOID = (%x, %x)\n",CHK_PubOtpOID,OTP_PubOtpOID);
1578 status = FALSE;
1579 }
1580
1581 MS_U32 KeyValid;
1582 HAL_NSK2_OTP_Get(0x3b1c,31,24, &KeyValid);
1583 HALNSK2_DBG(NSK2_DBGLV_INFO,"KeyValid = %x\n",KeyValid);
1584
1585 MS_U32 CheckSum[4];
1586 HAL_NSK2_OTP_Get(0x3c30,31,0, &CheckSum[0]);
1587 HAL_NSK2_OTP_Get(0x3c34,31,0, &CheckSum[1]);
1588 HAL_NSK2_OTP_Get(0x3c38,31,0, &CheckSum[2]);
1589 HAL_NSK2_OTP_Get(0x3c3c,31,0, &CheckSum[3]);
1590 HALNSK2_DBG(NSK2_DBGLV_INFO,"CheckSum = %x, %x, %x, %x\n",CheckSum[0],CheckSum[1],CheckSum[2],CheckSum[3]);
1591 return status;
1592 }
1593
HAL_NSK2_ReadDataTrans(MS_U32 read_data,MS_U8 * data)1594 static void HAL_NSK2_ReadDataTrans(MS_U32 read_data, MS_U8 *data)
1595 {
1596 data[3] = (MS_U8)(read_data & 0xff);
1597 data[2] = (MS_U8)((read_data>>8) & 0xff);
1598 data[1] = (MS_U8)((read_data>>16) & 0xff);
1599 data[0] = (MS_U8)((read_data>>24) & 0xff);
1600 }
1601
HAL_NSK2_WriteDataTrans(MS_U8 * data)1602 static MS_U32 HAL_NSK2_WriteDataTrans(MS_U8 *data)
1603 {
1604 MS_U32 write_data = 0;
1605
1606 write_data = (MS_U32)data[3] + ((MS_U32)data[2]<<8) + ((MS_U32)data[1]<<16) + ((MS_U32)data[0]<<24) ;
1607 return write_data;
1608 }
1609
HAL_NSK2_ReadData(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1610 MS_U32 HAL_NSK2_ReadData(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1611 {
1612 MS_U32 read_data, read_data_size;
1613 MS_U8 *read_ptr;
1614
1615 if(data_size < 4)
1616 {
1617 return FALSE;
1618 }
1619
1620 read_data_size = data_size;
1621 read_ptr = data;
1622
1623 while(read_data_size >= 4)
1624 {
1625 StatusCheck(HAL_NSK2_CheckBusy());
1626
1627 read_data = HAL_NSK2_ReadReg(addr_offset);
1628 HAL_NSK2_ReadDataTrans(read_data,read_ptr);
1629
1630 addr_offset += 4;
1631 read_ptr += 4;
1632 read_data_size -= 4;
1633 }
1634
1635 return TRUE;
1636 }
1637
HAL_NSK2_WriteData(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1638 MS_U32 HAL_NSK2_WriteData(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1639 {
1640 MS_U32 write_data, write_data_size;
1641 MS_U8 *write_ptr;
1642
1643 if(data_size < 4)
1644 {
1645 return FALSE;
1646 }
1647
1648 write_data_size = data_size;
1649 write_ptr = data;
1650
1651 while(write_data_size >= 4)
1652 {
1653 StatusCheck(HAL_NSK2_CheckBusy());
1654
1655 write_data = HAL_NSK2_WriteDataTrans(write_ptr);
1656 HAL_NSK2_WriteReg(addr_offset,write_data);
1657
1658 addr_offset += 4;
1659 write_ptr += 4;
1660 write_data_size -= 4;
1661 }
1662
1663
1664 return TRUE;
1665 }
1666
HAL_NSK2_ReadData8(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1667 MS_U32 HAL_NSK2_ReadData8(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1668 {
1669 MS_U32 read_data, read_data_size;
1670 MS_U8 *read_ptr;
1671
1672 if(data_size < 4)
1673 {
1674 return FALSE;
1675 }
1676
1677 read_data_size = data_size;
1678 read_ptr = data;
1679
1680 while(read_data_size >= 4)
1681 {
1682 StatusCheck(HAL_NSK2_CheckBusy());
1683
1684 read_data = HAL_NSK2_ReadReg(addr_offset);
1685 HAL_NSK2_ReadDataTrans(read_data,read_ptr);
1686
1687 //HALNSK2_DBG(0,"addr = %x, read_data = %x\n",addr_offset,read_data);
1688 addr_offset += 4;
1689 read_ptr += 4;
1690 read_data_size -= 4;
1691 }
1692
1693 return TRUE;
1694 }
1695
HAL_NSK2_WriteData8(MS_U32 addr_offset,MS_U32 data_size,MS_U8 * data)1696 MS_U32 HAL_NSK2_WriteData8(MS_U32 addr_offset, MS_U32 data_size, MS_U8 *data)
1697 {
1698 MS_U32 write_data, write_data_size;
1699 MS_U8 *write_ptr;
1700
1701 if(data_size < 4)
1702 {
1703 return FALSE;
1704 }
1705
1706 write_data_size = data_size;
1707 write_ptr = data;
1708
1709 while(write_data_size >= 4)
1710 {
1711 StatusCheck(HAL_NSK2_CheckBusy());
1712
1713 write_data = HAL_NSK2_WriteDataTrans(write_ptr);
1714 HAL_NSK2_WriteReg(addr_offset,write_data);
1715 //HALNSK2_DBG(0,"addr = %x, write_data = %x\n",addr_offset, write_data);
1716 addr_offset += 4;
1717 write_ptr += 4;
1718 write_data_size -= 4;
1719 }
1720
1721 return TRUE;
1722 }
1723
1724
HAL_NSK2_ReadData32(MS_U32 addr_offset,MS_U32 data_size,MS_U32 * data)1725 MS_U32 HAL_NSK2_ReadData32(MS_U32 addr_offset, MS_U32 data_size, MS_U32 *data)
1726 {
1727 MS_U32 read_data, read_data_size;
1728 MS_U32 *read_ptr;
1729 //MS_U32 test_read_data;
1730
1731 if(data_size < 1)
1732 {
1733 return FALSE;
1734 }
1735
1736 read_data_size = data_size;
1737 read_ptr = data;
1738
1739 while(read_data_size >= 1)
1740 {
1741 StatusCheck(HAL_NSK2_CheckBusy());
1742
1743 read_data = HAL_NSK2_ReadReg(addr_offset);
1744 *read_ptr = read_data;
1745
1746 //HALNSK2_DBG(0,"addr = %x, read_data = %x\n",addr_offset,read_data);
1747 addr_offset += 4;
1748 read_ptr ++;
1749 read_data_size --;
1750 }
1751
1752 return TRUE;
1753 }
1754
HAL_NSK2_WriteData32(MS_U32 addr_offset,MS_U32 data_size,MS_U32 * data)1755 MS_U32 HAL_NSK2_WriteData32(MS_U32 addr_offset, MS_U32 data_size, MS_U32 *data)
1756 {
1757 MS_U32 write_data, write_data_size;
1758 MS_U32 *write_ptr;
1759
1760 if(data_size < 1)
1761 {
1762 return FALSE;
1763 }
1764
1765 write_data_size = data_size;
1766 write_ptr = data;
1767
1768 while(write_data_size >= 1)
1769 {
1770 StatusCheck(HAL_NSK2_CheckBusy());
1771
1772 write_data = *write_ptr;
1773 HAL_NSK2_WriteReg(addr_offset,write_data);
1774 //HALNSK2_DBG(0,"addr = %x, write_data = %x\n",addr_offset, write_data);
1775 addr_offset += 4;
1776 write_ptr ++;
1777 write_data_size --;
1778 }
1779
1780
1781 return TRUE;
1782 }
1783
HAL_NSK2_EnableInt(void)1784 MS_U32 HAL_NSK2_EnableInt(void)
1785 {
1786 MS_U32 u32IntReg = 0;
1787 /*
1788 #define REG_NSK2_ACPU_INT 0xFC08
1789 #define NSK2_INT_CMD_EXIT __BIT0
1790 #define NSK2_INT_ASYNC_EVENT __BIT1
1791 #define NSK2_INT_ILLEGAL_CMD __BIT2
1792 #define NSK2_INT_ILLEGAL_ACCESS __BIT3
1793 #define NSK2_INT_RESET __BIT4
1794 #define NSK2_INT_HANG __BIT5
1795 #define NSK2_INT_KTE_VALID __BIT6
1796 #define NSK2_INT_MASK_CLEAR __BIT31
1797 */
1798
1799 u32IntReg = (NSK2_INT_CMD_EXIT | NSK2_INT_ASYNC_EVENT | NSK2_INT_ILLEGAL_CMD | \
1800 NSK2_INT_RESET | NSK2_INT_HANG | NSK2_INT_KTE_VALID | NSK2_INT_MASK_CLEAR);
1801
1802 HAL_NSK2_WriteReg(REG_NSK2_ACPU_INT,u32IntReg);
1803 return TRUE;
1804 }
1805
HAL_NSK2_DisableInt(void)1806 MS_U32 HAL_NSK2_DisableInt(void)
1807 {
1808 MS_U32 u32IntReg = 0;
1809
1810 HAL_NSK2_WriteReg(REG_NSK2_ACPU_INT,u32IntReg);
1811 return TRUE;
1812 }
1813
1814
HAL_NSK2_GetIntStatus(void)1815 MS_U32 HAL_NSK2_GetIntStatus(void)
1816 {
1817 MS_U32 u32IntValue;
1818 u32IntValue = HAL_NSK2_ReadReg(REG_NSK2_ACPU_INT);
1819
1820 //HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Int status = %x\n",u32IntValue);
1821 return u32IntValue;
1822 }
1823
HAL_NSK2_ClearInt(MS_U32 u32IntValue)1824 MS_U32 HAL_NSK2_ClearInt(MS_U32 u32IntValue)
1825 {
1826 //HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Clear Int = %x\n",u32IntValue);
1827 HAL_NSK2_WriteReg(REG_NSK2_ACPU_INT,u32IntValue);
1828 return TRUE;
1829 }
1830
1831
HAL_NSK2_WriteControl(MS_U32 control)1832 MS_U32 HAL_NSK2_WriteControl(MS_U32 control)
1833 {
1834 HAL_NSK2_WriteReg(REG_NSK2_ACPU_CTRL_BLOCK, control);
1835 return TRUE;
1836 }
1837
1838
HAL_NSK2_WriteCommand(MS_U32 command)1839 MS_U32 HAL_NSK2_WriteCommand(MS_U32 command)
1840 {
1841 HAL_NSK2_WriteReg(REG_NSK2_ACPU_CMD, command);
1842 return TRUE;
1843 }
1844
1845
HAL_NSK2_GetMaxXConn(void)1846 MS_U32 HAL_NSK2_GetMaxXConn(void)
1847 {
1848 return MaximumXConnection;
1849 }
1850
1851
HAL_NSK2_CMChannelNum(void)1852 MS_U32 HAL_NSK2_CMChannelNum(void)
1853 {
1854 return 1;
1855 }
1856
1857
1858 typedef struct
1859 {
1860 MS_U8 u8Tag;
1861 MS_U8 u8Length;
1862 MS_U32 Offset;
1863 MS_U32 MSB;
1864 MS_U32 LSB;
1865 } ASST_t;
1866
1867
1868 static ASST_t K6Asst[] =
1869 {
1870 //the first tag is the same called pub otp, we should implement one function to obtain this,
1871 //becasue this the same as HW test, we can check at HW Test also.
1872 {0x20, 9, 0x3DA8, 63, 0}, //U_OTP_v_pubOtpUniqueID1
1873 {0x21, 16, 0x7C00, 127, 0}, //Bulk data 1
1874 {0x22, 16, 0x7C10, 127, 0}, //Bulk data 2
1875 {0x23, 16, 0x7C20, 127, 0}, //Bulk data 3
1876 {0x24, 16, 0x7C30, 127, 0}, //Bulk data 4
1877
1878 {0x40, 1, 0x3B20, 27, 24}, //U_OTP_allow_illegalNDSFlagChk
1879 {0x41, 1, 0x3B24, 3, 0}, //U_OTP_ena_ACPUUseNSK2
1880 {0x42, 1, 0x3B24, 7, 4}, //U_OTP_ena_DBUSUseNSK2
1881 {0x43, 1, 0x3B24, 11, 8}, //U_OTP_ena_ForceOneMilSec
1882 {0x44, 1, 0x3B24, 15, 12}, //U_OTP_allow_SCCheck
1883 {0x45, 1, 0x3B24, 19, 16}, //U_OTP_ena_TestRCFreq
1884 {0x46, 1, 0x3B24, 23, 20}, //U_OTP_ena_SWRN
1885 {0x47, 1, 0x3B24, 27, 24}, //U_OTP_ena_NSKSeedPRNG
1886 {0x48, 1, 0x3B24, 31, 28}, //U_OTP_OTPWritePWDProtect
1887 {0x49, 1, 0x3B28, 11, 8}, //U_OTP_ena_EMMFilter
1888 {0x4A, 1, 0x3B28, 15, 12}, //U_OTP_ena_TestGenIN
1889 {0x4B, 1, 0x3B28, 7, 6}, //U_OTP_allow_NSK2_PWD_Mode
1890 {0x4C, 1, 0x3B2C, 3, 2}, //U_OTP_allow_NDSSC_ReadFail_BadPkt
1891 {0x4D, 1, 0x3B2C, 5, 4}, //U_OTP_allow_RANDOM_keybus
1892 {0x4E, 1, 0x3B2C, 7, 6}, //U_OTP_allow_RANDOM_byteacc
1893 {0x4F, 1, 0x3B2C, 9, 8}, //U_OTP_allow_NDS_Rd55AA
1894 {0x50, 1, 0x3B2C, 11, 10}, //U_OTP_allow_NDS_Parity_chk
1895 {0x51, 1, 0x3B2C, 15, 14}, //U_OTP_forbid_OTPBuiltInTest
1896 {0x52, 1, 0x3C58, 3, 0}, //U_OTP_ena_ESAAlgo_invalidate
1897 {0x53, 1, 0x3C58, 7, 4}, //U_OTP_ena_LocalAlgo_Invalidate
1898 {0x54, 1, 0x3C58, 11, 8}, //U_OTP_ContentProtEn
1899 {0x55, 1, 0x3C58, 13, 12}, //U_OTP_concurrency_configuration
1900 {0x56, 1, 0x3C58, 15, 14}, //U_OTP_allow_NSK_RNG_ROSC
1901 {0x57, 1, 0x3C58, 16, 16}, //U_OTP_nds_fc_disable
1902 {0x58, 1, 0x3C58, 17, 17}, //U_OTP_NDS_CPNR0_sel
1903 {0x59, 1, 0x3C58, 18, 18}, //U_OTP_NDS_CPNR_off
1904 {0x5A, 1, 0x3C60, 3, 2}, //U_OTP_OBFUSCATEVideoStream
1905 {0x5B, 1, 0x3C60, 1, 1}, //U_OTP_MOBF_TOP_use_DES
1906 {0x5C, 1, 0x3C74, 11, 8}, //U_OTP_ena_PlayBackRec0
1907 {0x5D, 1, 0x3C74, 15, 12}, //U_OTP_ena_PlayBackRec1
1908 {0x5E, 1, 0x3C74, 19, 16}, //U_OTP_ena_PlayBackRec2
1909 {0x5F, 1, 0x3C74, 23, 20}, //U_OTP_ena_PlayBackRec3
1910 {0x60, 1, 0x3C78, 3, 0}, //U_OTP_ena_PVR_secure_protect_0
1911 {0x61, 1, 0x3C78, 11, 8}, //U_OTP_ena_TSO
1912 {0x62, 1, 0x3C80, 17, 16}, //U_OTP_forbid_SW_SPSD_Key
1913 {0x63, 1, 0x3C80, 21, 20}, //U_OTP_allow_TSPCPUCodeProt
1914 {0x64, 1, 0x3CC0, 13, 12}, //U_OTP_allow_RANDOM
1915 {0x65, 1, 0x3CC8, 3, 0}, //U_OTP_SBoot
1916 {0x66, 1, 0x3CC8, 7, 4}, //U_OTP_SecretAreaEnable
1917 {0x67, 2, 0x3CCC, 8, 0}, //U_OTP_SCAN_MODE
1918 {0x68, 1, 0x3CCC, 15, 10}, //U_OTP_MBIST_MODE
1919 {0x69, 1, 0x3CCC, 21, 16}, //U_OTP_I2C_MODE
1920 {0x6A, 1, 0x3CCC, 31, 26}, //U_OTP_EJTAG_MODE
1921 {0x6B, 1, 0x3C68, 3, 0}, //U_OTP_forbid_USBSlaveMode
1922 {0x6C, 1, 0x3CD0, 9, 8}, //U_OTP_allow_DRAM_MOBF
1923 {0x6D, 1, 0x3CD4, 15, 14}, //U_OTP_forbid_BCKGND_CHK
1924 {0x6E, 1, 0x3CD4, 21, 16}, //U_OTP_SCPUBootMode
1925 {0x6F, 1, 0x3CE0, 31, 30}, //U_OTP_forbid_STR
1926 {0x70, 1, 0x3D24, 11, 8}, //U_OTP_ena_NSK2
1927 {0x71, 1, 0x3D24, 15, 14}, //U_OTP_ena_DMA
1928 {0x72, 1, 0x3D24, 19, 16}, //U_OTP_ena_SCPU
1929 {0x73, 1, 0x3D44, 3, 0}, //U_OTP_ena_ACPU2KT
1930 {0x74, 1, 0x3D44, 7, 4}, //U_OTP_ena_NSK2KT
1931 {0x75, 1, 0x3D44, 19, 16}, //U_OTP_ena_ACPUWrNSKKey2KT
1932 {0x76, 1, 0x3D44, 27, 24}, //U_OTP_ena_NSKCW2CryptoDMA
1933 {0x77, 1, 0x3D4C, 7, 4}, //U_OTP_ena_DMA_DESBasedCipher
1934 {0x78, 1, 0x3D6C, 19, 16}, //U_OTP_ena_LowerPathRec
1935 {0x79, 1, 0x3B2C, 17, 16}, //U_OTP_forbid_Kilo_ProgRepair
1936 {0x7A, 1, 0x3CC8, 19, 16}, //U_OTP_SecR2_Sboot
1937 {0x7B, 1, 0x3C88, 27, 24}, //U_OTP_NDS_CODE_INTEGRITY_RSA_KEY_SEL
1938 {0x7C, 1, 0x3CC8, 23, 20}, //U_OTP_xCPU_Sboot
1939 };
1940
1941
endian_change(MS_U8 * ptr,MS_U32 bytes)1942 void endian_change(MS_U8* ptr, MS_U32 bytes)
1943 {
1944
1945 MS_U32 u32halve;
1946 MS_U32 u32tmp;
1947 MS_U32 i;
1948
1949 u32halve = bytes/2;
1950 for(i=0; i<u32halve; i++)
1951 {
1952 u32tmp = ptr[i];
1953 ptr[i] = ptr[bytes-i-1];
1954 ptr[bytes-i-1] = u32tmp;
1955 }
1956 }
1957
HAL_NSK2_GetOTPProperties(MS_U32 * desc_size,MS_U8 * desc)1958 MS_U32 HAL_NSK2_GetOTPProperties(MS_U32 *desc_size, MS_U8 *desc)
1959 {
1960 MS_U32 NumOfTag = sizeof(K6Asst)/sizeof(ASST_t);
1961 MS_U32 ret_size = 0, i, j;
1962 MS_U8 *pDesc = (MS_U8 *)desc;
1963 MS_U32 OTPValue;
1964 MS_U8 RunLens;
1965 MS_U32 RunOffset;
1966
1967 ret_size = 0;
1968 for( i=0; i<NumOfTag; i++)
1969 {
1970 ret_size += (K6Asst[i].u8Length + 2);
1971 }
1972
1973 *desc_size = ret_size;
1974
1975 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"length of OTP Tag = %x\n",ret_size);
1976 if(desc == NULL)
1977 {
1978 return TRUE;
1979 }
1980
1981 for( i=0; i<NumOfTag; i++)
1982 {
1983 *pDesc++ = K6Asst[i].u8Tag;
1984 *pDesc++ = K6Asst[i].u8Length;
1985
1986 if(0x20 == K6Asst[i].u8Tag) //pubOTP...special case....
1987 {
1988 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"begin of Tag 0x20\n");
1989 *pDesc++ = 0;
1990 //4 Chip ID
1991 MS_U8 PubOTP[8];
1992 for(j=0;j<8;j+=4)
1993 {
1994 MS_U32 u32Tmp;
1995 u32Tmp = MDrv_CA_OTP_Read(K6Asst[i].Offset + j);
1996 memcpy(&PubOTP[j], &u32Tmp, 4);
1997 }
1998
1999
2000 endian_change(PubOTP, 8);
2001
2002 memcpy(pDesc,PubOTP,8);
2003 pDesc += 8;
2004
2005 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"end of Tag 0x20\n");
2006 }
2007 else if (0x25 == K6Asst[i].u8Tag) //NV Counter...special case....
2008 {
2009 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"begin of Tag 0x25\n");
2010 MS_U32 MaxNVCounter = 1024;
2011 *pDesc++ = (MS_U8)((MaxNVCounter>>24)&0xff);
2012 *pDesc++ = (MS_U8)((MaxNVCounter>>16)&0xff);
2013 *pDesc++ = (MS_U8)((MaxNVCounter>>8)&0xff);
2014 *pDesc++ = (MS_U8)(MaxNVCounter&0xff);
2015
2016 *pDesc++ = 0;
2017 *pDesc++ = 0;
2018 *pDesc++ = 0;
2019 *pDesc++ = 0;
2020
2021 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"end of Tag 0x25\n");
2022 }
2023 else
2024 {
2025 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"begin of Tag 0x%x\n",K6Asst[i].u8Tag);
2026 RunLens = K6Asst[i].u8Length;
2027 RunOffset = K6Asst[i].Offset;
2028 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"Offset = %x, length = %x\n",RunOffset, RunLens);
2029 if(K6Asst[i].u8Length <= 4)
2030 {
2031 HAL_NSK2_OTP_Get(K6Asst[i].Offset, K6Asst[i].MSB, K6Asst[i].LSB, &OTPValue);
2032 if(1 == RunLens)
2033 *pDesc++ = (MS_U8)(OTPValue&0xff);
2034 else if(2 == RunLens)
2035 {
2036 *pDesc++ = (MS_U8)((OTPValue>>8)&0xff);
2037 *pDesc++ = (MS_U8)(OTPValue&0xff);
2038 }
2039 else if(4 == RunLens)
2040 {
2041 *pDesc++ = (MS_U8)((OTPValue>>24)&0xff);
2042 *pDesc++ = (MS_U8)((OTPValue>>16)&0xff);
2043 *pDesc++ = (MS_U8)((OTPValue>>8)&0xff);
2044 *pDesc++ = (MS_U8)(OTPValue&0xff);
2045 }
2046 }
2047 else //length > 4, tmp solution
2048 {
2049 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"length = %x\n",RunLens);
2050 MS_U8 BulkData[16];
2051 for( j=0; j<RunLens; j+=4 )
2052 {
2053 HAL_NSK2_OTP_Get(RunOffset + j, 31, 0, &OTPValue);
2054 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"run offset = %x, Value = %x\n", (RunOffset + j),OTPValue);
2055 memcpy(&BulkData[j],&OTPValue,4);
2056 }
2057 endian_change(BulkData, 16);
2058 memcpy(pDesc,BulkData,16);
2059 pDesc += 16;
2060 }
2061
2062 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"end of Tag 0x%x\n",K6Asst[i].u8Tag);
2063 }
2064 }
2065
2066 #if 0
2067 MS_U32 size = *desc_size;
2068
2069 for(i=0;i<size;i++)
2070 {
2071 printf(" (%d, %x) \n", i , desc[i]);
2072 }
2073 #endif
2074 return TRUE;
2075 }
2076
2077
2078
2079 typedef struct
2080 {
2081 MS_U32 Offset;
2082 MS_U32 MSB;
2083 MS_U32 LSB;
2084 MS_U32 Bits;
2085 } ChipOTPCfg_t;
2086
2087
2088 static ChipOTPCfg_t K6ChipCfg[] =
2089 {
2090 {0x3B20, 7, 0, 8}, //[127:120] U_OTP_forbid_NSK_wr_sck[7:0] 11111111
2091 {0x3B20, 15, 8, 8}, //[119:112] U_OTP_UseCheckSum[7:0] 11111111
2092 {0x3B20, 17, 16, 2}, //[111:110] U_OTP_allow_NDSKey_BlankChk[1:0] 11
2093 {0x3B20, 19, 18, 2}, //[109:108] U_OTP_allow_ProgFail_RuinNDSKey[1:0] 11
2094 {0x3B20, 21, 20, 2}, //[107:106] U_OTP_allow_NDSReadKeyWait200ms[1:0] 11
2095 {0x3B20, 23, 22, 2}, //[105:104] U_OTP_allow_ReadErrorRstOtp[1:0] 11
2096 {0x3B20, 27, 24, 4}, //[103:100] U_OTP_allow_illegalNDSFlagChk[3:0] 1111
2097 {0x3B20, 31, 28, 4}, //[99:96] U_OTP_allow_Rst_NDS_SCFlag_ParityFail[3:0] 1111
2098 {0x3B24, 3, 0, 4}, //[95:92] U_OTP_ena_ACPUUseNSK2[3:0] 0001
2099 {0x3B28, 7, 6, 2}, //[91:90] U_OTP_allow_NSK2_PWD_Mode[1:0] 11
2100 {0x3B2C, 15, 14, 2}, //[[89:88] U_OTP_forbid_OTPBuiltInTest[1:0] 11
2101 {0x3B2C, 17, 16, 2}, //[87:86] U_OTP_forbid_Kilo_ProgRepair[1:0] 11
2102 {0x3C50, 1, 0, 2}, //[85:84] U_OTP_NDS_ESCK_Key1_obfuscation[1:0] 11
2103 {0x3C50, 17, 16, 2}, //[83:82] U_OTP_NDS_Key1_integrity_chk[1:0] 11
2104 {0x3C50, 3, 2, 2}, //[81:80] U_OTP_NDS_ESCK_Key2_obfuscation[1:0] 11
2105 {0x3C50, 19, 18, 2}, //[79:78] U_OTP_NDS_Key2_integrity_chk[1:0] 11
2106 {0x3C50, 5, 4, 2}, //[77:76] U_OTP_NDS_ESCK_Key3_obfuscation[1:0] 11
2107 {0x3C50, 21, 20, 2}, //[75:74] U_OTP_NDS_Key3_integrity_chk[1:0] 11
2108 {0x3C50, 7, 6, 2}, //[73:72] U_OTP_NDS_ESCK_Key4_obfuscation[1:0] 11
2109 {0x3C50, 23, 22, 2}, //[71:70] U_OTP_NDS_Key4_integrity_chk[1:0] 11
2110 {0x3C50, 9, 8, 2}, //[69:68] U_OTP_NDS_ESCK_Key5_obfuscation[1:0] 11
2111 {0x3C50, 25, 24, 2}, //[67:66] U_OTP_NDS_Key5_integrity_chk[1:0] 11
2112 {0x3C50, 11, 10, 2}, //[65:64] U_OTP_NDS_ESCK_Key6_obfuscation[1:0] 11
2113 {0x3C50, 27, 26, 2}, //[63:62] U_OTP_NDS_Key6_integrity_chk[1:0] 11
2114 {0x3C50, 13, 12, 2}, //[61:60] U_OTP_NDS_ESCK_Key7_obfuscation[1:0] 11
2115 {0x3C50, 29, 28, 2}, //[59:58] U_OTP_NDS_Key7_integrity_chk[1:0] 11
2116 {0x3C50, 15, 14, 2}, //[57:56] U_OTP_NDS_ESCK_Key8_obfuscation[1:0] 11
2117 {0x3C50, 31, 30, 2}, //[55:54] U_OTP_NDS_Key8_integrity_chk[1:0] 11
2118 {0x3C58, 11, 8, 4}, //[53:50] U_OTP_ContentProtEn[3:0] 1111
2119 {0x3C58, 13, 12, 2}, //[49:48] U_OTP_concurrency_configuration[1:0] 10
2120 {0x3C58, 15, 14, 2}, //[47:46] U_OTP_allow_NSK_RNG_ROSC[1:0] 11
2121 {0x3C60, 0, 0, 1}, //[45] U_OTP_forbid_CLK_SEED_TEST 1
2122 {0x3C60, 3, 2, 2}, //[44:43] U_OTP_OBFUSCATEVideoStream[1:0] 00
2123 {0x3C78, 3, 0, 4}, //[42:39] U_OTP_ena_PVR_secure_protect_0[3:0] 0001
2124 {0x3C78, 11, 8, 4}, //[38:35] U_OTP_dis_TSO[3:0] 0001
2125 {0x3CC0, 13, 12, 2}, //[34:33] U_OTP_allow_RANDOM[1:0] 11
2126 {0x3CC8, 3, 0, 4}, //[32:29] U_OTP_SBoot[3:0] 0000
2127 {0x3C68, 3, 0, 4}, //[28:25] U_OTP_forbid_USBSlaveMode[3:0] 1111
2128 {0x3CD0, 9, 8, 2}, //[24:23] U_OTP_allow_DRAM_MOBF[1:0] 00
2129 {0x3CD0, 18, 16, 3}, //[22:20] U_OTP_forbid_clk_otp_sel[2:0] 111
2130 {0x3CE0, 31, 30, 2}, //[19:18] U_OTP_forbid_STR[1:0] 00
2131 {0x3D24, 11, 8, 4}, //[17:14] U_OTP_ena_NSK2[3:0] 0001
2132 {0x3D24, 15, 14, 2}, //[13:12] U_OTP_ena_DMA[1:0] 01
2133 {0x3D24, 19, 16, 4}, //[11:8] U_OTP_ena_SCPU[3:0] 0001
2134 {0x3D44, 3, 0, 4}, //[7:4] U_OTP_ena_ACPU2KT[3:0] 0001
2135 {0x3D44, 7, 4, 4}, //[3:0] U_OTP_ena_NSK2KT[3:0] 0001
2136
2137 {0x3D44, 19, 16, 4}, //[127:124] U_OTP_ena_ACPUWrNSKKey2KT[3:0] 0111
2138 {0x3D50, 3, 0, 4}, //[123:120] U_OTP_ena_LSACPCM[3:0] 0001
2139 {0x3D50, 7, 4, 4}, //[119:116] U_OTP_ena_AESBasedCipher[3:0] 0001
2140 {0x3D50, 11, 8, 4}, //[115:112] U_OTP_ena_DESBasedCipher[3:0] 0001
2141 {0x3D50, 15, 12, 4}, //[111:108] U_OTP_ena_3DESBasedCipher[3:0] 0001
2142 {0x3D50, 19, 16, 4}, //[107:104] U_OTP_ena_Multi2BasedCipher[3:0] 0001
2143 {0x3D50, 23, 20, 4}, //[103:100] U_OTP_ena_DVBCSA2ConfCipher[3:0] 0001
2144 {0x3D50, 27, 24, 4}, //[99:96] U_OTP_ena_DVBCSA2Cipher[3:0] 0001
2145 {0x3D50, 31, 28, 4}, //[95:92] U_OTP_ena_DVBCSA3BasedCipher[3:0] 0001
2146 {0x3D54, 31, 0, 32}, //[91:28] U_OTP_Ch_SwitchComb[63:0] 1111111111111111111111111111111111111111111111111111111111111111
2147 {0x3D58, 31, 0, 32}, //[91:28] U_OTP_Ch_SwitchComb[63:0] 1111111111111111111111111111111111111111111111111111111111111111
2148 {0x3D5C, 3, 0, 4}, //[27:24] U_OTP_ena_LSAD_MDI[3:0] 0001
2149 {0x3D5C, 7, 4, 4}, //[23:20] U_OTP_ena_LSAD_MDD[3:0] 0001
2150 {0x3D5C, 11, 8, 4}, //[19:16] U_OTP_ena_LSAD_CIPLUS_AES[3:0] 0001
2151 {0x3D5C, 15, 12, 4}, //[15:12] U_OTP_ena_LSAD_AES_ECB_CLEAR[3:0] 0001
2152 {0x3D5C, 19, 16, 4}, //[11:8] U_OTP_ena_LSAD_SCTE41_SCTE52_DES[3:0] 0001
2153 {0x3D60, 3, 0, 4}, //[7:4] U_OTP_ena_ESA_CIPLUS_AES[3:0] 0001
2154 {0x3D60, 7, 4, 4}, //[3:0] U_OTP_ena_ESA_CIPLUS_DES[3:0] 0001
2155
2156 {0x3D60, 11, 8, 4}, //[127:124] U_OTP_ena_ESA_SCTE52_DES[3:0] 0001
2157 {0x3D60, 15, 12, 4}, //[123:120] U_OTP_ena_ESA_tDES_CBC_CLEAR[3:0] 0001
2158 {0x3D64, 3, 0, 4}, //[119:116] U_OTP_ena_LSAS_MDI[3:0] 0001
2159 {0x3D64, 7, 4, 4}, //[115:112] U_OTP_ena_LSAS_MDD[3:0] 0001
2160 {0x3D64, 11, 8, 4}, //[111:108] U_OTP_ena_LSAS_CIPLUS_AES[3:0] 0001
2161 {0x3D64, 15, 12, 4}, //[107:104] U_OTP_ena_LSAS_AES_ECB_CLEAR[3:0] 0001
2162 {0x3D64, 19, 16, 4}, //[103:100] U_OTP_ena_LSAS_SCTE41_SCTE52_DES[3:0] 0001
2163 {0x3D68, 7, 4, 4}, //[99:96] U_OTP_ena_ReviewFailPkt[3:0] 0001
2164 {0x3D68, 11, 8, 4}, //[95:92] U_OTP_dis_NonSecRangeEncrypt[3:0] 0001
2165 {0x3D6C, 3, 0, 4}, //[91:88] U_OTP_ena_CA_PVR_secure_protect_0[3:0] 0001
2166 {0x3D6C, 19, 16, 4}, //[87:84] U_OTP_ena_LowerPathRec[3:0] 0111
2167 {0x3FA0, 9, 8, 2}, //[83:82] U_OTP_I2C_PWD_obfuscation[1:0] 11
2168 {0x3FA0, 11, 10, 2}, //[81:80] U_OTP_EJTAG_PWD_obfuscation[1:0] 11
2169 {0x3FA0, 13, 12, 2}, //[79:78] U_OTP_SCAN_PWD_obfuscation[1:0] 11
2170 {0x3FA0, 15, 14, 2}, //[77:76] U_OTP_MBIST_PWD_obfuscation[1:0] 11
2171 //[63:0] 0 0000000000000000000000000000000000000000000000000000000000000000
2172
2173 };
2174
2175 #define FullChipConfigSize 0x27
2176
HAL_NSK2_GetFullChipSize(void)2177 MS_U32 HAL_NSK2_GetFullChipSize(void)
2178 {
2179 return FullChipConfigSize;
2180 }
2181
HAL_NSK2_GetFullChipConfig(MS_U32 * desc_size,MS_U8 * desc)2182 MS_U32 HAL_NSK2_GetFullChipConfig(MS_U32 *desc_size, MS_U8 *desc)
2183 {
2184 *desc_size = FullChipConfigSize;
2185 if(desc == NULL)
2186 {
2187 return TRUE;
2188 }
2189
2190 MS_U32 i, j, remain_bits, shift_bits;
2191 MS_U32 NumOfConfigs = sizeof(K6ChipCfg)/sizeof(ChipOTPCfg_t);
2192 MS_U32 TotalOTPValue[100];
2193
2194 memset(desc, 0x0, FullChipConfigSize);
2195 memset(TotalOTPValue, 0x0, 100*sizeof(MS_U32));
2196 //desc[0x40-1] = 0x28;
2197 //desc[0x28] = 0x80;
2198
2199 for(i=0; i<NumOfConfigs; i++)
2200 {
2201 HAL_NSK2_OTP_Get(K6ChipCfg[i].Offset, K6ChipCfg[i].MSB, K6ChipCfg[i].LSB, &TotalOTPValue[i]);
2202 HALNSK2_DBG(NSK2_DBGLV_INFO,"%d, %x\n",i, TotalOTPValue[i]);
2203 }
2204
2205 j = 0;
2206 remain_bits = 8;
2207 for(i=0; i<NumOfConfigs; i++)
2208 {
2209 if(K6ChipCfg[i].Bits>remain_bits)
2210 {
2211 if(K6ChipCfg[i].Bits == 32)
2212 {
2213 if(remain_bits != 8)
2214 {
2215 shift_bits = 8-remain_bits;
2216 desc[j] |= 0xf;
2217 j++;
2218 desc[j] = 0xff;
2219 j++;
2220 desc[j] = 0xff;
2221 j++;
2222 desc[j] = 0xff;
2223 j++;
2224 desc[j] = 0xf0;
2225 remain_bits = 4;
2226 }
2227 else
2228 {
2229 memcpy(&desc[j], &TotalOTPValue[i], 4);
2230 j += 4;
2231 remain_bits = 0;
2232 }
2233 }
2234 else
2235 {
2236
2237 shift_bits = K6ChipCfg[i].Bits-remain_bits;
2238 //printf("not equal case (%d), shift_bits = %x\n",i,shift_bits);
2239 desc[j] |= (TotalOTPValue[i] >> shift_bits);
2240
2241 j++;
2242
2243 remain_bits = (8-shift_bits);
2244 desc[j] |= (( TotalOTPValue[i] << remain_bits ) & 0xff); }
2245
2246 }
2247 else
2248 {
2249 remain_bits -= K6ChipCfg[i].Bits;
2250
2251 desc[j] |= (TotalOTPValue[i] << (remain_bits));
2252
2253 }
2254
2255 if(remain_bits == 0)
2256 {
2257 remain_bits = 8;
2258 j++;
2259 }
2260 }
2261
2262 return TRUE;
2263 }
2264
2265
2266 static NVCounter_Desc_t nvcounter_desc = {
2267 .descriptor_tag = NSK2HDI_OTP_NVCOUNTER_DESC_TAG,
2268 .descriptor_length = 8, //sizeof(NVCounter_Desc_t) - 2,
2269 .max_nvcounter[0] = 0x00,
2270 .max_nvcounter[1] = 0x00,
2271 .max_nvcounter[2] = 0x04,
2272 .max_nvcounter[3] = 0x00,
2273 .left_nvcounter[0] = 0x00,
2274 .left_nvcounter[1] = 0x00,
2275 .left_nvcounter[2] = 0x04,
2276 .left_nvcounter[3] = 0x00,
2277 };
2278
2279 #define TotalNVNumber 1024
2280
2281
2282
HAL_NSK2_GetNVCounterConfig(MS_U32 * desc_size,MS_U8 * desc)2283 MS_U32 HAL_NSK2_GetNVCounterConfig(MS_U32 *desc_size, MS_U8 *desc)
2284 {
2285 MS_U32 u32NvCounter = 0;
2286 MS_U32 u32LeftNvCounter = 0;
2287
2288 if(desc == NULL)
2289 {
2290 *desc_size = sizeof(nvcounter_desc);
2291 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_NVCounterUpdates return desc_size = %x\n",*desc_size);
2292 return TRUE;
2293 }
2294
2295 *desc_size = sizeof(nvcounter_desc);
2296 // Read NV Counter from register directly
2297 #if 1
2298 u32NvCounter = NI_REG (REG_NI_NSK21_GET_NVCOUNTER);
2299 #else
2300 HAL_NSK2_WriteControl(0x1);
2301 MsOS_DelayTaskUs(10);
2302 HAL_NSK2_WriteCommand(0x73);
2303 MsOS_DelayTaskUs(10);
2304 StatusCheck(HAL_NSK2_CheckBusy());
2305
2306 MS_U32 NVValue, LeftNVCounter;
2307 HAL_NSK2_ReadData32(0x1C, 0x1, &NVValue);
2308 #endif
2309
2310 u32LeftNvCounter = TotalNVNumber - u32NvCounter;
2311
2312 HALNSK2_DBG(NSK2_DBGLV_INFO,"NVValue = %d, LeftNVCounter = %d \n", u32NvCounter, u32LeftNvCounter);
2313
2314 nvcounter_desc.left_nvcounter[0] = (MS_U8)((u32LeftNvCounter>>24)&0xff);
2315 nvcounter_desc.left_nvcounter[1] = (MS_U8)((u32LeftNvCounter>>16)&0xff);
2316 nvcounter_desc.left_nvcounter[2] = (MS_U8)((u32LeftNvCounter>>8)&0xff);
2317 nvcounter_desc.left_nvcounter[3] = (MS_U8)(u32LeftNvCounter&0xff);
2318
2319 memcpy(desc,&nvcounter_desc,sizeof(nvcounter_desc));
2320
2321 return TRUE;
2322 }
2323
HAL_NSK2_SetDbgLevel(MS_U32 u32Level)2324 void HAL_NSK2_SetDbgLevel(MS_U32 u32Level)
2325 {
2326 _g32NSK2HalDbgLv = u32Level;
2327 HALNSK2_DBG(NSK2_DBGLV_INFO, "%s level: %x\n", __FUNCTION__, u32Level);
2328 return;
2329 }
2330
HAL_NSK2_SetPollingCnt(MS_U32 u32Cnt)2331 void HAL_NSK2_SetPollingCnt(MS_U32 u32Cnt)
2332 {
2333 dead_polling_cnt = u32Cnt;
2334 }
2335
2336 #if 0
2337 void HAL_NSK2_BurstLen(MS_U32 u32PVREng, MS_U32 u32BurstMode)
2338 {
2339 HAL_PVR_BurstLen(u32PVREng, u32BurstMode);
2340 }
2341 #endif
2342
HAL_NSK2_ClockTest(MS_U32 testnum)2343 void HAL_NSK2_ClockTest(MS_U32 testnum)
2344 {
2345
2346 MS_U32 u32Data;
2347 switch(testnum)
2348 {
2349 case 0:
2350 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
2351 MsOS_DelayTaskUs(1);
2352
2353 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2354 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2355
2356
2357 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2358 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2359
2360 //bit 0 set to 1...
2361 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_NSK2_RESET_DISABLE | NI_NSK2_CLK_ENABLE;
2362
2363 MsOS_DelayTaskUs(1);
2364 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2365 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2366 break;
2367
2368
2369 case 1:
2370 RSA_REG(REG_RSA_CLK_ENABLE) |= RSA_PM_NSKCLK_ENABLE;
2371 MsOS_DelayTaskUs(1);
2372
2373 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2374 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2375
2376
2377 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2378 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2379
2380 //disable nsk2 clock
2381 NI_REG(REG_NI_NSK2_CTRL) = u32Data & ~(NI_NSK2_CLK_ENABLE) ;
2382 MsOS_DelayTask(1);
2383 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2384 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2385
2386 break;
2387
2388 case 2:
2389 RSA_REG(REG_RSA_CLK_ENABLE) &= (~RSA_PM_NSKCLK_ENABLE);
2390 MsOS_DelayTaskUs(1);
2391
2392 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2393 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2394
2395
2396 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2397 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2398
2399 //bit 0 set to 1...
2400 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_NSK2_RESET_DISABLE | NI_NSK2_CLK_ENABLE;
2401
2402 MsOS_DelayTaskUs(1);
2403 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2404 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2405 break;
2406
2407 case 3:
2408 RSA_REG(REG_RSA_CLK_ENABLE) &= (~RSA_PM_NSKCLK_ENABLE);
2409 MsOS_DelayTaskUs(1);
2410
2411 u32Data = RSA_REG(REG_RSA_CLK_ENABLE);
2412 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "RSA REG_RSA_CLK_ENABLE = %x\n",u32Data);
2413
2414 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2415 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2416
2417 //disable nsk2 clock
2418 NI_REG(REG_NI_NSK2_CTRL) = u32Data & ~(NI_NSK2_CLK_ENABLE) ;
2419 MsOS_DelayTask(1);
2420 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2421 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "NI REG_NI_NSK2_CTRL = %x\n",u32Data);
2422 break;
2423 }
2424 }
2425
HAL_NSK2_GetRNGThroughPut(void * pRngData,MS_U32 u32DataSize,MS_BOOL bDump)2426 void HAL_NSK2_GetRNGThroughPut(void *pRngData, MS_U32 u32DataSize, MS_BOOL bDump)
2427 {
2428 MS_U32 u32StartTime;
2429 MS_U32 *pRNG_Data = (MS_U32 *)pRngData;
2430 MS_U32 valid = 0;
2431 MS_U32 i = 0;
2432
2433 NI_REG(REG_NI_NSK2_CTRL) = NI_REG(REG_NI_NSK2_CTRL) & (~NI_NSK2_RESET_DISABLE);
2434 NI_REG(REG_NI_NSK2_FREERUN) = NI_REG(REG_NI_NSK2_FREERUN) & (~ (NI_NSK2_RANDOM_FREERUN | NI_NSK2_RANDOM_ONEBYONE) );
2435
2436 u32StartTime = MsOS_GetSystemTime();
2437
2438 for(i=0; i< u32DataSize; i++)
2439 {
2440 do
2441 {
2442 valid = NI_REG(REG_NI_NSK2_TRNG_VALID) & NI_NSK2_TRNG_VALID_MASK; //trng_sw_read_valid_nsk ;
2443 }while(valid != 1);
2444
2445 pRNG_Data[i] = NI_REG(REG_NI_NSK2_TRNG_DATA);//trng_sw_read_data_nsk;
2446 NI_REG(REG_NI_NSK2_FREERUN) = NI_REG(REG_NI_NSK2_FREERUN) | NI_NSK2_RANDOM_ONEBYONE; //lfsr_get_go_nsk = 1 ;
2447 }
2448 MS_U32 u32EndTime = MsOS_GetSystemTime();
2449
2450 HALNSK2_DBG(NSK2_DBGLV_ERR, "1M bit data size, total Time = %1d ms\n", (MS_U32)(u32EndTime - u32StartTime));
2451
2452 if(bDump)
2453 {
2454 for(i = 0 ; i < u32DataSize ; i ++)
2455 {
2456 HALNSK2_DBG(NSK2_DBGLV_ERR, "%08x\n", (unsigned int)(pRNG_Data[i]));
2457 }
2458 }
2459 }
2460
HAL_NSK2_RunFree(MS_BOOL bRunFree)2461 void HAL_NSK2_RunFree(MS_BOOL bRunFree)
2462 {
2463 HALNSK2_DBG(NSK2_DBGLV_DEBUG, "bRunFree = %d\n", bRunFree);
2464
2465 if(bRunFree)
2466 {
2467 _gCheckBusyFlag = FALSE;
2468 }
2469 else
2470 {
2471 _gCheckBusyFlag = TRUE;
2472 }
2473 }
2474
2475
HAL_NSK2_PushSlowClock(MS_BOOL HaltClk,MS_U32 NumOfMs)2476 MS_U32 HAL_NSK2_PushSlowClock ( MS_BOOL HaltClk, MS_U32 NumOfMs)
2477 {
2478 //HALNSK2_DBG(NSK2_DBGLV_DEBUG, "HaltClk = %d NumofTenSecond = %d\n", HaltClk, NumofTenSecond);
2479 _gCheckBusyFlag = TRUE;
2480 StatusCheck(HAL_NSK2_CheckBusy());
2481 MS_U32 u32Data = NI_REG(REG_NI_NSK2_CTRL);
2482
2483 if(HaltClk == TRUE)//close clk
2484 {
2485 NI_REG(REG_NI_NSK2_CTRL) = u32Data & (~NI_NSK2_CLK_ENABLE) ;
2486 _gCheckBusyFlag = FALSE;
2487 }
2488 else //open clk
2489 {
2490 _gCheckBusyFlag = TRUE;
2491 //_gCheckBusyFlag = FALSE;
2492 if( (u32Data & NI_NSK2_CLK_ENABLE) == 0)
2493 {
2494 NI_REG(REG_NI_NSK2_CTRL) = u32Data | NI_NSK2_CLK_ENABLE ;
2495 //MsOS_DelayTaskUs(1);
2496 }
2497 }
2498
2499 //printf("REG_NI_NSK2_CTRL = %x\n",NI_REG(REG_NI_NSK2_CTRL));
2500
2501 //u32Data = 0;
2502 u32Data = NI_REG(REG_NI_NSK2_CLK_CSA);
2503
2504
2505 NI_REG(REG_NI_NSK2_CLK_CSA) = u32Data | NSK2_PUSH_SLOW_CLK;
2506
2507
2508 if(NumOfMs <= 2)
2509 {
2510 MsOS_DelayTaskUs(NumOfMs*500);
2511 }
2512 else
2513 {
2514 MsOS_DelayTask(NumOfMs-1);
2515 }
2516
2517 return TRUE;
2518 }
2519
2520
2521
HAL_NSK2_GetCMProperties(MS_U32 * desc_size,MS_U8 * desc)2522 MS_U32 HAL_NSK2_GetCMProperties(MS_U32 *desc_size, MS_U8 *desc)
2523 {
2524 MS_U32 i;
2525 if(desc == NULL)
2526 {
2527 *desc_size = sizeof(cmchannel_group_capability_descriptor_t) + sizeof(cm_algo) /*sizeof(cmchannel_group_algorithm_record_descriptor_t)*CMChannelDescSize*/ ;
2528 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetCMProperties return desc_size = %x\n",*desc_size);
2529 return TRUE;
2530 }
2531
2532 for(i=0;i<32;i++)
2533 {
2534 cm_capb.switch_combination_bitmap[i] = 0xFF;
2535 }
2536
2537 *desc_size = sizeof(cmchannel_group_capability_descriptor_t) + sizeof(cm_algo);
2538
2539 memcpy(desc,&cm_capb,sizeof(cmchannel_group_capability_descriptor_t));
2540 memcpy(desc+sizeof(cmchannel_group_capability_descriptor_t), &cm_algo[0] , sizeof(cm_algo) /*sizeof(cmchannel_group_algorithm_record_descriptor_t)*CMChannelDescSize*/ );
2541
2542 HALNSK2_DBG(NSK2_DBGLV_INFO,"\nHAL_NSK2_GetCMProperties return *desc_size = %x,desc = %x\n",*desc_size,(MS_U32)desc);
2543
2544 return TRUE;
2545 }
2546
HAL_NSK2_GetM2MProperties(MS_U32 * desc_size,MS_U8 * desc)2547 MS_U32 HAL_NSK2_GetM2MProperties(MS_U32 *desc_size, MS_U8 *desc)
2548 {
2549 if(desc == NULL)
2550 {
2551 *desc_size = sizeof(m2m_capa_desc) + sizeof(m2m_algo);
2552 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetM2MProperties #1 return desc_size = %x\n",*desc_size);
2553 return TRUE;
2554 }
2555
2556 *desc_size = sizeof(m2m_capa_desc) + sizeof(m2m_algo);
2557
2558 memcpy(desc, &m2m_capa_desc, sizeof(m2m_capa_desc));
2559 memcpy(desc+sizeof(m2m_capa_desc), &m2m_algo[0], sizeof(m2m_algo));
2560
2561 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetM2MProperties #2 return desc_size = %x\n",*desc_size);
2562 return TRUE;
2563 }
2564
HAL_NSK2_GetDMAProperties(MS_U32 * desc_size,MS_U8 * desc)2565 MS_U32 HAL_NSK2_GetDMAProperties(MS_U32 *desc_size, MS_U8 *desc)
2566 {
2567 if(desc == NULL)
2568 {
2569 *desc_size = sizeof(dma_capa_desc);
2570 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_GetDMAProperties return desc_size = %x\n",*desc_size);
2571 return TRUE;
2572 }
2573
2574 *desc_size = sizeof(dma_capa_desc);
2575
2576 memcpy(desc, &dma_capa_desc, *desc_size);
2577
2578 return TRUE;
2579 }
2580
2581 //---------------Debug Information----------------------------//
2582 //------------------------------------------------------------//
2583
HAL_NSK2_ReadTSPInfo(MS_U32 pid_no)2584 void HAL_NSK2_ReadTSPInfo(MS_U32 pid_no)
2585 {
2586 MS_U32 pid_data;
2587 MS_U32 FltPid, TS_SRC, dscmb_key_en, prim, pid_pair;
2588
2589 FltPid = TS_SRC = dscmb_key_en = prim = pid_pair = 0;
2590 REG_PidFlt *pPidFlt = PPIDFLT0(pid_no);
2591
2592 pid_data = TSP32_IdrR(pPidFlt);
2593
2594 HALNSK2_DBG(NSK2_DBGLV_INFO,"pid_data = %x\n",pid_data);
2595
2596 FltPid = (pid_data & 0x1fff);
2597 TS_SRC = ((pid_data>>13) & 0x7);
2598 dscmb_key_en = ((pid_data>>16) & 0x1);
2599 prim = ((pid_data>>17) & 0x1);
2600 pid_pair = ((pid_data>>18) & 0xf);
2601
2602 if(dscmb_key_en)
2603 {
2604 HALNSK2_DBG(NSK2_DBGLV_INFO,"(%d) = (FltPid=%x, TS_SRC=%d, prim=%d, pid_pair=%d\n",pid_no,FltPid,TS_SRC,prim,pid_pair);
2605 }
2606 }
2607
HAL_NSK2_ReadTSPDstInfo(MS_U32 pid_no)2608 void HAL_NSK2_ReadTSPDstInfo(MS_U32 pid_no)
2609 {
2610 MS_U32 pid_data;
2611 REG_PidFlt *pPidFlt = PPIDFLT1(pid_no);
2612
2613 pid_data = TSP32_IdrR(pPidFlt);
2614
2615 HALNSK2_DBG(NSK2_DBGLV_INFO,"dst_data = %x\n",pid_data);
2616 }
2617
HAL_NSK2_AllTSPPidFilter(void)2618 void HAL_NSK2_AllTSPPidFilter(void)
2619 {
2620 MS_U32 i;
2621 for(i=0;i<0x100;i++)
2622 {
2623 HAL_NSK2_ReadTSPInfo(i);
2624 }
2625
2626 for(i=0;i<0x100;i++)
2627 {
2628 HAL_NSK2_ReadTSPDstInfo(i);
2629 }
2630 }
2631
HAL_NSK2_ChangePidFilter(MS_U32 pid_no,MS_U32 Data)2632 void HAL_NSK2_ChangePidFilter(MS_U32 pid_no, MS_U32 Data)
2633 {
2634 REG_PidFlt *pPidFlt = PPIDFLT0(pid_no);
2635 TSP32_IdrW(pPidFlt,Data);
2636 }
2637
2638
2639
HAL_NSK2_ReadSwitchFromNSK2(void)2640 MS_U32 HAL_NSK2_ReadSwitchFromNSK2(void)
2641 {
2642
2643 #if 0
2644 2. N2_KteValid=1. NI bank offset 13 bit[3].
2645 3. N2_KteDest=0. NI bank offset 13 bit[2:0].
2646 4. Read the NSK bank offset 0xfc40-0xfc48 to read the NSK driven switch value. (see NSK-ICD-253 page21).
2647 In the read 96 bits, you can find:
2648 Bit[55] AU
2649 Bit[54] BU
2650 Bit[53] DU
2651 Bit[52] EU
2652 Bit[51] AL
2653 Bit[50] BL
2654 Bit[49] DL
2655 Bit[48] EL
2656 Bit[47:44] LocalSelectD
2657 Bit[43:40] LocalSelectS
2658 Bit[39:36] ESA select
2659 Bit[35:33] ESA subselect
2660 Please print out these fields and send the log to me.
2661 #endif
2662
2663 #ifdef ReadSwitchInfoNSK2
2664 MS_U32 NI13 = NI_REG(13);
2665 HALNSK2_DBG(0,"NI13 = %x\n",NI13);
2666
2667 MS_U32 NSK2Debug[3];
2668 NSK2Debug[0] = HAL_NSK2_ReadReg(0xFC40);
2669 NSK2Debug[1] = HAL_NSK2_ReadReg(0xFC44);
2670 NSK2Debug[2] = HAL_NSK2_ReadReg(0xFC48);
2671
2672 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"NSK2Debug = (%x,%x,%x)\n",NSK2Debug[0],NSK2Debug[1],NSK2Debug[2]);
2673 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"AU=%x,BU=%x,DU=%x,EU=%x \n",(NSK2Debug[1]>>23)&0x1,(NSK2Debug[1]>>22)&0x1,(NSK2Debug[1]>>21)&0x1,(NSK2Debug[1]>>20)&0x1);
2674 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"AL=%x,BL=%x,DL=%x,EL=%x \n",(NSK2Debug[1]>>19)&0x1,(NSK2Debug[1]>>18)&0x1,(NSK2Debug[1]>>17)&0x1,(NSK2Debug[1]>>16)&0x1);
2675 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"LocalSelectD = %x, LocalSelectS = %x\n",(NSK2Debug[1]>>12)&0xf,(NSK2Debug[1]>>8)&0xf);
2676 HALNSK2_DBG(NSK2_DBGLV_DEBUG,"ESA select = %x, ESA subselect = %x\n",(NSK2Debug[1]>>4)&0xf,(NSK2Debug[1]>>0)&0xf);
2677 #endif
2678 return TRUE;
2679 }
2680
HAL_NSK2_GetSRAlignBit(void)2681 MS_U32 HAL_NSK2_GetSRAlignBit(void)
2682 {
2683 return 16;
2684 }
2685
2686 /* Temporary, since RSA sec_range drv is non-ready*/
HAL_NSK2_RSA_SetSecureRange(MS_U32 u32SecSet,MS_U32 u32SecStart,MS_U32 u32SecEnd,MS_BOOL bEnable)2687 MS_BOOL HAL_NSK2_RSA_SetSecureRange(MS_U32 u32SecSet, MS_U32 u32SecStart, MS_U32 u32SecEnd, MS_BOOL bEnable)
2688 {
2689 if(u32SecSet > REG_MPROT_SECRANGE_SET || u32SecEnd <= u32SecStart)
2690 return FALSE;
2691
2692 *(volatile MS_U32*) (_gBasicAddr + REG_MPROT_SECRANGE_START(u32SecSet)) = (u32SecStart & MPROT_SECRANGE_MASK);
2693
2694 if (TRUE == bEnable)
2695 {
2696 *(volatile MS_U32*) (_gBasicAddr + REG_MPROT_SECRANGE_END(u32SecSet)) = REG_MPROT_SECRANGE_ENABLE & ( u32SecEnd & MPROT_SECRANGE_MASK);
2697 }
2698 else
2699 {
2700 *(volatile MS_U32*) (_gBasicAddr + REG_MPROT_SECRANGE_END(u32SecSet)) = (~REG_MPROT_SECRANGE_ENABLE) | ( u32SecEnd & MPROT_SECRANGE_MASK);
2701 }
2702
2703 return TRUE;
2704 }
2705 /**
2706 * @brief Configure CA secure range mask
2707 */
HAL_NSK2_RSA_SetSR_Mask(MS_U32 u32DramSize)2708 void HAL_NSK2_RSA_SetSR_Mask(MS_U32 u32DramSize)
2709 {
2710 MS_U32 u32Mask = 0x00000000;
2711
2712 if (0 != ((u32DramSize >> 16) >> 8))
2713 {
2714 u32Mask = (((u32DramSize >> 16) >> 8) - 1) & 0xFF;
2715
2716 *(volatile MS_U32*) (_gBasicAddr + REG_MPROT_SECRANGE_MASK) = u32Mask;
2717 }
2718 }
2719 //=====================================
2720 //====== NSK2.1 new functions ======
2721 //=====================================
2722
2723
HAL_NSK2_ReadAllOTP(void)2724 void HAL_NSK2_ReadAllOTP(void)
2725 {
2726 MS_U32 u32RetValue, addr;
2727
2728 for( addr=0 ; addr<0x4000; addr+=4)
2729 {
2730 HAL_NSK2_OTP_Get(addr, 31, 0, &u32RetValue);
2731 //if( (addr&0xf) == 0)
2732 // printf("\n");
2733
2734 if(u32RetValue != 0)
2735 {
2736 HALNSK2_DBG(NSK2_DBGLV_INFO,"addr = %x, value = %x \n",addr, u32RetValue);
2737 }
2738 }
2739 }
2740
HAL_NSK2_ReadKTEResp(void)2741 MS_U32 HAL_NSK2_ReadKTEResp(void)
2742 {
2743 StatusCheck(HAL_NSK2_CheckBusy());
2744
2745 MS_U32 u32KTEResp;
2746 u32KTEResp = NI_REG(REG_NI_NSK2_KTE_RESP);
2747
2748 HALNSK2_DBG(NSK2_DBGLV_INFO,"KTE_RESP = %x\n",u32KTEResp);
2749
2750 return u32KTEResp;
2751 }
2752
HAL_NSK2_GetPubOTP(MS_U8 * pPubOTP)2753 MS_BOOL HAL_NSK2_GetPubOTP(MS_U8 *pPubOTP)
2754 {
2755 #if 0
2756 Table 7 Public OTP Bits
2757 Bit Name Description
2758 127:64 U_OTP_v_pubOtpUniqueID1 OTP unique ID.
2759 This field is unique chip data that can be shared with other non-NDS modules.
2760 63:48 U_OTP_v_PubOtpGP General purpose OTP field.
2761 47:40 U_OTP_v_PubOtpMinConfVer OTPpublic minimum configuration version.
2762 39:36 U_OTP_v_PubOtpRsaIndex OTP public RSA index
2763 35:32 U_OTP_v_PubOtpBID OTP public BlackBox ID
2764 31:16 U_OTP_v_PubOtpVID OTP public version ID
2765 15:0 U_OTP_v_PubOtpOID OTP public owner ID
2766 #endif
2767
2768 //U_OTP_v_pubOtpUniqueID1 0x3DA8 63 0
2769 //U_OTP_v_PubOtpGP 0x3B08 15 0
2770 //U_OTP_v_PubOtpMinConfVer 0x3B14 7 0
2771 //U_OTP_v_PubOtpRsaIndex 0x3B10 3 0
2772 //U_OTP_v_PubOtpBID 0x3B0C 3 0
2773 //U_OTP_v_PubOtpVID 0x3B04 15 0
2774 //U_OTP_v_PubOtpOID 0x3B00 15 0
2775
2776 MS_U8 *pRunPubOTP = (MS_U8 *)pPubOTP;
2777 MS_U32 ReadValue,ReadValue2;
2778
2779 HAL_NSK2_OTP_Get(0x3B00, 15, 0, &ReadValue);
2780 HALNSK2_DBG(NSK2_DBGLV_INFO,"U_OTP_v_PubOtpOID = %x\n",ReadValue);
2781 memcpy(pRunPubOTP,&ReadValue,2);
2782 pRunPubOTP += 2;
2783
2784 HAL_NSK2_OTP_Get(0x3B04, 15, 0, &ReadValue);
2785 HALNSK2_DBG(NSK2_DBGLV_INFO,"U_OTP_v_PubOtpVID = %x\n",ReadValue);
2786 memcpy(pRunPubOTP,&ReadValue,2);
2787 pRunPubOTP += 2;
2788
2789 HAL_NSK2_OTP_Get(0x3B0C, 3, 0, &ReadValue);
2790 HALNSK2_DBG(NSK2_DBGLV_INFO,"U_OTP_v_PubOtpBID = %x\n",ReadValue);
2791 HAL_NSK2_OTP_Get(0x3B10, 3, 0, &ReadValue2);
2792 HALNSK2_DBG(NSK2_DBGLV_INFO,"U_OTP_v_PubOtpRsaIndex = %x\n",ReadValue2);
2793 *pRunPubOTP = (MS_U8)(ReadValue&0xF) + (MS_U8)((ReadValue2&0xF)<<4);
2794 pRunPubOTP ++;
2795
2796 HAL_NSK2_OTP_Get(0x3B14, 7, 0, &ReadValue);
2797 HALNSK2_DBG(NSK2_DBGLV_INFO,"U_OTP_v_PubOtpMinConfVer = %x\n",ReadValue);
2798 memcpy(pRunPubOTP,&ReadValue,1);
2799 pRunPubOTP ++;
2800
2801 HAL_NSK2_OTP_Get(0x3B08, 15, 0, &ReadValue);
2802 HALNSK2_DBG(NSK2_DBGLV_INFO,"U_OTP_v_PubOtpGP = %x\n",ReadValue);
2803 memcpy(pRunPubOTP,&ReadValue,2);
2804 pRunPubOTP += 2;
2805
2806 HAL_NSK2_OTP_Get(0x3DA8, 31, 0, &ReadValue);
2807 HALNSK2_DBG(NSK2_DBGLV_INFO,"U_OTP_v_pubOtpUniqueID1 = %x\n",ReadValue);
2808 memcpy(pRunPubOTP,&ReadValue,4);
2809 pRunPubOTP += 4;
2810
2811 HAL_NSK2_OTP_Get(0x3DAC, 31, 0, &ReadValue);
2812 memcpy(pRunPubOTP,&ReadValue,4);
2813 pRunPubOTP += 4;
2814
2815 return TRUE;
2816 }
2817
HAL_NSK21_InvalidCmChannel(MS_U16 PidSlot)2818 MS_U32 HAL_NSK21_InvalidCmChannel(MS_U16 PidSlot)
2819 {
2820 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s PidSlot = %x\n", __FUNCTION__,PidSlot);
2821
2822 MS_U32 u32PidSlot = 0;
2823 StatusCheck(HAL_NSK2_CheckBusy());
2824
2825 u32PidSlot = (((MS_U32)PidSlot<<NI_WriteTKey_PidNo_Shift)&NI_WriteTransportKey_PidNo);
2826 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_InvalidateCmChannel | u32PidSlot);
2827
2828 return TRUE;
2829 }
2830
2831 typedef enum
2832 {
2833 NSK21_DVBCSA2 = 0,
2834 NSK21_DVBCSA2_CONF,
2835 NSK21_DVBCSA3,
2836 NSK21_CPCM_LSA_MDI_CBC,
2837 NSK21_CPCM_LSA_MDI_RCBC,
2838 NSK21_CPCM_LSA_MDD_CBC, //5
2839 NSK21_CPCM_LSA_MDD_RCBC,
2840 NSK21_SYNAMEDIA_AES,
2841 NSK21_AES_ECB_CLR,
2842 NSK21_CIPLUS_AES,
2843 NSK21_SCTE41_DES, //10
2844 NSK21_SCTE52_DES,
2845 NSK21_TDES_ECB_CLR,
2846 NSK21_MULTI2_TS,
2847 NSK21_TDES_ECB_CTS,
2848 NSK21_DES_ECB_CTS, //15
2849 NSK21_IDSA_AES,
2850 }NSK21_CMChAlgo_e;
2851
HAL_NSK21_CfgCmChannel(MS_U16 PidSlot,MS_U16 LocalDAlgo,MS_U16 ESAAlgo,MS_U16 LocalSAlgo,MS_U16 SysKeyIndex)2852 MS_U32 HAL_NSK21_CfgCmChannel(MS_U16 PidSlot, MS_U16 LocalDAlgo, MS_U16 ESAAlgo, MS_U16 LocalSAlgo, MS_U16 SysKeyIndex)
2853 {
2854
2855 #define Algoffset 100
2856 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK2_CfgCmChannel PidSlot = %x, LocalDAlgo = %x, ESAAlgo = %x, LocalSAlgo = %x, SysKeyIndex = %x\n",PidSlot, LocalDAlgo, ESAAlgo, LocalSAlgo, SysKeyIndex);
2857 StatusCheck(HAL_NSK2_CheckBusy());
2858 MS_U32 algorithms = 0, u32PidSlot = 0;
2859
2860 if(LocalDAlgo < Algoffset)
2861 LocalDAlgo = 0;
2862 else
2863 LocalDAlgo -= Algoffset;
2864
2865 if(ESAAlgo < Algoffset)
2866 ESAAlgo = 0;
2867 else
2868 ESAAlgo -= Algoffset;
2869
2870 if(LocalSAlgo < Algoffset)
2871 LocalSAlgo = 0;
2872 else
2873 LocalSAlgo -= Algoffset;
2874
2875 #if 0 //tmp solution...
2876 algorithms = ((LocalDAlgo - 100) & NI_KIW_LSAD_ALGO_MASK) +
2877 (((ESAAlgo - 100) << NI_KIW_ESA_ALGO_SHIFT) & NI_KIW_ESA_ALGO_MASK) +
2878 (((LocalSAlgo - 100) << NI_KIW_LSAS_ALGO_SHIFT) & NI_KIW_LSAS_ALGO_MASK) ;
2879 #else
2880 algorithms = (LocalDAlgo & NI_KIW_LSAD_ALGO_MASK) +
2881 ((ESAAlgo << NI_KIW_ESA_ALGO_SHIFT) & NI_KIW_ESA_ALGO_MASK) +
2882 ((LocalSAlgo << NI_KIW_LSAS_ALGO_SHIFT) & NI_KIW_LSAS_ALGO_MASK) ;
2883 #endif
2884
2885 HALNSK2_DBG(NSK2_DBGLV_INFO,"algorithms = %x\n",algorithms);
2886 NI_REG(REG_NI_DSCMB_ALGO) = algorithms;
2887
2888 u32PidSlot = (((MS_U32)PidSlot<<NI_WriteTKey_PidNo_Shift)&NI_WriteTransportKey_PidNo);
2889 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_ConfigureCmChannel | u32PidSlot);
2890 MsOS_DelayTaskUs(1);
2891 HALNSK2_DBG(NSK2_DBGLV_INFO,"REG_NI_DSCMB_ALGO = %x\n",NI_REG(REG_NI_DSCMB_ALGO));
2892
2893 return TRUE;
2894 }
2895
HAL_NSK21_WriteTransportKey(MS_U8 SCB,MS_U8 ForceSCB,void * pLocalDIV1,void * pLocalDIV2,void * pESAIV1,void * pESAIV2,void * pLocalSIV1,void * pLocalSIV2,MS_U16 PidSlot)2896 MS_U32 HAL_NSK21_WriteTransportKey(MS_U8 SCB, MS_U8 ForceSCB, void *pLocalDIV1, void *pLocalDIV2,
2897 void *pESAIV1, void *pESAIV2, void *pLocalSIV1, void *pLocalSIV2, MS_U16 PidSlot )
2898 {
2899 HALNSK2_DBG(NSK2_DBGLV_INFO,"HAL_NSK21_WriteTransportKey PidSlot = %x, SCB = %x, ForceSCB = %x\n", PidSlot, SCB, ForceSCB);
2900
2901 MS_U32 data,data2;
2902 //check NULL pointer or not....
2903
2904 StatusCheck(HAL_NSK2_CheckBusy());
2905
2906 data = NI_REG(REG_NI_KTE_STATUS);
2907 if( ( data & NI_KTE_DEST_MASK ) == 0 )
2908 {
2909
2910 ForceSCB = HAL_NSK2_SCBTransToHW(ForceSCB);
2911
2912 HALNSK2_DBG(NSK2_DBGLV_INFO,"PidSlot: %x\n", PidSlot);
2913 data2 = (((MS_U32)PidSlot<<NI_WriteTKey_PidNo_Shift)&NI_WriteTransportKey_PidNo) +
2914 (((MS_U32)SCB<<NI_WriteTKey_SCB_Shift) & NI_WriteTKey_SCB_MASK)
2915 + ( ( (MS_U32)ForceSCB<<NI_WriteTKey_FSCB_Shift) & NI_WriteTKey_FSCB_MASK) ;
2916
2917 #if 1
2918 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteTransportKey | data2 | NI_OTP_ACK_NSK2 | NI_ERR_INVALID_SLOT);
2919 #else
2920 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteTransportKey | data2);
2921 #endif
2922 HALNSK2_DBG(NSK2_DBGLV_INFO,"NI 6 = %x\n", NI_REG(REG_NI_COMMAND));
2923
2924 StatusCheck(HAL_NSK2_KIW_BusyPolling());
2925 }
2926 else
2927 {
2928 HALNSK2_DBG(NSK2_DBGLV_ERR,"WriteTransportKey abnormal ignored: KteDest not zero\n");
2929 return HAL_NSK2_ReadKTEResp();
2930 }
2931
2932 return HAL_NSK2_ReadKTEResp();
2933 }
2934
HAL_NSK21_WriteM2MKey(MS_U32 M2MAlgo)2935 MS_U32 HAL_NSK21_WriteM2MKey(MS_U32 M2MAlgo)
2936 {
2937 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s M2MAlgo = %x\n",__FUNCTION__,M2MAlgo);
2938
2939 MS_U32 algorithms;
2940
2941 StatusCheck(HAL_NSK2_CheckBusy());
2942
2943 algorithms = (M2MAlgo & NI_KIW_LSAD_ALGO_MASK) +
2944 ((M2MAlgo << NI_KIW_LSAS_ALGO_SHIFT) & NI_KIW_LSAS_ALGO_MASK) ;
2945
2946 HALNSK2_DBG(NSK2_DBGLV_INFO,"algorithms = %x\n",algorithms);
2947 NI_REG(REG_NI_DSCMB_ALGO) = algorithms;
2948 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteM2MKey);
2949
2950 MsOS_DelayTaskUs(1);
2951
2952 return HAL_NSK2_ReadKTEResp();
2953 }
2954
HAL_NSK21_ModifyGenIn(MS_U32 MaskVal,MS_U32 XorVal)2955 MS_U32 HAL_NSK21_ModifyGenIn(MS_U32 MaskVal,MS_U32 XorVal)
2956 {
2957 MS_U32 GenIn = 0, WriteGenIn = 0;
2958
2959 StatusCheck(HAL_NSK2_CheckBusy());
2960
2961 GenIn = NI_REG(REG_NI_NSK2_REG_GENIN);
2962
2963 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s GenIn = %x\n",__FUNCTION__,GenIn);
2964
2965 GenIn = (GenIn&MaskVal);
2966
2967 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s GenIn = %x, XorVal = %x\n",__FUNCTION__,GenIn,XorVal);
2968
2969 WriteGenIn = GenIn^XorVal;
2970 HALNSK2_DBG(NSK2_DBGLV_INFO,"WriteGenIn = %x\n",WriteGenIn);
2971
2972 #ifdef TestGenIn
2973 NI_REG(REG_NI_NSK21_GENIN) = WriteGenIn;
2974 MsOS_DelayTaskUs(10);
2975 #else
2976
2977 //NI_REG(REG_NI_NSK21_GENIN) = ( (WriteGenIn & BMASK(9:0)) | (WriteGenIn & __BIT(13)) );
2978 NI_REG(REG_NI_NSK21_GENIN) = WriteGenIn;
2979
2980 NI_REG(REG_NI_NSK21_CONCURR_PROT_EN) = ((WriteGenIn>>10) & BMASK(1:0));
2981 NI_REG(REG_NI_NSK21_CONCURR_SET) = ((WriteGenIn>>12) & BMASK(0:0));
2982 NI_REG(REG_NI_NSK21_GEN_SHOT) = ((WriteGenIn>>14) & BMASK(3:0));
2983
2984 MsOS_DelayTaskUs(10);
2985
2986 HALNSK2_DBG(NSK2_DBGLV_INFO,"CONCURR_PROT_EN = %x, CONCURR_SET = %x, GEN_SHOT = %x\n", NI_REG(REG_NI_NSK21_CONCURR_PROT_EN), NI_REG(REG_NI_NSK21_CONCURR_SET), NI_REG(REG_NI_NSK21_GEN_SHOT));
2987 #endif
2988 GenIn = NI_REG(REG_NI_NSK2_REG_GENIN);
2989
2990 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s GenIn = %x\n",__FUNCTION__,GenIn);
2991
2992 if(GenIn == WriteGenIn)
2993 return TRUE;
2994 else
2995 return FALSE;
2996
2997 }
2998
HAL_NSK21_GetGenIn(void)2999 MS_U32 HAL_NSK21_GetGenIn(void)
3000 {
3001 return NI_REG(REG_NI_NSK2_REG_GENIN);
3002 }
3003
HAL_NSK21_ReadNIReg(MS_U32 offset)3004 MS_U32 HAL_NSK21_ReadNIReg(MS_U32 offset)
3005 {
3006 return NI_REG(offset);
3007 }
3008
HAL_NSK21_WriteNIReg(MS_U32 offset,MS_U32 Value)3009 void HAL_NSK21_WriteNIReg(MS_U32 offset, MS_U32 Value)
3010 {
3011 NI_REG(offset) = Value;
3012 }
3013
HAL_NSK21_WriteJTagKey(MS_U32 OverrideOid,MS_U32 Select)3014 MS_U32 HAL_NSK21_WriteJTagKey(MS_U32 OverrideOid, MS_U32 Select)
3015 {
3016 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s OverrideOid = %x, Select = %x\n",__FUNCTION__,OverrideOid,Select);
3017
3018 MS_U32 functionality = 0, OID = 0;
3019
3020 StatusCheck(HAL_NSK2_CheckBusy());
3021
3022 if(OverrideOid>1) //invalid OverrideOid
3023 {
3024 HALNSK2_DBG(NSK2_DBGLV_ERR,"invalid OverrideOid\n");
3025 return FALSE;
3026 }
3027
3028 OID = (OverrideOid << NI_KIW_OID_SHIFT) & NI_KIW_OID_MASK ;
3029 #if 0
3030 functionality = (Select << NI_WriteTKey_PidNo_Shift) & NI_WriteTransportKey_PidNo ;
3031 #else
3032 functionality = 0; //N21_EJTAG_PWD
3033 #endif
3034
3035 HALNSK2_DBG(NSK2_DBGLV_INFO,"functionality = %x\n",functionality);
3036 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteJTAGKey | functionality | OID);
3037
3038 MsOS_DelayTaskUs(1);
3039
3040 return HAL_NSK2_ReadKTEResp();
3041 }
3042
HAL_NSK21_IncrementNvCounter(void)3043 MS_U32 HAL_NSK21_IncrementNvCounter(void)
3044 {
3045 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n",__FUNCTION__);
3046
3047 StatusCheck(HAL_NSK2_CheckBusy());
3048
3049 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_IncrementNvCounter);
3050 MsOS_DelayTaskUs(1);
3051
3052 return HAL_NSK2_ReadKTEResp();
3053 }
3054
HAL_NSK2_WriteOtpKey(void)3055 MS_U32 HAL_NSK2_WriteOtpKey(void)
3056 {
3057 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n",__FUNCTION__);
3058 StatusCheck(HAL_NSK2_CheckBusy());
3059
3060 NI_REG(REG_NI_COMMAND) = (NI_COMMAND_START | NI_WriteOTPKey);
3061 MsOS_DelayTask(10);
3062
3063 return HAL_NSK2_ReadKTEResp();
3064 }
3065
HAL_NSK2_ReadPWD_Status(void)3066 MS_U32 HAL_NSK2_ReadPWD_Status(void)
3067 {
3068 HALNSK2_DBG(NSK2_DBGLV_INFO,"%s \n",__FUNCTION__);
3069 StatusCheck(HAL_NSK2_CheckBusy());
3070 MS_U32 RegPwd;
3071
3072 RegPwd = NI_REG(REG_NI_NSK2_PWD_ON);
3073
3074 if(RegPwd & N2_JTAGPWD0_ON)
3075 {
3076 HALNSK2_DBG(NSK2_DBGLV_INFO,"JTAG PWD0 ON \n");
3077 }
3078
3079 if(RegPwd & N2_JTAGPWD1_ON)
3080 {
3081 HALNSK2_DBG(NSK2_DBGLV_INFO,"JTAG PWD1 ON \n");
3082 }
3083
3084 if(RegPwd & N2_SCANPWD_ON)
3085 {
3086 HALNSK2_DBG(NSK2_DBGLV_INFO,"SCAN PWD ON \n");
3087 }
3088
3089 if(RegPwd & N2_MBISTPWD_ON)
3090 {
3091 HALNSK2_DBG(NSK2_DBGLV_INFO,"MBIST PWD ON \n");
3092 }
3093
3094 if(RegPwd & N2_M2MKEY_ON)
3095 {
3096 HALNSK2_DBG(NSK2_DBGLV_INFO,"M2M KEY ON \n");
3097 }
3098
3099 if(RegPwd & N2_SCPUKEY0_ON)
3100 {
3101 HALNSK2_DBG(NSK2_DBGLV_INFO,"SCPU KEY0 ON \n");
3102 }
3103
3104 if(RegPwd & N2_SCPUKEY1_ON)
3105 {
3106 HALNSK2_DBG(NSK2_DBGLV_INFO,"SCPU KEY1 ON \n");
3107 }
3108
3109 if(RegPwd & N2_RNGVALUE0_ON)
3110 {
3111 HALNSK2_DBG(NSK2_DBGLV_INFO,"RNG VALUE0 ON \n");
3112 }
3113
3114 if(RegPwd & N2_RNGVALUE1_ON)
3115 {
3116 HALNSK2_DBG(NSK2_DBGLV_INFO,"RNG VALUE1 ON \n");
3117 }
3118
3119 return TRUE;
3120 }
3121
HAL_NSK2_CtrlClk(MS_BOOL Enable)3122 MS_U32 HAL_NSK2_CtrlClk(MS_BOOL Enable)
3123 {
3124 if(Enable)
3125 {
3126 HALNSK2_DBG(NSK2_DBGLV_INFO,"enable NSK clock\n");
3127 NI_REG(REG_NI_NSK2_CTRL) |= (NI_NSK2_CLK_ENABLE | NI_NSK2_RESET_DISABLE);
3128 HAL_NSK2_ColdReset();
3129 }
3130 else
3131 {
3132 HALNSK2_DBG(NSK2_DBGLV_INFO,"disable NSK clock\n");
3133 NI_REG(REG_NI_NSK2_CTRL) &= ~(NI_NSK2_CLK_ENABLE | NI_NSK2_RESET_DISABLE);
3134 _gReset = FALSE;
3135 _gCheckBusyFlag = FALSE;
3136 }
3137
3138 MsOS_DelayTask(1);
3139
3140
3141 HALNSK2_DBG(NSK2_DBGLV_INFO,"REG_NI_NSK2_CTRL = %x\n",NI_REG(REG_NI_NSK2_CTRL));
3142 return TRUE;
3143 }
3144
HAL_NSK2_ReadClkStatus(void)3145 MS_U32 HAL_NSK2_ReadClkStatus(void)
3146 {
3147 MS_U32 status;
3148 MS_U32 rom[4];
3149
3150 status = (NI_REG(REG_NI_KTE_STATUS)& NI_SLOW_CLOCK_DETECT);
3151
3152 HALNSK2_DBG(NSK2_DBGLV_INFO,"REG_NI_KTE_STATUS = %x\n",NI_REG(REG_NI_KTE_STATUS));
3153 HALNSK2_DBG(NSK2_DBGLV_INFO,"NI_SLOW_CLOCK_DETECT = %x\n", (status>>5));
3154
3155 if(status)
3156 {
3157 HALNSK2_DBG(NSK2_DBGLV_INFO,"no clock for NSK\n");
3158 }
3159 else
3160 {
3161 HALNSK2_DBG(NSK2_DBGLV_INFO,"clock is alive for NSK\n");
3162 }
3163
3164 HALNSK2_DBG(NSK2_DBGLV_INFO,"read NSK ROM value\n");
3165 HAL_NSK2_ReadData32(0x8000, 4, &rom[0]);
3166
3167 HALNSK2_DBG(NSK2_DBGLV_INFO,"%x, %x, %x, %x,\n",rom[0],rom[1],rom[2],rom[3]);
3168
3169 return TRUE;
3170 }
3171
3172