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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halCA.c
97 // @brief CA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include "string.h"
104 #endif
105
106 #include "MsCommon.h"
107 #include "regCA.h"
108 #include "drvCA.h"
109 #include "halCA.h"
110
111 #include <drvSYS.h>
112
113 // #undef MS_DEBUG_MSG
114 // #define MS_DEBUG_MSG(x) x
115
116 //--------------------------------------------------------------------------------------------------
117 // Driver Compiler Option
118 //--------------------------------------------------------------------------------------------------
119
120
121 //--------------------------------------------------------------------------------------------------
122 // Global Definition
123 //--------------------------------------------------------------------------------------------------
124 #define MAX_RESERVED_SIZE 64
125
126
127 //--------------------------------------------------------------------------------------------------
128 // CA Hardware Abstraction Layer
129 //--------------------------------------------------------------------------------------------------
130 static MS_VIRT _u32REGBase = 0;
131 static MS_VIRT _u32REGPMBase = 0;
132 static MS_VIRT _u32REG_OTP_Base = 0;
133 static MS_VIRT _u32REG_RSA_Base = 0;
134
135 #define REG16(addr) (*(volatile unsigned short *)(_u32REGBase + (addr)))
136 #define REG16_WRITE(addr, value, mask) do { REG16(addr) = (REG16(addr) & ~(mask)) | ((value) & (mask)); } while(0)
137
138 #define REG32(addr) (*(volatile unsigned *)(_u32REGBase + (addr)))
139 #define REG32_WRITE(addr, value, mask) do { REG32(addr) = (REG32(addr) & ~(mask)) | ((value) & (mask)); } while(0)
140
141 #define REG32_PM(addr) (*(volatile unsigned *)(_u32REGPMBase + (addr)))
142 #define REG16_PM(addr) (*(volatile unsigned short *)(_u32REGPMBase + (addr)))
143
144 #ifdef CA_NO_PRINTF
145 #define HAL_CA_DEBUG(fmt, args...)
146 #else
147 #define HAL_CA_DEBUG(fmt, args...) do{ \
148 printf("[%s][%d]"fmt"\n", __FUNCTION__, __LINE__, ## args);}\
149 while(0)
150 #endif
bitmask(unsigned hi,unsigned lo)151 static unsigned bitmask(unsigned hi, unsigned lo)
152 {
153 unsigned x, s = hi - lo + 1;
154 // printf("hi=%d lo=%d size=%d\n", hi, lo, s);
155
156 if(s >= sizeof(unsigned) * 8)
157 x = (unsigned)-1;
158 else
159 x = (1U << s) - 1;
160 return x << lo;
161 }
162
163 struct {
164 MS_U32 u32Addr;
165 MS_U32 u32Hi;
166 MS_U32 u32Lo;
167 } _HAL_CA_OTP_Addr[] = {
168 //Parse from otp mapping
169 [U_OTP_CA_reserved0] = {0x003500, 255, 0},
170 [U_OTP_CA_reserved1] = {0x003520, 255, 0},
171 [U_OTP_CA_reserved2] = {0x003540, 255, 0},
172 [U_OTP_CA_reserved3] = {0x003560, 255, 0},
173 [U_OTP_CA_reserved4] = {0x003580, 255, 0},
174 [U_OTP_CA_reserved5] = {0x0035A0, 255, 0},
175 [U_OTP_CA_reserved6] = {0x0035C0, 255, 0},
176 [U_OTP_CA_reserved7] = {0x0035E0, 255, 0},
177 [U_OTP_CA_reserved8] = {0x003600, 255, 0},
178 [U_OTP_CA_reserved9] = {0x003620, 255, 0},
179 [U_OTP_CA_reserved10] = {0x003640, 255, 0},
180 [U_OTP_CA_reserved11] = {0x003660, 255, 0},
181 [U_OTP_CA_reserved12] = {0x003680, 255, 0},
182 [U_OTP_CA_reserved13] = {0x0036A0, 255, 0},
183 [U_OTP_CA_reserved14] = {0x0036C0, 255, 0},
184 [U_OTP_CA_reserved15] = {0x0036E0, 255, 0},
185 [U_OTP_Chip_Extension_ID] = {0x003700, 127, 0},
186 [U_OTP_PVConfiguration] = {0x003710, 23, 0},
187 [U_OTP_EncryptLoader_Key_sel] = {0x003710, 27, 24},
188 [U_OTP_EncryptLoader_KL_level] = {0x003710, 29, 28},
189 [U_OTP_SW_Reserved0] = {0x003710, 31, 30},
190 [U_OTP_EncryptLoader_ForceEnc] = {0x003714, 1, 0},
191 [U_OTP_SW_Reserved1] = {0x003714, 31, 2},
192 [U_OTP_SW_Reserved2] = {0x003724, 31, 0},
193 [U_OTP_Versioning] = {0x003728, 511, 0},
194 [U_OTP_Preenablement_0] = {0x003768, 31, 0},
195 [U_OTP_Preenablement_1] = {0x00376C, 31, 0},
196 [U_OTP_Preenablement_2] = {0x003770, 31, 0},
197 [U_OTP_Preenablement_3] = {0x003774, 31, 0},
198 [U_OTP_Preenablement_4] = {0x003778, 31, 0},
199 [U_OTP_Preenablement_5] = {0x00377C, 31, 0},
200 [U_OTP_Preenablement_6] = {0x003780, 31, 0},
201 [U_OTP_Preenablement_7] = {0x003784, 31, 0},
202 [U_OTP_CAdata_0] = {0x003788, 31, 0},
203 [U_OTP_CAdata_1] = {0x00378C, 31, 0},
204 [U_OTP_CAdata_2] = {0x003790, 31, 0},
205 [U_OTP_CAdata_3] = {0x003794, 31, 0},
206 [U_OTP_CAdata_4] = {0x003798, 31, 0},
207 [U_OTP_CAdata_5] = {0x00379C, 31, 0},
208 [U_OTP_CAdata_6] = {0x0037A0, 31, 0},
209 [U_OTP_CAdata_7] = {0x0037A4, 31, 0},
210 [U_OTP_CAdata_8] = {0x0037A8, 31, 0},
211 [U_OTP_CAdata_9] = {0x0037AC, 31, 0},
212 [U_OTP_CAdata_10] = {0x0037B0, 31, 0},
213 [U_OTP_CAdata_11] = {0x0037B4, 31, 0},
214 [U_OTP_CAdata_12] = {0x0037B8, 31, 0},
215 [U_OTP_CAdata_13] = {0x0037BC, 31, 0},
216 [U_OTP_CAdata_14] = {0x0037C0, 31, 0},
217 [U_OTP_CAdata_15] = {0x0037C4, 31, 0},
218 [U_OTP_CAdata_16] = {0x0037C8, 31, 0},
219 [U_OTP_CAdata_17] = {0x0037CC, 31, 0},
220 [U_OTP_CAdata_18] = {0x0037D0, 31, 0},
221 [U_OTP_CAdata_19] = {0x0037D4, 31, 0},
222 [U_OTP_CAdata_20] = {0x0037D8, 31, 0},
223 [U_OTP_CAdata_21] = {0x0037DC, 31, 0},
224 [U_OTP_CAdata_22] = {0x0037E0, 31, 0},
225 [U_OTP_CAdata_23] = {0x0037E4, 31, 0},
226 [U_OTP_CAdata_24] = {0x0037E8, 31, 0},
227 [U_OTP_CAdata_25] = {0x0037EC, 31, 0},
228 [U_OTP_CAdata_26] = {0x0037F0, 31, 0},
229 [U_OTP_CAdata_27] = {0x0037F4, 31, 0},
230 [U_OTP_CAdata_28] = {0x0037F8, 31, 0},
231 [U_OTP_CAdata_29] = {0x0037FC, 31, 0},
232 [U_OTP_CAdata_30] = {0x003800, 31, 0},
233 [U_OTP_CAdata_31] = {0x003804, 31, 0},
234 [U_OTP_CAdata_32] = {0x003808, 31, 0},
235 [U_OTP_CAdata_33] = {0x00380C, 31, 0},
236 [U_OTP_CAdata_34] = {0x003810, 31, 0},
237 [U_OTP_CAdata_35] = {0x003814, 31, 0},
238 [U_OTP_CAdata_36] = {0x003818, 31, 0},
239 [U_OTP_CAdata_37] = {0x00381C, 31, 0},
240 [U_OTP_forbid_SCPU2DRAM] = {0x003820, 3, 0},
241 [U_OTP_forbid_SCPUQMEM_to_DRAM] = {0x003820, 7, 4},
242 [U_OTP_forbid_CryptoDMA_keyslot_QMEM] = {0x003820, 11, 8},
243 [U_OTP_forbid_SCPU2UART] = {0x003820, 15, 12},
244 [U_OTP_IXSC_config1] = {0x003820, 19, 16},
245 [U_OTP_IXSC_config2] = {0x003820, 23, 20},
246 [U_OTP_IXSC_config3] = {0x003820, 27, 24},
247 [U_OTP_IXSC_config4] = {0x003820, 31, 28},
248 [U_OTP_LockWord_Preenablement_0_W] = {0x003824, 1, 0},
249 [U_OTP_LockWord_Preenablement_1_W] = {0x003824, 3, 2},
250 [U_OTP_LockWord_Preenablement_2_W] = {0x003824, 5, 4},
251 [U_OTP_LockWord_Preenablement_3_W] = {0x003824, 7, 6},
252 [U_OTP_LockWord_Preenablement_4_W] = {0x003824, 9, 8},
253 [U_OTP_LockWord_Preenablement_5_W] = {0x003824, 11, 10},
254 [U_OTP_LockWord_Preenablement_6_W] = {0x003824, 13, 12},
255 [U_OTP_LockWord_Preenablement_7_W] = {0x003824, 15, 14},
256 [U_OTP_Test_Switch] = {0x003824, 23, 16},
257 [U_OTP_IXSC_Reserved0] = {0x003824, 31, 24},
258 [U_OTP_NOCS3_00] = {0x003828, 383, 0},
259 [U_OTP_NOCS3_01] = {0x003858, 383, 0},
260 [U_OTP_NOCS3_02] = {0x003888, 127, 0},
261 [U_OTP_NOCS3_03] = {0x003898, 127, 0},
262 [U_OTP_MSID] = {0x0038A8, 31, 0},
263 [U_OTP_CFG_STB_CA_SN] = {0x0038AC, 31, 0},
264 [U_OTP_HASH0_VER_REF] = {0x0038c8, 31, 0},
265 [U_OTP_HASH1_VER_REF] = {0x0038cc, 31, 0},
266 [U_OTP_HASH2_VER_REF] = {0x0038d0, 31, 0},
267 [U_OTP_RSA_0] = {0x0039B0, 2047, 0},
268 [U_OTP_RSA_1] = {0x003628, 2047, 0},
269 [U_OTP_RSA_0_integrity_chk] = {0x003AB0, 1, 0},
270 [U_OTP_RSA_1_integrity_chk] = {0x003AB0, 3, 2},
271 [U_OTP_ena_ACPUUseHWRSAKey] = {0x003AB0, 7, 4},
272 [U_OTP_forbid_ACPUReadRSAKey0] = {0x003AB0, 10, 8},
273 [U_OTP_forbid_ACPUReadRSAKey1] = {0x003AB0, 13, 11},
274 [U_OTP_forbid_ACPUWrite_Versioning] = {0x003AB0, 15, 14},
275 [U_OTP_forbid_ACPURead_Versioning] = {0x003AB0, 17, 16},
276 [U_OTP_RSA_Reserved0] = {0x003AB0, 31, 18},
277 [U_OTP_RSA_0_CRC] = {0x003AB4, 15, 0},
278 [U_OTP_RSA_1_CRC] = {0x003AB4, 31, 16},
279 [U_OTP_PGMask0] = {0x003AB8, 31, 0},
280 [U_OTP_PGMask1] = {0x003ABC, 31, 0},
281 [U_OTP_PGMask2] = {0x003AC0, 31, 0},
282 [U_OTP_PGMask3] = {0x003AC4, 31, 0},
283 [U_OTP_PGMask4] = {0x003AC8, 31, 0},
284 [U_OTP_PGMask5] = {0x003ACC, 31, 0},
285 [U_OTP_PGMask6] = {0x003AD0, 31, 0},
286 [U_OTP_PGMask7] = {0x003AD4, 31, 0},
287 [U_OTP_PGMask8] = {0x003AD8, 31, 0},
288 [U_OTP_PGMask9] = {0x003ADC, 31, 0},
289 [U_OTP_PGMask10] = {0x003AE0, 31, 0},
290 [U_OTP_PGMask11] = {0x003AE4, 31, 0},
291 [U_OTP_PGMask12] = {0x003AE8, 31, 0},
292 [U_OTP_PGMask13] = {0x003AEC, 31, 0},
293 [U_OTP_PGMask14] = {0x003AF0, 31, 0},
294 [U_OTP_PGMask15] = {0x003AF4, 31, 0},
295 [U_OTP_PGMask16] = {0x003AF8, 31, 0},
296 [U_OTP_PGMask17] = {0x003AFC, 31, 0},
297 [U_OTP_v_PubOtpOID] = {0x003B00, 15, 0},
298 [U_OTP_NDS_Reserved0] = {0x003B00, 31, 16},
299 [U_OTP_v_PubOtpVID] = {0x003B04, 15, 0},
300 [U_OTP_NDS_Reserved1] = {0x003B04, 31, 16},
301 [U_OTP_v_PubOtpGP] = {0x003B08, 15, 0},
302 [U_OTP_LockWord_GP_group_W] = {0x003B08, 31, 16},
303 [U_OTP_v_PubOtpBID] = {0x003B0C, 3, 0},
304 [U_OTP_NDS_Reserved2] = {0x003B0C, 31, 4},
305 [U_OTP_v_PubOtpRsaIndex] = {0x003B10, 3, 0},
306 [U_OTP_NDS_Reserved3] = {0x003B10, 31, 4},
307 [U_OTP_v_PubOtpMinConfVer] = {0x003B14, 7, 0},
308 [U_OTP_NDS_Reserved4] = {0x003B14, 31, 8},
309 [U_OTP_VenderConstSel] = {0x003B18, 2, 0},
310 [U_OTP_NDS_Reserved5] = {0x003B18, 31, 3},
311 [U_OTP_LockWord_NDS_Key1] = {0x003B1C, 2, 0},
312 [U_OTP_LockWord_NDS_Key2] = {0x003B1C, 5, 3},
313 [U_OTP_LockWord_NDS_Key3] = {0x003B1C, 8, 6},
314 [U_OTP_LockWord_NDS_Key4] = {0x003B1C, 11, 9},
315 [U_OTP_LockWord_NDS_Key5] = {0x003B1C, 14, 12},
316 [U_OTP_LockWord_NDS_Key6] = {0x003B1C, 17, 15},
317 [U_OTP_LockWord_NDS_Key7] = {0x003B1C, 20, 18},
318 [U_OTP_LockWord_NDS_Key8] = {0x003B1C, 23, 21},
319 [U_OTP_NDSKeyValid] = {0x003B1C, 31, 24},
320 [U_OTP_forbid_NSK_wr_sck] = {0x003B20, 7, 0},
321 [U_OTP_UseCheckSum] = {0x003B20, 15, 8},
322 [U_OTP_allow_NDSKey_BlankChk] = {0x003B20, 17, 16},
323 [U_OTP_allow_ProgFail_RuinNDSKey] = {0x003B20, 19, 18},
324 [U_OTP_allow_NDSReadKeyWait200ms] = {0x003B20, 21, 20},
325 [U_OTP_allow_ReadErrorRstOtp] = {0x003B20, 23, 22},
326 [U_OTP_allow_illegalNDSFlagChk] = {0x003B20, 27, 24},
327 [U_OTP_allow_Rst_NDS_SCFlag_ParityFail] = {0x003B20, 31, 28},
328 [U_OTP_ena_ACPUUseNSK2] = {0x003B24, 3, 0},
329 [U_OTP_ena_DBUSUseNSK2] = {0x003B24, 7, 4},
330 [U_OTP_ena_ForceOneMilSec] = {0x003B24, 11, 8},
331 [U_OTP_allow_SCCheck] = {0x003B24, 15, 12},
332 [U_OTP_ena_TestRCFreq] = {0x003B24, 19, 16},
333 [U_OTP_ena_SWRN] = {0x003B24, 23, 20},
334 [U_OTP_ena_NSKSeedPRNG] = {0x003B24, 27, 24},
335 [U_OTP_OTPWritePWDProtect] = {0x003B24, 31, 28},
336 [U_OTP_NDS_keysel] = {0x003B28, 5, 0},
337 [U_OTP_allow_NSK2_PWD_Mode] = {0x003B28, 7, 6},
338 [U_OTP_ena_EMMFilter] = {0x003B28, 11, 8},
339 [U_OTP_ena_TestGenIN] = {0x003B28, 15, 12},
340 [U_OTP_RCFreq_map] = {0x003B28, 20, 16},
341 [U_OTP_NDS_Reserved6] = {0x003B28, 31, 21},
342 [U_OTP_allow_SkipBadNVBit] = {0x003B2C, 1, 0},
343 [U_OTP_allow_NDSSC_ReadFail_BadPkt] = {0x003B2C, 3, 2},
344 [U_OTP_allow_RANDOM_keybus] = {0x003B2C, 5, 4},
345 [U_OTP_allow_RANDOM_byteacc] = {0x003B2C, 7, 6},
346 [U_OTP_allow_NDS_Rd55AA] = {0x003B2C, 9, 8},
347 [U_OTP_allow_NDS_Parity_chk] = {0x003B2C, 11, 10},
348 [U_OTP_allow_NDS_KeyRd55AA] = {0x003B2C, 13, 12},
349 [U_OTP_forbid_OTPBuiltInTest] = {0x003B2C, 15, 14},
350 [U_OTP_forbid_Kilo_ProgRepair] = {0x003B2C, 17, 16},
351 [U_OTP_NDS_Reserved7] = {0x003B2C, 31, 18},
352 [U_OTP_NVCOUNT] = {0x003B30, 1023, 0},
353 [U_OTP_NDS_SecretKey1] = {0x003BB0, 127, 0},
354 [U_OTP_NDS_SecretKey2] = {0x003BC0, 127, 0},
355 [U_OTP_NDS_SecretKey3] = {0x003BD0, 127, 0},
356 [U_OTP_NDS_SecretKey4] = {0x003BE0, 127, 0},
357 [U_OTP_NDS_SecretKey5] = {0x003BF0, 127, 0},
358 [U_OTP_NDS_SecretKey6] = {0x003C00, 127, 0},
359 [U_OTP_NDS_SecretKey7] = {0x003C10, 127, 0},
360 [U_OTP_NDS_SecretKey8] = {0x003C20, 127, 0},
361 [U_OTP_NDSKey1Chksum] = {0x003C30, 7, 0},
362 [U_OTP_NDSKey1Tag] = {0x003C30, 15, 8},
363 [U_OTP_NDSKey2Chksum] = {0x003C30, 23, 16},
364 [U_OTP_NDSKey2Tag] = {0x003C30, 31, 24},
365 [U_OTP_NDSKey3Chksum] = {0x003C34, 7, 0},
366 [U_OTP_NDSKey3Tag] = {0x003C34, 15, 8},
367 [U_OTP_NDSKey4Chksum] = {0x003C34, 23, 16},
368 [U_OTP_NDSKey4Tag] = {0x003C34, 31, 24},
369 [U_OTP_NDSKey5Chksum] = {0x003C38, 7, 0},
370 [U_OTP_NDSKey5Tag] = {0x003C38, 15, 8},
371 [U_OTP_NDSKey6Chksum] = {0x003C38, 23, 16},
372 [U_OTP_NDSKey6Tag] = {0x003C38, 31, 24},
373 [U_OTP_NDSKey7Chksum] = {0x003C3C, 7, 0},
374 [U_OTP_NDSKey7Tag] = {0x003C3C, 15, 8},
375 [U_OTP_NDSKey8Chksum] = {0x003C3C, 23, 16},
376 [U_OTP_NDSKey8Tag] = {0x003C3C, 31, 24},
377 [U_OTP_NDS_Key1_CRC] = {0x003C40, 15, 0},
378 [U_OTP_NDS_Key2_CRC] = {0x003C40, 31, 16},
379 [U_OTP_NDS_Key3_CRC] = {0x003C44, 15, 0},
380 [U_OTP_NDS_Key4_CRC] = {0x003C44, 31, 16},
381 [U_OTP_NDS_Key5_CRC] = {0x003C48, 15, 0},
382 [U_OTP_NDS_Key6_CRC] = {0x003C48, 31, 16},
383 [U_OTP_NDS_Key7_CRC] = {0x003C4C, 15, 0},
384 [U_OTP_NDS_Key8_CRC] = {0x003C4C, 31, 16},
385 [U_OTP_NDS_ESCK_Key1_obfuscation] = {0x003C50, 1, 0},
386 [U_OTP_NDS_Key1_integrity_chk] = {0x003C50, 3, 2},
387 [U_OTP_NDS_ESCK_Key2_obfuscation] = {0x003C50, 5, 4},
388 [U_OTP_NDS_Key2_integrity_chk] = {0x003C50, 7, 6},
389 [U_OTP_NDS_ESCK_Key3_obfuscation] = {0x003C50, 9, 8},
390 [U_OTP_NDS_Key3_integrity_chk] = {0x003C50, 11, 10},
391 [U_OTP_NDS_ESCK_Key4_obfuscation] = {0x003C50, 13, 12},
392 [U_OTP_NDS_Key4_integrity_chk] = {0x003C50, 15, 14},
393 [U_OTP_NDS_ESCK_Key5_obfuscation] = {0x003C50, 17, 16},
394 [U_OTP_NDS_Key5_integrity_chk] = {0x003C50, 19, 18},
395 [U_OTP_NDS_ESCK_Key6_obfuscation] = {0x003C50, 21, 20},
396 [U_OTP_NDS_Key6_integrity_chk] = {0x003C50, 23, 22},
397 [U_OTP_NDS_ESCK_Key7_obfuscation] = {0x003C50, 25, 24},
398 [U_OTP_NDS_Key7_integrity_chk] = {0x003C50, 27, 26},
399 [U_OTP_NDS_ESCK_Key8_obfuscation] = {0x003C50, 29, 28},
400 [U_OTP_NDS_Key8_integrity_chk] = {0x003C50, 31, 30},
401 [U_OTP_EJTAG_MODE_Parity_bit] = {0x003C54, 0, 0},
402 [U_OTP_I2C_MODE_Parity_bit] = {0x003C54, 1, 1},
403 [U_OTP_SCAN_MODE_Parity_bit] = {0x003C54, 2, 2},
404 [U_OTP_VenderConstSel_Parity_bit] = {0x003C54, 3, 3},
405 [U_OTP_v_PubOtpRsaIndex_Parity_bit] = {0x003C54, 4, 4},
406 [U_OTP_NDS_ESCK_Key1_obfuscation_Parity_bit] = {0x003C54, 5, 5},
407 [U_OTP_NDS_ESCK_Key2_obfuscation_Parity_bit] = {0x003C54, 6, 6},
408 [U_OTP_NDS_ESCK_Key3_obfuscation_Parity_bit] = {0x003C54, 7, 7},
409 [U_OTP_NDS_ESCK_Key4_obfuscation_Parity_bit] = {0x003C54, 8, 8},
410 [U_OTP_NDS_ESCK_Key5_obfuscation_Parity_bit] = {0x003C54, 9, 9},
411 [U_OTP_NDS_ESCK_Key6_obfuscation_Parity_bit] = {0x003C54, 10, 10},
412 [U_OTP_NDS_ESCK_Key7_obfuscation_Parity_bit] = {0x003C54, 11, 11},
413 [U_OTP_NDS_ESCK_Key8_obfuscation_Parity_bit] = {0x003C54, 12, 12},
414 [U_OTP_allow_ReadErrorRstOtp_Parity_bit] = {0x003C54, 13, 13},
415 [U_OTP_ena_ACPUUseNSK2_Parity_bit] = {0x003C54, 14, 14},
416 [U_OTP_BootMode_Parity_bit] = {0x003C54, 15, 15},
417 [U_OTP_ena_ACPU2KT_Parity_bit] = {0x003C54, 16, 16},
418 [U_OTP_ena_EMMFilter_Parity_bit] = {0x003C54, 17, 17},
419 [U_OTP_allow_NDS_Rd55AA_Parity_bit] = {0x003C54, 18, 18},
420 [U_OTP_forbid_OTPBuiltInTest_Parity_bit] = {0x003C54, 19, 19},
421 [U_OTP_allow_NSK_RNG_ROSC_Parity_bit] = {0x003C54, 20, 20},
422 [U_OTP_SecretAreaEnable_Parity_bit] = {0x003C54, 21, 21},
423 [U_OTP_forbid_SW_SPSD_Key_Parity_bit] = {0x003C54, 22, 22},
424 [U_OTP_allow_OTP_BgCRC_Parity_bit] = {0x003C54, 23, 23},
425 [U_OTP_forbid_USBSlaveMode_Parity_bit] = {0x003C54, 24, 24},
426 [U_OTP_OTPWritePWDProtect_Parity_bit] = {0x003C54, 25, 25},
427 [U_OTP_ena_NSK2_Parity_bit] = {0x003C54, 26, 26},
428 [U_OTP_NDS_Reserved8] = {0x003C54, 31, 27},
429 [U_OTP_ena_ESAAlgo_invalidate] = {0x003C58, 3, 0},
430 [U_OTP_ena_LocalAlgo_Invalidate] = {0x003C58, 7, 4},
431 [U_OTP_ContentProtEn] = {0x003C58, 11, 8},
432 [U_OTP_concurrency_configuration] = {0x003C58, 13, 12},
433 [U_OTP_allow_NSK_RNG_ROSC] = {0x003C58, 15, 14},
434 [U_OTP_nds_fc_disable] = {0x003C58, 16, 16},
435 [U_OTP_NDS_CPNR0_sel] = {0x003C58, 17, 17},
436 [U_OTP_NDS_CPNR_off] = {0x003C58, 18, 18},
437 [U_OTP_NDS_Reserved9] = {0x003C58, 31, 19},
438 [U_OTP_PM51_ST_ADDR] = {0x003C5C, 11, 0},
439 [U_OTP_PM51_ED_ADDR] = {0x003C5C, 23, 12},
440 [U_OTP_forbid_PM51ReadOTP] = {0x003C5C, 25, 24},
441 [U_OTP_forbid_PM51WriteOTP] = {0x003C5C, 27, 26},
442 [U_OTP_allow_PM51] = {0x003C5C, 29, 28},
443 [U_OTP_PM51_SW_R2] = {0x003C5C, 31, 30},
444 [U_OTP_forbid_CLK_SEED_TEST] = {0x003C60, 0, 0},
445 [U_OTP_MOBF_TOP_use_DES] = {0x003C60, 1, 1},
446 [U_OTP_OBFUSCATEVideoStream] = {0x003C60, 3, 2},
447 [U_OTP_forbid_EJTAG_Pinshare] = {0x003C60, 5, 4},
448 [U_OTP_allow_clear_sram] = {0x003C60, 6, 6},
449 [U_OTP_forbid_dft_md_sram] = {0x003C60, 7, 7},
450 [U_OTP_LINK_ISOEN2GPIO4] = {0x003C60, 8, 8},
451 [U_OTP_PM_SLEEP_WR_PROT_EN] = {0x003C60, 9, 9},
452 [U_OTP_PWR_HW_RST_MODE_EN] = {0x003C60, 10, 10},
453 [U_OTP_ISOC_TST_DIG_EN_GATE] = {0x003C60, 11, 11},
454 [U_OTP_OTHERS_Reserved0] = {0x003C60, 15, 12},
455 [U_OTP_Rsv_Feature] = {0x003C60, 31, 16},
456 [U_OTP_forbid_CA_MCM] = {0x003C64, 2, 0},
457 [U_OTP_forbid_DIAMOND_PMU] = {0x003C64, 5, 3},
458 [U_OTP_allow_force_dual_core] = {0x003C64, 6, 6},
459 [U_OTP_disable_jpi] = {0x003C64, 7, 7},
460 [U_OTP_forbid_DIG_PMU] = {0x003C64, 10, 8},
461 [U_OTP_forbid_WHOLECHIP_alive_when_NOCORE_alive] = {0x003C64, 13, 11},
462 [U_OTP_OTHERS_Reserved2] = {0x003C64, 15, 14},
463 [U_OTP_allow_CORE0_always_alive] = {0x003C64, 18, 16},
464 [U_OTP_allow_NONCORE0_default_reset] = {0x003C64, 21, 19},
465 [U_OTP_pwrgd_int_en] = {0x003C64, 22, 22},
466 [U_OTP_OTHERS_Reserved3] = {0x003C64, 31, 23},
467 [U_OTP_LOGICBIST_SCAN_OUT_CRC32] = {0x003C68, 31, 0},
468 [U_OTP_OTHERS_Reserved4] = {0x003C6C, 31, 0},
469 [U_OTP_RC_OPTION] = {0x003C70, 7, 0},
470 [U_OTP_RC_OPTION_EN] = {0x003C70, 8, 8},
471 [U_OTP_GCR_TRVBG] = {0x003C70, 14, 9},
472 [U_OTP_OTHERS_Reserved5] = {0x003C70, 15, 15},
473 [U_OTP_TEST_Status_TE] = {0x003C70, 23, 16},
474 [U_OTP_TEST_Status] = {0x003C70, 31, 24},
475 [U_OTP_ena_PVRNS2S] = {0x003C74, 3, 0},
476 [U_OTP_ena_PVRS2NS] = {0x003C74, 7, 4},
477 [U_OTP_ena_PlayBackRec0] = {0x003C74, 11, 8},
478 [U_OTP_ena_PlayBackRec1] = {0x003C74, 15, 12},
479 [U_OTP_ena_PlayBackRec2] = {0x003C74, 19, 16},
480 [U_OTP_ena_PlayBackRec3] = {0x003C74, 23, 20},
481 [U_OTP_ena_PlayBackRec4] = {0x003C74, 27, 24},
482 [U_OTP_ena_PlayBackRec5] = {0x003C74, 31, 28},
483 [U_OTP_ena_PVR_secure_protect_0] = {0x003C78, 3, 0},
484 [U_OTP_ena_PVR_secure_protect_1] = {0x003C78, 7, 4},
485 [U_OTP_ena_VQ_secure_protect_0] = {0x003C78, 11, 8},
486 [U_OTP_TSP_Reserved0] = {0x003C78, 15, 12},
487 [U_OTP_dis_TSO] = {0x003C78, 19, 16},
488 [U_OTP_ena_TS2TSO_0] = {0x003C78, 23, 20},
489 [U_OTP_ena_TS2TSO_1] = {0x003C78, 27, 24},
490 [U_OTP_ena_TSO_SecRange] = {0x003C78, 31, 28},
491 [U_OTP_CAVIDEnforcedTS0] = {0x003C7C, 5, 0},
492 [U_OTP_CAVIDEnforcedTS1] = {0x003C7C, 11, 6},
493 [U_OTP_CAVIDEnforcedTS2] = {0x003C7C, 17, 12},
494 [U_OTP_CAVIDEnforcedTS3] = {0x003C7C, 23, 18},
495 [U_OTP_CAVIDEnforcedTS4] = {0x003C7C, 29, 24},
496 [U_OTP_TSP_Reserved1] = {0x003C7C, 31, 30},
497 [U_OTP_CAVIDEnforcedTS5] = {0x003C80, 5, 0},
498 [U_OTP_ForbidAVtoSec] = {0x003C80, 6, 6},
499 [U_OTP_TSP_Reserved2] = {0x003C80, 7, 7},
500 [U_OTP_dis_clear_stream_to_PVR] = {0x003C80, 11, 8},
501 [U_OTP_forbid_SW_SPSD_Key] = {0x003C80, 13, 12},
502 [U_OTP_forbid_KL_SPSD_Key] = {0x003C80, 15, 14},
503 [U_OTP_allow_TSPCPUCodeProt] = {0x003C80, 17, 16},
504 [U_OTP_TSP_Reserved3] = {0x003C80, 31, 18},
505 [U_OTP_ena_KeyLadder_0_lock] = {0x003C84, 3, 0},
506 [U_OTP_ena_KeyLadder_1_lock] = {0x003C84, 7, 4},
507 [U_OTP_ena_NSK2_lock] = {0x003C84, 11, 8},
508 [U_OTP_ena_CERT_IP_lock] = {0x003C84, 15, 12},
509 [U_OTP_ena_DMA_lock] = {0x003C84, 19, 16},
510 [U_OTP_ena_SCPU_lock] = {0x003C84, 23, 20},
511 [U_OTP_Dlock_Reserved0] = {0x003C84, 31, 24},
512 [U_OTP_ena_ACPU2KT_lock] = {0x003C88, 3, 0},
513 [U_OTP_ena_NSK2KT_lock] = {0x003C88, 7, 4},
514 [U_OTP_ena_KL2KT_lock] = {0x003C88, 11, 8},
515 [U_OTP_ena_SCPU2KT_lock] = {0x003C88, 15, 12},
516 [U_OTP_ena_ACPU2DMA_lock] = {0x003C88, 19, 16},
517 [U_OTP_ena_DMA_DESBasedCipher_lock] = {0x003C88, 23, 20},
518 [U_OTP_Dlock_Reserved1] = {0x003C88, 31, 24},
519 [U_OTP_ena_LSACPCM_lock] = {0x003C8C, 3, 0},
520 [U_OTP_ena_AESBasedCipher_lock] = {0x003C8C, 7, 4},
521 [U_OTP_ena_DESBasedCipher_lock] = {0x003C8C, 11, 8},
522 [U_OTP_ena_3DESBasedCipher_lock] = {0x003C8C, 15, 12},
523 [U_OTP_ena_Multi2BasedCipher_lock] = {0x003C8C, 19, 16},
524 [U_OTP_ena_DVBCSA2ConfCipher_lock] = {0x003C8C, 23, 20},
525 [U_OTP_ena_DVBCSA2Cipher_lock] = {0x003C8C, 27, 24},
526 [U_OTP_ena_DVBCSA3BasedCipher_lock] = {0x003C8C, 31, 28},
527 [U_OTP_dis_kl0_hostkey_lock] = {0x003C90, 3, 0},
528 [U_OTP_dis_kl1_hostkey_lock] = {0x003C90, 7, 4},
529 [U_OTP_NDSKeyValid_lock] = {0x003C90, 11, 8},
530 [U_OTP_RC_OPTION_lock] = {0x003C90, 15, 12},
531 [U_OTP_Dlock_Reserved2] = {0x003C90, 31, 16},
532 [U_OTP_Dlock_Reserved3] = {0x003C94, 31, 0},
533 [U_OTP_LockWord_CA_reserved0_W] = {0x003C98, 1, 0},
534 [U_OTP_LockWord_CA_reserved1_W] = {0x003C98, 3, 2},
535 [U_OTP_LockWord_CA_reserved2_W] = {0x003C98, 5, 4},
536 [U_OTP_LockWord_CA_reserved3_W] = {0x003C98, 7, 6},
537 [U_OTP_LockWord_CA_reserved4_W] = {0x003C98, 9, 8},
538 [U_OTP_LockWord_CA_reserved5_W] = {0x003C98, 11, 10},
539 [U_OTP_LockWord_CA_reserved6_W] = {0x003C98, 13, 12},
540 [U_OTP_LockWord_CA_reserved7_W] = {0x003C98, 15, 14},
541 [U_OTP_LockWord_CA_reserved8_W] = {0x003C98, 17, 16},
542 [U_OTP_LockWord_CA_reserved9_W] = {0x003C98, 19, 18},
543 [U_OTP_LockWord_CA_reserved10_W] = {0x003C98, 21, 20},
544 [U_OTP_LockWord_CA_reserved11_W] = {0x003C98, 23, 22},
545 [U_OTP_LockWord_CA_reserved12_W] = {0x003C98, 25, 24},
546 [U_OTP_LockWord_CA_reserved13_W] = {0x003C98, 27, 26},
547 [U_OTP_LockWord_CA_reserved14_W] = {0x003C98, 29, 28},
548 [U_OTP_LockWord_CA_reserved15_W] = {0x003C98, 31, 30},
549 [U_OTP_LockWord_RSA_0_W] = {0x003C9C, 1, 0},
550 [U_OTP_LockWord_RSA_1_W] = {0x003C9C, 3, 2},
551 [U_OTP_LockWord_RSA_CTRL_W] = {0x003C9C, 5, 4},
552 [U_OTP_LockWord_IXSC_Config_W] = {0x003C9C, 7, 6},
553 [U_OTP_LockWord_v_PubOtpOID_W] = {0x003C9C, 9, 8},
554 [U_OTP_LockWord_v_PubOtpVID_W] = {0x003C9C, 11, 10},
555 [U_OTP_LockWord_v_PubOtpBID_W] = {0x003C9C, 13, 12},
556 [U_OTP_LockWord_v_PubOtpRsaIndex_W] = {0x003C9C, 15, 14},
557 [U_OTP_LockWord_v_PubOtpMinConfVer_W] = {0x003C9C, 17, 16},
558 [U_OTP_LockWord_VenderConstSel_W] = {0x003C9C, 19, 18},
559 [U_OTP_LockWord_NDS_info_W] = {0x003C9C, 21, 20},
560 [U_OTP_LockWord_PM51_W] = {0x003C9C, 23, 22},
561 [U_OTP_LockWord_OTHERS_W] = {0x003C9C, 25, 24},
562 [U_OTP_LockWord_Reserved0] = {0x003C9C, 31, 26},
563 [U_OTP_LockWord_NOCS3_MEM0_W] = {0x003CA0, 1, 0},
564 [U_OTP_LockWord_NOCS3_MEM1_W] = {0x003CA0, 3, 2},
565 [U_OTP_LockWord_NOCS3_MEM2_W] = {0x003CA0, 5, 4},
566 [U_OTP_LockWord_NOCS3_MEM3_W] = {0x003CA0, 7, 6},
567 [U_OTP_LockWord_MSID_W] = {0x003CA0, 9, 8},
568 [U_OTP_LockWord_CFG_STB_CA_SN_W] = {0x003CA0, 11, 10},
569 [U_OTP_LockWord_TSP_W] = {0x003CA0, 13, 12},
570 [U_OTP_LockWord_PGMask_W] = {0x003CA0, 15, 14},
571 [U_OTP_LockWord_ClkDet_Para_W] = {0x003CA0, 17, 16},
572 [U_OTP_LockWord_OTP_CTRL_W] = {0x003CA0, 19, 18},
573 [U_OTP_LockWord_CPU_bank_W] = {0x003CA0, 21, 20},
574 [U_OTP_LockWord_trimming_W] = {0x003CA0, 23, 22},
575 [U_OTP_LockWord_BOND0_W] = {0x003CA0, 25, 24},
576 [U_OTP_LockWord_BOND_Reserved_W] = {0x003CA0, 27, 26},
577 [U_OTP_LockWord_Reserved1] = {0x003CA0, 31, 28},
578 [U_OTP_LockWord_LOT_INFO_W] = {0x003CA4, 1, 0},
579 [U_OTP_LockWord_CA_Enable_W] = {0x003CA4, 3, 2},
580 [U_OTP_LockWord_KL_bank_W] = {0x003CA4, 5, 4},
581 [U_OTP_LockWord_KT_bank_W] = {0x003CA4, 7, 6},
582 [U_OTP_LockWord_DMA_bank_W] = {0x003CA4, 9, 8},
583 [U_OTP_LockWord_TSCE_W] = {0x003CA4, 11, 10},
584 [U_OTP_LockWord_HDCP_KEY_W] = {0x003CA4, 13, 12},
585 [U_OTP_LockWord_Multi2SysKey_W] = {0x003CA4, 15, 14},
586 [U_OTP_LockWord_CAV_Key1_W] = {0x003CA4, 17, 16},
587 [U_OTP_LockWord_CAV_Key2_W] = {0x003CA4, 19, 18},
588 [U_OTP_LockWord_CAV_Key3_W] = {0x003CA4, 21, 20},
589 [U_OTP_LockWord_CAV_Key4_W] = {0x003CA4, 23, 22},
590 [U_OTP_LockWord_CAV_Key5_W] = {0x003CA4, 25, 24},
591 [U_OTP_LockWord_CAV_Key6_W] = {0x003CA4, 27, 26},
592 [U_OTP_LockWord_CAV_Key7_W] = {0x003CA4, 29, 28},
593 [U_OTP_LockWord_CAV_Key8_W] = {0x003CA4, 31, 30},
594 [U_OTP_LockWord_CAVID_W] = {0x003CA8, 1, 0},
595 [U_OTP_LockWord_CAV_KP1_W] = {0x003CA8, 3, 2},
596 [U_OTP_LockWord_CAV_KP2_W] = {0x003CA8, 5, 4},
597 [U_OTP_LockWord_CAV_KP3_W] = {0x003CA8, 7, 6},
598 [U_OTP_LockWord_CAV_KP4_W] = {0x003CA8, 9, 8},
599 [U_OTP_LockWord_CAV_KP5_W] = {0x003CA8, 11, 10},
600 [U_OTP_LockWord_CAV_KP6_W] = {0x003CA8, 13, 12},
601 [U_OTP_LockWord_CAV_KP7_W] = {0x003CA8, 15, 14},
602 [U_OTP_LockWord_CAV_KP8_W] = {0x003CA8, 17, 16},
603 [U_OTP_LockWord_CAV_KP9_W] = {0x003CA8, 19, 18},
604 [U_OTP_LockWord_CAV_KP10_W] = {0x003CA8, 21, 20},
605 [U_OTP_LockWord_CAV_KP11_W] = {0x003CA8, 23, 22},
606 [U_OTP_LockWord_CAV_KP12_W] = {0x003CA8, 25, 24},
607 [U_OTP_LockWord_CAV_KP13_W] = {0x003CA8, 27, 26},
608 [U_OTP_LockWord_CAV_KP14_W] = {0x003CA8, 29, 28},
609 [U_OTP_LockWord_CAV_KP15_W] = {0x003CA8, 31, 30},
610 [U_OTP_LockWord_PubOTPUniqueID1_W] = {0x003CAC, 1, 0},
611 [U_OTP_LockWord_PubOTPUniqueID2_W] = {0x003CAC, 3, 2},
612 [U_OTP_LockWord_PubOTPUniqueID3_W] = {0x003CAC, 5, 4},
613 [U_OTP_LockWord_PubOTPUniqueID4_W] = {0x003CAC, 7, 6},
614 [U_OTP_LockWord_AES_MOD_MASK_W] = {0x003CAC, 9, 8},
615 [U_OTP_LockWord_ACPU_Property_W] = {0x003CAC, 11, 10},
616 [U_OTP_LockWord_SCPU_Property_W] = {0x003CAC, 13, 12},
617 [U_OTP_LockWord_CA_PWD_W] = {0x003CAC, 15, 14},
618 [U_OTP_LockWord_CA_PWD_CTRL_W] = {0x003CAC, 17, 16},
619 [U_OTP_LockWord_VtrackData_W] = {0x003CAC, 19, 18},
620 [U_OTP_LockWord_FAKE_W] = {0x003CAC, 21, 20},
621 [U_OTP_LockWord_SW0_W] = {0x003CAC, 23, 22},
622 [U_OTP_LockWord_Reserved2] = {0x003CAC, 31, 26},
623 [U_OTP_LockWord_0000_0511_W] = {0x003CB0, 1, 0},
624 [U_OTP_LockWord_0512_1023_W] = {0x003CB0, 3, 2},
625 [U_OTP_LockWord_1024_1535_W] = {0x003CB0, 5, 4},
626 [U_OTP_LockWord_1536_2047_W] = {0x003CB0, 7, 6},
627 [U_OTP_LockWord_2048_2559_W] = {0x003CB0, 9, 8},
628 [U_OTP_LockWord_2560_3071_W] = {0x003CB0, 11, 10},
629 [U_OTP_LockWord_3072_3391_W] = {0x003CB0, 13, 12},
630 [U_OTP_LockWord_Chip_Extension_ID] = {0x003CB0, 15, 14},
631 [U_OTP_LockWord_Reserved3] = {0x003CB0, 31, 16},
632 [U_OTP_LockWord_CAV_Key1_R] = {0x003CB4, 1, 0},
633 [U_OTP_LockWord_CAV_Key2_R] = {0x003CB4, 3, 2},
634 [U_OTP_LockWord_CAV_Key3_R] = {0x003CB4, 5, 4},
635 [U_OTP_LockWord_CAV_Key4_R] = {0x003CB4, 7, 6},
636 [U_OTP_LockWord_CAV_Key5_R] = {0x003CB4, 9, 8},
637 [U_OTP_LockWord_CAV_Key6_R] = {0x003CB4, 11, 10},
638 [U_OTP_LockWord_CAV_Key7_R] = {0x003CB4, 13, 12},
639 [U_OTP_LockWord_CAV_Key8_R] = {0x003CB4, 15, 14},
640 [U_OTP_LockWord_RSA_0_R] = {0x003CB4, 17, 16},
641 [U_OTP_LockWord_RSA_1_R] = {0x003CB4, 19, 18},
642 [U_OTP_LockWord_HDCP_KEY_R] = {0x003CB4, 21, 20},
643 [U_OTP_LockWord_Multi2SysKey_R] = {0x003CB4, 23, 22},
644 [U_OTP_LockWord_AES_MOD_MASK_R] = {0x003CB4, 25, 24},
645 [U_OTP_LockWord_VtrackData_R] = {0x003CB4, 27, 26},
646 [U_OTP_LockWord_CA_PWD_R] = {0x003CB4, 29, 28},
647 [U_OTP_LockWord_Reserved4] = {0x003CB4, 31, 30},
648 [U_OTP_ClkDet_Para] = {0x003CB8, 63, 0},
649 [U_OTP_forbid_ACPUWriteOTP] = {0x003CC0, 1, 0},
650 [U_OTP_forbid_ACPUReadOTP] = {0x003CC0, 3, 2},
651 [U_OTP_forbid_SCPUWriteOTP] = {0x003CC0, 5, 4},
652 [U_OTP_forbid_SCPUReadOTP] = {0x003CC0, 7, 6},
653 [U_OTP_forbid_DBBUSWriteOTP] = {0x003CC0, 9, 8},
654 [U_OTP_forbid_DBBUSReadOTP] = {0x003CC0, 11, 10},
655 [U_OTP_allow_RANDOM] = {0x003CC0, 13, 12},
656 [U_OTP_allow_NOISE_Rd] = {0x003CC0, 15, 14},
657 [U_OTP_allow_OTP_BgCRC] = {0x003CC0, 17, 16},
658 [U_OTP_allow_SKIP_0] = {0x003CC0, 19, 18},
659 [U_OTP_allow_SKIP_1] = {0x003CC0, 21, 20},
660 [U_OTP_allow_Mask_AES] = {0x003CC0, 23, 22},
661 [U_OTP_ena_Mstar_Wrapper] = {0x003CC0, 25, 24},
662 [U_OTP_CTRL_Reserved0] = {0x003CC0, 31, 26},
663 [U_OTP_allow_XOR_ROMCODE] = {0x003CC4, 6, 0},
664 [U_OTP_allow_XOR_FIX] = {0x003CC4, 7, 7},
665 [U_OTP_allow_PWD_OTP_prog] = {0x003CC4, 9, 8},
666 [U_OTP_CTRL_Reserved1] = {0x003CC4, 31, 10},
667 [U_OTP_SBoot] = {0x003CC8, 3, 0},
668 [U_OTP_SecretAreaEnable] = {0x003CC8, 7, 4},
669 [U_OTP_forbid_TestInOut] = {0x003CC8, 9, 8},
670 [U_OTP_allow_FlashProtect] = {0x003CC8, 11, 10},
671 [U_OTP_PERSO_done] = {0x003CC8, 13, 12},
672 [U_OTP_CERT_PERSO_done] = {0x003CC8, 15, 14},
673 [U_OTP_DBUG_Reserved0] = {0x003CC8, 31, 16},
674 [U_OTP_SCAN_MODE] = {0x003CCC, 8, 0},
675 [U_OTP_DBUG_Reserved1] = {0x003CCC, 9, 9},
676 [U_OTP_MBIST_MODE] = {0x003CCC, 15, 10},
677 [U_OTP_I2C_MODE] = {0x003CCC, 21, 16},
678 [U_OTP_DBUG_Reserved2] = {0x003CCC, 25, 22},
679 [U_OTP_EJTAG_MODE] = {0x003CCC, 31, 26},
680 [U_OTP_RMA_MODE] = {0x003CD0, 5, 0},
681 [U_OTP_LicRework] = {0x003CD0, 7, 6},
682 [U_OTP_forbid_USBSlaveMode] = {0x003CD0, 11, 8},
683 [U_OTP_allow_DRAM_MOBF] = {0x003CD0, 13, 12},
684 [U_OTP_allow_DRAMOBF_4ROUND] = {0x003CD0, 15, 14},
685 [U_OTP_ena_DRAMOBF_NS_MASK_ADDR] = {0x003CD0, 17, 16},
686 [U_OTP_forbid_clk_otp_sel] = {0x003CD0, 20, 18},
687 [U_OTP_forbid_acpu_access_sec_bridge] = {0x003CD0, 23, 21},
688 [U_OTP_forbid_dbbus_access_sec_bridge] = {0x003CD0, 26, 24},
689 [U_OTP_XPM_State] = {0x003CD0, 29, 27},
690 [U_OTP_DBUG_Reserved3] = {0x003CD0, 31, 30},
691 [U_OTP_DeactiveDRAMBoot] = {0x003CD4, 3, 0},
692 [U_OTP_ACPU_Reserved0] = {0x003CD4, 7, 4},
693 [U_OTP_BootMode] = {0x003CD4, 13, 8},
694 [U_OTP_forbid_BCKGND_CHK] = {0x003CD4, 15, 14},
695 [U_OTP_SCPUBootMode] = {0x003CD4, 21, 16},
696 [U_OTP_ACPU_Reserved1] = {0x003CD4, 23, 22},
697 [U_OTP_PM_MCU_RST_MOD] = {0x003CD4, 26, 24},
698 [U_OTP_boot_host_sel] = {0x003CD4, 29, 27},
699 [U_OTP_ACPU_Reserved2] = {0x003CD4, 31, 30},
700 [U_OTP_ACPU_Reserved3] = {0x003CD8, 11, 0},
701 [U_OTP_PostMskAreaRangeU] = {0x003CD8, 23, 12},
702 [U_OTP_ACPUasHost] = {0x003CD8, 26, 24},
703 [U_OTP_BONDING] = {0x003CD8, 28, 27},
704 [U_OTP_NON_BLANK] = {0x003CD8, 29, 29},
705 [U_OTP_ACPU_Reserved4] = {0x003CD8, 31, 30},
706 [U_OTP_PE_LOT_INFO] = {0x003CDC, 47, 0},
707 [U_OTP_BootDevice] = {0x003CDC, 55, 48},
708 [U_OTP_MAX_RDNTBLK] = {0x003CDC, 61, 56},
709 [U_OTP_forbid_STR] = {0x003CDC, 63, 62},
710 [U_OTP_Bootcode_project] = {0x003CE4, 7, 0},
711 [U_OTP_Bootcode_subversion] = {0x003CE4, 15, 8},
712 [U_OTP_Bootcode_version] = {0x003CE4, 31, 16},
713 [U_OTP_Analog_Usage] = {0x003CE8, 63, 0},
714 [U_OTP_Analog_Usage2] = {0x003CF0, 95, 0},
715 [U_OTP_trim_dac] = {0x003CFC, 125, 0},
716 [U_OTP_Trim_Reserved0] = {0x003CFC, 127, 126},
717 [U_OTP_BOND0] = {0x003D0C, 95, 0},
718 [U_OTP_BOND_Reserved] = {0x003D18, 95, 0},
719 [U_OTP_ena_KeyLadder_0] = {0x003D24, 3, 0},
720 [U_OTP_ena_KeyLadder_1] = {0x003D24, 7, 4},
721 [U_OTP_ena_NSK2] = {0x003D24, 11, 8},
722 [U_OTP_ena_CERT_IP] = {0x003D24, 13, 12},
723 [U_OTP_ena_DMA] = {0x003D24, 15, 14},
724 [U_OTP_ena_SCPU] = {0x003D24, 19, 16},
725 [U_OTP_CA_EN_Reserved0] = {0x003D24, 31, 20},
726 [U_OTP_allow_IXSC] = {0x003D28, 3, 0},
727 [U_OTP_forbid_IXSC] = {0x003D28, 7, 4},
728 [U_OTP_forbid_PAVOSC] = {0x003D28, 9, 8},
729 [U_OTP_cfDeactiveFuse] = {0x003D28, 10, 10},
730 [U_OTP_SOC_UID_SEL] = {0x003D28, 12, 11},
731 [U_OTP_CA_EN_Reserved2] = {0x003D28, 31, 13},
732 [U_OTP_dis_kl0_hostkey] = {0x003D2C, 1, 0},
733 [U_OTP_dis_kl1_hostkey] = {0x003D2C, 3, 2},
734 [U_OTP_dis_kl0_hostkey_property] = {0x003D2C, 5, 4},
735 [U_OTP_dis_kl1_hostkey_property] = {0x003D2C, 7, 6},
736 [U_OTP_kl_protect0_mode] = {0x003D2C, 9, 8},
737 [U_OTP_kl_protect1_mode] = {0x003D2C, 11, 10},
738 [U_OTP_kl_protect2_mode] = {0x003D2C, 13, 12},
739 [U_OTP_kl_protect3_mode] = {0x003D2C, 15, 14},
740 [U_OTP_dis_kl_protect0] = {0x003D2C, 17, 16},
741 [U_OTP_dis_kl_protect1] = {0x003D2C, 19, 18},
742 [U_OTP_dis_kl_protect2] = {0x003D2C, 21, 20},
743 [U_OTP_dis_kl_protect3] = {0x003D2C, 23, 22},
744 [U_OTP_dis_kl_protect4] = {0x003D2C, 25, 24},
745 [U_OTP_kl_TA_LUT0_mode] = {0x003D2C, 27, 26},
746 [U_OTP_kl_TA_LUT1_mode] = {0x003D2C, 29, 28},
747 [U_OTP_ena_kl_StopClkChk] = {0x003D2C, 31, 30},
748 [U_OTP_KDF_secret_mask] = {0x003D30, 127, 0},
749 [U_OTP_IMLB_ROTATION] = {0x003D40, 15, 0},
750 [U_OTP_IrdetoTweakedCSAv3] = {0x003D40, 17, 16},
751 [U_OTP_allow_SPSSPDKeyShuffle] = {0x003D40, 21, 18},
752 [U_OTP_kl_BISS_MODE] = {0x003D40, 23, 22},
753 [U_OTP_ena_kl_xor_func] = {0x003D40, 25, 24},
754 [U_OTP_KL_Reserved2] = {0x003D40, 31, 26},
755 [U_OTP_ena_ACPU2KT] = {0x003D44, 3, 0},
756 [U_OTP_ena_NSK2KT] = {0x003D44, 7, 4},
757 [U_OTP_ena_KL2KT] = {0x003D44, 11, 8},
758 [U_OTP_ena_SCPU2KT] = {0x003D44, 15, 12},
759 [U_OTP_ena_ACPUWrNSKKey2KT] = {0x003D44, 19, 16},
760 [U_OTP_ena_ACPUWrCFBKey2KT] = {0x003D44, 23, 20},
761 [U_OTP_ena_NSKCW2CryptoDMA] = {0x003D44, 27, 24},
762 [U_OTP_ena_ACPU2LSA] = {0x003D44, 31, 28},
763 [U_OTP_BISS_MODE] = {0x003D48, 3, 0},
764 [U_OTP_BISS_SUBMODE] = {0x003D48, 5, 4},
765 [U_OTP_KT_Reserved0] = {0x003D48, 31, 6},
766 [U_OTP_ena_ACPU2DMA] = {0x003D4C, 3, 0},
767 [U_OTP_ena_DMA_DESBasedCipher] = {0x003D4C, 7, 4},
768 [U_OTP_ena_AESMAC_MaxRate] = {0x003D4C, 9, 8},
769 [U_OTP_allow_DMAtDES2KeyEQChk] = {0x003D4C, 12, 10},
770 [U_OTP_DMA_Reserved0] = {0x003D4C, 13, 13},
771 [U_OTP_ena_DMA_ClearKeySlot ] = {0x003D4C, 15, 14},
772 [U_OTP_dis_DMA_mask_engine] = {0x003D4C, 17, 16},
773 [U_OTP_DMA_Reserved1] = {0x003D4C, 31, 18},
774 [U_OTP_ena_LSACPCM] = {0x003D50, 3, 0},
775 [U_OTP_ena_AESBasedCipher] = {0x003D50, 7, 4},
776 [U_OTP_ena_DESBasedCipher] = {0x003D50, 11, 8},
777 [U_OTP_ena_3DESBasedCipher] = {0x003D50, 15, 12},
778 [U_OTP_ena_Multi2BasedCipher] = {0x003D50, 19, 16},
779 [U_OTP_ena_DVBCSA2ConfCipher] = {0x003D50, 23, 20},
780 [U_OTP_ena_DVBCSA2Cipher] = {0x003D50, 27, 24},
781 [U_OTP_ena_DVBCSA3BasedCipher] = {0x003D50, 31, 28},
782 [U_OTP_Ch_SwitchComb] = {0x003D54, 63, 0},
783 [U_OTP_ena_LSAD_MDI] = {0x003D5C, 3, 0},
784 [U_OTP_ena_LSAD_MDD] = {0x003D5C, 7, 4},
785 [U_OTP_ena_LSAD_CIPLUS_AES] = {0x003D5C, 11, 8},
786 [U_OTP_ena_LSAD_AES_ECB_CLEAR] = {0x003D5C, 15, 12},
787 [U_OTP_ena_LSAD_SCTE41_SCTE52_DES] = {0x003D5C, 19, 16},
788 [U_OTP_TSCE_Reserved0] = {0x003D5C, 31, 20},
789 [U_OTP_ena_ESA_CIPLUS_AES] = {0x003D60, 3, 0},
790 [U_OTP_ena_ESA_CIPLUS_DES] = {0x003D60, 7, 4},
791 [U_OTP_ena_ESA_SCTE52_DES] = {0x003D60, 11, 8},
792 [U_OTP_ena_ESA_tDES_CBC_CLEAR] = {0x003D60, 15, 12},
793 [U_OTP_TSCE_Reserved1] = {0x003D60, 31, 16},
794 [U_OTP_ena_LSAS_MDI] = {0x003D64, 3, 0},
795 [U_OTP_ena_LSAS_MDD] = {0x003D64, 7, 4},
796 [U_OTP_ena_LSAS_CIPLUS_AES] = {0x003D64, 11, 8},
797 [U_OTP_ena_LSAS_AES_ECB_CLEAR] = {0x003D64, 15, 12},
798 [U_OTP_ena_LSAS_SCTE41_SCTE52_DES] = {0x003D64, 19, 16},
799 [U_OTP_TSCE_Reserved2] = {0x003D64, 31, 20},
800 [U_OTP_ena_DRMAreaEncrypt] = {0x003D68, 3, 0},
801 [U_OTP_ena_ReviewFailPkt] = {0x003D68, 7, 4},
802 [U_OTP_dis_NonSecRangeEncrypt] = {0x003D68, 11, 8},
803 [U_OTP_TSCE_Reserved3] = {0x003D68, 31, 12},
804 [U_OTP_ena_CA_PVR_secure_protect_0] = {0x003D6C, 3, 0},
805 [U_OTP_ena_CA_PVR_secure_protect_1] = {0x003D6C, 7, 4},
806 [U_OTP_ena_CA_PVR_secure_protect_2] = {0x003D6C, 11, 8},
807 [U_OTP_ena_CA_PVR_secure_protect_3] = {0x003D6C, 15, 12},
808 [U_OTP_ena_LowerPathRec] = {0x003D6C, 19, 16},
809 [U_OTP_ena_SWMulti2SysKey] = {0x003D6C, 23, 20},
810 [U_OTP_TSCE_Reserved4] = {0x003D6C, 31, 24},
811 [U_OTP_HDCP_KEY] = {0x003D70, 55, 0},
812 [U_OTP_HDCP_Reserved0] = {0x003D70, 7, 0},
813 [U_OTP_Multi2SysKey] = {0x003D78, 255, 0},
814 [U_OTP_AES_MOD_MASK] = {0x003D98, 127, 0},
815 [U_OTP_v_pubOtpUniqueID1] = {0x003DA8, 63, 0},
816 [U_OTP_v_pubOtpUniqueID2] = {0x003DB0, 63, 0},
817 [U_OTP_v_pubOtpUniqueID3] = {0x003DB8, 63, 0},
818 [U_OTP_v_pubOtpUniqueID4] = {0x003DC0, 63, 0},
819 [U_OTP_CAV_ESCK_KeyValid] = {0x003DC8, 7, 0},
820 [U_OTP_CAV_Reserved0] = {0x003DC8, 15, 8},
821 [U_OTP_CAV_SCK_KeyValid] = {0x003DC8, 31, 16},
822 [U_OTP_CAV_Reserved1] = {0x003DCC, 31, 0},
823 [U_OTP_CAV_Key1_SCK_mapping] = {0x003DD0, 15, 0},
824 [U_OTP_CAV_Key1_integrity_chk] = {0x003DD0, 17, 16},
825 [U_OTP_CAV_Key1_allow_ChkNum] = {0x003DD0, 19, 18},
826 [U_OTP_CAV_Key1_obfuscation] = {0x003DD0, 21, 20},
827 [U_OTP_CAV_Key1_IdSel] = {0x003DD0, 23, 22},
828 [U_OTP_CAV_Key1_KeySel] = {0x003DD0, 29, 24},
829 [U_OTP_CAV_Key1_reserved] = {0x003DD0, 31, 30},
830 [U_OTP_CAV_Key1_ChkNum_Gold] = {0x003DD4, 31, 0},
831 [U_OTP_CAV_Key2_SCK_mapping] = {0x003DD8, 15, 0},
832 [U_OTP_CAV_Key2_integrity_chk] = {0x003DD8, 17, 16},
833 [U_OTP_CAV_Key2_allow_ChkNum] = {0x003DD8, 19, 18},
834 [U_OTP_CAV_Key2_obfuscation] = {0x003DD8, 21, 20},
835 [U_OTP_CAV_Key2_IdSel] = {0x003DD8, 23, 22},
836 [U_OTP_CAV_Key2_KeySel] = {0x003DD8, 29, 24},
837 [U_OTP_CAV_Key2_reserved] = {0x003DD8, 31, 30},
838 [U_OTP_CAV_Key2_ChkNum_Gold] = {0x003DDC, 31, 0},
839 [U_OTP_CAV_Key3_SCK_mapping] = {0x003DE0, 15, 0},
840 [U_OTP_CAV_Key3_integrity_chk] = {0x003DE0, 17, 16},
841 [U_OTP_CAV_Key3_allow_ChkNum] = {0x003DE0, 19, 18},
842 [U_OTP_CAV_Key3_obfuscation] = {0x003DE0, 21, 20},
843 [U_OTP_CAV_Key3_IdSel] = {0x003DE0, 23, 22},
844 [U_OTP_CAV_Key3_KeySel] = {0x003DE0, 29, 24},
845 [U_OTP_CAV_Key3_reserved] = {0x003DE0, 31, 30},
846 [U_OTP_CAV_Key3_ChkNum_Gold] = {0x003DE4, 31, 0},
847 [U_OTP_CAV_Key4_SCK_mapping] = {0x003DE8, 15, 0},
848 [U_OTP_CAV_Key4_integrity_chk] = {0x003DE8, 17, 16},
849 [U_OTP_CAV_Key4_allow_ChkNum] = {0x003DE8, 19, 18},
850 [U_OTP_CAV_Key4_obfuscation] = {0x003DE8, 21, 20},
851 [U_OTP_CAV_Key4_IdSel] = {0x003DE8, 23, 22},
852 [U_OTP_CAV_Key4_KeySel] = {0x003DE8, 29, 24},
853 [U_OTP_CAV_Key4_reserved] = {0x003DE8, 31, 30},
854 [U_OTP_CAV_Key4_ChkNum_Gold] = {0x003DEC, 31, 0},
855 [U_OTP_CAV_Key5_SCK_mapping] = {0x003DF0, 15, 0},
856 [U_OTP_CAV_Key5_integrity_chk] = {0x003DF0, 17, 16},
857 [U_OTP_CAV_Key5_allow_ChkNum] = {0x003DF0, 19, 18},
858 [U_OTP_CAV_Key5_obfuscation] = {0x003DF0, 21, 20},
859 [U_OTP_CAV_Key5_IdSel] = {0x003DF0, 23, 22},
860 [U_OTP_CAV_Key5_KeySel] = {0x003DF0, 29, 24},
861 [U_OTP_CAV_Key5_reserved] = {0x003DF0, 31, 30},
862 [U_OTP_CAV_Key5_ChkNum_Gold] = {0x003DF4, 31, 0},
863 [U_OTP_CAV_Key6_SCK_mapping] = {0x003DF8, 15, 0},
864 [U_OTP_CAV_Key6_integrity_chk] = {0x003DF8, 17, 16},
865 [U_OTP_CAV_Key6_allow_ChkNum] = {0x003DF8, 19, 18},
866 [U_OTP_CAV_Key6_obfuscation] = {0x003DF8, 21, 20},
867 [U_OTP_CAV_Key6_IdSel] = {0x003DF8, 23, 22},
868 [U_OTP_CAV_Key6_KeySel] = {0x003DF8, 29, 24},
869 [U_OTP_CAV_Key6_reserved] = {0x003DF8, 31, 30},
870 [U_OTP_CAV_Key6_ChkNum_Gold] = {0x003DFC, 31, 0},
871 [U_OTP_CAV_Key7_SCK_mapping] = {0x003E00, 15, 0},
872 [U_OTP_CAV_Key7_integrity_chk] = {0x003E00, 17, 16},
873 [U_OTP_CAV_Key7_allow_ChkNum] = {0x003E00, 19, 18},
874 [U_OTP_CAV_Key7_obfuscation] = {0x003E00, 21, 20},
875 [U_OTP_CAV_Key7_IdSel] = {0x003E00, 23, 22},
876 [U_OTP_CAV_Key7_KeySel] = {0x003E00, 29, 24},
877 [U_OTP_CAV_Key7_reserved] = {0x003E00, 31, 30},
878 [U_OTP_CAV_Key7_ChkNum_Gold] = {0x003E04, 31, 0},
879 [U_OTP_CAV_Key8_SCK_mapping] = {0x003E08, 15, 0},
880 [U_OTP_CAV_Key8_integrity_chk] = {0x003E08, 17, 16},
881 [U_OTP_CAV_Key8_allow_ChkNum] = {0x003E08, 19, 18},
882 [U_OTP_CAV_Key8_obfuscation] = {0x003E08, 21, 20},
883 [U_OTP_CAV_Key8_IdSel] = {0x003E08, 23, 22},
884 [U_OTP_CAV_Key8_KeySel] = {0x003E08, 29, 24},
885 [U_OTP_CAV_Key8_reserved] = {0x003E08, 31, 30},
886 [U_OTP_CAV_Key8_ChkNum_Gold] = {0x003E0C, 31, 0},
887 [U_OTP_ACPU_Property] = {0x003E10, 127, 0},
888 [U_OTP_SCPU_Property] = {0x003E20, 127, 0},
889 [U_OTP_CAV_Key1_Property] = {0x003E30, 127, 0},
890 [U_OTP_CAV_Key2_Property] = {0x003E40, 127, 0},
891 [U_OTP_CAV_Key3_Property] = {0x003E50, 127, 0},
892 [U_OTP_CAV_Key4_Property] = {0x003E60, 127, 0},
893 [U_OTP_CAV_Key5_Property] = {0x003E70, 127, 0},
894 [U_OTP_CAV_Key6_Property] = {0x003E80, 127, 0},
895 [U_OTP_CAV_Key7_Property] = {0x003E90, 127, 0},
896 [U_OTP_CAV_Key8_Property] = {0x003EA0, 127, 0},
897 [U_OTP_CAV_Key9_Property] = {0x003EB0, 127, 0},
898 [U_OTP_CAV_Key10_Property] = {0x003EC0, 127, 0},
899 [U_OTP_CAV_Key11_Property] = {0x003ED0, 127, 0},
900 [U_OTP_CAV_Key12_Property] = {0x003EE0, 127, 0},
901 [U_OTP_CAV_Key13_Property] = {0x003EF0, 127, 0},
902 [U_OTP_CAV_Key14_Property] = {0x003F00, 127, 0},
903 [U_OTP_CAV_Key15_Property] = {0x003F10, 127, 0},
904 [U_OTP_CAV_SecretKey1] = {0x003F20, 127, 0},
905 [U_OTP_CAV_SecretKey2] = {0x003F30, 127, 0},
906 [U_OTP_CAV_SecretKey3] = {0x003F40, 127, 0},
907 [U_OTP_CAV_SecretKey4] = {0x003F50, 127, 0},
908 [U_OTP_CAV_SecretKey5] = {0x003F60, 127, 0},
909 [U_OTP_CAV_SecretKey6] = {0x003F70, 127, 0},
910 [U_OTP_CAV_SecretKey7] = {0x003F80, 127, 0},
911 [U_OTP_CAV_SecretKey8] = {0x003F90, 127, 0},
912 [U_OTP_CA_PWD_integrity_chk] = {0x003FA0, 1, 0},
913 [U_OTP_Multi2SysKey_integrity_chk] = {0x003FA0, 3, 2},
914 [U_OTP_CA_PWD_Reserved0] = {0x003FA0, 7, 4},
915 [U_OTP_I2C_PWD_obfuscation] = {0x003FA0, 9, 8},
916 [U_OTP_EJTAG_PWD_obfuscation] = {0x003FA0, 11, 10},
917 [U_OTP_SCAN_PWD_obfuscation] = {0x003FA0, 13, 12},
918 [U_OTP_MBIST_PWD_obfuscation] = {0x003FA0, 15, 14},
919 [U_OTP_Multi2SysKey_CRC] = {0x003FA0, 31, 16},
920 [U_OTP_I2C_PWD_CRC] = {0x003FA4, 15, 0},
921 [U_OTP_EJTAG_PWD_CRC] = {0x003FA4, 31, 16},
922 [U_OTP_SCAN_PWD_CRC] = {0x003FA8, 15, 0},
923 [U_OTP_MBIST_PWD_CRC] = {0x003FA8, 31, 16},
924 [U_OTP_CA_PWD_Keysel] = {0x003FAC, 5, 0},
925 [U_OTP_ena_TP_PWD] = {0x003FAC, 7, 6},
926 [U_OTP_ena_KDF_I2C_PWD] = {0x003FAC, 9, 8},
927 [U_OTP_ena_KDF_EJTAG_PWD] = {0x003FAC, 11, 10},
928 [U_OTP_ena_KDF_SCAN_PWD] = {0x003FAC, 13, 12},
929 [U_OTP_ena_KDF_MBIST_PWD] = {0x003FAC, 15, 14},
930 [U_OTP_I2C_TP_ID] = {0x003FAC, 19, 16},
931 [U_OTP_EJTAG_TP_ID] = {0x003FAC, 23, 20},
932 [U_OTP_SCAN_TP_ID] = {0x003FAC, 27, 24},
933 [U_OTP_MBIST_TP_ID] = {0x003FAC, 31, 28},
934 [U_OTP_I2C_PWD] = {0x003FB0, 127, 0},
935 [U_OTP_EJTAG_PWD] = {0x003FC0, 127, 0},
936 [U_OTP_SCAN_PWD] = {0x003FD0, 127, 0},
937 [U_OTP_MBIST_PWD] = {0x003FE0, 127, 0},
938 [U_OTP_VtrackID] = {0x003FF0, 31, 0},
939 [U_OTP_VtrackKey] = {0x003FF4, 31, 0},
940 [U_OTP_VtrackID_select] = {0x003FF8, 0, 0},
941 [U_OTP_VtrackKey_select] = {0x003FF8, 1, 1},
942 [U_OTP_Vtrack_Reserved0] = {0x003FF8, 31, 2},
943 [U_OTP_FAKE] = {0x003FFC, 23, 0},
944 [U_OTP_allow_CPU_rst_release] = {0x003FFC, 31, 24},
945 [U_OTP_REGION31] = {0x007E00,1023,0}
946
947 };
948
949
950 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value);
951 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value);
952
953 //--------------------------------------------------------------------------------------------------
954 // Macro of bit operations
955 //--------------------------------------------------------------------------------------------------
956
957 //--------------------------------------------------------------------------------------------------
958 // Inline Function
959 //--------------------------------------------------------------------------------------------------
HAL_CA_SetBank(MS_U32 u32RegAddr)960 void HAL_CA_SetBank(MS_U32 u32RegAddr)
961 {
962 _u32REGBase = u32RegAddr;
963 _u32REGPMBase = u32RegAddr - 0x200000UL;
964 _u32REG_OTP_Base = u32RegAddr + REG_OTP_BASE;
965 _u32REG_RSA_Base = u32RegAddr + REG_RSA_BASE;
966 }
967
HAL_CA_Init(void)968 MS_BOOL HAL_CA_Init(void)
969 {
970 return TRUE;
971 }
972
HAL_CA_BGC_ISR(void)973 void HAL_CA_BGC_ISR(void)
974 {
975 MS_U32 u32Excp = REG32(BGC_RESP_FAIL);
976 // MS_U32 u32SecID = u32Excp & BGC_RESP_SECID;
977
978 if((u32Excp & BGC_RESP_RESET_AV) == BGC_RESP_RESET_AV)
979 {
980 //AV reset
981 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset AV.");
982 }
983
984 if((u32Excp & BGC_RESP_RESET_ACPU) == BGC_RESP_RESET_ACPU)
985 {
986 //ACPU reset
987 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset ACPU.");
988 }
989
990 if((u32Excp & BGC_RESP_RESET_SCPU) == BGC_RESP_RESET_SCPU)
991 {
992 //SCPU reset
993 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset SCPU.");
994 }
995
996 if((u32Excp & BGC_RESP_RESET_SYSTEM) == BGC_RESP_RESET_SYSTEM)
997 {
998 //If error is reset system, run reset system(only in keres)
999 //System reset
1000 HAL_CA_DEBUG("BGC: unexpected modification of protected area detected. Reset system.");
1001 // REG32_PM(REG_TOP_SW_RST) = ((REG32_PM(REG_TOP_SW_RST) & ~REG_TOP_SW_RST_MSK) | REG_TOP_SW_RST_PASSWD);
1002 }
1003
1004
1005 }
1006
HAL_CA_BGC_DisableINT(void)1007 void HAL_CA_BGC_DisableINT(void)
1008 {
1009 REG32(REG_INTR_CPUINIT_HST3) = REG32(REG_INTR_CPUINIT_HST3) & (~REG_HST3TO2_INT);
1010 }
1011
HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr,MS_U32 u32FwSize)1012 MS_BOOL HAL_CA_BGC_LoadFW(MS_U32 u32FwAddr, MS_U32 u32FwSize)
1013 {
1014 if(u32FwSize > 0x2000)
1015 { //max size is 8K
1016 return FALSE;
1017 }
1018
1019 if((REG32(REG_ONEWAY_42) & SEC51_SW_RST) == 0x0)//bit0, reset sec51
1020 {
1021 return TRUE;//already enable sec51
1022 }
1023
1024 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1025 REG32(REG_BDMA_CTRL) = 0x0; //disable
1026 REG32(REG_BDMA_SRC_SEL) = 0x0940; //MIU0 to Sec_51
1027 REG32(REG_BDMA_SRC_ADDR_L) = u32FwAddr & 0xFFFF;
1028 REG32(REG_BDMA_SRC_ADDR_H) = (u32FwAddr >> 16) & 0xFFFF;
1029 REG32(REG_BDMA_DST_ADDR_L) = 0x0;
1030 REG32(REG_BDMA_DST_ADDR_H) = 0x0;
1031 REG32(REG_BDMA_SIZE_L) = u32FwSize & 0xFFFF; //size
1032 REG32(REG_BDMA_SIZE_H) = 0x0;
1033 REG32(REG_BDMA_CTRL) = 0x1; // triger bdma
1034 while((REG32(REG_BDMA_CTRL) & 0x1) != 0); //wait bdma done
1035
1036 REG32(REG_BDMA_STATUS) = REG32(REG_BDMA_STATUS) | 0x10; // triger bdma
1037
1038 REG32(REG_ONEWAY_42) = REG32(REG_ONEWAY_42) & (~SEC51_SW_RST);//bit 0, release sec51
1039
1040 REG32(REG_ONEWAY_52) = REG32(REG_ONEWAY_52) | SEC51_SW_LOCK;//bit 0, oneway lock sec51
1041
1042 //enable MIU cross bar
1043 REG32(REG_MIU_CROSSBAR_CTRL) = REG32(REG_MIU_CROSSBAR_CTRL) | REG_MIU_CROSSBAR_EN;
1044 return TRUE;
1045 }
1046
HAL_CA_BGC_Ctrl(MS_U32 u32Cmd,MS_U32 u32Data)1047 MS_BOOL HAL_CA_BGC_Ctrl(MS_U32 u32Cmd, MS_U32 u32Data)
1048 {
1049 MS_U16 u16Cmd = ((u32Data << BGC_CMD_SEC_DATA_SHT) & BGC_CMD_SEC_DATA) |
1050 ((u32Cmd << BGC_CMD_SEC_TYPE_SHT) & BGC_CMD_SEC_TYPE);
1051
1052 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1053
1054 REG32(BGC_CMD_CTRL) = u16Cmd;
1055 REG32(BGC_CMD_CTRL) = u16Cmd | BGC_CMD_SEC_GO;
1056 // printf("[BGC Cmd]:%04X\n", u16Cmd);
1057
1058 while((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_GO) == BGC_CMD_SEC_GO);
1059 // printf("[BGC Cmd]:after write:%04X\n", REG32(BGC_CMD_CTRL));
1060
1061 if((REG32(BGC_CMD_CTRL) & BGC_CMD_SEC_STATUS) == BGC_CMD_SEC_STATUS)
1062 {
1063 return FALSE;
1064 }
1065 return TRUE;
1066 }
1067
HAL_CA_BGC_SetSec(MS_U32 u32SecId,const CA_BGC_SEC_CFG * pstSecCfg)1068 MS_BOOL HAL_CA_BGC_SetSec(MS_U32 u32SecId, const CA_BGC_SEC_CFG* pstSecCfg)
1069 {
1070 MS_U32 i = 0;
1071 MS_U32 u32Fail = 0;
1072
1073 if(u32SecId >= BGC_SEC_MAX )
1074 {
1075 return FALSE;
1076 }
1077
1078 //set section id
1079 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1080 {
1081 u32Fail = 1;
1082 goto BGC_CONFIG_FAIL;
1083 }
1084
1085 //set BGC mode
1086 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_MODE, pstSecCfg->u32BGCMode == 1 ? BGC_SEC_MODE_STATIC : BGC_SEC_MODE_DYNAMIC) == FALSE)
1087 {
1088 u32Fail = 2;
1089 goto BGC_CONFIG_FAIL;
1090 }
1091
1092 //set protect address and input cmd length
1093 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1094 {
1095 u32Fail = 3;
1096 goto BGC_CONFIG_FAIL;
1097 }
1098
1099 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x000000FF)>>0) == FALSE) |
1100 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x0000FF00)>>8) == FALSE) |
1101 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0x00FF0000)>>16) == FALSE) |
1102 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ADDR, (pstSecCfg->u32ProtectAddr & 0xFF000000)>>24) == FALSE))
1103 {
1104 u32Fail = 4;
1105 goto BGC_CONFIG_FAIL;
1106 }
1107
1108 //set protect size and input cmd length
1109 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1110 {
1111 u32Fail = 5;
1112 goto BGC_CONFIG_FAIL;
1113 }
1114 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x000000FF)>>0) == FALSE) |
1115 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x0000FF00)>>8) == FALSE) |
1116 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0x00FF0000)>>16) == FALSE) |
1117 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SIZE, (pstSecCfg->u32ProtectSize & 0xFF000000)>>24) == FALSE))
1118 {
1119 u32Fail = 6;
1120 goto BGC_CONFIG_FAIL;
1121 }
1122
1123 //set interval bwteen two BGC check and input cmd length
1124 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x2) == FALSE)
1125 {
1126 u32Fail = 7;
1127 goto BGC_CONFIG_FAIL;
1128 }
1129 if((HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0x00FF)>>0) == FALSE) |
1130 (HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_INTERVAL, (pstSecCfg->u16Interval & 0xFF00)>>8) == FALSE))
1131 {
1132 u32Fail = 8;
1133 goto BGC_CONFIG_FAIL;
1134 }
1135
1136
1137 //set golden and incput golden length
1138 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x20) == FALSE)
1139 {
1140 u32Fail = 9;
1141 goto BGC_CONFIG_FAIL;
1142 }
1143
1144 for(i = 0 ; i < 0x20 ; i ++)
1145 {
1146 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_GOLDEN, pstSecCfg->u8Golden[i]) == FALSE)
1147 {
1148 u32Fail = 10;
1149 goto BGC_CONFIG_FAIL;
1150 }
1151 }
1152
1153 //set password and incput length
1154 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1155 {
1156 u32Fail = 11;
1157 goto BGC_CONFIG_FAIL;
1158 }
1159
1160 for(i = 0 ; i < 0x4 ; i ++)
1161 {
1162 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SET_PASSWD, pstSecCfg->u8ResetPassword[i]) == FALSE)
1163 {
1164 u32Fail = 12;
1165 goto BGC_CONFIG_FAIL;
1166 }
1167 }
1168
1169 //set algorithm to sha256
1170 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ALGO, BGC_SEC_ALGO_SHA256) == FALSE)
1171 {
1172 u32Fail = 13;
1173 goto BGC_CONFIG_FAIL;
1174 }
1175
1176 //set the reset mode if BGC check fail
1177 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_MODE, BGC_SEC_RESET_INTERRUPT | BGC_SEC_RESET_SYSTEM) == FALSE)
1178 {
1179 u32Fail = 14;
1180 goto BGC_CONFIG_FAIL;
1181 }
1182
1183 //enable section id
1184 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_ENABLE, TRUE) == FALSE)
1185 {
1186 u32Fail = 15;
1187 goto BGC_CONFIG_FAIL;
1188 }
1189
1190 return TRUE;
1191
1192 BGC_CONFIG_FAIL:
1193 HAL_CA_DEBUG("BGC config fail:%08X\n", u32Fail);
1194 return FALSE;
1195 }
1196
HAL_CA_BGC_ResetSec(MS_U32 u32SecId,const MS_U8 * pu8RstPSWD)1197 MS_BOOL HAL_CA_BGC_ResetSec(MS_U32 u32SecId, const MS_U8* pu8RstPSWD)
1198 {
1199 MS_U32 i = 0;
1200 MS_U32 u32Fail = 0;
1201
1202 if((u32SecId >= BGC_SEC_MAX) || (pu8RstPSWD == NULL))
1203 {
1204 return FALSE;
1205 }
1206
1207 //check bgc mode, if mode = 1, return fail
1208 //set section id
1209 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_SECID, u32SecId) == FALSE)
1210 {
1211 u32Fail = 1;
1212 goto BGC_RESET_FAIL;
1213 }
1214
1215 //set reset password and incput length
1216 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_LENGTH, 0x4) == FALSE)
1217 {
1218 u32Fail = 2;
1219 goto BGC_RESET_FAIL;
1220 }
1221
1222 for(i = 0 ; i < 0x4 ; i ++)
1223 {
1224 if(HAL_CA_BGC_Ctrl(BGC_CMD_TYPE_RESET_PASSWD, pu8RstPSWD[i]) == FALSE)
1225 {
1226 u32Fail = 3;
1227 goto BGC_RESET_FAIL;
1228 }
1229 }
1230 return TRUE;
1231
1232 BGC_RESET_FAIL:
1233 HAL_CA_DEBUG("BGC reset fail:%08X\n", u32Fail);
1234 return FALSE;
1235
1236 }
1237
HAL_CA_OTP_IsBlank(MS_U32 addr)1238 MS_BOOL HAL_CA_OTP_IsBlank(MS_U32 addr)
1239 {
1240 MS_U32 value;
1241
1242 if(addr >= CA_OTP_SIZE)
1243 return 0;
1244
1245 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1246
1247 return value == 0;
1248 }
1249
1250
_HAL_CA_OTP_Read_Real(MS_U32 addr,MS_BOOL bXor)1251 MS_U32 _HAL_CA_OTP_Read_Real(MS_U32 addr, MS_BOOL bXor)
1252 {
1253 MS_U32 value;
1254
1255 if(addr >= CA_OTP_SIZE)
1256 return 0;
1257
1258 value = *(volatile MS_U32 *)(_u32REG_OTP_Base + addr);
1259
1260 return value;
1261 }
1262
1263
HAL_CA_OTP_Read(MS_U32 addr)1264 MS_U32 HAL_CA_OTP_Read(MS_U32 addr)
1265 {
1266 return _HAL_CA_OTP_Read_Real(addr, FALSE);
1267 }
1268
1269
_HAL_CA_OTP_Write_Real(MS_U32 addr,MS_U8 value)1270 MS_BOOL _HAL_CA_OTP_Write_Real(MS_U32 addr, MS_U8 value)
1271 {
1272 MS_DEBUG_MSG(printf("[_HAL_CA_OTP_Write_Real] addr=0x%04lx value=0x%02lx\n", addr, (MS_U32)value);)
1273 #if 0
1274 printf("[_HAL_CA_OTP_Write_Real] NO REAL WRITE!!!\n");
1275 #else
1276 *(volatile MS_U8 *)(_u32REG_OTP_Base + addr) = value;
1277 #endif
1278
1279 MS_U32 v;
1280 v = REG32(REG_OTP_CTRL_PV) & REG_OTP_CTRL_PG_VERIFY_FAIL_FLAG;
1281 if(v == 0) {
1282 return TRUE;
1283 }
1284
1285 HAL_CA_DEBUG("[_HAL_CA_OTP_Write_Real] PV fail (0x%08x)\n", v);
1286 return FALSE;
1287 }
1288
HAL_CA_OTP_Write(MS_U32 addr,MS_U32 value)1289 MS_BOOL HAL_CA_OTP_Write(MS_U32 addr, MS_U32 value)
1290 {
1291 int i;
1292 if(addr >= CA_OTP_SIZE)
1293 return FALSE;
1294
1295 if(addr % 4 != 0)
1296 return FALSE;
1297
1298 REG32(REG_OTP_CTRL_0) = REG_OTP_CTRL_0_VALUE;
1299
1300 MS_U32 orig = _HAL_CA_OTP_Read_Real(addr, TRUE);
1301 MS_U32 write = value & (orig ^ value); // only write the bit from 0 to 1
1302
1303 if(write == 0)
1304 return TRUE;
1305
1306 for(i = 0; i < 4; i++) {
1307 if(_HAL_CA_OTP_Write_Real(addr + i, (value >> (i * 8)) & 0xff) == FALSE)
1308 return FALSE;
1309 }
1310
1311 MS_U32 result = _HAL_CA_OTP_Read_Real(addr, TRUE);
1312 if((result & value) == value) // only check the bit 1
1313 {
1314 return TRUE;
1315 }
1316
1317 return FALSE;
1318 }
1319
_HAL_CA_OTP_GetConfig(MS_U32 u32Idx,MS_U32 * pu32Value)1320 MS_BOOL _HAL_CA_OTP_GetConfig(MS_U32 u32Idx, MS_U32 *pu32Value)
1321 {
1322 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1323 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1324 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1325 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1326
1327 if(pu32Value == NULL)
1328 return FALSE;
1329
1330 if(u32Len > 32)
1331 return FALSE;
1332
1333 *pu32Value = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1334
1335 return TRUE;
1336 }
1337
_HAL_CA_OTP_SetConfig(MS_U32 u32Idx,MS_U32 u32Value)1338 MS_BOOL _HAL_CA_OTP_SetConfig(MS_U32 u32Idx, MS_U32 u32Value)
1339 {
1340 //printf("[_HAL_CA_OTP_SetConfig] u32Idx=%ld u32Value=0x%08lx\n", u32Idx, u32Value);
1341
1342 MS_U32 u32Addr = _HAL_CA_OTP_Addr[u32Idx].u32Addr;
1343 MS_U32 u32Shift = _HAL_CA_OTP_Addr[u32Idx].u32Lo;
1344 MS_U32 u32Len = _HAL_CA_OTP_Addr[u32Idx].u32Hi - _HAL_CA_OTP_Addr[u32Idx].u32Lo + 1;
1345 MS_U32 u32Mask = bitmask(_HAL_CA_OTP_Addr[u32Idx].u32Hi, _HAL_CA_OTP_Addr[u32Idx].u32Lo);
1346
1347 if(u32Len > 32)
1348 return FALSE;
1349
1350 u32Value = (u32Value << u32Shift) & u32Mask;
1351
1352 return HAL_CA_OTP_Write(u32Addr, u32Value);
1353 }
1354
HAL_CA_OTP_EnableSecureBoot(void)1355 MS_BOOL HAL_CA_OTP_EnableSecureBoot(void)
1356 {
1357 return _HAL_CA_OTP_SetConfig(U_OTP_SBoot, 0xf);
1358 }
1359
HAL_CA_OTP_IsSecureBootEnabled(void)1360 MS_BOOL HAL_CA_OTP_IsSecureBootEnabled(void)
1361 {
1362 MS_U32 u32Value = 0;
1363 MS_BOOL ret = FALSE;
1364
1365 ret = _HAL_CA_OTP_GetConfig(U_OTP_SBoot, &u32Value);
1366
1367 if (ret == FALSE)
1368 {
1369 return FALSE;
1370 }
1371 return u32Value != 0;
1372 }
1373
1374
HAL_CA_OTP_SetBlockLock(MS_U32 u32Start,MS_U32 u32End,CA_LOCK_TYPE eLockType)1375 MS_BOOL HAL_CA_OTP_SetBlockLock(MS_U32 u32Start, MS_U32 u32End, CA_LOCK_TYPE eLockType)
1376 {
1377 //Not support
1378 MS_DEBUG_MSG(printf("[%s][%d] do not support\n", __FUNCTION__, __LINE__));
1379 return FALSE;
1380 }
1381
HAL_CA_OTP_GetBlockLock(MS_U32 * pu32Start,MS_U32 * pu32End,CA_LOCK_TYPE * peLockType)1382 MS_BOOL HAL_CA_OTP_GetBlockLock(MS_U32 *pu32Start, MS_U32 *pu32End, CA_LOCK_TYPE *peLockType)
1383 {
1384 //Not support
1385 MS_DEBUG_MSG(printf("[%s][%d] do not support\n", __FUNCTION__, __LINE__));
1386 return FALSE;
1387 }
1388
1389
1390 //=======================================================
1391 // RSA bank for Secure Range
1392 //=======================================================
1393
HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet,MS_U32 u32SecStart,MS_U32 u32SecEnd)1394 MS_BOOL HAL_CA_RSA_SetSecureRange(MS_U32 u32SecSet, MS_U32 u32SecStart, MS_U32 u32SecEnd)
1395 {
1396 if(u32SecSet > REG_RSA_SEC_RANGE_SET || u32SecEnd <= u32SecStart)
1397 return FALSE;
1398
1399 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_START(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecStart & REG_RSA_SEC_RANGE_MASK);
1400 *(volatile MS_U32*) (_u32REGBase + REG_RSA_SEC_RANGE_END(u32SecSet)) = REG_RSA_SEC_RANGE_ENABLE | ( u32SecEnd & REG_RSA_SEC_RANGE_MASK);
1401
1402 return TRUE;
1403 }
1404
HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)1405 MS_BOOL HAL_CA_OTP_Lock(CA_OTP_LOCK eLock)
1406 {
1407 switch(eLock)
1408 {
1409 // Boot Area
1410 case E_BOOT_LockWord_W0000_0511_Addr:
1411 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0000_0511_W, 0x3);
1412 case E_BOOT_LockWord_W0512_1023_Addr:
1413 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_0512_1023_W, 0x3);
1414 case E_BOOT_LockWord_W1024_1535_Addr:
1415 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1024_1535_W, 0x3);
1416 case E_BOOT_LockWord_W1536_2047_Addr:
1417 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_1536_2047_W, 0x3);
1418 case E_BOOT_LockWord_W2048_2559_Addr:
1419 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2048_2559_W, 0x3);
1420 case E_BOOT_LockWord_W2560_3071_Addr:
1421 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_2560_3071_W, 0x3);
1422 case E_BOOT_LockWord_W3072_3391_Addr:
1423 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_3072_3391_W, 0x3);
1424
1425 // IDs
1426 case E_LockWord_v_PubOtpOID:
1427 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpOID_W, 0x3);
1428 case E_LockWord_v_PubOtpVID:
1429 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_v_PubOtpVID_W, 0x3);
1430 case E_LockWord_v_pubOtpUniqueID1:
1431 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, 0x3);
1432 case E_LockWord_v_pubOtpUniqueID2:
1433 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, 0x3);
1434 case E_LockWord_v_pubOtpUniqueID3:
1435 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, 0x3);
1436 case E_LockWord_v_pubOtpUniqueID4:
1437 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, 0x3);
1438 case E_LockWord_CA_MSID:
1439 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_MSID_W, 0x3);
1440
1441 //CA_SecretKey
1442 case E_LockWord_CAV_SecretKey6_W:
1443 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CAV_Key6_W, 0x3);
1444 case E_LockWord_CAV_SecretKey6_R:
1445 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CAV_Key6_R, 0x3);
1446
1447 case E_LockWord_RSA_1_W:
1448 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_RSA_1_W, 0x3);
1449
1450 //Debug ports
1451 case E_LockWord_Debugport_PWD_W:
1452 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_PWD_W, 0x3);
1453 case E_LockWord_Debugport_PWD_R:
1454 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_PWD_R, 0x3);
1455
1456 // Reserved
1457 case E_LockWord_CA_reserved0:
1458 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved0_W, 0x3);
1459 case E_LockWord_CA_reserved1:
1460 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved1_W, 0x3);
1461 case E_LockWord_CA_reserved2:
1462 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved2_W, 0x3);
1463 case E_LockWord_CA_reserved3:
1464 return _HAL_CA_OTP_SetConfig(U_OTP_LockWord_CA_reserved3_W, 0x3);
1465
1466 default:
1467 return FALSE;
1468 }
1469 }
1470
HAL_CA_Locked(CA_OTP_LOCK eLock)1471 MS_BOOL HAL_CA_Locked(CA_OTP_LOCK eLock)
1472 {
1473 MS_U32 u32Value = 0;
1474 MS_BOOL ret = FALSE;
1475 switch(eLock)
1476 {
1477 // Boot Area
1478 case E_BOOT_LockWord_W0000_0511_Addr:
1479 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0000_0511_W, &u32Value);
1480 break;
1481 case E_BOOT_LockWord_W0512_1023_Addr:
1482 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_0512_1023_W, &u32Value);
1483 break;
1484 case E_BOOT_LockWord_W1024_1535_Addr:
1485 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1024_1535_W, &u32Value);
1486 break;
1487 case E_BOOT_LockWord_W1536_2047_Addr:
1488 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_1536_2047_W, &u32Value);
1489 break;
1490 case E_BOOT_LockWord_W2048_2559_Addr:
1491 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2048_2559_W, &u32Value);
1492 break;
1493 case E_BOOT_LockWord_W2560_3071_Addr:
1494 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_2560_3071_W, &u32Value);
1495 break;
1496 case E_BOOT_LockWord_W3072_3391_Addr:
1497 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_3072_3391_W, &u32Value);
1498 break;
1499
1500 // IDs
1501 case E_LockWord_v_PubOtpOID:
1502 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpOID_W, &u32Value);
1503 break;
1504 case E_LockWord_v_PubOtpVID:
1505 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_v_PubOtpVID_W, &u32Value);
1506 break;
1507 case E_LockWord_v_pubOtpUniqueID1:
1508 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID1_W, &u32Value);
1509 break;
1510 case E_LockWord_v_pubOtpUniqueID2:
1511 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID2_W, &u32Value);
1512 break;
1513 case E_LockWord_v_pubOtpUniqueID3:
1514 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID3_W, &u32Value);
1515 break;
1516 case E_LockWord_v_pubOtpUniqueID4:
1517 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_PubOTPUniqueID4_W, &u32Value);
1518 case E_LockWord_CA_MSID:
1519 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_MSID_W, &u32Value);
1520 break;
1521
1522 //CA_SecretKey
1523 case E_LockWord_CAV_SecretKey6_W:
1524 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CAV_Key6_W, &u32Value);
1525 break;
1526 case E_LockWord_CAV_SecretKey6_R:
1527 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CAV_Key6_R, &u32Value);
1528 break;
1529
1530 case E_LockWord_RSA_1_W:
1531 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_RSA_1_W, &u32Value);
1532 break;
1533
1534 //Debug ports
1535 case E_LockWord_Debugport_PWD_W:
1536 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_PWD_W, &u32Value);
1537 break;
1538 case E_LockWord_Debugport_PWD_R:
1539 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_PWD_R, &u32Value);
1540 break;
1541
1542 // Reserved
1543 break;
1544 case E_LockWord_CA_reserved0:
1545 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved0_W, &u32Value);
1546 break;
1547 case E_LockWord_CA_reserved1:
1548 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved1_W, &u32Value);
1549 break;
1550 case E_LockWord_CA_reserved2:
1551 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved2_W, &u32Value);
1552 break;
1553 case E_LockWord_CA_reserved3:
1554 ret = _HAL_CA_OTP_GetConfig(U_OTP_LockWord_CA_reserved3_W, &u32Value);
1555 break;
1556 break;
1557 default:
1558 ret = FALSE;
1559 }
1560
1561 if(ret == FALSE)
1562 return FALSE;
1563
1564 if(u32Value == 0x01) // 0x01 : unlock, xx : locked
1565 return FALSE;
1566
1567 return TRUE;
1568 }
1569
HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)1570 MS_BOOL HAL_CA_OTP_SetRSAextID(MS_U32 u32Value)
1571 {
1572 return _HAL_CA_OTP_SetConfig(U_OTP_MSID, u32Value);
1573 }
1574
HAL_CA_OTP_GetRSAextID(void)1575 MS_U32 HAL_CA_OTP_GetRSAextID(void)
1576 {
1577
1578 MS_U32 u32Value = 0;
1579 MS_BOOL ret = FALSE;
1580
1581 ret = _HAL_CA_OTP_GetConfig(U_OTP_MSID, &u32Value);
1582
1583 if (ret == FALSE)
1584 {
1585 return FALSE;
1586 }
1587 return u32Value;
1588 }
1589
1590
HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH1_REF_VER,MS_U32 u32HASH2_REF_VER)1591 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER_Ex(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH1_REF_VER, MS_U32 u32HASH2_REF_VER)
1592 {
1593 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH0_VER_REF, u32HASH0_REF_VER) == FALSE)
1594 {
1595 return FALSE;
1596 }
1597
1598 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH1_VER_REF, u32HASH1_REF_VER) == FALSE)
1599 {
1600 return FALSE;
1601 }
1602
1603 if(_HAL_CA_OTP_SetConfig(U_OTP_HASH2_VER_REF, u32HASH2_REF_VER) == FALSE)
1604 {
1605 return FALSE;
1606 }
1607
1608 return TRUE;
1609 }
1610
HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH1_REF_VER,MS_U32 * pu32HASH2_REF_VER)1611 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER_Ex(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH1_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1612 {
1613 MS_U32 u32Value = 0;
1614
1615 if(pu32HASH0_REF_VER != NULL)
1616 {
1617 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH0_VER_REF, &u32Value) == FALSE)
1618 {
1619 return FALSE;
1620 }
1621
1622 *pu32HASH0_REF_VER = (u32Value);
1623 }
1624
1625 if(pu32HASH1_REF_VER != NULL)
1626 {
1627 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH1_VER_REF, &u32Value) == FALSE)
1628 {
1629 return FALSE;
1630 }
1631 *pu32HASH1_REF_VER = (u32Value);
1632 }
1633
1634 if(pu32HASH2_REF_VER != NULL)
1635 {
1636 if(_HAL_CA_OTP_GetConfig(U_OTP_HASH2_VER_REF, &u32Value) == FALSE)
1637 {
1638 return FALSE;
1639 }
1640
1641 *pu32HASH2_REF_VER = (u32Value);
1642 }
1643
1644 return TRUE;
1645 }
1646
HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)1647 MS_BOOL HAL_CA_OTP_SetHASH1_REF_VER(MS_U32 u32HASH1_REF_VER)
1648 {
1649 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(0, u32HASH1_REF_VER, 0) == FALSE)
1650 {
1651 return FALSE;
1652 }
1653
1654 return TRUE;
1655 }
1656
HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 * pu32HASH1_REF_VER)1657 MS_BOOL HAL_CA_OTP_GetHASH1_REF_VER(MS_U32 *pu32HASH1_REF_VER)
1658 {
1659 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(NULL, pu32HASH1_REF_VER, NULL) == FALSE)
1660 {
1661 return FALSE;
1662 }
1663
1664 return TRUE;
1665 }
1666
1667
HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER,MS_U32 u32HASH2_REF_VER)1668 MS_BOOL HAL_CA_OTP_SetHASH_REF_VER(MS_U32 u32HASH0_REF_VER, MS_U32 u32HASH2_REF_VER)
1669 {
1670 if(HAL_CA_OTP_SetHASH_REF_VER_Ex(u32HASH0_REF_VER, 0, u32HASH2_REF_VER) == FALSE)
1671 {
1672 return FALSE;
1673 }
1674
1675 return TRUE;
1676 }
1677
HAL_CA_OTP_GetHASH_REF_VER(MS_U32 * pu32HASH0_REF_VER,MS_U32 * pu32HASH2_REF_VER)1678 MS_BOOL HAL_CA_OTP_GetHASH_REF_VER(MS_U32 *pu32HASH0_REF_VER, MS_U32 *pu32HASH2_REF_VER)
1679 {
1680 if(HAL_CA_OTP_GetHASH_REF_VER_Ex(pu32HASH0_REF_VER, NULL, pu32HASH2_REF_VER) == FALSE)
1681 {
1682 return FALSE;
1683 }
1684
1685 return TRUE;
1686 }
1687
1688
HAL_CA_MaxDeviceIdSize(void)1689 MS_U32 HAL_CA_MaxDeviceIdSize(void)
1690 {
1691 return MAX_DEVICEID_SIZE;
1692 }
1693
HAL_CA_OTP_SetDeviceId(const MS_U8 * pu8Did,MS_U32 u32Size)1694 MS_BOOL HAL_CA_OTP_SetDeviceId(const MS_U8 *pu8Did, MS_U32 u32Size)
1695 {
1696 MS_U32 did[8] = {0};
1697 MS_U32 i, u32Addr;
1698 MS_U32 Did_Size = 2;
1699 MS_U8 *p = (MS_U8 *)did;
1700
1701 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1702 {
1703 p[i] = pu8Did[i];
1704 }
1705
1706 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1707 for(i = 0; i < Did_Size; i++)
1708 {
1709 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1710 {
1711 return FALSE;
1712 }
1713 u32Addr += 4;
1714 }
1715 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1716 for(i = Did_Size; i < (2*Did_Size); i++)
1717 {
1718 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1719 {
1720 return FALSE;
1721 }
1722 u32Addr += 4;
1723 }
1724 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1725 for(i = (2*Did_Size); i < (3*Did_Size); i++)
1726 {
1727 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1728 {
1729 return FALSE;
1730 }
1731 u32Addr += 4;
1732 }
1733 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1734 for(i = (3*Did_Size); i < (4*Did_Size); i++)
1735 {
1736 if(HAL_CA_OTP_Write(u32Addr,did[i]) == FALSE)
1737 {
1738 return FALSE;
1739 }
1740 u32Addr += 4;
1741 }
1742
1743 return TRUE;
1744 }
1745
HAL_CA_OTP_GetDeviceId(MS_U8 * pu8Did,MS_U32 u32Size)1746 MS_BOOL HAL_CA_OTP_GetDeviceId(MS_U8 *pu8Did, MS_U32 u32Size)
1747 {
1748 MS_U32 did[8] = {0};
1749 MS_U32 Did_Size = 2;
1750 MS_U32 i, u32Addr;
1751 MS_U8 *p = (MS_U8 *)did;
1752
1753 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID1].u32Addr;
1754 for(i = 0; i < Did_Size; i++)
1755 {
1756 did[i] = HAL_CA_OTP_Read(u32Addr);
1757 u32Addr += 4;
1758 }
1759 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID2].u32Addr;
1760 for(i = Did_Size; i < (2*Did_Size) ; i++)
1761 {
1762 did[i] = HAL_CA_OTP_Read(u32Addr);
1763 u32Addr += 4;
1764 }
1765 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID3].u32Addr;
1766 for(i = (2*Did_Size) ; i < (3*Did_Size) ; i++)
1767 {
1768 did[i] = HAL_CA_OTP_Read(u32Addr);
1769 u32Addr += 4;
1770 }
1771 u32Addr = _HAL_CA_OTP_Addr[U_OTP_v_pubOtpUniqueID4].u32Addr;
1772 for(i = (3*Did_Size); i < (4*Did_Size) ; i++)
1773 {
1774 did[i] = HAL_CA_OTP_Read(u32Addr);
1775 u32Addr += 4;
1776 }
1777
1778 for(i = 0; i < sizeof(did) && i < u32Size; i++)
1779 {
1780 pu8Did[i] = p[i];
1781 }
1782
1783 return TRUE;
1784 }
1785
HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE eMode)1786 MS_BOOL HAL_CA_OTP_SetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE eMode)
1787 {
1788 MS_U32 idx = 0;
1789 MS_U32 v = 0;
1790
1791 switch(eDebugPort)
1792 {
1793 case E_CA_DEBUG_PORT_I2C:
1794 idx = U_OTP_I2C_MODE;
1795 break;
1796 case E_CA_DEBUG_PORT_JTAG:
1797 idx = U_OTP_EJTAG_MODE;
1798 break;
1799 case E_CA_DEBUG_PORT_SCAN:
1800 idx = U_OTP_SCAN_MODE;
1801 break;
1802 default:
1803 return FALSE;
1804 }
1805
1806 switch(eMode)
1807 {
1808 case E_CA_DEBUG_PORT_OPEN:
1809 return TRUE;
1810 case E_CA_DEBUG_PORT_PASSWD:
1811 v = 0x7;
1812 break;
1813 case E_CA_DEBUG_PORT_CLOSE:
1814 v = 0x3f;
1815 break;
1816 default:
1817 return FALSE;
1818 }
1819
1820 return _HAL_CA_OTP_SetConfig(idx, v);
1821
1822 }
1823
1824
HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort,CA_DEBUG_PORT_MODE * eMode)1825 MS_BOOL HAL_CA_OTP_GetDebugPortMode(CA_DEBUG_PORT eDebugPort, CA_DEBUG_PORT_MODE *eMode)
1826 {
1827 MS_U32 v = 0;
1828 MS_BOOL ret = FALSE;
1829
1830 if(eMode == NULL)
1831 {
1832 return FALSE;
1833 }
1834
1835 switch(eDebugPort)
1836 {
1837 case E_CA_DEBUG_PORT_I2C:
1838 ret = _HAL_CA_OTP_GetConfig(U_OTP_I2C_MODE, &v);
1839 break;
1840 case E_CA_DEBUG_PORT_JTAG:
1841 ret = _HAL_CA_OTP_GetConfig(U_OTP_EJTAG_MODE, &v);
1842 break;
1843 case E_CA_DEBUG_PORT_SCAN:
1844 ret = _HAL_CA_OTP_GetConfig(U_OTP_SCAN_MODE, &v);
1845 break;
1846 default:
1847 return FALSE;
1848 }
1849
1850 if (ret == FALSE)
1851 {
1852 return FALSE;
1853 }
1854
1855 if(v & 0x38)
1856 {
1857 *eMode = E_CA_DEBUG_PORT_CLOSE;
1858 }
1859 else if(v)
1860 {
1861 *eMode = E_CA_DEBUG_PORT_PASSWD;
1862 }
1863 else
1864 {
1865 *eMode = E_CA_DEBUG_PORT_OPEN;
1866 }
1867
1868 return TRUE;
1869 }
1870
1871
1872 // This function is created to used for another hal driver: NSK2
HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)1873 MS_BOOL HAL_CA_OTP_GetCfg(MS_U32 u32Idx,MS_U32 * pu32Value)
1874 {
1875 return _HAL_CA_OTP_GetConfig(u32Idx, pu32Value);
1876 }
1877
HAL_CA_OTP_EnableSecureCWMode(void)1878 MS_BOOL HAL_CA_OTP_EnableSecureCWMode(void)
1879 {
1880 return _HAL_CA_OTP_SetConfig(U_OTP_ena_ACPU2KT, 0xF);
1881 }
1882
HAL_CA_OTP_IsSecureCWMode(void)1883 MS_BOOL HAL_CA_OTP_IsSecureCWMode(void)
1884 {
1885 MS_U32 u32Value = 0;
1886 MS_BOOL ret = FALSE;
1887
1888 ret = _HAL_CA_OTP_GetConfig(U_OTP_ena_ACPU2KT, &u32Value);
1889
1890 if (ret == FALSE)
1891 {
1892 return FALSE;
1893 }
1894
1895 if(u32Value == 1)
1896 {
1897 return FALSE;
1898 }
1899 else
1900 {
1901 return TRUE;
1902 }
1903 }
1904
_HAL_CA_Random(void)1905 MS_U16 _HAL_CA_Random(void)
1906 {
1907 MS_U32 n;
1908
1909 do{
1910 n = REG32(REG_RNG_TRNG);
1911 if( n & REG_RNG_TRNG_VALID_MASK) //check valid
1912 {
1913 n &= REG_RNG_TRNG_OUT_MASK; // get random number
1914 REG32(REG_RNG_TRNG) = REG_RNG_TRNG_ACK; //ack
1915 break;
1916 }
1917 }while(1);
1918
1919 return n;
1920 }
1921
1922
HAL_CA_Random(void)1923 MS_U32 HAL_CA_Random(void)
1924 {
1925 MS_U32 u32Val = 0;
1926
1927 u32Val += _HAL_CA_Random()<<16;
1928 u32Val += _HAL_CA_Random();
1929
1930 return u32Val;
1931
1932 }
1933
HAL_CA_OTP_ReadCAVendor(void)1934 MS_U32 HAL_CA_OTP_ReadCAVendor(void)
1935 {
1936 MS_U32 u32CAV_Key_VendorID[CA_SCK_NUM] = {0}; // Store all VendorID
1937 MS_U32 u32CAV_Key_VendorID_Hi = 24; //High bit of VendorID in Key property
1938 MS_U32 u32CAV_Key_VendorID_Lo = 20; //Low bit of VendorID in Key property
1939
1940 MS_U32 u32CAV1_VendorID = 0;
1941 MS_U32 u32CAV2_VendorID = 0;
1942 MS_U32 u32CAV_Vendor = 0;
1943 MS_U32 u32CAV_Vendor_Shift = 16;
1944 MS_U32 u32CAV_Vendor_Num = 0; // Calculate how many different VendorID
1945
1946 MS_U32 u32Idx = 0;
1947 MS_U32 u32Addr = 0;
1948 MS_U32 u32Shift = 0;
1949 MS_U32 u32Mask = 0;
1950
1951 // Read VendorID of U_OTP_CAV_Keyn_Property
1952 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1953 {
1954 u32Addr = _HAL_CA_OTP_Addr[u32Idx + U_OTP_CAV_Key1_Property].u32Addr;
1955 u32Shift = u32CAV_Key_VendorID_Lo;
1956 u32Mask = bitmask(u32CAV_Key_VendorID_Hi, u32CAV_Key_VendorID_Lo);
1957
1958 u32CAV_Key_VendorID[u32Idx] = (HAL_CA_OTP_Read(u32Addr) & u32Mask) >> u32Shift;
1959 }
1960
1961 // Assign VendorID
1962 for(u32Idx = 0; u32Idx < CA_SCK_NUM; u32Idx++)
1963 {
1964 // First non NULL VendorID assign to u32CAV1_VendorID
1965 if( (0 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1966 {
1967 u32CAV1_VendorID = u32CAV_Key_VendorID[u32Idx];
1968 u32CAV_Vendor_Num++;
1969 }
1970 // Second non NULL and not u32CAV1_VendorID VendorID assign to u32CAV2_VendorID
1971 else if( (1 == u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1972 {
1973 if(u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx])
1974 {
1975 u32CAV2_VendorID = u32CAV_Key_VendorID[u32Idx];
1976 u32CAV_Vendor_Num++;
1977 }
1978 }
1979 // If third non NULL, not u32CAV1_VendorID and not u32CAV2_VendorID VendorID
1980 else if( (2 <= u32CAV_Vendor_Num) && (CA_OTP_VENDOR_ID_NULL != u32CAV_Key_VendorID[u32Idx]) )
1981 {
1982 if( (u32CAV1_VendorID != u32CAV_Key_VendorID[u32Idx]) && (u32CAV2_VendorID != u32CAV_Key_VendorID[u32Idx]) )
1983 {
1984 u32CAV1_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1985 u32CAV2_VendorID = CA_OTP_VENDOR_ID_UNKNOW;
1986 u32CAV_Vendor_Num++;
1987 }
1988
1989 }
1990 }
1991
1992 // Transform VendorID to Vendor code
1993 switch(u32CAV1_VendorID)
1994 {
1995 case CA_OTP_VENDOR_ID_NULL:
1996 break;
1997 case CA_OTP_VENDOR_ID_NDS:
1998 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS;
1999 break;
2000 case CA_OTP_VENDOR_ID_NAGRA:
2001 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA;
2002 break;
2003 case CA_OTP_VENDOR_ID_VIACCESS:
2004 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS;
2005 break;
2006 case CA_OTP_VENDOR_ID_IRDETO:
2007 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO;
2008 break;
2009 case CA_OTP_VENDOR_ID_VERIMATRIX:
2010 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX;
2011 break;
2012 case CA_OTP_VENDOR_ID_SMI:
2013 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI;
2014 break;
2015 case CA_OTP_VENDOR_ID_CONAX:
2016 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX;
2017 break;
2018 case CA_OTP_VENDOR_ID_LATENS:
2019 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS;
2020 break;
2021 case CA_OTP_VENDOR_ID_ECHOSTAR:
2022 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR;
2023 break;
2024 default:
2025 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW;
2026 }
2027
2028 switch(u32CAV2_VendorID)
2029 {
2030 case CA_OTP_VENDOR_ID_NULL:
2031 break;
2032 case CA_OTP_VENDOR_ID_NDS:
2033 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NDS << u32CAV_Vendor_Shift;
2034 break;
2035 case CA_OTP_VENDOR_ID_NAGRA:
2036 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_NAGRA << u32CAV_Vendor_Shift;
2037 break;
2038 case CA_OTP_VENDOR_ID_VIACCESS:
2039 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VIACCESS << u32CAV_Vendor_Shift;
2040 break;
2041 case CA_OTP_VENDOR_ID_IRDETO:
2042 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_IRDETO << u32CAV_Vendor_Shift;
2043 break;
2044 case CA_OTP_VENDOR_ID_VERIMATRIX:
2045 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_VERIMATRIX << u32CAV_Vendor_Shift;
2046 break;
2047 case CA_OTP_VENDOR_ID_SMI:
2048 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_SMI << u32CAV_Vendor_Shift;
2049 break;
2050 case CA_OTP_VENDOR_ID_CONAX:
2051 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_CONAX << u32CAV_Vendor_Shift;
2052 break;
2053 case CA_OTP_VENDOR_ID_LATENS:
2054 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_LATENS << u32CAV_Vendor_Shift;
2055 break;
2056 case CA_OTP_VENDOR_ID_ECHOSTAR:
2057 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_ECHOSTAR << u32CAV_Vendor_Shift;
2058 break;
2059 default:
2060 u32CAV_Vendor = u32CAV_Vendor | E_CA_VENDOR_UNKNOW << u32CAV_Vendor_Shift;
2061 }
2062
2063 return u32CAV_Vendor;
2064 }
2065
2066
HAL_CA_STR_SetBank(MS_U32 u32Bank)2067 void HAL_CA_STR_SetBank(MS_U32 u32Bank)
2068 {
2069 _u32REGPMBase = u32Bank;
2070
2071 return;
2072 }
2073
HAL_CA_STR_EnableKey(void)2074 void HAL_CA_STR_EnableKey(void)
2075 {
2076 MS_U16 u16Tmp = 0;
2077 u16Tmp = REG16_PM(REG_STR_KEY);
2078 u16Tmp |= REG_STR_DMA_KEY_VALID;
2079 REG16_PM(REG_STR_KEY) = u16Tmp;
2080
2081 return;
2082 }
2083
HAL_CA_STR_SetMAC(MS_U8 * pu8STRMAC,MS_U32 u32STRMACSize)2084 void HAL_CA_STR_SetMAC(MS_U8* pu8STRMAC, MS_U32 u32STRMACSize)
2085 {
2086 MS_U8 i = 0;
2087
2088 for(i = 0; i < (u32STRMACSize/2); i++) {
2089 REG16_PM(REG_STR_AUTH_RESULT + i*4) = (pu8STRMAC[i*2 + 1]<<8 |pu8STRMAC[i*2]);
2090 }
2091
2092 return;
2093 }
2094
HAL_CA_STR_SetParamAddr(MS_U8 * pu8BAddr)2095 void HAL_CA_STR_SetParamAddr(MS_U8 *pu8BAddr)
2096 {
2097 MS_U16 u16Tmp = 0;
2098
2099 u16Tmp = ((MS_VIRT)pu8BAddr & 0x0000FFFF);
2100 REG16_PM(REG_STR_PTR) = u16Tmp;
2101
2102 u16Tmp = ((MS_VIRT)pu8BAddr & 0xFFFF0000)>>16;
2103 REG16_PM(REG_STR_PTR + 4) = u16Tmp;
2104
2105 return;
2106 }
2107
HAL_CA_STR_EnableWarmBoot(void)2108 void HAL_CA_STR_EnableWarmBoot(void)
2109 {
2110 //Oneway
2111 REG16_PM(REG_WARM_BOOT_IND) = REG_WARM_BOOT_IND_MAGIC;
2112
2113 return;
2114 }
HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel,const MS_U8 * pu8SecretKey,MS_U32 u32Size)2115 MS_BOOL HAL_CA_OTP_SetSecretKey(CA_SECRET_KEY eKeySel, const MS_U8 *pu8SecretKey, MS_U32 u32Size)
2116 {
2117
2118 MS_U32 secret_key[4] = {0};
2119 MS_U32 i, j, u32Addr;
2120 MS_U8 *p = (MS_U8 *)secret_key;
2121 switch(eKeySel)
2122 {
2123 case E_CA_SECRET_KEY1:
2124 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2125 break;
2126 case E_CA_SECRET_KEY2:
2127 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2128 break;
2129 case E_CA_SECRET_KEY3:
2130 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2131 break;
2132 case E_CA_SECRET_KEY4:
2133 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2134 break;
2135 case E_CA_SECRET_KEY5:
2136 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2137 break;
2138 case E_CA_SECRET_KEY6:
2139 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2140 break;
2141 case E_CA_SECRET_KEY7:
2142 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2143 break;
2144 case E_CA_SECRET_KEY8:
2145 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2146 break;
2147 default:
2148 return FALSE;
2149 }
2150
2151 if(sizeof(secret_key)>u32Size)
2152 {
2153 j = u32Size;
2154 }
2155 else
2156 {
2157 j=sizeof(secret_key);
2158 }
2159 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2160 {
2161 p[i] = pu8SecretKey[(j-1)-i]; // Array reverse, for user easy viewing
2162 }
2163
2164 for(i = 0; i < 4; i++)
2165 {
2166 if(HAL_CA_OTP_Write(u32Addr,secret_key[i]) == FALSE)
2167 {
2168 return FALSE;
2169 }
2170 u32Addr += 4;
2171 }
2172 return TRUE;
2173 }
2174
HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel,MS_U8 * pu8SecretKey,MS_U32 u32Size)2175 MS_BOOL HAL_CA_OTP_GetSecretKey(CA_SECRET_KEY eKeySel, MS_U8 *pu8SecretKey, MS_U32 u32Size)
2176 {
2177 MS_U32 secret_key[4] = {0};
2178 MS_U32 i, j, u32Addr;
2179 MS_U8 *p = (MS_U8 *)secret_key;
2180
2181 switch(eKeySel)
2182 {
2183 case E_CA_SECRET_KEY1:
2184 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey1].u32Addr;
2185 break;
2186 case E_CA_SECRET_KEY2:
2187 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey2].u32Addr;
2188 break;
2189 case E_CA_SECRET_KEY3:
2190 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey3].u32Addr;
2191 break;
2192 case E_CA_SECRET_KEY4:
2193 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey4].u32Addr;
2194 break;
2195 case E_CA_SECRET_KEY5:
2196 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey5].u32Addr;
2197 break;
2198 case E_CA_SECRET_KEY6:
2199 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey6].u32Addr;
2200 break;
2201 case E_CA_SECRET_KEY7:
2202 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey7].u32Addr;
2203 break;
2204 case E_CA_SECRET_KEY8:
2205 u32Addr = _HAL_CA_OTP_Addr[U_OTP_CAV_SecretKey8].u32Addr;
2206 break;
2207 default:
2208 return FALSE;
2209 }
2210 for(i = 0; i < 4; i++)
2211 {
2212 secret_key[i] = HAL_CA_OTP_Read(u32Addr);
2213 u32Addr += 4;
2214 }
2215
2216 if(sizeof(secret_key)>u32Size)
2217 {
2218 j = u32Size;
2219 }
2220 else
2221 {
2222 j=sizeof(secret_key);
2223 }
2224
2225 for(i = 0; i < sizeof(secret_key) && i < u32Size; i++)
2226 {
2227 pu8SecretKey[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2228 }
2229
2230 return TRUE;
2231 }
2232
HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel,const MS_U8 * pu8RSAKey,MS_U32 u32Size)2233 MS_BOOL HAL_CA_OTP_SetRSAKey(CA_RSA_KEY eKeySel, const MS_U8 *pu8RSAKey, MS_U32 u32Size)
2234 {
2235 MS_U32 RSA_key[64] = {0};
2236 MS_U32 i, u32Addr;
2237 MS_U8 *p = (MS_U8 *)RSA_key;
2238
2239 switch(eKeySel)
2240 {
2241 case E_CA_RSA_KEY0:
2242 return FALSE;
2243 case E_CA_RSA_KEY1:
2244 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2245 break;
2246 default:
2247 return FALSE;
2248 }
2249
2250 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2251 {
2252 p[i] = pu8RSAKey[i];
2253 }
2254 for(i = 0; i < 64; i++)
2255 {
2256 if(HAL_CA_OTP_Write(u32Addr,RSA_key[i]) == FALSE)
2257 {
2258 return FALSE;
2259 }
2260 u32Addr += 4;
2261 }
2262
2263 return TRUE;
2264 }
HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel,MS_U8 * pu8RSAKey,MS_U32 u32Size)2265 MS_BOOL HAL_CA_OTP_GetRSAKey(CA_RSA_KEY eKeySel, MS_U8 *pu8RSAKey, MS_U32 u32Size)
2266 {
2267 MS_U32 RSA_key[64] = {0};
2268 MS_U32 i, u32Addr;
2269 MS_U8 *p = (MS_U8 *)RSA_key;
2270
2271 switch(eKeySel)
2272 {
2273 case E_CA_RSA_KEY0:
2274 return FALSE;
2275 break;
2276 case E_CA_RSA_KEY1:
2277 u32Addr = _HAL_CA_OTP_Addr[U_OTP_RSA_1].u32Addr;
2278 break;
2279 default:
2280 return FALSE;
2281 }
2282 for(i = 0; i < 64; i++)
2283 {
2284 RSA_key[i] = HAL_CA_OTP_Read(u32Addr);
2285 u32Addr += 4;
2286 }
2287 for(i = 0; i < sizeof(RSA_key) && i < u32Size; i++)
2288 {
2289 pu8RSAKey[i] = p[i];
2290 }
2291
2292 return TRUE;
2293 }
2294
2295
HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort,const MS_U8 * pu8Password,MS_U32 u32Size)2296 MS_BOOL HAL_CA_OTP_SetDebugPortPassword(CA_DEBUG_PORT eDebugPort, const MS_U8 *pu8Password, MS_U32 u32Size)
2297 {
2298
2299 MS_U32 pwd[4] = {0};
2300 MS_U32 i, j, u32Addr;
2301 MS_U8 *p = (MS_U8 *)pwd;
2302
2303 switch(eDebugPort)
2304 {
2305 case E_CA_DEBUG_PORT_I2C:
2306 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2307 break;
2308 case E_CA_DEBUG_PORT_JTAG:
2309 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2310 break;
2311 case E_CA_DEBUG_PORT_SCAN:
2312 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2313 break;
2314 default:
2315 return FALSE;
2316 }
2317 if(sizeof(pwd)>u32Size)
2318 {
2319 j = u32Size;
2320 }
2321 else
2322 {
2323 j=sizeof(pwd);
2324 }
2325
2326 for(i = 0; i < sizeof(pwd) && i < u32Size; i++)
2327 {
2328 p[i] = pu8Password[(j-1)-i]; // Array reverse, for user easy viewing
2329 }
2330
2331
2332 for(i = 0; i < 4; i++)
2333 {
2334 if(HAL_CA_OTP_Write(u32Addr,pwd[i]) == FALSE)
2335 {
2336 return FALSE;
2337 }
2338 u32Addr += 4;
2339 }
2340
2341 return TRUE;
2342 }
2343
HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort,MS_U8 * pu8Password,MS_U32 u32Size)2344 MS_BOOL HAL_CA_OTP_GetDebugPortPassword(CA_DEBUG_PORT eDebugPort, MS_U8 *pu8Password, MS_U32 u32Size)
2345 {
2346 MS_U32 pwd[4] = {0};
2347 MS_U32 i, j, u32Addr;
2348 MS_U8 *p = (MS_U8 *)pwd;
2349
2350 switch(eDebugPort)
2351 {
2352 case E_CA_DEBUG_PORT_I2C:
2353 u32Addr = _HAL_CA_OTP_Addr[U_OTP_I2C_PWD].u32Addr;
2354 break;
2355 case E_CA_DEBUG_PORT_JTAG:
2356 u32Addr = _HAL_CA_OTP_Addr[U_OTP_EJTAG_PWD].u32Addr;
2357 break;
2358 case E_CA_DEBUG_PORT_SCAN:
2359 u32Addr = _HAL_CA_OTP_Addr[U_OTP_SCAN_PWD].u32Addr;
2360 break;
2361 default:
2362 return FALSE;
2363 }
2364 for(i = 0; i < 4; i++)
2365 {
2366 pwd[i] = HAL_CA_OTP_Read(u32Addr);
2367 u32Addr += 4;
2368 }
2369 if(sizeof(pwd)>u32Size)
2370 {
2371 j = u32Size;
2372 }
2373 else
2374 {
2375 j=sizeof(pwd);
2376 }
2377 for(i = 0; i < sizeof(pwd) &&i < u32Size; i++)
2378 {
2379 pu8Password[i] = p[(j-1)-i]; // Array reverse, for user easy viewing
2380 }
2381 return TRUE;
2382 }
2383
HAL_CA_MaxReservedSize(void)2384 MS_U32 HAL_CA_MaxReservedSize(void)
2385 {
2386 HAL_CA_DEBUG("Not Implement\n");
2387 return FALSE;
2388 }
2389
HAL_CA_OTP_WriteReserved(const MS_U8 * pu8RData,MS_U32 u32Size)2390 MS_BOOL HAL_CA_OTP_WriteReserved(const MS_U8 *pu8RData, MS_U32 u32Size)
2391 {
2392 MS_U32 u32rdata[32] = {0};
2393 MS_U32 i, u32Addr;
2394 MS_U32 u32ReservedSize = MAX_RESERVED_SIZE/4 ;
2395 MS_U8 *p = (MS_U8 *)u32rdata;
2396
2397 for(i = 0; i < sizeof(u32rdata) && i < u32Size; i++)
2398 {
2399 p[i] = pu8RData[i];
2400 }
2401
2402 u32Addr = _HAL_CA_OTP_Addr[U_OTP_REGION31].u32Addr;
2403 for(i = 0; i <u32ReservedSize; i++)
2404 {
2405 if(HAL_CA_OTP_Write(u32Addr,u32rdata[i]) == FALSE)
2406 {
2407 return FALSE;
2408 }
2409 u32Addr += 4;
2410 }
2411
2412 return TRUE;
2413 }
2414
HAL_CA_OTP_ReadReserved(MS_U8 * pu8RData,MS_U32 u32Size)2415 MS_BOOL HAL_CA_OTP_ReadReserved(MS_U8 *pu8RData, MS_U32 u32Size)
2416 {
2417 MS_U32 u32rdata[32] = {0};
2418 MS_U32 i, u32Addr;
2419 MS_U32 u32ReservedSize = MAX_RESERVED_SIZE/4 ;
2420 MS_U8 *p = (MS_U8 *)u32rdata;
2421
2422 u32Addr = _HAL_CA_OTP_Addr[U_OTP_REGION31].u32Addr;
2423 for(i = 0; i < u32ReservedSize; i++)
2424 {
2425 u32rdata[i] = HAL_CA_OTP_Read(u32Addr);
2426 u32Addr += 4;
2427 }
2428
2429 for(i = 0; i < sizeof(u32rdata) && i < u32Size; i++)
2430 {
2431 pu8RData[i] = p[i];
2432 }
2433
2434 return TRUE;
2435 }
2436