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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvNDS.c
98 /// @brief NDS Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102 //-------------------------------------------------------------------------------------------------
103 // Include Files
104 //-------------------------------------------------------------------------------------------------
105 #include "MsCommon.h"
106
107 #include "asmCPU.h"
108 #include "regNDS.h"
109 #include "drvNDS.h"
110 #include "halNDS.h"
111
112 #include "ddiNDS_HDI.h"
113
114 #include "nds.h"
115
116 #ifdef MSOS_TYPE_LINUX_KERNEL
117 #include <linux/delay.h>
118 #endif
119
120 //-------------------------------------------------------------------------------------------------
121 // Driver Compiler Options
122 //-------------------------------------------------------------------------------------------------
123
124
125 //-------------------------------------------------------------------------------------------------
126 // Local Defines
127 //-------------------------------------------------------------------------------------------------
128 #define NDS_SC_FIFO_SIZE (256 + 64) // Rx/Tx fifo size
129 #define NDS_SC_RX_REQ_MAX 32
130 #define NDS_SC_RX_TIMEOUT 1500//1600// 1000ms
131 #define NDS_SC_VCC_DELAY 10
132
133 #define NDS_SC_CHK_TIMER 500
134
135 #define NDS_SC_EVENT_CARD 0x00000001 // 0x00000010-0x00000019
136 #define NDS_SC_EVENT_RX 0x00000010
137 #define NDS_SC_EVENT_RX_OVERFLOW 0x00000020
138 #define NDS_SC_EVENT_RX_ERROR 0x00000040
139
140 #define NDS_SC_OS_AttachInterrupt(isr) MsOS_AttachInterrupt(NDS_INT_UART_CA, isr)
141 #define NDS_SC_OS_EnableInterrupt() MsOS_EnableInterrupt(NDS_INT_UART_CA);
142 #define NDS_SC_OS_DisableInterrupt() MsOS_DisableInterrupt(NDS_INT_UART_CA);
143 #define NDS_SC_OS_DetachInterrupt() MsOS_DetachInterrupt(NDS_INT_UART_CA);
144
145 #define NDS_SC_LOCK() { MsOS_ObtainMutex(_nds_sc_dev.s32Mutex, MSOS_WAIT_FOREVER); }
146 #define NDS_SC_UNLOCK() { MsOS_ReleaseMutex(_nds_sc_dev.s32Mutex); }
147 #define NDS_SC_ENTRY() { }
148 #define NDS_SC_RETURN(_ret) { return _ret; }
149 #define NDS_SC_RXQ_LOCK() { MsOS_ObtainMutex(_nds_sc_dev.s32MutexIdRx, MSOS_WAIT_FOREVER); }
150 #define NDS_SC_RXQ_UNLOCK() { MsOS_ReleaseMutex(_nds_sc_dev.s32MutexIdRx); }
151
152 #define SC_RX_TIMEOUT_ENABLE 0
153 #define SC_FLOWCTRL_ENABLE 1
154
155 #if 1 //defined(MS_DEBUG)
156 #define NDS_SC_DBG(_fmt, _args...) printf(_fmt, ##_args)
157 #else
158 #define NDS_SC_DBG(_fmt, _args...) { }
159 #endif
160
161
162 //-------------------------------------------------------------------------------------------------
163 // Local Structurs
164 //-------------------------------------------------------------------------------------------------
165 typedef struct _NDS_SC_Dev
166 {
167 // device info
168
169 // device identification
170
171 // device context
172 MS_BOOL bOpened;
173 MS_BOOL bCardRdy; // since Vcc is controlled by user
174 MS_BOOL bAborting;
175
176 MS_U8 Rxfifo[NDS_SC_FIFO_SIZE];
177 MS_U8 Txfifo[NDS_SC_FIFO_SIZE];
178 MS_U16 Rxfifo_r;
179 MS_U16 Rxfifo_w;
180 MS_U16 Txfifo_r;
181 MS_U16 Txfifo_w;
182
183 // system specified
184 MS_S32 s32DevEventId;
185 MS_S32 s32TaskId;
186 MS_S32 s32Mutex;
187 MS_S32 s32MutexIdRx;
188
189 NDS_SC_Clk clk;
190 NDS_SC_Param param;
191
192 } NDS_SC_Dev;
193
194
195 typedef struct _NDS_SC_Rx
196 {
197 // system specified
198 MS_BOOL bUse;
199 MS_S32 s32Len;
200 MS_S32 s32Num;
201 MS_BOOL bNullFilter;
202 MS_BOOL bFlowCtrl;
203 MS_U8 *pAddr;
204 MS_U32 u32Timeout;
205 } NDS_SC_Rx;
206
207
208 //-------------------------------------------------------------------------------------------------
209 // Global Variables
210 //-------------------------------------------------------------------------------------------------
211
212 #if 1 //[VERIFIER]
213 //TODO: remove it
214 extern MS_BOOL bEmmOverflow;
215 extern MS_U32 emm_overflow_time;
216 #endif
217
218
219 //-------------------------------------------------------------------------------------------------
220 // Local Variables
221 //-------------------------------------------------------------------------------------------------
222 static MS_U32 _nds_sc_stack[4096/4];
223
224 // Rx Request Queue
225 static NDS_SC_Rx _nds_sc_rxq[NDS_SC_RX_REQ_MAX];
226 static MS_U8 _nds_sc_rxq_read = 0; // User read queue (HDI)
227 static MS_U8 _nds_sc_rxq_cur = 0; // Current active queue (ISR)
228 static MS_U8 _nds_sc_rxq_next = 0; // The next non-used queue for request (HDI)
229
230 static NDS_SC_Dev _nds_sc_dev = {
231 .bOpened = FALSE,
232 .bCardRdy = FALSE,
233 .bAborting = FALSE,
234 .clk = E_NDS_SC_CLK_27M_D6,
235 .param.cbSetVcc = NULL,
236 .param.cbEvent = NULL,
237 .param.bCommDump = FALSE,
238 };
239
240 static MS_BOOL _nds_sc_cardin = FALSE;
241 static MS_BOOL _nds_sc_last_cardin = 2; // other than TRUE / FALSE
242 static MS_U16 _nds_sc_rx_cnt = 0; // for flow control
243 static MS_U8 _nds_sc_reg_ctrl = 0;
244
245
246 //-------------------------------------------------------------------------------------------------
247 // Debug Functions
248 //-------------------------------------------------------------------------------------------------
249
250
251 //-------------------------------------------------------------------------------------------------
252 // Local Functions
253 //-------------------------------------------------------------------------------------------------
254
NDS_SC_DBG_PrintData(MS_U8 * pu8Data,MS_U16 u16DataLen)255 void NDS_SC_DBG_PrintData(MS_U8 *pu8Data, MS_U16 u16DataLen)
256 {
257 int i;
258 //printf("(%d)>>", u16DataLen);
259 for (i = 0; i < u16DataLen; i++)
260 {
261 if ((i % 16) == 0)
262 {
263 NDS_SC_DBG("\n ");
264 }
265 NDS_SC_DBG(" %02X ", pu8Data[i]);
266 }
267 NDS_SC_DBG("\n");
268 }
269
270
_NDS_SC_SET_CTRL(MS_U8 bits)271 void _NDS_SC_SET_CTRL(MS_U8 bits)
272 {
273 //try
274 MS_U8 dbg;
275 dbg = _nds_sc_reg_ctrl | bits;
276 MS_U32 old_int = MsOS_DisableAllInterrupts();
277 //try
278
279 NDS_SC_OS_DisableInterrupt();
280 NDS_SC_LOCK();
281 _nds_sc_reg_ctrl |= bits;
282 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
283 NDS_SC_UNLOCK();
284 NDS_SC_OS_EnableInterrupt();
285
286 //try
287 old_int = MsOS_RestoreAllInterrupts(old_int);
288 if (dbg != _nds_sc_reg_ctrl)
289 {
290 while (1);
291 }
292 //try
293 }
294
_NDS_SC_CLR_CTRL(MS_U8 bits)295 void _NDS_SC_CLR_CTRL(MS_U8 bits)
296 {
297 //try
298 MS_U8 dbg;
299 dbg = _nds_sc_reg_ctrl & ~bits;
300 MS_U32 old_int = MsOS_DisableAllInterrupts();
301 //try
302
303 NDS_SC_OS_DisableInterrupt();
304 NDS_SC_LOCK();
305 _nds_sc_reg_ctrl &= ~(bits);
306 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
307 NDS_SC_UNLOCK();
308 NDS_SC_OS_EnableInterrupt();
309
310 //tt
311 old_int = MsOS_RestoreAllInterrupts(old_int);
312 if (dbg != _nds_sc_reg_ctrl)
313 {
314 while (1);
315 }
316 //tt
317 }
318
319
_NDS_SC_ResetRxIdx(void)320 static void _NDS_SC_ResetRxIdx(void)
321 {
322 MS_U32 i = 0;
323 for (i = 0; i < NDS_SC_RX_REQ_MAX; i++)
324 {
325 _nds_sc_rxq[i].bUse = FALSE;
326 //_smart_rx[i].pAddr = NULL;
327 _nds_sc_rxq[i].s32Num = 0;
328 _nds_sc_rxq[i].u32Timeout = 0;
329 _nds_sc_rxq[i].bFlowCtrl = 0;
330 _nds_sc_rxq[i].bNullFilter = 0;
331 _nds_sc_rxq[i].s32Len = 0;
332 }
333 _nds_sc_rxq_read = 0;
334 _nds_sc_rxq_cur = 0;
335 _nds_sc_rxq_next = 0;
336 _nds_sc_rx_cnt = 0;
337 }
338
339
_NDS_SC_Isr(InterruptNum eIntNum)340 static void _NDS_SC_Isr(InterruptNum eIntNum)
341 {
342 MS_U32 events = 0;
343 MS_U16 u16RegRead = 0, u16RegCtrl = 0;
344 MS_U8 u8Char;
345
346 // NDS_SC_OS_DisableInterrupt(); // @FIXME: why?
347
348 // Recieve all data in fifo
349 u16RegRead = CAM_REG(REG_CAM_UART_INT);
350 CAM_REG(REG_CAM_UART_INT) = (CAM_UART_INT_MASK_RESET | u16RegRead); // clear interrupt
351
352 if (u16RegRead & CAM_UART_INT_CD)
353 {
354 _nds_sc_dev.bCardRdy = FALSE;
355
356 // [NOTE] ICAM2 certification needs the Vcc to be OFF after removal.
357 _nds_sc_reg_ctrl &= ~(CAM_UART_CTRL_VCC_ACTIVE);
358 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
359
360 u16RegRead &= ~(CAM_UART_INT_CD);
361 MsOS_SetEvent(_nds_sc_dev.s32DevEventId, NDS_SC_EVENT_CARD);// Notify ISR event
362 }
363
364 // recv ALL bytes if avaiable
365 if (u16RegRead & (CAM_UART_INT_RX | CAM_UART_INT_RX_OVERFLOW | CAM_UART_INT_PARITY_ERR_RX))
366 {
367 if (u16RegRead & CAM_UART_INT_RX)
368 {
369 if (u16RegRead & CAM_UART_INT_RX_OVERFLOW)
370 {
371 events |= NDS_SC_EVENT_RX_OVERFLOW;
372 }
373 else if (u16RegRead & CAM_UART_INT_PARITY_ERR_RX)
374 {
375 events |= NDS_SC_EVENT_RX_ERROR;
376 }
377
378 while (1) // read all Rx data received regardless of any software status, e.g. bCardIn
379 {
380 u16RegCtrl = CAM_REG(REG_CAM_UART_CTRL);
381 if ((u16RegCtrl & CAM_UART_STAT_RX_RDY) /* && (_nds_sc_dev.bCardIn)*/)
382 {
383 MS_U32 u32tmp;
384
385 u8Char = CAM_REG(REG_CAM_UART_DATA);
386 _nds_sc_dev.Rxfifo[_nds_sc_dev.Rxfifo_w] = u8Char;
387 u32tmp = _nds_sc_dev.Rxfifo_w + 1;
388 #if 0
389 if ( (NDS_SC_FIFO_SIZE == u32tmp) && (_nds_sc_dev.Rxfifo_r != 0))
390 {
391 // Not overflow but wrap
392 _nds_sc_dev.Rxfifo_w = 0;
393 }
394 else if ( u32tmp != _nds_sc_dev.Rxfifo_r )
395 {
396 // Not overflow
397 _nds_sc_dev.Rxfifo_w = u32tmp;
398 }
399 else
400 {
401 break; //overflow
402 //_NDS_ASSERT_();
403 }
404 #else
405 if (u32tmp >= NDS_SC_FIFO_SIZE)
406 {
407 u32tmp = 0;
408 }
409
410 if (u32tmp != _nds_sc_dev.Rxfifo_r)
411 {
412 // Not overflow
413 _nds_sc_dev.Rxfifo_w = u32tmp;
414 }
415 else
416 {
417 MAsm_CPU_SwDbgBp();
418 break; // overflow
419 }
420 #endif
421
422 _nds_sc_rx_cnt--; // _nds_sc_rx_cnt > 0
423
424 #if SC_FLOWCTRL_ENABLE
425 // Do flow control by current rxq
426 // _nds_sc_rx_cur could be 2 over than _nds_sc_rx_read
427 if ( (_nds_sc_rx_cnt == 0) && (_nds_sc_rxq_cur != _nds_sc_rxq_next) )
428 {
429 // switch to next rxq
430 _nds_sc_rxq_cur++;
431 if (_nds_sc_rxq_cur >= (NDS_SC_RX_REQ_MAX-2))
432 {
433 _nds_sc_rxq_cur = 0;
434 }
435 if (_nds_sc_rxq_cur != _nds_sc_rxq_next)
436 {
437 _nds_sc_rx_cnt = _nds_sc_rxq[_nds_sc_rxq_cur].s32Len;
438 }
439 }
440
441 if (_nds_sc_rx_cnt != 0)
442 {
443 _nds_sc_reg_ctrl &= ~(CAM_UART_CTRL_FLOWCTRL); // open (high)
444 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
445 if (_nds_sc_rxq[_nds_sc_rxq_cur].bFlowCtrl)
446 {
447 _nds_sc_reg_ctrl |= (CAM_UART_CTRL_FLOWCTRL); // close (low)
448 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
449 }
450 }
451 else
452 {
453 // do nothing, flow control is be defined by the last byte
454 }
455
456 #else
457 if ((_nds_sc_rx_cnt != 0) && (_nds_sc_rxq[_nds_sc_rxq_read].bFlowCtrl))
458 {
459 _nds_sc_reg_ctrl &= ~(CAM_UART_CTRL_FLOWCTRL); // open (high)
460 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
461 //__asm__ __volatile__("nop;");
462 _nds_sc_reg_ctrl |= (CAM_UART_CTRL_FLOWCTRL); // close (low)
463 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
464 }
465 else
466 {
467 _nds_sc_rx_cnt = 0;
468 break;
469 }
470 #endif
471 }
472 else
473 {
474 break;
475 //_NDS_ASSERT_();
476 }
477 }
478 events |= NDS_SC_EVENT_RX;
479 }
480
481 MsOS_SetEvent(_nds_sc_dev.s32DevEventId, events);
482 u16RegRead &= ~(CAM_UART_INT_RX | CAM_UART_INT_RX_OVERFLOW | CAM_UART_INT_PARITY_ERR_RX);
483 }
484
485 // send ONE byte if avaiable
486 if (u16RegRead & (CAM_UART_INT_TX | CAM_UART_INT_PARITY_ERR_TX))
487 {
488 if (u16RegRead & CAM_UART_INT_PARITY_ERR_TX)
489 {
490 NDS_ASSERT(FALSE, , "NDS_ASSERT [%s]-[%d]\n", __FUNCTION__, __LINE__);
491 }
492 else
493 {
494 u16RegCtrl = CAM_REG(REG_CAM_UART_CTRL);
495 if (u16RegCtrl & CAM_UART_STAT_TX_RDY)
496 {
497 if(_nds_sc_dev.Txfifo_r != _nds_sc_dev.Txfifo_w)
498 {
499 CAM_REG(REG_CAM_UART_DATA) = _nds_sc_dev.Txfifo[_nds_sc_dev.Txfifo_r];
500 _nds_sc_dev.Txfifo[_nds_sc_dev.Txfifo_r] = 0xff;
501 _nds_sc_dev.Txfifo_r++;
502 if (NDS_SC_FIFO_SIZE == _nds_sc_dev.Txfifo_r)
503 {
504 _nds_sc_dev.Txfifo_r = 0;
505 }
506 }
507 }
508 }
509 u16RegRead &= ~(CAM_UART_INT_TX | CAM_UART_INT_PARITY_ERR_TX);
510 }
511
512 // for debugging
513 if (u16RegRead)
514 {
515 NDS_ASSERT(FALSE, , "NDS_ASSERT [%s]-[%d]\n", __FUNCTION__, __LINE__);
516 }
517
518 // IRQ handled
519 NDS_SC_OS_EnableInterrupt();
520 }
521
522
_NDS_SC_IsrTask(void)523 static void _NDS_SC_IsrTask(void)
524 {
525 MS_U8 u8Reg;
526 MS_U32 u32Events, u32Timer;
527
528 NDS_DBG("%s\n", __FUNCTION__);
529
530 while(1)
531 {
532 u32Events = 0;
533
534 #if SC_RX_TIMEOUT_ENABLE
535 MsOS_WaitEvent(_nds_sc_dev.s32DevEventId, 0xFFFF, &u32Events, E_OR_CLEAR, NDS_SC_CHK_TIMER);
536 #else
537 MsOS_WaitEvent(_nds_sc_dev.s32DevEventId, 0xFFFF, &u32Events, E_OR_CLEAR, MSOS_WAIT_FOREVER);
538 #endif
539
540 if (u32Events & NDS_SC_EVENT_CARD)
541 {
542 MsOS_DelayTask(10); // skip glitch
543
544 // event notification
545 u8Reg = CAM_REG(REG_CAM_UART_CTRL);
546 if (u8Reg & CAM_UART_STAT_DETECT)
547 {
548 _nds_sc_cardin = TRUE;
549 }
550 else
551 {
552 _nds_sc_cardin = FALSE;
553 }
554 if (_nds_sc_cardin)
555 {
556 if (_nds_sc_last_cardin == _nds_sc_cardin)
557 { //[NOTE] Since reset is control by upper level, the REMOVE event can never be LOST!!
558 // -- Jerry
559 //printf("ISR_SC_REMOVED_2\n");
560 CORECA_SmartCardComm(SC_REMOVED);
561 if (_nds_sc_dev.param.cbEvent)
562 {
563 _nds_sc_dev.param.cbEvent(E_NDS_SC_EVENT_CARD_REMOVED);
564 }
565 // MsOS_DelayTask(100);
566 }
567 //printf("ISR_SC_REMOVED\n");
568 CORECA_SmartCardComm(SC_INSERTED);
569 if (_nds_sc_dev.param.cbEvent)
570 {
571 _nds_sc_dev.param.cbEvent(E_NDS_SC_EVENT_CARD_INSERTED);
572 }
573 }
574 else
575 {
576 //printf("ISR_SC_REMOVED_1\n");
577 if (_nds_sc_last_cardin != _nds_sc_cardin)
578 {
579 CORECA_SmartCardComm(SC_REMOVED);
580 if (_nds_sc_dev.param.cbEvent)
581 {
582 _nds_sc_dev.param.cbEvent(E_NDS_SC_EVENT_CARD_REMOVED);
583 }
584 }
585 }
586 _nds_sc_last_cardin = _nds_sc_cardin;
587
588 } // NDS_SC_EVENT_CARD
589
590 if (u32Events & NDS_SC_EVENT_RX)
591 {
592 if ( (u32Events == (NDS_SC_EVENT_RX | NDS_SC_EVENT_RX_OVERFLOW))
593 && (_nds_sc_dev.bAborting != TRUE) )
594 {
595 printf("SC_COMM_OVERFLOW[%d]\n", __LINE__);
596 CORECA_SmartCardComm(SC_COMM_OVERFLOW);
597 }
598 if ( (u32Events == (NDS_SC_EVENT_RX | NDS_SC_EVENT_RX_ERROR))
599 && (_nds_sc_dev.bAborting != TRUE) )
600 {
601 printf("SC_PARITY[%d]\n", __LINE__);
602 CORECA_SmartCardComm(SC_PARITY);
603 }
604
605 if ( (_nds_sc_rxq_read != _nds_sc_rxq_next) && (_nds_sc_dev.bCardRdy) ) // incompleted Rx queue
606 {
607 while(1)
608 {
609 if (_nds_sc_dev.Rxfifo_w != _nds_sc_dev.Rxfifo_r) // data in fifo
610 {
611 u32Timer = 0;
612
613 if (_nds_sc_rxq[_nds_sc_rxq_read].bUse)
614 {
615 if (_nds_sc_dev.bCardRdy != TRUE)
616 {
617 break;
618 }
619
620 NDS_SC_RXQ_LOCK();
621 if ( (_nds_sc_rxq[_nds_sc_rxq_read].s32Len == 1)
622 && (_nds_sc_rxq[_nds_sc_rxq_read].bNullFilter == TRUE)
623 && (_nds_sc_dev.Rxfifo[_nds_sc_dev.Rxfifo_r] == 0x60) )
624 {
625 //NOTE:
626 // Will NULL only comes when the s32Len == 1?
627 // - jerry
628 _nds_sc_dev.Rxfifo_r++;
629
630 if (_nds_sc_dev.param.bCommDump)
631 {
632 NDS_SC_DBG("NULL(0x60)\n");
633 }
634 }
635 else
636 {
637 if (_nds_sc_rxq[_nds_sc_rxq_read].s32Num > 0)
638 {
639 // receive one byte from Rx FIFO
640 *(MS_U8 *)_nds_sc_rxq[_nds_sc_rxq_read].pAddr = _nds_sc_dev.Rxfifo[_nds_sc_dev.Rxfifo_r++];
641 _nds_sc_rxq[_nds_sc_rxq_read].s32Num--;
642 _nds_sc_rxq[_nds_sc_rxq_read].pAddr++;
643 }
644
645 // check Rx queue completion
646 if (_nds_sc_rxq[_nds_sc_rxq_read].s32Num <= 0)
647 {
648 // Dump communcation for NDS tests
649 if (_nds_sc_dev.param.bCommDump)
650 {
651 NDS_SC_DBG("RX= ");
652 NDS_SC_DBG_PrintData( (_nds_sc_rxq[_nds_sc_rxq_read].pAddr - _nds_sc_rxq[_nds_sc_rxq_read].s32Len),
653 _nds_sc_rxq[_nds_sc_rxq_read].s32Len);
654 }
655
656 // reset queue
657 _nds_sc_rxq[_nds_sc_rxq_read].bUse = FALSE;
658 _nds_sc_rxq[_nds_sc_rxq_read].s32Num = 0;
659 // next queue
660 _nds_sc_rxq_read++;
661 if (_nds_sc_rxq_read >= (NDS_SC_RX_REQ_MAX-2))
662 {
663 _nds_sc_rxq_read = 0;
664 }
665
666 if (_nds_sc_dev.bAborting == FALSE)
667 {
668 if (_nds_sc_dev.bCardRdy == TRUE)
669 {
670 // printf("SC_COMM_OK\n");
671 CORECA_SmartCardComm(SC_COMM_OK);
672 }
673 }
674 }
675 }
676 // wrap FIFO
677 if (_nds_sc_dev.Rxfifo_r >= NDS_SC_FIFO_SIZE)
678 {
679 _nds_sc_dev.Rxfifo_r = 0;
680 }
681 NDS_SC_RXQ_UNLOCK();
682
683 }
684 else // not bUsed
685 {
686 //_NDS_ASSERT_();
687 }
688 }
689 else
690 {
691 #if 1 //[VERIFIER] try '50' for verifier overnight instead of '1'
692 //TODO: more overnight & smartcard single test for verification
693 NDS_DELAY(1);
694 #endif
695 }
696
697 if ( (!_nds_sc_dev.bCardRdy) || (!_nds_sc_rxq[_nds_sc_rxq_read].bUse) )
698 {
699 break;
700 }
701 }
702 }
703 }
704
705 #if SC_RX_TIMEOUT_ENABLE // WaitEvent should have timer to support timeout
706 //---- Time Out ------
707 // @TODO reset the new u32Timeout for next queued read request
708 if (_nds_sc_rxq[_nds_sc_rxq_read].bUse == TRUE)
709 {
710 if (u32Timer > _nds_sc_rxq[_nds_sc_rxq_read].u32Timeout)
711 {
712 u32Timer = 0; // reset timer
713
714 NDS_SC_RXQ_LOCK();
715
716 // Dump communcation for NDS tests
717 if (_nds_sc_dev.param.bCommDump)
718 {
719 NDS_SC_DBG("RX= ");
720 NDS_SC_DBG_PrintData( (_nds_sc_rxq[_nds_sc_rxq_read].pAddr - (_nds_sc_rxq[_nds_sc_rxq_read].s32Len-_nds_sc_rxq[_nds_sc_rxq_read].s32Num)),
721 (_nds_sc_rxq[_nds_sc_rxq_read].s32Len-_nds_sc_rxq[_nds_sc_rxq_read].s32Num));
722 }
723
724 // reset queue
725 _nds_sc_rxq[_nds_sc_rxq_read].bUse = FALSE;
726 _nds_sc_rxq[_nds_sc_rxq_read].s32Num = 0;
727 // next queue
728 _nds_sc_rxq_read++;
729 if (_nds_sc_rxq_read >= (NDS_SC_RX_REQ_MAX-2))
730 {
731 _nds_sc_rxq_read = 0;
732 }
733 NDS_SC_RXQ_UNLOCK();
734
735 if ( (_nds_sc_dev.bAborting == FALSE)
736 && (_nds_sc_dev.bCardIn)
737 && (CAM_REG(REG_CAM_UART_CTRL) & CAM_UART_STAT_DETECT))
738 {
739 printf("SC_ERROR line %d\n", __LINE__);
740 CORECA_SmartCardComm(SC_ERROR); // time out
741 }
742
743 #if 0 // Only send one SC_ERROR and clear all the rest. But it may also resolved by AbortCommSession
744 NDS_SC_RXQ_LOCK();
745 while (_nds_sc_rxq[_nds_sc_rxq_read].bUse)
746 {
747 // reset queue
748 _nds_sc_rxq[_nds_sc_rxq_read].bUse = FALSE;
749 _nds_sc_rxq[_nds_sc_rxq_read].s32Num = 0;
750 // next queue
751 _nds_sc_rxq_read++;
752 if (_nds_sc_rxq_read >= (NDS_SC_RX_REQ_MAX-2))
753 {
754 _nds_sc_rxq_read = 0;
755 }
756 }
757 NDS_SC_RXQ_UNLOCK();
758 #endif
759 }
760 u32Timer += NDS_SC_CHK_TIMER;
761 }
762 #endif
763 }
764 }
765
766
767 //-------------------------------------------------------------------------------------------------
768 // Global Functions
769 //-------------------------------------------------------------------------------------------------
770
_NDS_SC_ResetFifo(void)771 void _NDS_SC_ResetFifo(void)
772 {
773 //printf("--- SmartNDS_ResetFifo ---\n");
774 NDS_SC_OS_DisableInterrupt();
775
776 // @TODO: is it possible to lost card detection interrupt becuase clear it?
777 CAM_REG(REG_CAM_UART_INT) = (CAM_UART_INT_MASK_RESET | CAM_UART_INT_ALL);
778
779 NDS_SC_RXQ_LOCK();
780 _nds_sc_dev.Rxfifo_r = 0;
781 _nds_sc_dev.Rxfifo_w = 0;
782 _NDS_SC_ResetRxIdx();
783 NDS_SC_RXQ_UNLOCK();
784
785 _nds_sc_dev.Txfifo_r = 0;
786 _nds_sc_dev.Txfifo_w = 0;
787 NDS_SC_OS_EnableInterrupt();
788 }
789
790
_NDS_SC_Write(MS_U8 * buf,MS_U32 len,MS_BOOL nfc)791 int _NDS_SC_Write(MS_U8 *buf, MS_U32 len, MS_BOOL nfc)
792 {
793 int i, retry;
794
795 NDS_SC_ENTRY();
796
797 if ( (len <= 0) || (_nds_sc_dev.bCardRdy != TRUE) )
798 {
799 NDS_SC_RETURN(0);
800 }
801
802 NDS_SC_OS_DisableInterrupt();
803 for (i = 1; i < len; i++)
804 {
805 if (_nds_sc_dev.bCardRdy != TRUE)
806 {
807 break;
808 }
809 _nds_sc_dev.Txfifo[_nds_sc_dev.Txfifo_w++] = buf[i];
810 if (_nds_sc_dev.Txfifo_w >= NDS_SC_FIFO_SIZE)
811 {
812 _nds_sc_dev.Txfifo_w = 0;
813 }
814
815 if (i >= len)
816 {
817 break;
818 }
819 }
820 NDS_SC_OS_EnableInterrupt();
821
822 // Flow Control
823 retry = 0;
824 while (!(CAM_REG(REG_CAM_UART_CTRL)&CAM_UART_STAT_TX_RDY))
825 {
826 if ( ((retry++) > 10) || (_nds_sc_dev.bCardRdy != TRUE) )
827 {
828 NDS_SC_OS_DisableInterrupt();
829 _nds_sc_dev.Txfifo_w = _nds_sc_dev.Txfifo_r;
830 NDS_SC_OS_EnableInterrupt();
831
832 NDS_SC_RETURN(0);
833 }
834 NDS_DELAY(1);
835 }
836 //printf("MStar. SC TX ing..\n");
837 CAM_REG(REG_CAM_UART_DATA) = buf[0];
838
839 NDS_SC_RETURN(i);
840
841 }
842
843
_NDS_SC_Read(MS_U8 * buf,MS_U32 len,MS_BOOL bnf,MS_BOOL bfc,MS_U32 timeout)844 int _NDS_SC_Read(MS_U8 *buf, MS_U32 len, MS_BOOL bnf, MS_BOOL bfc, MS_U32 timeout)
845 {
846 NDS_SC_ENTRY();
847
848 if ( (len > 255) || (len == 0) || (_nds_sc_dev.bCardRdy != TRUE) )
849 {
850 NDS_SC_RETURN(0);
851 }
852
853 NDS_SC_RXQ_LOCK();
854 if ( (_nds_sc_rxq[_nds_sc_rxq_next].bUse) || (buf == NULL) )
855 {
856 NDS_SC_RXQ_UNLOCK();
857 //_NDS_ASSERT_();
858 //GEN_EXCEP;
859 NDS_SC_RETURN(0);
860 }
861
862 _nds_sc_rxq[_nds_sc_rxq_next].pAddr = buf;
863 _nds_sc_rxq[_nds_sc_rxq_next].s32Num = len;
864 _nds_sc_rxq[_nds_sc_rxq_next].s32Len = len;
865 _nds_sc_rxq[_nds_sc_rxq_next].u32Timeout = timeout;
866 _nds_sc_rxq[_nds_sc_rxq_next].bNullFilter = bnf;
867 _nds_sc_rxq[_nds_sc_rxq_next].bFlowCtrl = bfc;
868
869 // Flow control
870 #if SC_FLOWCTRL_ENABLE
871
872 _nds_sc_rxq[_nds_sc_rxq_next].bUse = TRUE;
873
874 NDS_SC_OS_DisableInterrupt();
875 _nds_sc_rxq_next++;
876 if (_nds_sc_rxq_next >= (NDS_SC_RX_REQ_MAX-2))
877 {
878 _nds_sc_rxq_next = 0;
879 }
880 NDS_SC_OS_EnableInterrupt();
881
882 // @TODO: check read request queue overflow
883 {
884 //NDS_SC_OS_DisableInterrupt();
885 // read is protected by RXQ_LOCK, but cur is touched at ISR
886 if (_nds_sc_rxq_next == _nds_sc_rxq_read)
887 {
888 NDS_ERR("[%s]-[%d] -- sc_rxq vverflow\n", __FUNCTION__, __LINE__);
889 while(1);
890 }
891 //NDS_SC_OS_EnableInterrupt();
892 }
893
894 if (_nds_sc_rx_cnt == 0) // cur == next
895 {
896 //printf("DEBUG:rx_cnt==0\n");
897 //NOTE:
898 // rx_cnt == 0 iff cur == next
899 // there is no race condition between USER function and ISR
900 // -- jerry
901 _nds_sc_rx_cnt = len;
902
903 NDS_SC_OS_DisableInterrupt();
904 NDS_SC_LOCK();
905 _nds_sc_reg_ctrl &= ~(CAM_UART_CTRL_FLOWCTRL); // open (high)
906 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
907 if (bfc)
908 {
909 _nds_sc_reg_ctrl |= (CAM_UART_CTRL_FLOWCTRL); // close (low)
910 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
911 }
912 NDS_SC_UNLOCK();
913 NDS_SC_OS_EnableInterrupt();
914 }
915
916 #else
917 _nds_sc_rx_cnt = len;
918 _nds_sc_rxq_next++;
919 if (_nds_sc_rxq_next >= (NDS_SC_RX_REQ_MAX-2))
920 {
921 _nds_sc_rxq_next = 0;
922 }
923 #endif
924 NDS_SC_RXQ_UNLOCK();
925
926 if (_nds_sc_dev.bCardRdy != TRUE)
927 {
928 NDS_SC_RETURN(0);
929 }
930
931 NDS_SC_RETURN(len);
932 }
933
934
NDS_SC_Open(void)935 NDS_Result NDS_SC_Open(void)
936 {
937 if (CAM_REG(REG_CAM_UART_CTRL) & CAM_UART_STAT_DETECT)
938 {
939 _nds_sc_cardin = TRUE;
940 }
941 else
942 {
943 _nds_sc_cardin = FALSE;
944 }
945
946 // register interrupt handler//enable interrupt for Icam-2
947 NDS_SC_OS_AttachInterrupt(_NDS_SC_Isr);
948 NDS_SC_OS_EnableInterrupt();
949 CAM_REG(REG_CAM_UART_INT) = CAM_UART_INT_ALL;//(CAM_UART_INT_TX|CAM_UART_INT_RX|CAM_UART_INT_CD|CAM_UART_INT_RX_OVERFLOW);//0x3F;
950
951 //MsOS_SetEvent(_smart_dev.s32DevEventId, 0x0001);
952 _nds_sc_dev.bOpened = TRUE;
953 return E_NDS_OK;
954 }
955
956
NDS_SC_Close(void)957 NDS_Result NDS_SC_Close(void)
958 {
959 NDS_SC_OS_DisableInterrupt();
960 NDS_SC_OS_DetachInterrupt();
961
962 // clear interrupt
963 CAM_REG(REG_CAM_UART_INT) = (CAM_UART_INT_MASK_RESET | CAM_UART_INT_ALL);
964
965 _nds_sc_dev.bOpened = FALSE;
966 return E_NDS_OK;
967 }
968
969
NDS_SC_Init(NDS_SC_Param * param)970 NDS_Result NDS_SC_Init(NDS_SC_Param *param)
971 {
972 NDS_FUNC("[%s]-[%d] cbSetVcc:0x%08lX, cbEvent:0x%08lX\n", __FUNCTION__, __LINE__, (MS_U32)param->cbSetVcc, (MS_U32)param->cbEvent);
973
974 _nds_sc_reg_ctrl = 0;
975 CAM_REG(REG_CAM_UART_CTRL) = _nds_sc_reg_ctrl;
976
977 _nds_sc_dev.param.cbSetVcc = param->cbSetVcc;
978 _nds_sc_dev.param.cbEvent = param->cbEvent;
979 _nds_sc_dev.param.bCommDump = param->bCommDump;
980 HAL_NDS_SC_Init(param);
981
982 _NDS_SC_ResetFifo();
983 //SmartNDS_ResetRxIdx();
984 //NDS_SC_OS_DisableInterrupt();
985 //NDS_SC_OS_DetachInterrupt();
986
987
988 // Initialize inter-process variable --------------------------------------
989 _nds_sc_dev.s32DevEventId = MsOS_CreateEventGroup("DevSmart_Event");
990 if (_nds_sc_dev.s32DevEventId < 0)
991 {
992 MsOS_DeleteTask(_nds_sc_dev.s32TaskId);
993 return E_NDS_FAIL;
994 }
995
996 _nds_sc_dev.s32Mutex = MsOS_CreateMutex(E_MSOS_FIFO, "NDS_SC_MutexRx", MSOS_PROCESS_SHARED);
997 if (_nds_sc_dev.s32Mutex < 0)
998 {
999 MsOS_DeleteEventGroup(_nds_sc_dev.s32DevEventId);
1000 MsOS_DeleteTask(_nds_sc_dev.s32TaskId);
1001 return E_NDS_FAIL;
1002 }
1003
1004 _nds_sc_dev.s32MutexIdRx = MsOS_CreateMutex(E_MSOS_FIFO, "NDS_SC_MutexRx", MSOS_PROCESS_SHARED);
1005 if (_nds_sc_dev.s32MutexIdRx < 0)
1006 {
1007 MsOS_DeleteMutex(_nds_sc_dev.s32Mutex);
1008 MsOS_DeleteEventGroup(_nds_sc_dev.s32DevEventId);
1009 MsOS_DeleteTask(_nds_sc_dev.s32TaskId);
1010 return E_NDS_FAIL;
1011 }
1012
1013 _nds_sc_dev.s32TaskId = MsOS_CreateTask( (TaskEntry) _NDS_SC_IsrTask,
1014 NULL,
1015 #if 1 //[VERIFIER]
1016 //TODO: try to be lower-priority for system banlance and smartcard single test for verification
1017 (TaskPriority) (E_TASK_PRI_SYS+2),
1018 #else
1019 (TaskPriority) (E_TASK_PRI_SYS),
1020 #endif
1021 TRUE,
1022 _nds_sc_stack,
1023 4096,
1024 "NDS_SC_IsrTask");
1025
1026 return E_NDS_OK;
1027 }
1028
1029
NDS_SC_Exit(void)1030 NDS_Result NDS_SC_Exit(void)
1031 {
1032 MsOS_DeleteTask(_nds_sc_dev.s32TaskId);
1033 MsOS_DeleteMutex(_nds_sc_dev.s32MutexIdRx);
1034 MsOS_DeleteMutex(_nds_sc_dev.s32Mutex);
1035 MsOS_DeleteEventGroup(_nds_sc_dev.s32DevEventId);
1036
1037 HAL_NDS_SC_Exit();
1038
1039 return E_NDS_FAIL;
1040 }
1041
1042
1043 // 6.3.3
HDICA_SetCardClockDivisor(NDS_BYTE clock_divisor)1044 NDS_STATUS HDICA_SetCardClockDivisor(NDS_BYTE clock_divisor)
1045 {
1046 NDS_FUNC("[%s]-[%d] -- clock_divisor[%d]\n", __FUNCTION__, __LINE__, clock_divisor);
1047
1048 // ND-T189
1049 switch (clock_divisor)
1050 {
1051 case HIGHEST_CLOCK : // 13.5 MHz
1052 _nds_sc_dev.clk = E_NDS_SC_CLK_27M_D2;
1053 break;
1054 case MEDIUM_CLOCK : // 6.75 MHz
1055 _nds_sc_dev.clk = E_NDS_SC_CLK_27M_D4;
1056 break;
1057 case LOWEST_CLOCK : // 4.5 MHz
1058 _nds_sc_dev.clk = E_NDS_SC_CLK_27M_D6;
1059 break;
1060 default:
1061 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1062 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1063 }
1064
1065 if (!HAL_NDS_SC_SetClockDivisor(_nds_sc_dev.clk))
1066 {
1067 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1068 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1069 }
1070
1071 MsOS_DelayTask(10);
1072
1073 return CA_OK;
1074 }
1075
1076
1077 // 6.3.4
HDICA_SetConvention(NDS_BYTE convention)1078 NDS_STATUS HDICA_SetConvention (NDS_BYTE convention)
1079 {
1080 NDS_FUNC("[%s]-[%d] -- convention[%d] \n", __FUNCTION__, __LINE__, convention);
1081
1082 switch (convention)
1083 {
1084 case HDICA_CONVENTION_INVERSE:
1085 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_CONV_DIRECT);
1086 break;
1087 case HDICA_CONVENTION_DIRECT:
1088 _NDS_SC_SET_CTRL(CAM_UART_CTRL_CONV_DIRECT);
1089 break;
1090 default:
1091 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1092 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1093 }
1094
1095 return CA_OK;
1096 }
1097
1098
1099 // 6.3.5
HDICA_SetUartBaudRate(NDS_BYTE baud_rate)1100 NDS_STATUS HDICA_SetUartBaudRate (NDS_BYTE baud_rate)
1101 {
1102 MS_U16 n;
1103 MS_U32 br, div;
1104
1105 NDS_FUNC("[%s]-[%d] -- baud_rate[%d]\n", __FUNCTION__, __LINE__, baud_rate);
1106
1107 // Real baudrate (BR) for ICAM2_clk = 50 MHz, SM_clk = 27MHz/6 = 4.5 MHz
1108
1109 br = 580645; // Nominal BAUD_RATE (153600) for HIGH_CLOCK (13.5 MHz) : 13.5 * 153600 / 3.5712
1110 div = 1;
1111 switch (_nds_sc_dev.clk)
1112 {
1113 case E_NDS_SC_CLK_27M_D2:
1114 // do nothing
1115 break;
1116 case E_NDS_SC_CLK_27M_D4:
1117 div = 2;
1118 break;
1119 case E_NDS_SC_CLK_27M_D6:
1120 default:
1121 div = 3;
1122 break;
1123 }
1124
1125 switch (baud_rate)
1126 {
1127 case HDICA_BAUD_RATE_9600:
1128 div = div << 1;
1129 case HDICA_BAUD_RATE_19200:
1130 div = div << 1;
1131 case HDICA_BAUD_RATE_38400:
1132 div = div << 1;
1133 case HDICA_BAUD_RATE_76800:
1134 div = div << 1;
1135 case HDICA_BAUD_RATE_153600:
1136 // do nothing
1137 break;
1138 case HDICA_BAUD_RATE_223200:
1139 default:
1140 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1141 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1142 }
1143
1144 n = NDS_CAM_CLK / br * div; // clk / (br / div)
1145 /*
1146 switch(_nds_sc_dev.clk)
1147 {
1148 case E_NDS_SC_CLK_27M_D2:
1149 clkdiv = 72580; // 72580.5
1150 break;
1151 case E_NDS_SC_CLK_27M_D4:
1152 clkdiv = 36290; // 36290.25
1153 break;
1154 case E_NDS_SC_CLK_27M_D6:
1155 default:
1156 clkdiv = 24193; // 24193.5 (BR) for
1157 break;
1158 }
1159
1160 // N = MCLK / BReal
1161 switch (baud_rate)
1162 {
1163 case HDICA_BAUD_RATE_153600:
1164 //div = (div>>1) + (div&0x1);
1165 n = (clk/193548)-2 ;
1166 break;
1167 case HDICA_BAUD_RATE_76800:
1168 //div = (div>>1) + (div&0x1);
1169 n = (clk/96774)-2 ;
1170 break;
1171 case HDICA_BAUD_RATE_38400:
1172 //div = (div>>1) + (div&0x1);
1173 n = (clk/48387)-2 ;
1174 break;
1175 case HDICA_BAUD_RATE_19200:
1176 //div = (div>>1) + (div&0x1);
1177 n = (clk/clkdiv)-2 ;
1178 break;
1179 case HDICA_BAUD_RATE_9600:
1180 n = (clk/12096)-2 ;
1181 break;
1182 case HDICA_BAUD_RATE_223200:
1183 default:
1184 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1185 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1186 }
1187 */
1188
1189 n = n - 2;
1190 CAM_REG(REG_CAM_UART_BDRT_L) = n & 0xFF;
1191 CAM_REG(REG_CAM_UART_BDRT_H) = n >> 8;
1192
1193 return CA_OK;
1194 }
1195
1196
1197 // 6.3.6
HDICA_SetVccLevel(NDS_BYTE vcc_level)1198 NDS_STATUS HDICA_SetVccLevel(NDS_BYTE vcc_level)
1199 {
1200 NDS_FUNC("[%s]-[%d] -- vcc_level[%d]\n", __FUNCTION__, __LINE__, vcc_level);
1201
1202 if (!_nds_sc_dev.param.cbSetVcc)
1203 {
1204 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1205 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1206 }
1207
1208 switch (vcc_level)
1209 {
1210 case HDICA_VCC_3V:
1211 if (FALSE == _nds_sc_dev.param.cbSetVcc(FALSE))
1212 {
1213 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1214 }
1215 break;
1216 case HDICA_VCC_5V:
1217 if (FALSE == _nds_sc_dev.param.cbSetVcc(TRUE))
1218 {
1219 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1220 }
1221 break;
1222 }
1223
1224 return CA_OK;
1225
1226 /*
1227 switch (vcc_level)
1228 {
1229 case HDICA_VCC_3V:
1230 *((volatile unsigned int*)0xBF203CC0) = 0x0B00;//TODO:: GPIO_OEN pad enable
1231 *((volatile unsigned int*)0xBF203CC0) |= 0xB000;//TODO:: GPIO
1232 break;
1233 case HDICA_VCC_5V:
1234
1235 *((volatile unsigned int*)0xBF203CC0) = 0x4F00;//TODO:: GPIO_OEN pad enable
1236 *((volatile unsigned int*)0xBF203CC0) &= ~0xB000;//TODO:: GPIO
1237 break;
1238 default:
1239 }
1240 */
1241
1242 return CA_OK;
1243 }
1244
1245 // 6.3.7
HDICA_SetVcc(NDS_BYTE vcc_switch)1246 NDS_STATUS HDICA_SetVcc (NDS_BYTE vcc_switch)
1247 {
1248 NDS_FUNC("[%s]-[%d] -- vcc_switch[%d]\n", __FUNCTION__, __LINE__, vcc_switch);
1249
1250 if (_nds_sc_dev.bOpened)
1251 {
1252 NDS_SC_RXQ_LOCK(); // for SetVcc, bCardIn
1253 {
1254 if (vcc_switch == HDICA_VCC_ON) //(HDICA_VCC_ON)
1255 {
1256 // NDS_DBG("HDICA_VCC_ON\n");
1257
1258 //[NOTE]
1259 // When ACTIVE, only remove could be detected.
1260 // When DEACTIVE, both remove & insert could be detected.
1261 // If the card is removed and Vcc is ON, the DETECT will never work
1262 // -- Jerry
1263 _NDS_SC_SET_CTRL(CAM_UART_CTRL_VCC_ACTIVE);
1264 if ( !(CAM_REG(REG_CAM_UART_CTRL) & CAM_UART_STAT_DETECT) )
1265 {
1266 // NDS_DBG("HDICA_VCC_ON[FAIL]\n");
1267 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_VCC_ACTIVE);
1268 NDS_SC_RXQ_UNLOCK(); // for SetVcc, bCardIn
1269 return CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW;
1270 }
1271 #ifdef MSOS_TYPE_LINUX_KERNEL
1272 mdelay(NDS_SC_VCC_DELAY);
1273 #else
1274 MsOS_DelayTask(NDS_SC_VCC_DELAY);
1275 #endif
1276
1277 _nds_sc_dev.bAborting = FALSE;
1278 _nds_sc_dev.bCardRdy = TRUE;
1279 }
1280 else
1281 {
1282 // NDS_DBG("HDICA_VCC_OFF\n");
1283 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_VCC_ACTIVE);
1284
1285 #ifdef MSOS_TYPE_LINUX_KERNEL
1286 mdelay(10);
1287 #else
1288 MsOS_DelayTask(10);
1289 #endif
1290 }
1291 }
1292 NDS_SC_RXQ_UNLOCK(); // for SetVcc, bCardIn
1293
1294 _NDS_SC_ResetFifo();
1295 }
1296
1297 return CA_OK;
1298 }
1299
1300
1301 // 6.3.8
HDICA_SetVpp(NDS_BYTE vpp_switch)1302 NDS_STATUS HDICA_SetVpp (NDS_BYTE vpp_switch)
1303 {
1304 NDS_FUNC("[%s][%d]\n", __FUNCTION__, __LINE__);
1305
1306 if (vpp_switch == HDICA_VCC_ON)
1307 {
1308 _NDS_SC_SET_CTRL(CAM_UART_CTRL_VPP_ACTIVE);
1309 }
1310 else
1311 {
1312 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_VPP_ACTIVE);
1313 }
1314
1315 return CA_OK;
1316 }
1317
1318
1319 // 6.3.9
HDICA_SetGuardTime(NDS_BYTE guard_time)1320 NDS_STATUS HDICA_SetGuardTime (NDS_BYTE guard_time)
1321 {
1322 NDS_FUNC("[%s]-[%d] -- guard_time[%d]\n", __FUNCTION__, __LINE__, guard_time);
1323
1324 CAM_REG(REG_CAM_UART_GUARD) = guard_time;
1325
1326 return CA_OK;
1327 }
1328
1329
1330 // 6.3.10
HDICA_GetInputByte(NDS_BYTE * input_byte)1331 NDS_STATUS HDICA_GetInputByte (NDS_BYTE *input_byte)
1332 {
1333 NDS_FUNC("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1334
1335 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1336 }
1337
1338
1339 // 6.3.11
HDICA_PutOutputByte(NDS_BYTE output_byte)1340 NDS_STATUS HDICA_PutOutputByte (NDS_BYTE output_byte)
1341 {
1342 NDS_FUNC("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1343
1344 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1345 }
1346
1347
1348 MS_U32 sc_poll_time = 0;
1349
1350 // 6.3.12
HDICA_ResetCard(NDS_BYTE reset_switch)1351 NDS_STATUS HDICA_ResetCard (NDS_BYTE reset_switch)
1352 {
1353 NDS_FUNC("[%s]-[%d] -- reset_switch[%d]\n", __FUNCTION__, __LINE__, reset_switch);
1354
1355 #if 0 //[VERIFIER]
1356 // Debug Only
1357 MS_U32 time = MsOS_GetSystemTime();
1358 printf("HDICA_ResetCard %ld poll:%ld overflow:%ld\n", time, time-sc_poll_time, time-emm_overflow_time);
1359 #else
1360 printf("HDICA_ResetCard %ld\n", MsOS_GetSystemTime());
1361 #endif
1362
1363 switch (reset_switch)
1364 {
1365 case ACTIVE:
1366 _NDS_SC_SET_CTRL(CAM_UART_CTRL_RST);
1367 break;
1368
1369 case INACTIVE:
1370 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_RST);
1371 break;
1372
1373 case RESET_CYCLE:
1374 MsOS_DelayTask(10); /* Delay for Vcc to rise */
1375 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_RST);
1376 MsOS_DelayTask(5);
1377 _NDS_SC_SET_CTRL(CAM_UART_CTRL_RST);
1378 MsOS_DelayTask(5);
1379 //CAM_REG(REG_CAM_UART_CTRL) = 0;//_NDS_SC_Ctrl_Reg;
1380 //MsOS_DelayTask(2); /* should be 10 msec - Zvika */
1381
1382 /* perform card reset cycle */
1383 /* enable RX interrupts (should already be enabled!) */
1384 //ICAM_RegisterWrite(SmartCardICAM, ICAM_UART_INT, IC_UI_DETECT_INT + IC_UI_RX_INT + IC_UI_RX_OV_INT);
1385 CAM_REG(REG_CAM_UART_INT) = CAM_UART_INT_ALL; //enable (CAM_UART_INT_TX|CAM_UART_INT_RX|CAM_UART_INT_CD|CAM_UART_INT_RX_OVERFLOW);
1386
1387 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_RST);
1388
1389 //printf("================> RESET VAR:[%02X]\n", _nds_sc_reg_ctrl);
1390 break;
1391
1392 default:
1393 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1394 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER;
1395 }
1396
1397 return CA_OK;
1398 }
1399
1400
1401 // 6.3.13
HDICA_GetUartStatus(NDS_BYTE * uart_status)1402 NDS_STATUS HDICA_GetUartStatus (NDS_BYTE *uart_status)
1403 {
1404 *uart_status = 0;
1405
1406 if (CAM_REG(REG_CAM_UART_CTRL) & CAM_UART_STAT_TX_RDY)
1407 {
1408 *uart_status |= HDICA_UART_STATUS_TX_IS_READY; /* Bit 0 */
1409 }
1410
1411 if (CAM_REG(REG_CAM_UART_CTRL) & CAM_UART_STAT_RX_RDY)
1412 {
1413 *uart_status |= HDICA_UART_STATUS_RX_IS_READY; /* Bit 1 */
1414 }
1415
1416 if (CAM_REG(REG_CAM_UART_INT) & CAM_UART_INT_PARITY_ERR_RX)
1417 {
1418 *uart_status |= HDICA_UART_STATUS_RCV_PARITY_ERROR; /* Bit 2 */
1419 }
1420
1421 if (CAM_REG(REG_CAM_UART_INT) & CAM_UART_INT_RX_OVERFLOW)
1422 {
1423 *uart_status |= HDICA_UART_STATUS_OVERFLOW; /* Bit 3 */
1424 }
1425
1426 if (CAM_REG(REG_CAM_UART_INT) & CAM_UART_INT_PARITY_ERR_TX)
1427 {
1428 *uart_status |= HDICA_UART_STATUS_TX_PARITY_ERROR; /* Bit 4 */
1429 }
1430
1431 if (_nds_sc_reg_ctrl & CAM_UART_CTRL_CONV_DIRECT)
1432 {
1433 *uart_status |= HDICA_UART_STATUS_CONVENTION_DIRECT; /* Bit 5 */
1434 }
1435
1436 if (CAM_REG(REG_CAM_UART_CTRL) & CAM_UART_STAT_INT_PEND)
1437 {
1438 *uart_status |= HDICA_UART_STATUS_INTERRUPT_PENDING; /* Bit 6 */
1439 }
1440
1441 if (CAM_REG(REG_CAM_UART_CTRL) & CAM_UART_STAT_DETECT)
1442 {
1443 *uart_status |= HDICA_UART_STATUS_CARD_INSERTED; /* Bit 7 */
1444 }
1445
1446 NDS_FUNC("[%s]-[%d] -- status[0x%x]\n", __FUNCTION__, __LINE__, *uart_status);
1447
1448 return CA_OK;
1449 }
1450
1451
1452 // 6.3.14
HDICA_SetUartCommand(NDS_BYTE pin_mask)1453 NDS_STATUS HDICA_SetUartCommand (NDS_BYTE pin_mask)
1454 {
1455 NDS_FUNC("[%s]-[%d]\n", __FUNCTION__, __LINE__);
1456
1457 CAM_REG(REG_CAM_UART_COM) = pin_mask;
1458
1459 if (pin_mask & (CAM_UART_COM_C4 | CAM_UART_COM_C8))
1460 {
1461 HAL_NDS_SC_SetUartC48(TRUE);
1462 }
1463 else
1464 {
1465 HAL_NDS_SC_SetUartC48(FALSE);
1466 }
1467
1468 return CA_OK;
1469 }
1470
1471
1472 // 6.3.15
HDICA_SendAndReceiveBytesSession(NDS_BYTE * xmt_ptr,NDS_BYTE xmit_length,CAHDI_BOOLEAN null_filter,CAHDI_BOOLEAN use_flow_control,NDS_BYTE * rcv_ptr,NDS_BYTE rcv_length)1473 NDS_STATUS HDICA_SendAndReceiveBytesSession (NDS_BYTE *xmt_ptr,
1474 NDS_BYTE xmit_length,
1475 CAHDI_BOOLEAN null_filter,
1476 CAHDI_BOOLEAN use_flow_control,
1477 NDS_BYTE *rcv_ptr,
1478 NDS_BYTE rcv_length)
1479 {
1480 MS_U32 len;
1481
1482 NDS_FUNC("[%s]-[%d] -- xmit[%d], rcv[%d]\n", __FUNCTION__, __LINE__, xmit_length, rcv_length);
1483
1484 // check busy
1485 if (_nds_sc_dev.bAborting)
1486 {
1487 return CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW;
1488 }
1489
1490 // Dump communcation for NDS tests
1491 if (_nds_sc_dev.param.bCommDump)
1492 {
1493 NDS_SC_DBG("TX= ");
1494 NDS_SC_DBG_PrintData(xmt_ptr, xmit_length);
1495 }
1496
1497 #if 1 // debug
1498 if (xmt_ptr[0] == 0x48) // 0x40, 0x54, 0x5c
1499 {
1500 switch (xmt_ptr[1])
1501 {
1502 case 0x5C:
1503 //sc_poll_time = MsOS_GetSystemTime();
1504 printf("NDS_POLL(%02X)\n", xmt_ptr[1]);
1505 break;
1506 default:
1507 break;
1508 }
1509 }
1510 #endif // debug
1511
1512 // Rx
1513 len = _NDS_SC_Read(rcv_ptr, rcv_length, null_filter, use_flow_control, NDS_SC_RX_TIMEOUT);
1514 if (len != rcv_length)
1515 {
1516 return CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW;
1517 }
1518
1519 // Tx
1520 if ( (_NDS_SC_Write(xmt_ptr, xmit_length, use_flow_control) <= 0) ||
1521 (_nds_sc_dev.bAborting) )
1522 {
1523 return CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW;
1524 }
1525
1526 #if 1 //[VERIFIER]
1527 //TODO: check if delay necessary and smartcard single test
1528 MsOS_DelayTask(5); // yield for ISR_Task
1529 #endif
1530
1531 return CA_OK;
1532 }
1533
1534
HDICA_ReceiveBytesSession(CAHDI_BOOLEAN null_filter,CAHDI_BOOLEAN use_flow_control,NDS_BYTE * rcv_ptr,NDS_BYTE rcv_length)1535 NDS_STATUS HDICA_ReceiveBytesSession (CAHDI_BOOLEAN null_filter,
1536 CAHDI_BOOLEAN use_flow_control,
1537 NDS_BYTE *rcv_ptr,
1538 NDS_BYTE rcv_length)
1539 {
1540 MS_U32 len;
1541
1542 NDS_FUNC("[%s]-[%d] rcv[%d]\n", __FUNCTION__, __LINE__, rcv_length);
1543
1544 // check busy
1545 if (_nds_sc_dev.bAborting)
1546 {
1547 return CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW;
1548 }
1549
1550 // Flow control
1551 #if SC_FLOWCTRL_ENABLE
1552 #else
1553 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_FLOWCTRL); // open (high)
1554 if (bfc)
1555 {
1556 _NDS_SC_SET_CTRL(CAM_UART_CTRL_FLOWCTRL); // close (low)
1557 }
1558 #endif
1559
1560 // Rx
1561 len = _NDS_SC_Read(rcv_ptr, rcv_length, null_filter, use_flow_control, NDS_SC_RX_TIMEOUT);
1562 if (len != rcv_length)
1563 {
1564 return CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW;
1565 }
1566
1567 #if 1 //[VERIFIER]
1568 //TODO: check if delay necessary and smartcard single test
1569 MsOS_DelayTask(5); // yield for ISR_Task
1570 #endif
1571
1572 return CA_OK;
1573 }
1574
1575
HDICA_AbortSmartCardCommSession(void)1576 NDS_STATUS HDICA_AbortSmartCardCommSession (void)
1577 {
1578 NDS_FUNC("[%s]-[%d] \n", __FUNCTION__, __LINE__);
1579
1580 printf("HDICA_AbortSmartCardCommSession\n");
1581
1582 _nds_sc_dev.bAborting = TRUE;
1583 //tt
1584 // disable flow control
1585 _NDS_SC_CLR_CTRL(CAM_UART_CTRL_FLOWCTRL); // open (high)
1586 //tt
1587
1588 _NDS_SC_ResetFifo();
1589
1590 _nds_sc_dev.bAborting = FALSE;
1591
1592 return CA_OK;
1593 }
1594
1595
1596