1 2 3 #include "MsCommon.h" 4 5 #ifdef MSOS_TYPE_LINUX 6 #include "string.h" 7 #endif 8 9 10 #if 0 11 12 #include "asmCPU.h" 13 #include "regNDS.h" 14 #include "drvNDS.h" 15 #include "halNDS.h" 16 #include "../rasp/regRASP.h" 17 #include "../rasp/halRASP.h" 18 #include "../tsp2/drvTSP2.h" 19 20 #include "ddiNDS_HDI.h" 21 22 #include "nds.h" 23 24 //------------------------------------------------------------------------// 25 // Macro Definition 26 //------------------------------------------------------------------------// 27 28 #define RASP_INT_EVENT_ALL (RASP_INT_EFRAME_RD_OVF | RASP_INT_EFRAME_WT_OVF| \ 29 /*RASP_INT_STR2MIU|*/RASP_INT_PAYLD2MIU | RASP_INT_ECM2MIU|\ 30 RASP_INT_TIME_WATER_MARK|RASP_INT_EVENT_WATER_MARK |\ 31 RASP_INT_ECM_PKT_RDY ) 32 33 34 #define NDS_RASP_TASK_STACK_SIZE (1024 * 4 ) 35 36 37 38 39 #define NDS_RASP_ECM_OVERFLOW_SHIFT 0x00000016 40 41 #define NDS_RASP_EVENT_ALL 0xFFFFFFFF 42 43 44 //------------------------------------------------------------------------// 45 // Local Structure definition 46 //------------------------------------------------------------------------// 47 48 typedef struct 49 { 50 51 MS_U16 pid ; 52 MS_U16 ecmid; 53 MS_U8 ecm_ctrl; 54 MS_U32 Xconn; 55 MS_BOOL b_defined; 56 57 } NDS_RASP_ECM_FLT; 58 59 //------------------------------------------------------------------------// 60 // Variable declaration 61 //------------------------------------------------------------------------// 62 63 64 static MS_U8 *_rasp_ecm_addr[RASP_NUM] ;//{[0 ... (RASP_NUM)] = NULL } ; 65 66 static MS_U32 _nds_rasp_eventid = -1 , _nds_rasp_taskid = -1 ; 67 68 MS_U8 _u8RaspEcmBuf[RASP_NUM][NDS_CAM_ECM_FLT_NUM][2][NDS_CAM_FLT_BUF_SIZE]; 69 70 NDS_RASP_ECM_FLT _rasp_ecm_flt[RASP_NUM][NDS_CAM_ECM_FLT_NUM]; 71 72 static MS_U32 _nds_rasp_stack[NDS_RASP_TASK_STACK_SIZE/sizeof(MS_U32)]; 73 74 #ifdef MSOS_TYPE_LINUX_KERNEL 75 static irqreturn_t _NDS_RASP_Isr(int irq, void *dev_id); 76 #else 77 static void _NDS_RASP_Isr(InterruptNum eIntNum); 78 #endif 79 80 static void _NDS_RASP_IsrTask(void); 81 82 // -----------------------------------------------------------------------// 83 // 84 // RASP LDI Driver IMPLEMENTATION 85 // 86 // -----------------------------------------------------------------------// 87 XSTATUS RASPLDI_GetCapabilities(RASP_CAPS *RaspCaps) 88 { 89 90 // [FIXME] 91 RaspCaps->Supported_Event = 0x800001FF ; 92 RaspCaps->Event_Timer_Rate = 0x200; //[FIXME] 93 RaspCaps->Num_Rasps = RASP_NUM ; 94 RaspCaps->Max_Event_Num_In_Fifo = RASP_EVENT_FIFO_DEPTH ; 95 RaspCaps->Num_of_Payloaad_Buffers = 1; // ? 96 RaspCaps->Num_of_Filters = RASP_EVENT_NUM ; 97 RaspCaps->Event_Generation_Every_Slot_Time = TRUE ; 98 RaspCaps->PCR_Stamp = TRUE ; 99 RaspCaps->Local_Clock_Stamp = TRUE ; 100 RaspCaps->Trigger_by_Evnet = TRUE ; 101 RaspCaps->Trigger_by_Time = TRUE ; 102 103 104 return X_OK ; 105 106 } 107 108 XSTATUS RASPLDI_GetEventMask 109 ( 110 XCONNECTION Xconn, 111 XUCHAR FilterNum, 112 XUSHORT *Pid, 113 F_RASP_EV_MASK *EventMask, 114 F_RASP_EV_MASK *PayLoadMask 115 ) ; 116 117 XSTATUS RASPLDI_GetTimerAndPacketNumber 118 ( 119 XCONNECTION Xconn, 120 XULONG *Time, 121 XULONG *PacketNumber 122 ) ; 123 124 XSTATUS RASPLDI_GetTSPayload 125 ( 126 XCONNECTION Xconn, 127 XULONG PacketNum, 128 XUCHAR Buffer[188] 129 ); 130 131 XSTATUS RASPLDI_Reset(XCONNECTION Xconn) ; 132 133 XSTATUS RASPLDI_SetEventNotifyFunction 134 ( 135 XCONNECTION Xconn, 136 RASP_EVENT_NOTIFY_FOUNCTION *RaspEventCB 137 ); 138 139 XSTATUS RASPLDI_SetOverflowNotifyFunction 140 ( 141 XCONNECTION Xconn, 142 RASP_OVERFLOW_NOTIFY_FUNCTION *RaspOvfCB 143 ) ; 144 145 146 XSTATUS RASPLDI_Configure 147 ( 148 XCONNECTION Xconn, 149 TRIGGER_EXECUTOR TriggerExecutor, 150 XUSHORT EventHighMark, 151 XUSHORT TimeHighMark, 152 F_RASP_EV_MASK PidIndEvent 153 ); 154 155 156 XSTATUS RASPLDI_SetEventMask 157 ( 158 XCONNECTION Xconn, 159 XUCHAR FilterNum, 160 XUSHORT Pid, 161 F_RASP_EV_MASK EventMask, 162 F_RASP_EV_MASK PayloadMask 163 ); 164 165 166 XSTATUS RASPLDI_ReplacePackets(XCONNECTION Xconn, XUSHORT Pid, XUCHAR FromByte, XUCHAR NumBytes, XUCHAR *ReplaceData) 167 { 168 169 MS_U32 EngId = 0, i ; 170 MS_U16 FltPid = 0 ; 171 172 173 for( i = 0 ; i < RASP_EVENT_NUM ; i++) 174 { 175 HAL_RASP_GetPidflt(EngId, i , &FltPid); 176 if (FltPid == Pid) break ; 177 } 178 179 if (RASP_EVENT_NUM == i) return FALSE ; 180 181 HAL_RASP_SetCorptData(EngId ,FromByte ,FromByte+NumBytes ,*ReplaceData); 182 183 HAL_RASP_SetCorptFlt(EngId,i,TRUE); 184 185 return X_OK; 186 187 } 188 189 190 XSTATUS RASPLDI_Start(XCONNECTION Xconn); 191 192 193 194 //------------------------------------------------------------------// 195 // 196 // Mstar Driver Implementation 197 // 198 //------------------------------------------------------------------// 199 200 201 202 NDS_Result NDS_RASP_Init(NDS_RASP_Param *Param) 203 { 204 205 //MS_U32 regstatus=0; 206 207 if (Param->ecm_size < RASP_NUM*(NDS_CAM_FLT_BUF_SIZE*NDS_CAM_ECM_FLT_NUM) ) 208 { 209 NDS_ERR("RASP ECM buffer size is less than FLT_BUF_SIZE*ECM_FLT_NUM\n"); 210 } 211 212 HAL_RASP_SetECM_StartAddr( 0 ,Param->ecm_addr); 213 HAL_RASP_SetECM_MidAddr( 0 ,Param->ecm_addr); 214 HAL_RASP_SetECM_EndAddr( 0 ,Param->ecm_addr +NDS_CAM_FLT_BUF_SIZE*NDS_CAM_ECM_FLT_NUM ); 215 216 _rasp_ecm_addr[0] = (MS_U8*)Param->ecm_addr; 217 218 memset((MS_U8*)MS_PA2KSEG1(Param->ecm_addr),0x0,NDS_CAM_FLT_BUF_SIZE*NDS_CAM_ECM_FLT_NUM); 219 memset(_u8RaspEcmBuf ,0x0, sizeof(_u8RaspEcmBuf)); 220 221 222 HAL_RASP_ECM_Enable(0 , TRUE); 223 224 //Param->ecm_size ; 225 //Param->payload_addr; 226 //Param->pu8payload_buf; 227 //Param->payload_size; 228 229 MsOS_AttachInterrupt(E_INT_IRQ_RASP, _NDS_RASP_Isr); // 230 MsOS_EnableInterrupt(E_INT_IRQ_RASP); 231 232 RASP_REG(REG_RASP_CA_INT)= RASP_CA_INT_ECM | RASP_CA_INT_MASK_RESET_MODE ; 233 RASP_REG(REG_RASP_CA_INT)= RASP_CA_INT_ECM ; 234 RASP_REG(REG_RASP_ECM_INT_STAT) = RASP_ECM_INT_FLT_MASK ; 235 236 237 //HAL_RASP_INT_Enable(0,(MS_U16)RASP_INT_EVENT_ALL); 238 HAL_RASP_INT_Enable(0,0xffff); 239 240 241 if (-1 == _nds_rasp_eventid) 242 { 243 _nds_rasp_eventid = MsOS_CreateEventGroup("NDS_RASP_Event"); 244 } 245 246 if (-1 == _nds_rasp_taskid) 247 { 248 _nds_rasp_taskid = MsOS_CreateTask( (TaskEntry) _NDS_RASP_IsrTask, 249 (MS_U32)NULL, 250 (TaskPriority) (E_TASK_PRI_SYS+1), 251 TRUE, 252 _nds_rasp_stack, 253 NDS_RASP_TASK_STACK_SIZE, 254 "NDS_RASP_IsrTask"); 255 } 256 257 258 return E_NDS_OK ; 259 } 260 261 262 NDS_Result NDS_RASP_DefineEcmFilter 263 (NDS_ULONG Xconn , NDS_BYTE ecm_filter_num , NDS_BYTE ecm_filter_control) 264 { 265 MS_U16 ecm_pid , i ; 266 267 268 //NDS_FUNC("[%s]-[%d] -- ecm_filter_num[%d]\n", __FUNCTION__, __LINE__, ecm_filter_num); 269 270 //printf("[%s]-[%d] --xconn = %ld , ecm_filter_num[%d]\n", __FUNCTION__, __LINE__,Xconn, ecm_filter_num); 271 272 if (ecm_filter_num >= NDS_CAM_ECM_FLT_NUM) 273 { 274 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__); 275 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER; 276 } 277 for (i = 0; i < NDS_CAM_ECM_FLT_NUM; i++) // 8.2.2 Note 278 { 279 280 if( 281 (i != ecm_filter_num)&& //[FIXME] 282 (_rasp_ecm_flt[0][i].pid == _rasp_ecm_flt[0][ecm_filter_num].pid )&& 283 (_rasp_ecm_flt[0][i].Xconn == _rasp_ecm_flt[0][ecm_filter_num].Xconn)&& 284 (_rasp_ecm_flt[0][i].b_defined = TRUE ) 285 ) 286 { 287 return CA_ECM_PID_FILTER_ALREADY_DEFINED; 288 } 289 } 290 291 //-------// 292 if ((_rasp_ecm_flt[0][ecm_filter_num].pid < 0x2 || _rasp_ecm_flt[0][ecm_filter_num].pid > 0x1FFE)) 293 { 294 return CA_OK ; 295 } 296 297 ecm_pid = _rasp_ecm_flt[0][ecm_filter_num].pid; 298 if (ecm_filter_control & HDICA_ECM_FILTER_CONTROL_ENABLE_ODD_RECEPTION) 299 { 300 ecm_pid |=RASP_ECM_PID_TID_ODD; 301 } 302 if (ecm_filter_control & HDICA_ECM_FILTER_CONTROL_ENABLE_EVEN_RECEPTION) 303 { 304 ecm_pid |= RASP_ECM_PID_TID_EVEN; 305 } 306 if (ecm_filter_control & HDICA_ECM_ENABLE_RECEPTION) 307 { 308 ecm_pid |= RASP_ECM_PID_ENABLE; 309 _rasp_ecm_flt[0][ecm_filter_num].b_defined = TRUE; 310 } 311 else 312 { 313 _rasp_ecm_flt[0][ecm_filter_num].b_defined = FALSE; 314 } 315 316 RASP_REG(REG_RASP_ECM_PID(ecm_filter_num)) = 0; 317 RASP_REG(REG_RASP_ECM_LOCK(ecm_filter_num)) |= RASP_ECM_LOCK_AUTO(ecm_filter_num) ; 318 RASP_REG(REG_RASP_ECM_PID(ecm_filter_num)) = ecm_pid; 319 320 return CA_OK; 321 322 } 323 324 325 326 NDS_Result NDS_RASP_DefineEcmPid (NDS_ULONG Xconn , NDS_BYTE ecm_filter_num , 327 NDS_USHORT Pid, NDS_BYTE odd_ecm_table_id , NDS_BYTE even_ecm_table_id ) 328 { 329 MS_U16 u16EcmTid = 0; 330 331 //NDS_FUNC("[%s]-[%d]--ecm_filter_num[%d]\n", __FUNCTION__, __LINE__, ecm_filter_num); 332 //printf("[%s]-[%d]-- xconn = %ld , ecm_filter_num[%d]\n", __FUNCTION__, __LINE__,Xconn ,ecm_filter_num); 333 334 if (ecm_filter_num >= NDS_CAM_ECM_FLT_NUM) 335 { 336 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__); 337 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER; 338 } 339 340 RASP_REG(REG_RASP_ECM_PID(ecm_filter_num)) = Pid & RASP_ECM_PID_MASK; 341 342 u16EcmTid |= ( even_ecm_table_id & RASP_ECM_TID_EVEN_MASK); 343 u16EcmTid |= ((odd_ecm_table_id<<8) & RASP_ECM_TID_ODD_MASK ); 344 345 RASP_REG(REG_RASP_ECM_TID) = u16EcmTid; 346 347 _rasp_ecm_flt[0][ecm_filter_num].pid = Pid ; 348 _rasp_ecm_flt[0][ecm_filter_num].Xconn = Xconn ; 349 350 if (Pid == 0xFFFF) 351 { 352 return CA_OK; 353 } 354 355 if ((Pid < 0x2 || Pid > 0x1FFE)) 356 { 357 NDS_DBG("[%s]-[%d]\n", __FUNCTION__, __LINE__); 358 return CA_REQUEST_NOT_SUPPORTED_BY_DRIVER; 359 } 360 361 362 return CA_OK; 363 364 } 365 366 367 368 #ifdef MSOS_TYPE_LINUX_KERNEL 369 static irqreturn_t _NDS_RASP_Isr(int irq, void *dev_id) 370 #else 371 static void _NDS_RASP_Isr(InterruptNum eIntNum) 372 #endif 373 { 374 375 MS_U8 u8EcmReg; 376 MS_U8 ecm_polarity; 377 MS_U16 IntStatus; 378 MS_U32 i,EngId = 0 ; 379 380 381 //E_INT_IRQ_RASP 382 IntStatus = HAL_RASP_INT_GetHW(0); 383 //printf("[RASP]Interrupt!!----- eIntNum = %d / Status = %04X \n",eIntNum,IntStatus); 384 385 if (IntStatus & RASP_INT_ECM_PKT_RDY) // ECM Packet Ready 386 { 387 RASP_REG(REG_RASP_CA_INT) = (RASP_CA_INT_ECM ); 388 389 u8EcmReg = RASP_REG(REG_RASP_ECM_INT_STAT); 390 //printf("== Ecm Reg Int = %08X == \n",u8EcmReg); 391 392 for (i = 0; i < NDS_CAM_ECM_FLT_NUM; i++) 393 { 394 if (u8EcmReg & (0x1 << i)) 395 { 396 MS_U8 *pEcmData; 397 398 RASP_REG(REG_RASP_ECM_INT_STAT) = (0x1 << i); 399 400 //if (_EcmFlt[i].u8Drop == 1) 401 // continue; 402 pEcmData = (void *)MS_PA2KSEG1((MS_U32)_rasp_ecm_addr[0] + (NDS_CAM_FLT_BUF_SIZE*i)); 403 MsOS_ReadMemory(); 404 405 if (pEcmData[4] != 0x47) 406 { 407 continue; //_NDS_ASSERT_; 408 } 409 410 if (pEcmData[9] == 0x80) 411 { 412 ecm_polarity = 0; // EVEN 413 } 414 else if (pEcmData[9] == 0x81) 415 { 416 ecm_polarity = 1; // ODD 417 } 418 else 419 { 420 NDS_ASSERT(FALSE, , "[%s]-[%d]\n", __FUNCTION__, __LINE__); 421 } 422 423 if (_u8RaspEcmBuf[EngId][i][ecm_polarity][0] == 0) // if buffer empty , copy pkt from hw buffer to sw buffer. 424 { 425 426 MsOS_ReadMemory(); 427 memcpy(_u8RaspEcmBuf[EngId][i][ecm_polarity], pEcmData+4, 188); 428 429 430 if (RASP_REG(REG_RASP_ECM_INT_STAT) & ( 0x1 << i)) 431 { 432 MsOS_SetEvent(_nds_rasp_eventid, 0x1 << (i + NDS_RASP_ECM_OVERFLOW_SHIFT ) ); 433 continue; 434 } 435 436 MsOS_SetEvent(_nds_rasp_eventid, (0x1 << (i*2 )) << ecm_polarity); 437 } 438 else 439 { 440 // set overflow event 441 MsOS_SetEvent(_nds_rasp_eventid, 0x1 << (i + NDS_RASP_ECM_OVERFLOW_SHIFT)); 442 break; 443 } 444 } 445 } 446 } 447 448 if(IntStatus & RASP_INT_PAYLD2MIU) 449 { 450 //[FIXME] WAIT FOR IMEPLEMENTATAION 451 452 } 453 454 if(IntStatus & RASP_INT_EVENT_WATER_MARK) 455 { 456 //[FIXME] not imeplemted 457 } 458 459 if(IntStatus & RASP_INT_TIME_WATER_MARK) 460 { 461 //[FIXME] not imeplemted 462 } 463 464 if(IntStatus & RASP_INT_EFRAME_RD_OVF) 465 { 466 //[FIXME] not imeplemted 467 } 468 469 if(IntStatus & RASP_INT_EFRAME_WT_OVF) 470 { 471 //[FIXME] not imeplemted 472 } 473 474 475 HAL_RASP_INT_ClrHW(EngId , 0xFFFF); 476 MsOS_EnableInterrupt(E_INT_IRQ_RASP); 477 478 //MsOS_EnableInterrupt(NDS_INT_EMM_ECM ); 479 480 } 481 482 483 484 485 static void _NDS_RASP_IsrTask(void) 486 { 487 488 MS_U32 u32Events ,i ,p ,hi_count ,lo_count;; 489 XECM_MSG ecm_msg; 490 MS_U32 EngId = 0; 491 492 while(1) 493 { 494 MsOS_WaitEvent(_nds_rasp_eventid, NDS_RASP_EVENT_ALL, &u32Events, E_OR_CLEAR, MSOS_WAIT_FOREVER); 495 496 //printf("Rasp Task Get Event = %08lX\n",u32Events); 497 498 for( i = 0 ; i < NDS_CAM_ECM_FLT_NUM ; i ++ ) 499 { 500 if(u32Events & (0x1 << (i + NDS_RASP_ECM_OVERFLOW_SHIFT))) 501 { 502 503 //memset(_u8RaspEcmBuf[EngId][i][0], 0x0 , 188 ); 504 //memset(_u8RaspEcmBuf[EngId][i][1], 0x0 , 188 ); 505 506 ecm_msg.ecm_buf_ptr = _u8RaspEcmBuf[EngId][i][0]; //NULL; 507 ecm_msg.rcv_status = ECM_OVERFLOW; 508 509 XCORECA_EcmReceived(_rasp_ecm_flt[EngId][i].Xconn , &ecm_msg , hi_count, lo_count); 510 } 511 else 512 { 513 MS_U8 valid = (u32Events >> (i*2)) & 0x3; 514 515 if(valid) 516 { 517 for (p = 0; p < 2; p++) 518 { 519 if ( (valid & (0x1<<p)) && _u8RaspEcmBuf[EngId][i][p][0] == 0x47 && _u8RaspEcmBuf[EngId][i][p][5] == (0x80|p)) 520 { 521 ecm_msg.ecm_filter_num = i; 522 ecm_msg.ecm_buf_ptr = _u8RaspEcmBuf[EngId][i][p]+8; 523 ecm_msg.ecm_polarity = ((p==0) ? HDICA_EVEN_BUFFER : HDICA_ODD_BUFFER); 524 ecm_msg.rcv_status = ECM_OK; 525 //_NDS_REC_GetPktCount(_EcmFlt[i].x_connect, &hi_count, &lo_count); 526 if (XCORECA_EcmReceived(_rasp_ecm_flt[EngId][i].Xconn , &ecm_msg , hi_count, lo_count) != CA_OK) 527 { 528 XHDICA_ReleaseEcmBuffer(_rasp_ecm_flt[EngId][i].Xconn , ecm_msg.ecm_filter_num, ecm_msg.ecm_polarity, ecm_msg.ecm_buf_ptr); 529 } 530 } 531 } 532 } 533 534 } //end if overflow 535 } // end for 536 537 538 RASP_REG(REG_RASP_CA_INT) = (RASP_CA_INT_ECM); 539 }// while(1) 540 } 541 542 543 #endif 544 545 546 547