1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 /****************************************************************************/ 79 /* */ 80 /* CAHDIVER.H */ 81 /* ---------- */ 82 /* */ 83 /* Description: Include file between CA HDI Interface and Jupiter Verifier */ 84 /* */ 85 /* $Revision: 2.0 $$Author : $$Date: 07 Jan 1999 19:50:10 $ */ 86 /****************************************************************************/ 87 88 #ifndef __N3_282_H__ 89 #define __N3_282_H__ 90 91 92 93 94 #ifndef H_NDSTYPES 95 typedef unsigned char NDS_BYTE; 96 typedef unsigned short NDS_USHORT; 97 typedef unsigned long NDS_ULONG; 98 typedef NDS_USHORT NDS_STATUS; 99 #endif 100 101 typedef unsigned char CAHDI_BOOLEAN; 102 103 #define CAHDI_TRUE ( (unsigned char) 1 ) 104 #define CAHDI_FALSE ( (unsigned char) 0 ) 105 106 107 108 /*******************/ 109 /* Value of status */ 110 /*******************/ 111 #define CA_OK 0 112 #define CA_REQUEST_NOT_SUPPORTED_BY_DRIVER 1 113 #define CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW 2 114 #define CA_GLOBAL_HARDWARE_FAILURE 3 115 #define CA_ECM_PID_FILTER_ALREADY_DEFINED 4 116 #define CA_DRIVER_INVALID_DATA_STREAM 5 117 #define CA_DRIVER_INVALID_LOGICAL_STREAM_ID 6 118 // #define CA_INSUFICIENT_BUFFER 7 119 #define CA_INFO_NOT_AVAILABLE 7 120 #define CA_INSUFFICIENT_BUFFER 8 121 #define CA_SCHEME_NOT_SUPPORTED 9 122 #define CA_FUNCTIONALITY_NOT_AVAILABLE_UNTIL_RESTART 10 123 #define CA_FUNCTIONALITY_PERMANENTLY_NOT_AVAILABLE 11 124 #define CA_FEATURE_NOT_SUPPORTED 12 125 126 #define MAX_PIDS 8 127 128 /****************************************************************************/ 129 /* */ 130 /* XCORECA_CbModuleType */ 131 /* */ 132 /****************************************************************************/ 133 134 typedef struct { 135 NDS_BYTE ca_module_type; 136 NDS_BYTE ca_module_version; 137 NDS_USHORT uart_module_version; 138 NDS_BYTE *ecm_buffers_ptr; 139 NDS_BYTE *emm_buffers_ptr; 140 NDS_BYTE num_emm_buffers; 141 NDS_BYTE num_ecm_buffer_pairs; 142 CAHDI_BOOLEAN auto_odd_to_even_ecm_filter; 143 NDS_BYTE num_descramblers; 144 NDS_ULONG hw_module_id; 145 NDS_BYTE reserved[9]; 146 } CA_MODULE_TYPE; 147 148 extern NDS_STATUS XCORECA_CbModuleType (int num_of_modules, 149 CA_MODULE_TYPE *ca_module_type); 150 151 /* Define values of ca_module_version (or icam version) */ 152 #define ICAM_1 0x1 153 #define ICAM_2 0x2 154 #define LSI 0x11 155 156 extern NDS_STATUS XHDICA_GetLogicalStreamId (int request_type, 157 NDS_ULONG x_connection, 158 NDS_BYTE *hw_module_id); 159 #define HDICA_GET_EMM_STREAM 1 160 #define HDICA_GET_ECM_STREAM 2 161 #define HDICA_GET_DESCRAMBLER_STREAM 3 162 163 /****************************************************************************/ 164 /* */ 165 /* ECM INTERFACE */ 166 /* */ 167 /****************************************************************************/ 168 /* HDICA_ECM_RECEPTION_MASK */ 169 #define HDICA_ECM_RECEPTION_DISABLE 0x00 170 #define HDICA_ECM_RECEPTION_ENABLE 0x80 171 172 #define HDICA_ECM_DISABLE_RECEPTION 0x00 /* it's multiply because of mismatch in the document */ 173 #define HDICA_ECM_ENABLE_RECEPTION 0x80 174 175 176 extern NDS_STATUS XHDICA_DefineEcmPid (NDS_ULONG x_connection, 177 NDS_BYTE ecm_buf_pair_num, 178 NDS_USHORT pid, 179 NDS_BYTE odd_ecm_table_id, 180 NDS_BYTE even_ecm_table_id); 181 182 extern NDS_STATUS XHDICA_DefineEcmFilter (NDS_ULONG x_connection, 183 NDS_BYTE ecm_filter_num, 184 NDS_BYTE ecm_filter_control); 185 186 /* HDICA_ECM_FILTER_CONTROL_ODD_RECEPTION_MASK */ 187 #define HDICA_ECM_FILTER_CONTROL_DISABLE_ODD_RECEPTION 0x00 188 #define HDICA_ECM_FILTER_CONTROL_ENABLE_ODD_RECEPTION 0x20 189 190 /* HDICA_ECM_FILTER_CONTROL_EVEN_RECEPTION_MASK */ 191 #define HDICA_ECM_FILTER_CONTROL_DISABLE_EVEN_RECEPTION 0x00 192 #define HDICA_ECM_FILTER_CONTROL_ENABLE_EVEN_RECEPTION 0x40 193 194 extern NDS_STATUS XHDICA_ReleaseEcmBuffer (NDS_ULONG x_connection, 195 NDS_BYTE ecm_filter_num, 196 NDS_BYTE ecm_polarity, 197 NDS_BYTE *ecm_buf); 198 extern NDS_STATUS XHDICA_ReleaseAllEcmBuffers (NDS_ULONG x_connection); 199 200 /* CORECA_EcmReceived Return Status */ 201 #define CA_ECM_CHECKSUM_ERROR 1 202 #define CA_INVALID_BUFFER_NUMBER 2 203 #define CA_ECM_WAS_NOT_USED 3 204 205 /* ECM_RECEIVED_STATUS */ 206 #define ECM_OK 0 207 #define ECM_OVERFLOW 1 208 209 /* ECM BUFFER */ 210 #define HDICA_EVEN_BUFFER 1 211 #define HDICA_ODD_BUFFER 2 212 213 214 typedef struct { 215 NDS_BYTE rcv_status; /* ECM_OK or ECM_OVERFLOW */ 216 NDS_BYTE ecm_filter_num; 217 NDS_BYTE ecm_polarity; /* HDICA_ODD_BUFFER or HDICA_EVEN_BUFFER */ 218 NDS_BYTE *ecm_buf_ptr; /* pointer to the ECM payload*/ 219 }XECM_MSG; 220 221 222 extern NDS_STATUS XCORECA_EcmReceived (NDS_ULONG x_connection, 223 XECM_MSG *ecm_msg, 224 NDS_ULONG hi_counter, 225 NDS_ULONG lo_counter); 226 227 /****************************************************************************/ 228 /* */ 229 /* EMM INTERFACE */ 230 /* */ 231 /****************************************************************************/ 232 extern NDS_STATUS XHDICA_SetEmmPid (NDS_ULONG x_connection, 233 NDS_USHORT pid, 234 NDS_BYTE emm_filter_control); 235 236 /* HDICA_EMM_RECEPTION_MASK */ 237 #define HDICA_EMM_RECEPTION_DISABLE 0x00 238 #define HDICA_EMM_RECEPTION_ENABLE 0x80 239 240 #define HDICA_EMM_DISABLE_RECEPTION 0x00 /* it's multiply because of mismatch in the document */ 241 #define HDICA_EMM_ENABLE_RECEPTION 0x80 242 243 /* HDICA_TABLE_ID_FILTERING_MASK */ 244 #define HDICA_TABLE_ID_FILTERING_IGNORE 0x00 245 #define HDICA_TABLE_ID_FILTERING_USE 0x40 246 247 extern NDS_STATUS XHDICA_EmmSetTableIdFilter (NDS_ULONG x_connection, 248 NDS_BYTE table_id[4]); 249 250 /* TABLE ID FILTER CONTROL NDS_BYTE */ 251 #define IGNORE_THIS_ID 0x00 252 #define RECEIVE_ALL 0x01 253 #define FILTER_BY_NDC 0x10 254 255 typedef struct { 256 NDS_BYTE reg1_address[4]; 257 NDS_BYTE reg1_mask[4]; 258 NDS_BYTE reg2_address[4]; 259 NDS_BYTE reg2_mask[4]; 260 NDS_BYTE reg3_address[4]; 261 NDS_BYTE reg3_mask[4]; 262 } EMM_REG; 263 264 extern NDS_STATUS XHDICA_SetPrivateEmmFilter (NDS_ULONG x_connection, 265 EMM_REG *emm_reg); 266 267 extern NDS_STATUS XHDICA_ReleaseEmmBuffer(NDS_ULONG x_connection, 268 NDS_BYTE *emm_buf); 269 270 /* CORECA_EmmReceivedMsg Return Status */ 271 #define CA_EMM_WAS_NOT_USED 3 272 273 /* EMM_RECEIVED_STATUS */ 274 #define EMM_OK 0 275 #define EMM_OVERFLOW 1 276 277 typedef struct 278 { 279 NDS_BYTE receive_status; 280 NDS_BYTE *emm_buf; 281 } XEMM_MSG; 282 283 extern NDS_STATUS XCORECA_EmmReceived (NDS_ULONG x_connection, 284 XEMM_MSG *emm_msg); 285 286 287 /****************************************************************************/ 288 /* */ 289 /* Descrambling Elementary Streams */ 290 /* */ 291 /****************************************************************************/ 292 extern NDS_STATUS XHDICA_DefineDescramblerEs (NDS_ULONG x_connection, 293 NDS_BYTE descrambler_num, 294 NDS_USHORT pid, 295 NDS_BYTE filter_control); 296 #define HDICA_DESCRAMBLER_CONTROL_ENABLE_DESCRAMBLING 0x80 297 #define HDICA_DESCRAMBLER_CONTROL_DISABLE_DESCRAMBLING 0x00 298 299 #define HDICA_DESCRAMBLE_TRANSPORT_PACKET_LEVEL 0x00 300 #define HDICA_DESCRAMBLE_PES_PACKET_LEVEL 0x40 301 302 extern NDS_STATUS XHDICA_SetEvenKey (NDS_ULONG x_connection, 303 NDS_BYTE descrambler_num, 304 NDS_BYTE *key_ptr); 305 extern NDS_STATUS XHDICA_SetOddKey (NDS_ULONG x_connection, 306 NDS_BYTE descrambler_num, 307 NDS_BYTE *key_ptr); 308 309 extern NDS_STATUS XHDICA_DefineDescramblerType(NDS_ULONG x_connection, 310 NDS_BYTE descrambler_type); 311 312 #define CSA 0 313 #define NSA 1 314 #define DES 2 315 #define AES 3 316 317 318 /****************************************************************************/ 319 /* */ 320 /* Smart Card Interface */ 321 /* */ 322 /****************************************************************************/ 323 324 #define SC_INSERTED 0 325 #define SC_REMOVED 1 326 #define SC_COMM_OK 2 327 #define SC_COMM_OVERFLOW 3 328 #define SC_PARITY 4 329 #define SC_ERROR 5 330 331 extern NDS_STATUS CORECA_SmartCardComm (NDS_BYTE smart_card_comm_msg); 332 333 334 extern NDS_STATUS HDICA_SetCardId(NDS_ULONG card_id); 335 extern NDS_STATUS HDICA_SetIrdId(NDS_ULONG ird_id); 336 extern NDS_STATUS HDICA_SetCardClockDivisor(NDS_BYTE clock_divisor); 337 338 /* CLOCK_DIVISOR */ 339 #define HIGHEST_CLOCK 1 340 #define MEDIUM_CLOCK 2 341 #define LOWEST_CLOCK 3 342 343 #define DIVIDE_BY_2 1 344 #define DIVIDE_BY_4 2 345 #define DIVIDE_BY_6 3 346 #define DIVIDE_BY_8 4 347 348 extern NDS_STATUS HDICA_SetVccLevel(NDS_BYTE vcc_level); 349 350 /* VCC LEVEL */ 351 #define HDICA_VCC_3V 0 352 #define HDICA_VCC_5V 1 353 354 355 extern NDS_STATUS HDICA_SetConvention (NDS_BYTE convention); 356 357 /* TRANSMISSION_CONVENTION */ 358 #define HDICA_CONVENTION_INVERSE 0x00 359 #define HDICA_CONVENTION_DIRECT 0x01 360 361 extern NDS_STATUS HDICA_SetUartBaudRate (NDS_BYTE baud_rate); 362 363 #define HDICA_BAUD_RATE_9600 1 364 #define HDICA_BAUD_RATE_19200 2 365 #define HDICA_BAUD_RATE_38400 3 366 #define HDICA_BAUD_RATE_76800 4 367 #define HDICA_BAUD_RATE_153600 5 368 #define HDICA_BAUD_RATE_223200 6 /* F= 512; D= 32 */ 369 370 extern NDS_STATUS HDICA_SetVcc (NDS_BYTE vcc_switch); 371 372 #define HDICA_VCC_ON 0 373 #define HDICA_VCC_OFF 1 374 375 extern NDS_STATUS HDICA_SetVpp (NDS_BYTE vpp_switch); 376 377 #define HDICA_VPP_ON 0 378 #define HDICA_VPP_OFF 1 379 380 extern NDS_STATUS HDICA_SetGuardTime (NDS_BYTE guard_time); 381 382 extern NDS_STATUS HDICA_GetInputByte (NDS_BYTE *input_byte); 383 extern NDS_STATUS HDICA_PutOutputByte (NDS_BYTE output_byte); 384 extern NDS_STATUS HDICA_ResetCard (NDS_BYTE reset_switch); 385 386 #define INACTIVE 0 387 #define ACTIVE 1 388 #define RESET_CYCLE 2 389 390 extern NDS_STATUS HDICA_GetUartStatus (NDS_BYTE *uart_status); 391 392 /* HDICA_UART_STATUS_TX_READY_MASK */ 393 #define HDICA_UART_STATUS_TX_IS_READY 0x01 /* bit 0 */ 394 #define HDICA_UART_STATUS_TX_IS_NOT_READY 0x00 395 396 /* HDICA_UART_RX_READY_MASK */ 397 #define HDICA_UART_STATUS_RX_IS_READY 0x02 /* bit 1 */ 398 #define HDICA_UART_STATUS_RX_IS_NOT_READY 0x00 399 400 /* HDICA_UART_STATUS_PARITY_ERROR_LAST_BYTE_RCVD_MASK */ 401 #define HDICA_UART_STATUS_RCV_PARITY_ERROR 0x04 /* bit 2 */ 402 #define HDICA_UART_STATUS_RCV_NO_PARITY_ERROR 0x00 403 404 /* HDICA_UART_STATUS_RCV_BUFFER_OVERFLOW_MASK */ 405 #define HDICA_UART_STATUS_OVERFLOW 0x08 /* bit 3 */ 406 #define HDICA_UART_STATUS_NO_OVERFLOW 0x00 407 408 /* HDICA_UART_STATUS_PARITY_ERROR_LAST_BYTE_TRANSMITTED_MASK */ 409 #define HDICA_UART_STATUS_TX_PARITY_ERROR 0x10 /* bit 4 */ 410 #define HDICA_UART_STATUS_TX_NO_PARITY_ERROR 0x00 411 412 /* HDICA_UART_STATUS_CONVENTION_MASK */ 413 #define HDICA_UART_STATUS_CONVENTION_INVERSE 0x00 414 #define HDICA_UART_STATUS_CONVENTION_DIRECT 0x20 /* bit 5 */ 415 416 /* HDICA_UART_STATUS_INTERRUPT_PENDING_MASK */ 417 #define HDICA_UART_STATUS_INTERRUPT_PENDING 0x40 /* bit 6 */ 418 #define HDICA_UART_STATUS_INTERRUPT_NOT_PENDING 0x00 419 420 /* HDICA_UART_STATUS_CARD_DETECT_MASK */ 421 #define HDICA_UART_STATUS_CARD_INSERTED 0x80 /* bit 7 */ 422 #define HDICA_UART_STATUS_CARD_NOT_INSERTED 0x00 423 424 extern NDS_STATUS HDICA_SetCaValue (NDS_BYTE ca_value); 425 extern NDS_STATUS XHDICA_SetCaValue (NDS_ULONG x_connection , NDS_BYTE ca_value); 426 extern NDS_STATUS HDICA_SetUartCommand (NDS_BYTE pin_mask); 427 428 extern NDS_STATUS HDICA_SendAndReceiveBytesSession (NDS_BYTE *xmt_ptr, 429 NDS_BYTE xmit_length, 430 CAHDI_BOOLEAN null_filter, 431 CAHDI_BOOLEAN use_flow_control, 432 NDS_BYTE *rcv_ptr, 433 NDS_BYTE rcv_length 434 ); 435 436 extern NDS_STATUS HDICA_ReceiveBytesSession (CAHDI_BOOLEAN null_filter, 437 CAHDI_BOOLEAN use_flow_control, 438 NDS_BYTE *rcv_ptr, 439 NDS_BYTE rcv_length); 440 441 extern NDS_STATUS HDICA_AbortSmartCardCommSession (void); 442 443 /****************************************************************************/ 444 /* */ 445 /* Recording control interface */ 446 /* */ 447 /****************************************************************************/ 448 #define CA_OP_BASE_KEY 0x00 449 #define CA_OP_READING 0x01 450 #define CA_OP_WRITING 0x02 451 452 extern NDS_STATUS XHDICA_ECMCorruptionSettings (NDS_BYTE CorruptDataByte, 453 NDS_BYTE FromByte); 454 extern NDS_STATUS XHDICA_EnableECMCorruption (NDS_ULONG x_connection, 455 NDS_USHORT pid, 456 NDS_BYTE enable_corruption); 457 extern NDS_STATUS XHDICA_SecondaryScramblingKey (NDS_ULONG x_connection, 458 NDS_BYTE operation, 459 NDS_BYTE* key_ptr); 460 461 462 463 464 465 466 //extern NDS_STATUS CORECA_EmmReceived( XEMM_MSG *emm_msg ); 467 //extern NDS_STATUS CORECA_EcmReceived( XECM_MSG *ecm_msg ); 468 469 /****************************************************************************/ 470 /* */ 471 /* Control Word Encryption Interface */ 472 /* */ 473 /****************************************************************************/ 474 #define ESD_CLEAR_CW_LENGTH 8 475 #define ESD_ENCRYPTED_CW_LENGTH 8 476 #define ESD_ENCRYPTED_CKEY_LENGTH 16 477 #define ESD_ENCRYPTED_ACKEY_LENGTH 16 478 479 /* The following are descriptor tags for ExtendedSetDescrambler */ 480 #define ESD_CLEAR_CW 0x01 481 #define ESD_ENCRYPTED_CW 0x02 482 #define ESD_EKEY 0x03 /* encrypted key - Ekpair/Eknopair used for CW encryption feature */ 483 #define ESD_VGS_CHAINING_KEY 0x08 484 #define ESD_VGS_AC_KEY 0x09 485 #define ESD_VGS_OPTIONS 0x10 486 487 /* The following are descriptor tags for the chip properties structure */ 488 #define CHIP_TYPE_DSCR_TAG 0x11 489 #define CHIP_ID_DSCR_TAG 0x12 490 #define HASH_KEY_DSCR_TAG 0x13 /* encrypted key - Ekpair/Eknopair used for CW encryption feature */ 491 #define KEY_LADDER_DEPTH_DSCR_TAG 0x14 492 #define ENABLE_FLAGS_DSCR_TAG 0x15 493 494 /* The following are descriptor tags for the descrambling key structure */ 495 #define CLEAR_CW_DSCR_TAG 0x01 496 #define ENCRYPTED_CW_DSCR_TAG 0x02 497 #define ENCRYPTED_KEY_DSCR_TAG 0x03 498 #define ENCRYPTION_SCHEME_DSCR_TAG 0x04 499 500 /* The following are Encryption Scheme Values Definition */ 501 #define ENS_3DES_DED_2KEY 2 502 #define ENS_3DES_DED_2KEY_TWIST 3 503 #define ENS_3DES_DED_2KEY_HALF_TWIST 4 504 #define ENS_AES_128_BITS 0x10 505 506 #define ESD_VGS_CONFORMANCE 0x80 507 508 /* 509 #define CA_INFO_NOT_AVAILABLE 7 510 #define CA_INSUFFICIENT_BUFFER 8 511 #define CA_SCHEME_NOT_SUPPORTED 9 512 #define CA_FUNCTIONALITY_NOT_AVAILABLE_UNTIL_RESTART 10 513 #define CA_FUNCTIONALITY_PERMANENTLY_NOT_AVAILABLE 11 514 #define CA_FEATURE_NOT_SUPPORTED 12 515 */ 516 517 /* The following define how Block Clear CWS should be performed */ 518 #define BLOCK_FOREVER 0 519 #define BLOCK_TILL_NEXT_RESET 1 520 521 #define KEY_IN_BOX 1 522 #define FLASH_ID 2 523 524 #define CTRL_ENCRYPTION_SUPPORTED (1<< 0) 525 #define CTRL_ENCRYPTION_PERMANENTLY_FORCED (1<< 1) 526 #define CTRL_ENCRYPTION_FORCED_UNTIL_RESET (1<< 2) 527 #define JTAG_PASSWORD_ENABLED (1<< 3) 528 #define BOOTRON_ENABLED (1<< 4) 529 #define DATA_ENCRYPTION_SUPPORTED (1<< 5) 530 #define SPARE_1 (1<< 6) 531 #define SPARE_2 (1<< 7) 532 533 #define ENCRYPT_IN_PARAMS_DSCR_TAG 0x0a 534 #define MAX_AUX_LEN 10 535 536 enum { 537 TID_ECM_EVEN = 0x80, 538 TID_ECM_ODD, 539 }; 540 541 enum { 542 POLARITY_CLEAR = 0, 543 POLARITY_ODD, 544 POLARITY_EVEN, 545 }; 546 547 extern NDS_STATUS XHDICA_GetChipProperties(NDS_ULONG hw_module_id, 548 unsigned int chip_prop_length, 549 unsigned int *actual_chip_prop_length, 550 NDS_BYTE *chip_properties, 551 void *auxiliary_data); 552 553 extern NDS_STATUS XHDICA_SetControlWord(NDS_ULONG x_connection, 554 NDS_USHORT descrambler_num, 555 unsigned int control_data_length, 556 NDS_BYTE *control_data, 557 unsigned int polarity_control); 558 559 extern NDS_STATUS XHDICA_GetSerializationInfo(unsigned int info_type, 560 unsigned int serializaion_data_len, 561 unsigned int *actual_serialization_data_len, 562 NDS_BYTE *serialization_data); 563 564 /****************************************************************************/ 565 /* */ 566 /* VGS Interface */ 567 /* */ 568 /****************************************************************************/ 569 NDS_STATUS XHDICA_GetResponseToChallenge(NDS_BYTE *nonce, 570 NDS_BYTE nonce_length, 571 int descrambling_key_length, 572 NDS_BYTE *descrambling_key_descrip, 573 NDS_BYTE *response, 574 NDS_BYTE *response_length); 575 576 /****************************************************************************/ 577 /* */ 578 /* Data Encryption Interface */ 579 /* */ 580 /****************************************************************************/ 581 unsigned short XHDICA_EncryptData(void *encrypt_in_params, 582 unsigned int *out_data_buf_len, 583 NDS_BYTE *out_data_buf); 584 585 586 //////------- NSK ------------////// 587 unsigned short HDIHAL_WriteNSKReg(unsigned long instance, 588 unsigned long offset, 589 unsigned long length, 590 unsigned long *reg_data_out); 591 592 unsigned short HDIHAL_ReadNSKReg(unsigned long instance, 593 unsigned long offset, 594 unsigned long length, 595 unsigned long *reg_data_in); 596 597 598 unsigned short HDIHAL_WriteNSKData(unsigned long instance, 599 unsigned long offset, 600 unsigned long length, 601 unsigned char *data_out); 602 603 604 unsigned short HDIHAL_ReadNSKData(unsigned long instance, 605 unsigned long offset, 606 unsigned long length, 607 unsigned char *data_in); 608 609 /*unsigned short HALHDI_InterruptServiceRoutine( 610 unsigned long instance, 611 unsigned long interrupt_source); 612 613 614 unsigned short HALHDI_InitSVP_HW(unsigned long instance);*/ 615 616 617 /////-------- SVP --------////// 618 unsigned short SVPHDI_ReadSerialData 619 ( 620 unsigned int offset, 621 unsigned int length, 622 unsigned char* data 623 ); 624 625 626 unsigned short SVPHDI_AllocateCmChannel 627 ( 628 unsigned long xconn, 629 unsigned int esa_select, 630 unsigned int esa_subselect, 631 unsigned int* cm_channel_handle 632 ); 633 634 635 unsigned short SVPHDI_DeallocateCmChannel 636 ( 637 unsigned int cm_channel_handle 638 ); 639 640 641 unsigned short SVPHDI_AddEsPidCmChannel 642 ( 643 unsigned int cm_channel_handle, 644 unsigned short es_pid 645 ); 646 647 648 unsigned short SVPHDI_RemoveEsPidCmChannel 649 ( 650 unsigned int cm_channel_handle, 651 unsigned short es_pid 652 ); 653 654 655 unsigned short SVPHDI_EnableCmChannel 656 ( 657 unsigned int cm_channel_handle 658 ); 659 660 661 unsigned short SVPHDI_DisableCmChannel 662 ( 663 unsigned int cm_channel_handle 664 ); 665 666 unsigned short SVPHDI_WriteKey 667 ( 668 unsigned long instance, 669 unsigned int cm_channel_handle, 670 unsigned char scb, 671 unsigned int scrambling_settings_len, 672 unsigned char* scrambling_settings 673 ); 674 675 676 unsigned short SVPHDI_GetContentModuleProperties 677 ( 678 unsigned int cm_prop_length, 679 unsigned int* actual_cm_prop_len, 680 unsigned char* cm_properties 681 ); 682 683 684 685 686 /////---- no support now ----- 687 unsigned short SVPHDI_SetSecondaryVideoPid 688 ( 689 unsigned int cm_channel_handle, 690 unsigned short primary_pid, 691 unsigned short secondary_pid 692 ); 693 694 695 unsigned short SVPHDI_ReleaseSecondaryVideoPid 696 ( 697 unsigned int cm_channel_handle, 698 unsigned short secondary_pid 699 ); 700 701 702 unsigned short SVPHDI_StartPacketInjection 703 ( 704 unsigned long xconn, 705 unsigned char* transport_packet, 706 unsigned int injection_type, 707 unsigned int injection_frequency 708 ); 709 710 711 unsigned short SVPHDI_InjectSinglePacket 712 ( 713 unsigned long xconn, 714 unsigned char* transport_packet 715 ); 716 717 718 unsigned short SVPHDI_ContinousReplacePacket 719 ( 720 unsigned long xconn, 721 unsigned short replace_pid, 722 unsigned char* transport_packet 723 ); 724 725 726 unsigned short SVPHDI_TerminatePacketWrite 727 ( 728 unsigned long xconn, 729 unsigned short pid 730 ); 731 732 unsigned short HDIHAL_WriteDescrambler 733 ( 734 unsigned long xconn, 735 unsigned short pid, 736 unsigned char scb, 737 unsigned char flags 738 ); 739 740 741 742 /****************************************************************************/ 743 /* */ 744 /* XTV RASP Low Level Driver Interdace */ 745 /* */ 746 /****************************************************************************/ 747 748 typedef enum _MS_XBOOL 749 { 750 _MS_XFALSE = 0, 751 _MS_XTRUE = 1 752 } _MS_XBOOL; 753 754 755 typedef struct 756 { 757 unsigned long Event_Descriptor; 758 unsigned short Pid; 759 unsigned short Reserved; 760 unsigned long PacketNum; 761 unsigned long Timer; 762 unsigned long PCR; 763 764 }RASP_EVENT; 765 766 typedef struct 767 { 768 unsigned long Supported_Event; 769 unsigned long Event_Timer_Rate; 770 unsigned short Num_Rasps; 771 unsigned short Max_Event_Num_In_Fifo; 772 unsigned short Num_of_Payloaad_Buffers; 773 unsigned short Num_of_Filters; 774 _MS_XBOOL Event_Generation_Every_Slot_Time; 775 _MS_XBOOL PCR_Stamp; 776 _MS_XBOOL Local_Clock_Stamp; 777 _MS_XBOOL Trigger_by_Evnet; 778 _MS_XBOOL Trigger_by_Time ; 779 780 }RASP_CAPS; 781 782 783 typedef unsigned short (*RASP_EVENT_NOTIFY_FOUNCTION) 784 ( 785 unsigned long Xconn, 786 unsigned short NumEvent, 787 RASP_EVENT RaspEvents[] 788 ); 789 790 typedef unsigned short (*RASP_OVERFLOW_NOTIFY_FUNCTION) 791 ( 792 unsigned long Xconn 793 ); 794 795 unsigned short RASPLDI_GetCapabilities(RASP_CAPS *RaspCaps) ; 796 unsigned short RASPLDI_GetEventMask 797 ( 798 unsigned long Xconn, 799 unsigned char FilterNum, 800 unsigned short *Pid, 801 unsigned long *EventMask, 802 unsigned long *PayLoadMask 803 ) ; 804 805 unsigned short RASPLDI_GetTimerAndPacketNumber 806 ( 807 unsigned long Xconn, 808 unsigned long *Time, 809 unsigned long *PacketNumber 810 ) ; 811 812 unsigned short RASPLDI_GetTSPayload 813 ( 814 unsigned long Xconn, 815 unsigned long PacketNum, 816 unsigned char Buffer[188] 817 ); 818 819 unsigned short RASPLDI_Reset(unsigned long Xconn) ; 820 821 unsigned short RASPLDI_SetEventNotifyFunction 822 ( 823 unsigned long Xconn, 824 RASP_EVENT_NOTIFY_FOUNCTION *RaspEventCB 825 ); 826 827 unsigned short RASPLDI_SetOverflowNotifyFunction 828 ( 829 unsigned long Xconn, 830 RASP_OVERFLOW_NOTIFY_FUNCTION *RaspOvfCB 831 ) ; 832 833 834 unsigned short RASPLDI_Configure 835 ( 836 unsigned long Xconn, 837 unsigned long TriggerExecutor, 838 unsigned short EventHighMark, 839 unsigned short TimeHighMark, 840 unsigned long PidIndEvent 841 ); 842 843 844 unsigned short RASPLDI_SetEventMask 845 ( 846 unsigned long Xconn, 847 unsigned char FilterNum, 848 unsigned short Pid, 849 unsigned long EventMask, 850 unsigned long PayloadMask 851 ); 852 853 854 unsigned short RASPLDI_ReplacePackets 855 ( 856 unsigned long Xconn, 857 unsigned short Pid, 858 unsigned char FromByte, 859 unsigned char NumBytes, 860 unsigned char *ReplaceData 861 ); 862 863 864 unsigned short RASPLDI_Start(unsigned long Xconn); 865 866 867 #endif 868 869