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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: mmfilein.h 98 // Description: Multimedia File In (MMFILEIN) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _MMFILEIN_REG_H_ 103 #define _MMFILEIN_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define MMFI_ENGINE_NUM (2UL) 137 138 #define MMFI_PIDFLT_GROUP0 (4UL) // filters reside in upper half of bank MMFI 139 #define MMFI_PIDFLT_GROUP1 (2UL) // filters reside in bottom half of bank MMFI 140 141 #define MMFI_PIDFLT0_NUM (MMFI_PIDFLT_GROUP0 + MMFI_PIDFLT_GROUP1) 142 #define MMFI_PIDFLT1_NUM (MMFI_PIDFLT0_NUM) 143 144 #define MMFI_PIDFLT_NUM_ALL (MMFI_PIDFLT0_NUM+MMFI_PIDFLT1_NUM) 145 146 #define MMFI_PID_NULL 0x1FFFUL 147 148 //------------------------------------------------------------------------------------------------- 149 // Harware Capability 150 //------------------------------------------------------------------------------------------------- 151 152 //------------------------------------------------------------------------------------------------- 153 // Type and Structure 154 //------------------------------------------------------------------------------------------------- 155 156 #define REG_CTRL_BASE_MMFI0 (0x3800UL) // 0xBF800000+(1c00/2)*4 157 #define REG_CTRL_BASE_MMFI1 (0x3880UL) 158 #define REG_CTRL2 (0x3900UL) // MMFI part 2 159 160 typedef struct _REG32 161 { 162 volatile MS_U16 L; 163 volatile MS_U16 empty_L; 164 volatile MS_U16 H; 165 volatile MS_U16 empty_H; 166 } REG32; 167 168 typedef struct _REG16 169 { 170 volatile MS_U16 data; 171 volatile MS_U16 _resv; 172 } REG16; 173 174 typedef struct _REG_Ctrl_MMFI 175 { 176 //---------------------------------------------- 177 // 0xBF802A00 MIPS direct access 178 //---------------------------------------------- 179 // Index(word) CPU(byte) MIPS(0x1500/2+index)*4 180 REG32 PidFlt[4]; // 0xbf803800 0x00 181 #define MMFI_PIDFLT_PID_MASK 0x00001FFFUL 182 #define MMFI_PIDFLT_EN_MASK 0x0007E000UL 183 #define MMFI_PIDFLT_AFIFOB_EN 0x00002000UL 184 #define MMFI_PIDFLT_AFIFO_EN 0x00004000UL 185 #define MMFI_PIDFLT_VFIFO_EN 0x00008000UL 186 #define MMFI_PIDFLT_V3DFIFO_EN 0x00010000UL 187 #define MMFI_PIDFLT_AFIFOC_EN 0x00020000UL 188 #define MMFI_PIDFLT_AFIFOD_EN 0x00040000UL 189 190 REG32 FileIn_RAddr; // 0xbf803820 0x08 //byte address 191 REG32 FileIn_RNum; // 0xbf803828 0x0a 192 193 REG16 FileIn_Ctrl; // 0xbf803830 0x0c 194 #define MMFI_FILEIN_CTRL_START 0x0001UL 195 #define MMFI_FILEIN_CTRL_DONE 0x0002UL 196 #define MMFI_FILEIN_CTRL_ABORT 0x0010UL 197 #define MMFI_FILEIN_CTRL_MASK 0x0013UL 198 #define MMFI_FILEIN_TIMER_MASK 0xFF00UL 199 #define MMFI_FILEIN_TIMER_SHIFT 8UL 200 201 REG16 CmdQSts; // 0xbf803834 0x0d 202 #define MMFI_CMDQ_SIZE 8UL 203 #define MMFI_CMDQSTS_WRCNT_MASK 0x001FUL 204 #define MMFI_CMDQSTS_FIFO_FULL 0x0040UL 205 #define MMFI_CMDQSTS_FIFO_EMPTY 0x0080UL 206 #define MMFI_CMDQSTS_FIFO_WRLEVEL_MASK 0x0300UL 207 #define MMFI_CMDQSTS_FIFO_WRLEVEL_SHIFT 8UL 208 209 REG32 Cfg; // 0xbf803838 0x0e 210 #define MMFI_CFG_LPCR2_LD 0x00000001UL 211 #define MMFI_CFG_LPCR2_WLD 0x00000002UL 212 #define MMFI_CFG_TEI_SKIP 0x00000004UL 213 #define MMFI_CFG_CLR_PIDFLT_BYTE_CNT 0x00000008UL 214 #define MMFI_CFG_APID_BYPASS 0x00000010UL 215 #define MMFI_CFG_APIDB_BYPASS 0x00000020UL 216 #define MMFI_CFG_VPID_BYPASS 0x00000040UL 217 #define MMFI_CFG_VPID3D_BYPASS 0x00000080UL 218 #define MMFI_CFG_AUD_ERR_EN 0x00000100UL 219 #define MMFI_CFG_AUDB_ERR_EN 0x00000200UL 220 #define MMFI_CFG_VD_ERR_EN 0x00000400UL 221 #define MMFI_CFG_V3D_ERR_EN 0x00000800UL 222 #define MMFI_CFG_APES_ERR_RM_EN 0x00001000UL 223 #define MMFI_CFG_APESB_ERR_RM_EN 0x00002000UL 224 #define MMFI_CFG_VPES_ERR_RM_EN 0x00004000UL 225 #define MMFI_CFG_VPES3D_ERR_RM_EN 0x00008000UL 226 #define MMFI_CFG_CLR_PKT_CNT 0x00010000UL 227 #define MMFI_CFG_DIS_MIU_RQ 0x00020000UL 228 #define MMFI_CFG_RADDR_READ 0x00040000UL 229 #define MMFI_CFG_BYTETIMER_EN 0x00080000UL 230 #define MMFI_CFG_PLY_FILE_INV_EN 0x00100000UL 231 #define MMFI_CFG_DUP_PKT_SKIP 0x00200000UL 232 #define MMFI_CFG_ALT_TS_SIZE 0x00400000UL 233 #define MMFI_CFG_2MI_RPRIORITY 0x00800000UL 234 #define MMFI_CFG_PS_AUD_EN 0x01000000UL 235 #define MMFI_CFG_PS_AUDB_EN 0x02000000UL 236 #define MMFI_CFG_PS_VD_EN 0x04000000UL 237 #define MMFI_CFG_PS_V3D_EN 0x08000000UL 238 #define MMFI_CFG_MEM_TS_ORDER 0x10000000UL 239 #define MMFI_CFG_MEM_TS_DATA_ENDIAN 0x20000000UL 240 #define MMFI_CFG_PKT192_EN 0x40000000UL 241 #define MMFI_CFG_PKT192_BLK_DISABLE 0x80000000UL 242 #define MMFI_CFG_FILEIN_MODE_MASK (MMFI_CFG_APID_BYPASS|MMFI_CFG_APIDB_BYPASS|MMFI_CFG_VPID_BYPASS \ 243 |MMFI_CFG_VPID3D_BYPASS|MMFI_CFG_PS_AUD_EN|MMFI_CFG_PS_AUDB_EN \ 244 |MMFI_CFG_PS_VD_EN|MMFI_CFG_PS_V3D_EN) 245 246 REG32 TsHeader; // 0xbf803840 0x10 247 #define MMFI_HD_CCNT_MASK 0x0000000FUL 248 #define MMFI_HD_AF_MASK 0x00000030UL 249 #define MMFI_HD_AF_SHIFT 4UL 250 #define MMFI_HD_SCRAMBLE_MASK 0x000000C0UL 251 #define MMFI_HD_SCRAMBLE_SHIFT 6UL 252 #define MMFI_HD_PID 0x001FFF00UL 253 #define MMFI_HD_PID_SHIFT 8UL 254 #define MMFI_HD_TS_PRIORITY_MASK 0x00200000UL 255 #define MMFI_HD_TS_PRIORITY_SHIFT 21UL 256 #define MMFI_HD_PAYLOAD_START_FLG_MASK 0x00400000UL 257 #define MMFI_HD_PAYLOAD_START_FLG_SHIFT 22UL 258 #define MMFI_HD_ERR_FLG_MASK 0x00800000UL 259 #define MMFI_HD_ERR_FLG_SHIFT 23UL 260 261 REG16 APid_Status; // 0xbf803848 0x12 262 #define MMFI_APID_MATCHED_MASK 0x00001FFFUL 263 #define MMFI_APID_CHANGE 0x00002000UL 264 REG16 APidB_Status; // 0xbf803848 0x13 265 #define MMFI_APIDB_MATCHED_MASK 0x00001FFFUL 266 #define MMFI_APIDB_CHANGE 0x00002000UL 267 REG16 VPID_Status; // 0xbf803850 0x14 268 #define MMFI_VPID_MATCHED_MASK 0x00001FFFUL 269 #define MMFI_VPID_CHANGE 0x00002000UL 270 REG16 VPID3D_Status; // 0xbf803854 0x15 271 #define MMFI_VPID3D_MATCHED_MASK 0x00001FFFUL 272 #define MMFI_VPID3D_CHANGE 0x00002000UL 273 274 REG32 LPcr2_Buf; // 0xbf803858 0x16 275 REG32 TimeStamp_FIn; // 0xbf803860 0x18 276 277 REG16 SWRst; // 0xbf803868 0x1a 278 #define MMFI_SWRST_MASK 0x07FFUL 279 #define MMFI_SW_RSTZ_MMFILEIN_DISABLE 0x0001UL // low active 280 #define MMFI_RST_WB_DMA0 0x0002UL 281 #define MMFI_RST_CMDQ0 0x0004UL 282 #define MMFI_RST_TSIF0 0x0008UL 283 #define MMFI_RST_WB0 0x0010UL 284 #define MMFI_RST_WB_DMA1 0x0020UL 285 #define MMFI_RST_CMDQ1 0x0040UL 286 #define MMFI_RST_TSIF1 0x0080UL 287 #define MMFI_RST_WB1 0x0100UL 288 #define MMFI_RST_PATH0 0x0200UL 289 #define MMFI_RST_PATH1 0x0400UL 290 #define MMFI_RST_MOBF_MMFI0 0x0800UL 291 #define MMFI_RST_MOBF_MMFI1 0x1000UL 292 #define MMFI_RST_ALL 0x1FFEUL 293 294 REG16 HWInt; // 0xbf80386c 0x1b 295 #define MMFI_HWINT_SRC_MASK 0x00FFUL 296 #define MMFI_HWINT_SRC_FILEIN_DONE1 0x0004UL 297 #define MMFI_HWINT_SRC_FILEIN_DONE0 0x0008UL 298 #define MMFI_HWINT_SRC_VD3D_ERR1 0x0010UL 299 #define MMFI_HWINT_SRC_AUAUB_ERR1 0x0020UL 300 #define MMFI_HWINT_SRC_VD3D_ERR0 0x0040UL 301 #define MMFI_HWINT_SRC_AUAUB_ERR0 0x0080UL 302 #define MMFI_HWINT_STS_MASK 0xFF00UL 303 #define MMFI_HWINT_STS_SHIFT 8UL 304 #define MMFI_HWINT_STS_FILEIN_DONE1 0x0400UL 305 #define MMFI_HWINT_STS_FILEIN_DONE0 0x0800UL 306 #define MMFI_HWINT_STS_VD3D_ERR1 0x1000UL 307 #define MMFI_HWINT_STS_AUAUB_ERR1 0x2000UL 308 #define MMFI_HWINT_STS_VD3D_ERR0 0x4000UL 309 #define MMFI_HWINT_STS_AUAUB_ERR0 0x8000UL 310 311 REG16 PktChkSize; // 0xbf803870 0x1c 312 #define MMFI_PKTCHK_SIZE_MASK 0x00FFUL 313 #define MMFI_SYNC_BYTE_MASK 0xFF00UL 314 #define MMFI_SYNC_BYTE_SHIFT 8UL 315 316 REG16 MOBFKey; // 0xbf803874 0x1d 317 #define MMFI_MOBFKEY_MASK 0x001FUL 318 #define MMFI_FILEIN_CTRL_MOBF_EN 0 //not used 319 320 REG32 RAddr; // 0xbf803878 0x1e 321 #define MMFI_TSP2MI_RADDR_MASK 0x07FFFFFFUL 322 } REG_Ctrl_MMFI; 323 324 // MMFI part 2 325 typedef struct _REG_Ctrl_MMFI2 326 { 327 REG16 RVU_config[2]; // 0x40- 0x41 328 #define MMFI_RVU_PSI_EN 0x0001UL 329 #define MMFI_RVU_TEI_EN 0x0002UL 330 #define MMFI_RVU_ERR_CLR 0x0004UL 331 #define MMFI_RVU_EN 0x0008UL 332 #define MMFI_RVU_TIMESTAMP_EN 0x0010UL 333 REG16 dummy[14]; // 0x42 ~ 0x4F 334 REG16 Cfg2[2]; // 0x50~ 0x51 335 #define MMFI_CFG2_MMFI_27M_EN 0x0001UL 336 #define MMFI_CFG2_MMFI_APIDC_BYPASS 0x0020UL 337 #define MMFI_CFG2_MMFI_APIDD_BYPASS 0x0040UL 338 #define MMFI_CFG2_MMFI_PS_AUDC_EN 0x0080UL 339 #define MMFI_CFG2_MMFI_PS_AUDD_EN 0x0100UL 340 #define MMFI_CFG2_TSP_FILEIN_PAUSE_EN 0x0200UL 341 #define MMFI_CFG2_WB_FSRM_RST 0x0400UL 342 343 #define MMFI_CFG2_FILEIN_MODE_MASK (MMFI_CFG2_MMFI_APIDC_BYPASS|MMFI_CFG2_MMFI_APIDD_BYPASS \ 344 |MMFI_CFG2_MMFI_PS_AUDC_EN|MMFI_CFG2_MMFI_PS_AUDD_EN) 345 346 REG16 MMFI0_APidC_Status; // 0xbf803948 0x52 347 REG16 MMFI0_APidD_Status; // 0xbf80394C 0x53 348 REG16 MMFI1_APidC_Status; // 0xbf803950 0x54 349 REG16 MMFI1_APidD_Status; // 0xbf803954 0x55 350 REG32 PidFlt[MMFI_ENGINE_NUM][MMFI_PIDFLT_GROUP1]; // 0xbf803958 0x56 , MMFI0/1 filter 4~5 351 REG16 MMFI_ats_config[2]; // 0x66~0x67 352 #define MMFI_ATS_MODE 0x0001UL 353 #define MMFI_ATS_OFFSET_EN 0x0002UL 354 #define MMFI_ATS_OFFSET_MASK 0x1F00UL 355 #define MMFI_ATS_OFFSET_SHIFT 8UL 356 } REG_Ctrl_MMFI2; 357 #endif // _MMFILEIN_REG_H_ 358 359