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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halTSP.c
97 // @brief Transport Stream Processer (TSP) HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "halTSP.h"
101 #include "halCHIP.h"
102
103 //--------------------------------------------------------------------------------------------------
104 // Driver Compiler Option
105 //--------------------------------------------------------------------------------------------------
106 #define TSP_HAL_REG_SAFE_MODE 1UL // Register protection access between 1 task and 1+ ISR
107
108 //[HWBUG]
109 #define MULTI_ACCESS_SW_PATCH 1UL // It's still risk becuase some registers like readaddr will
110
111 // @FIXME: remove the test later
112 #define LINUX_TEST 0UL
113 // cause overflow before patching to correct value.
114 #define MIU_BUS 4UL
115
116 #define VQ_PACKET_UNIT_LEN 192UL //192 bytes
117
118 //--------------------------------------------------------------------------------------------------
119 // TSP Hardware Abstraction Layer
120 //--------------------------------------------------------------------------------------------------
121 static REG_Ctrl* _TspCtrl = NULL; // TSP0 & TSP1
122 static REG_Ctrl2* _TspCtrl2 = NULL; // TSP2
123 static REG_Ctrl3* _TspCtrl3 = NULL; // TSP3
124
125 static MS_VIRT _virtRegBase = 0;
126
127 extern MS_BOOL _bIsHK;
128 static MS_S32 _s32HALTSPMutexId = -1;
129
130 static MS_PHY _phyOrLoadMiuOffset = 0;
131 static MS_PHY _phySecBufMiuOffset = 0;
132 static MS_PHY _phyFIBufMiuOffset = 0;
133 static MS_PHY _phyPVRBufMiuOffset[TSP_PVR_IF_NUM] = {[0 ... (TSP_PVR_IF_NUM-1)] = 0UL};
134
135 static MS_BOOL _bTsPadUsed[TSP_TS_PAD_NUM] = {[0 ... (TSP_TS_PAD_NUM-1)] = FALSE };
136
137 //[NOTE] Jerry
138 // Some register has write order, for example, writing PCR_L will disable PCR counter
139 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
140 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFFUL); \
141 (reg)->H = ((value) >> 16UL); } while(0)
142
143 #define _HAL_REG32L_W(reg, value) (reg)->data = ((value) & 0x0000FFFFUL);
144
145 #define _HAL_REG16_W(reg, value) (reg)->u16data = (value);
146
147
148 #define _HAL_HALTSP_ENTRY() do{ \
149 if(_s32HALTSPMutexId == -1) \
150 _s32HALTSPMutexId = MsOS_CreateMutex(E_MSOS_FIFO, "HALTSP_Mutex", MSOS_PROCESS_SHARED); \
151 }while(0)
152 #define _HAL_HALTSP_EXIT() do{ \
153 if(_s32HALTSPMutexId != -1) \
154 { \
155 MsOS_DeleteMutex(_s32HALTSPMutexId); _s32HALTSPMutexId = -1; \
156 } \
157 }while(0)
158
159 #define _HAL_HALTSP_LOCK() (MsOS_ObtainMutex(_s32HALTSPMutexId, MSOS_WAIT_FOREVER))
160 #define _HAL_HALTSP_UNLOCK() (MsOS_ReleaseMutex(_s32HALTSPMutexId))
161
162 //--------------------------------------------------------------------------------------------------
163 // Macro of bit operations
164 //--------------------------------------------------------------------------------------------------
165 #define HAS_FLAG(flag, bit) ((flag) & (bit))
166 #define SET_FLAG(flag, bit) ((flag)|= (bit))
167 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
168 #define SET_FLAG1(flag, bit) ((flag)| (bit))
169 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
170
171 //#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT)
172 //#define BIT(x) (1<<(x))
173 //#define BMASK(bits) (BIT(((1)?bits)+1)-BIT(((0)?bits)))
174 // #define BMASK_L(bits) (BMASK(bits)&0xFFFF)
175 // #define BMASK_H(bits) (BMASK(bits)>>16)
176 //#define BITS(bits,value) ((BIT(((1)?bits)+1)-BIT(((0)?bits))) & (value<<((0)?bits)))
177
178 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3200UL + ((addr)<<2UL))))
179
180 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x1600UL + ((addr)<<2UL))))
181 #define REG_CLKGEN0_DC0_SYTNTH 0x04UL
182 #define REG_CLKGEN0_STC_CW_SEL 0x0002UL
183 #define REG_CLKGEN0_STC_CW_EN 0x0004UL
184 #define REG_CLKGEN0_STC_REF_DIV2_EN 0x0008UL
185 #define REG_CLKGEN0_DC0_STC_CW_L 0x05UL
186 #define REG_CLKGEN0_DC0_STC_CW_H 0x06UL
187
188 #define REG_CLKGEN0_TSN_CLK 0x28UL
189 #define REG_CLKGEN0_TSN_CLK_MASK 0x1FUL
190 #define REG_CLKGEN0_TSN_CLK_DEMOD 0x1CUL
191 #define REG_CLKGEN0_TSN_CLK_TS0_SHIFT 0UL
192 #define REG_CLKGEN0_TSN_CLK_TS1_SHIFT 8UL
193 //#define TSP_CLK_TS0 0
194 //#define TSP_CLK_INDEMOD 7
195 // bit[4:0] -> ts0 -> 0: disable clock
196 // 1: invert clock
197 // bit [4:2] -> 0: TS0
198 // 7: Internal Demmod
199 // bit[12:8] -> ts1 -> 0: disable clock
200 // 1: invert clock
201 // bit [4:2] -> 0: TS0
202 // 7: Internal Demmod
203 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtRegBase + 0x3c00UL + ((addr)<<2UL))))
204 #define REG_TOP_TS0_PE 0x0EUL
205 #define REG_TOP_TS0_PE_MASK 0x07FFUL
206 #define REG_TOP_TS1_PE 0x06UL
207 #define REG_TOP_TS1_PE_MASK 0x07FFUL
208
209 #define REG_TOP_TSN_MUX 0x11UL
210 #define REG_TOP_TSN_MUX_MASK 0x0FUL
211 #define REG_TOP_TSN_MUX_TS0_SHIFT 0UL
212 #define REG_TOP_TSN_MUX_TS1_SHIFT 8UL
213 // bit[3:0] -> ts0 -> 0: TS0
214 // 1: TS1
215 // 7: Demod
216 // bit[10:8] -> ts1 -> 0: TS0
217 // 1: TS1
218 // 7: Demod
219 #define REG_TOP_TSCONFIG 0x57UL
220 #define REG_TOP_TS_TS0_CFG_MASK 0x0700UL
221 #define REG_TOP_TS_TS0_CFG_PARALLEL 0x0100UL
222 #define REG_TOP_TS_TS0_CFG_SERIAL 0x0200UL
223
224 #define REG_TOP_TS_TS1_CFG_MASK 0x3800UL
225 #define REG_TOP_TS_TS1_CFG_PARALLEL 0x0800UL
226 #define REG_TOP_TS_TS1_CFG_SERIAL 0x1800UL
227 // bit[10:8] -> 0: Disable
228 // 1: use all PAD_TS0 pads
229 // 2: e PAD_TS0_VLD, PAD_TS0_SYNC, PAD_TS0_CLK and PAD_TS0_D0 pads
230 // 3: mspi mode
231 // 4: 3 wire mode
232
233 #define ABS_DIFF(x1, x2) (((x1) > (x2))? ((x1) - (x2)) : ((x2) - (x1)))
234 #define IsCover(_start1, _end1, _start2, _end2) (ABS_DIFF(_end1, _end2) < (((_end1) > (_end2))?((_end1)-(_start1)):((_end2)-(_start2))) )?TRUE:FALSE
235 //--------------------------------------------------------------------------------------------------
236 // Forward declaration
237 //--------------------------------------------------------------------------------------------------
238 static void _HAL_TSP_FW_load(
239 MS_PHY phyFwAddrPhys,
240 MS_U32 u32FwSize,
241 MS_BOOL bFwDMA,
242 MS_BOOL bIQmem,
243 MS_BOOL bDQmem);
244
245 static void _HAL_TSP_tsif_select(MS_U8 u8_tsif);
246 // static void _HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 PadId);
247
248 //--------------------------------------------------------------------------------------------------
249 // Implementation
250 //--------------------------------------------------------------------------------------------------
_delay(void)251 static void _delay(void)
252 {
253 volatile MS_U32 i;
254 for (i = 0; i< 0xFFFFUL; i++);
255 }
256
_HAL_REG32_R(REG32 * reg)257 static MS_U32 _HAL_REG32_R(REG32 *reg)
258 {
259 MS_U32 value = 0UL;
260 value = (reg)->H << 16UL;
261 value |= (reg)->L;
262 return value;
263 }
264
_HAL_REG32L_R(REG32_L * reg)265 static MS_U16 _HAL_REG32L_R(REG32_L *reg)
266 {
267 MS_U16 value;
268 value = (reg)->data;
269 return value;
270 }
271
_HAL_REG16_R(REG16 * reg)272 static MS_U16 _HAL_REG16_R(REG16 *reg)
273 {
274 MS_U16 value = 0;
275 value = (reg)->u16data;
276 return value;
277 }
278
_HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)279 static MS_PHY _HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)
280 {
281 #ifdef HAL_MIU2_BASE
282 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
283 return (MS_PHY)HAL_MIU2_BASE;
284 else
285 #endif //HAL_MIU2_BUS_BASE
286 #ifdef HAL_MIU1_BASE
287 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
288 return (MS_PHY)HAL_MIU1_BASE;
289 else
290 #endif //HAL_MIU1_BUS_BASE
291 return (MS_PHY)HAL_MIU0_BASE;
292 }
293
294 #define REG16_T(addr) (*((volatile MS_U16*)(addr)))
295 #define ADDR_INDR_CTRL (_virtRegBase+ 0x2b20UL)
296 #define ADDR_INDR_ADDR0 (_virtRegBase+ 0x2b24UL)
297 #define ADDR_INDR_ADDR1 (_virtRegBase+ 0x2b28UL)
298 #define ADDR_INDR_WRITE0 (_virtRegBase+ 0x2b2cUL)
299 #define ADDR_INDR_WRITE1 (_virtRegBase+ 0x2b30UL)
300 #define ADDR_INDR_READ0 (_virtRegBase+ 0x2b34UL)
301 #define ADDR_INDR_READ1 (_virtRegBase+ 0x2b38UL)
302
303 #if 0
304 #define XBYTE_1591 (_virtRegBase+ 0x2a0cUL) // TsRec_Head21_Mid20
305 #define XBYTE_15A4 (_virtRegBase+ 0x2a10UL) // TsRec_Mid21_Tail20
306 #define XBYTE_15A6 (_virtRegBase+ 0x2b48UL) // TsRec_Mid
307
308 void HAL_TSP_HW_Lock_Init(void)
309 {
310 REG16_T(XBYTE_1591) = 0;
311 REG16_T(XBYTE_15A4) = 0;
312 REG16_T(XBYTE_15A6) = 0;
313 }
314
315 void _HAL_TSP_HW_Lock(void)
316 {
317 #ifdef MCU_HK
318 REG16_T(XBYTE_1591) = 0xFF;
319 REG16_T(XBYTE_15A4) = 0xFF;
320 while (REG16_T(XBYTE_15A4) && REG16_T(XBYTE_15A6));
321 REG16_T(XBYTE_1591) = 0xFF;
322 #else // MIPS HK
323 REG16_T(XBYTE_15A6) = 0xFF;
324 REG16_T(XBYTE_15A4) = 0x00;
325 while (REG16_T(XBYTE_1591) && (REG16_T(XBYTE_15A4)==0));
326 #endif
327 }
328
329 void _HAL_TSP_HW_Unlock(void)
330 {
331 #ifdef MCU_HK
332 REG16_T(XBYTE_1591) = 0x00;
333 #else
334 REG16_T(XBYTE_15A6) = 0x00;
335 #endif
336 }
337
338 #undef XBYTE_1591
339 #undef XBYTE_15A4
340 #undef XBYTE_15A6
341
342 #else
343
344 #define TSP_SEM_AEON (_virtRegBase+ 0xC1480UL) //TSP_HW_SEMAPHORE0, TS3 0x20
345 #define TSP_SEM_ORDER (_virtRegBase+ 0xC1484UL) // TSP_HW_SEMAPHORE1, TS3 0x21
346 #define TSP_SEM_MIPS (_virtRegBase+ 0xC1488UL) // TSP_HW_SEMAPHORE2, TS3 0x22
347
HAL_TSP_HW_Lock_Init(void)348 void HAL_TSP_HW_Lock_Init(void)
349 {
350 REG16_T(TSP_SEM_AEON) = 0;
351 REG16_T(TSP_SEM_MIPS) = 0;
352 REG16_T(TSP_SEM_ORDER) = 0;
353
354 _HAL_HALTSP_ENTRY();
355 }
356
_HAL_TSP_HW_TryLock(MS_BOOL bInit)357 static MS_BOOL _HAL_TSP_HW_TryLock(MS_BOOL bInit)
358 {
359 if (_bIsHK)
360 {
361 if (bInit)
362 {
363 REG16_T(TSP_SEM_AEON) = 0xFFFF;
364 REG16_T(TSP_SEM_ORDER) = 0xFFFF;
365 }
366 if (REG16_T(TSP_SEM_ORDER) && REG16_T(TSP_SEM_MIPS))
367 {
368 // REG16_T(TSP_SEM_AEON) = 0x0000;
369 return FALSE;
370 }
371 return TRUE;
372 }
373 else
374 {
375 if (bInit)
376 {
377 REG16_T(TSP_SEM_MIPS) = 0xFFFF;
378 REG16_T(TSP_SEM_ORDER) = 0x00;
379 }
380 if ((REG16_T(TSP_SEM_ORDER) ==0) && (REG16_T(TSP_SEM_AEON)))
381 {
382 // REG16_T(TSP_SEM_MIPS) = 0x0000;
383 return FALSE;
384 }
385 return TRUE;
386 }
387 }
388
_HAL_TSP_HW_Lock(void)389 static void _HAL_TSP_HW_Lock(void)
390 {
391 if (FALSE == _HAL_TSP_HW_TryLock(TRUE))
392 {
393 while (FALSE == _HAL_TSP_HW_TryLock(FALSE));
394 }
395 }
396
_HAL_TSP_HW_Unlock(void)397 static void _HAL_TSP_HW_Unlock(void)
398 {
399 if (_bIsHK)
400 {
401 REG16_T(TSP_SEM_AEON) = 0x00;
402 }
403 else
404 {
405 REG16_T(TSP_SEM_MIPS) = 0x00;
406 }
407 }
408
HAL_TSP_HW_Lock_Release(void)409 void HAL_TSP_HW_Lock_Release(void)
410 {
411 REG16_T(TSP_SEM_AEON) = 0x00;
412 REG16_T(TSP_SEM_MIPS) = 0x00;
413
414 _HAL_HALTSP_EXIT();
415
416
417 }
418
HAL_TSP_TTX_IsAccess(MS_U32 u32Try)419 MS_BOOL HAL_TSP_TTX_IsAccess(MS_U32 u32Try)
420 {
421 if(u32Try == 0)
422 return FALSE;
423
424 if (_bIsHK)
425 {
426 if ( REG16_T(TSP_SEM_AEON))
427 {
428 return FALSE;
429 }
430 }
431 else
432 {
433 if (REG16_T(TSP_SEM_MIPS))
434 {
435 return FALSE;
436 }
437 }
438
439 if (_HAL_TSP_HW_TryLock(TRUE))
440 {
441 return TRUE;
442 }
443
444 _HAL_TSP_HW_Unlock();
445 return FALSE;
446 }
447
HAL_TSP_TTX_UnlockAccess(void)448 void HAL_TSP_TTX_UnlockAccess(void)
449 {
450 _HAL_TSP_HW_Unlock();
451 }
452
453 #undef TSP_SEM_AEON
454 #undef TSP_SEM_MIPS
455 #undef TSP_SEM_ORDER
456
457 #endif
458
HAL_REG32_IndR(REG32 * reg)459 MS_U32 HAL_REG32_IndR(REG32 *reg)
460 {
461 MS_VIRT virtReg = (MS_VIRT)reg;
462 MS_U32 u32Ret;
463
464 _HAL_TSP_HW_Lock();
465
466 _HAL_HALTSP_LOCK();
467
468 // set address
469 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
470 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
471
472 // set command
473 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
474 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
475 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
476
477 // get read value
478 u32Ret = ((MS_U32)(REG16_T(ADDR_INDR_READ0))| ((MS_U32)(REG16_T(ADDR_INDR_READ1)<< 16UL)));
479
480 _HAL_HALTSP_UNLOCK();
481 _HAL_TSP_HW_Unlock();
482 return u32Ret;
483 }
484
HAL_REG32_IndR_tmp(REG32 * reg)485 static MS_U32 HAL_REG32_IndR_tmp(REG32 *reg)
486 {
487 MS_VIRT virtReg = (MS_VIRT)reg;
488 MS_U32 u32Ret;
489
490 _HAL_HALTSP_LOCK();
491
492 // set address
493 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
494 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
495
496 // set command
497 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
498 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
499 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_READ | TSP_IDR_START);
500
501 // get read value
502 u32Ret = ((MS_U32)(REG16_T(ADDR_INDR_READ0))| ((MS_U32)(REG16_T(ADDR_INDR_READ1)<< 16)));
503
504 _HAL_HALTSP_UNLOCK();
505
506 return u32Ret;
507 }
HAL_REG32_IndW_tmp(REG32 * reg,MS_U32 value)508 static void HAL_REG32_IndW_tmp(REG32 *reg, MS_U32 value)
509 {
510 MS_VIRT virtReg = (MS_VIRT)reg;
511 _HAL_HALTSP_LOCK();
512
513 // set address
514 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
515 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
516
517 // set write value
518 REG16_T(ADDR_INDR_WRITE0)= (MS_U16)value;
519 REG16_T(ADDR_INDR_WRITE1)= (MS_U16)(value >> 16UL);
520
521 // set command
522 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
523 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
524 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
525
526 _HAL_HALTSP_UNLOCK();
527 }
528
HAL_REG32_IndW(REG32 * reg,MS_U32 value)529 void HAL_REG32_IndW(REG32 *reg, MS_U32 value)
530 {
531 MS_VIRT virtReg = (MS_VIRT)reg;
532 _HAL_TSP_HW_Lock();
533
534 _HAL_HALTSP_LOCK();
535
536 // set address
537 REG16_T(ADDR_INDR_ADDR0)= (MS_U16)(virtReg>> 1UL);
538 REG16_T(ADDR_INDR_ADDR1)= (MS_U16)(virtReg>> 17UL);
539
540 // set write value
541 REG16_T(ADDR_INDR_WRITE0)= (MS_U16)value;
542 REG16_T(ADDR_INDR_WRITE1)= (MS_U16)(value >> 16UL);
543
544 // set command
545 // REG16_T(ADDR_INDR_CTRL)= (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
546 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) & 0xFF00;
547 REG16_T(ADDR_INDR_CTRL)= REG16_T(ADDR_INDR_CTRL) | (TSP_IDR_MCUWAIT | TSP_IDR_WRITE | TSP_IDR_START);
548
549 _HAL_HALTSP_UNLOCK();
550
551 _HAL_TSP_HW_Unlock();
552 }
553
554 static MS_U16 u16LastAddr0, u16LastAddr1, u16LastWrite0, u16LastWrite1, u16LastRead0, u16LastRead1;
555
556 static MS_U32 _u32PidFltBuf[(TSP_PIDFLT_NUM_ALL*sizeof(REG_PidFlt))>> 3];
557 static MS_U32 _u32SecFltBuf[TSP_SECFLT_NUM*((sizeof(REG_SecFlt)-sizeof((((REG_SecFlt*)0)->_x50)))>> 3)];
558 //[LEGACY] //[OBSOLETE]
559 MS_BOOL _bIsHK = TRUE;
560 //[LEGACY] //[OBSOLETE]
HAL_TSP_SaveFltState(void)561 void HAL_TSP_SaveFltState(void)
562 {
563 MS_U32 u32EngId;
564 MS_U32 i, j;
565 MS_U32 u32SecEnd = ((size_t)&(((REG_SecFlt*)0)->_x50))/sizeof(REG32);
566
567 for (u32EngId = 0; u32EngId < TSP_ENGINE_NUM; u32EngId++)
568 {
569 for (i = 0; i < TSP_PIDFLT_NUM_ALL; i++)
570 {
571 REG_PidFlt *pPidFilter = &(_TspPid[u32EngId].Flt[i]);
572 _u32PidFltBuf[i] = HAL_REG32_IndR(pPidFilter);
573 }
574 j = 0;
575 for (i = 0; i < TSP_SECFLT_NUM; i++)
576 {
577 REG32* pRegStart = (REG32*) &(_TspSec[u32EngId].Flt[i]);
578 // REG32* pRegEnd = (REG32*)&(_TspSec[u32EngId].Flt[i + 1]);
579 REG32* pRegEnd = pRegStart + u32SecEnd;
580 REG32* pReg = pRegStart;
581 while (pReg < pRegEnd)
582 {
583 _u32SecFltBuf[j] = HAL_REG32_IndR(pReg);
584 j++;
585 pReg++;
586 }
587 }
588 }
589 }
HAL_TSP_RestoreFltState(void)590 void HAL_TSP_RestoreFltState(void)
591 {
592 MS_U32 u32EngId;
593 MS_U32 i, j;
594 MS_U32 u32SecEnd = ((size_t)&(((REG_SecFlt*)0)->_x50))/sizeof(REG32);
595
596 for (u32EngId = 0; u32EngId < TSP_ENGINE_NUM; u32EngId++)
597 {
598 for (i = 0; i < TSP_PIDFLT_NUM_ALL; i++)
599 {
600 REG_PidFlt *pPidFilter = &(_TspPid[u32EngId].Flt[i]);
601 HAL_REG32_IndW(pPidFilter, _u32PidFltBuf[i]);
602 }
603 j = 0;
604 for (i = 0; i < TSP_SECFLT_NUM; i++)
605 {
606 REG32* pRegStart = (REG32*) &(_TspSec[u32EngId].Flt[i]);
607 REG32* pRegEnd = pRegStart + u32SecEnd;
608 REG32* pReg = pRegStart;
609 while (pReg < pRegEnd)
610 {
611 HAL_REG32_IndW(pReg, _u32SecFltBuf[j]);
612 j++;
613 pReg++;
614 }
615 }
616 }
617 }
618
619
HAL_TSP_ISR_SAVE_ALL(void)620 void HAL_TSP_ISR_SAVE_ALL(void)
621 {
622 // save address
623 u16LastAddr0= (MS_U16)REG16_T(ADDR_INDR_ADDR0);
624 u16LastAddr1= (MS_U16)REG16_T(ADDR_INDR_ADDR1);
625
626 // save write
627 u16LastWrite0= (MS_U16)REG16_T(ADDR_INDR_WRITE0);
628 u16LastWrite1= (MS_U16)REG16_T(ADDR_INDR_WRITE1);
629
630 // save read
631 u16LastRead0= (MS_U16)REG16_T(ADDR_INDR_READ0);
632 u16LastRead1= (MS_U16)REG16_T(ADDR_INDR_READ1);
633 }
634
HAL_TSP_ISR_RESTORE_ALL(void)635 void HAL_TSP_ISR_RESTORE_ALL(void)
636 {
637 // restore read
638 REG16_T(ADDR_INDR_READ0)= u16LastRead0;
639 REG16_T(ADDR_INDR_READ1)= u16LastRead1;
640
641 // restore write
642 REG16_T(ADDR_INDR_WRITE0)= u16LastWrite0;
643 REG16_T(ADDR_INDR_WRITE1)= u16LastWrite1;
644
645 // restore addr
646 REG16_T(ADDR_INDR_ADDR0)= u16LastAddr0;
647 REG16_T(ADDR_INDR_ADDR1)= u16LastAddr1;
648 }
649 #undef ADDR_INDR_CTRL
650 #undef ADDR_INDR_ADDR0
651 #undef ADDR_INDR_ADDR1
652 #undef ADDR_INDR_WRITE0
653 #undef ADDR_INDR_WRITE1
654 #undef ADDR_INDR_READ0
655 #undef ADDR_INDR_READ1
656
657 //--------------------------------------------------------------------------------------------------
658 // For MISC part
659 //--------------------------------------------------------------------------------------------------
HAL_TSP_Scmb_Detect(MS_BOOL bEnable)660 void HAL_TSP_Scmb_Detect(MS_BOOL bEnable)
661 {
662 if (bEnable)
663 {
664 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
665 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld));
666 }
667 else
668 {
669 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
670 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld| TSP_match_pid_scr_fi_ld));
671 }
672 }
673
HAL_TSP_CSA_Set_ScrmPath(MS_U32 u32ScrmPath)674 void HAL_TSP_CSA_Set_ScrmPath(MS_U32 u32ScrmPath)
675 {
676 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL, u32ScrmPath);
677 }
678
HAL_TSP_Set_AVPAUSE(MS_BOOL bSet)679 void HAL_TSP_Set_AVPAUSE(MS_BOOL bSet)
680 {
681 if (bSet)
682 {
683 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL,
684 SET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE));
685 }
686 else
687 {
688 _HAL_REG32L_W(&_TspCtrl[0].CA_CTRL,
689 RESET_FLAG1(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL), TSP_CA_AVPAUSE));
690 }
691 }
692
HAL_TSP_CSA_Get_ScrmPath(void)693 MS_U32 HAL_TSP_CSA_Get_ScrmPath(void)
694 {
695 return (MS_U32)(_HAL_REG32L_R(&_TspCtrl[0].CA_CTRL) & TSP_CA_CTRL_MASK);
696 }
697
698 //--------------------------------------------------------------------------------------------------
699 // For PID filter part
700 //--------------------------------------------------------------------------------------------------
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFilter)701 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFilter)
702 {
703 return (HAL_REG32_IndR((REG32 *)pPidFilter) & TSP_PIDFLT_OUT_MASK);
704 }
705
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFilter)706 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFilter)
707 {
708 return (HAS_FLAG(HAL_REG32_IndR((REG32 *)pPidFilter), TSP_PIDFLT_PID_MASK)>> TSP_PIDFLT_PID_SHFT);
709 }
710
HAL_TSP_PidFlt_SetPid(REG_PidFlt * pPidFilter,MS_U32 u32PID)711 void HAL_TSP_PidFlt_SetPid(REG_PidFlt *pPidFilter, MS_U32 u32PID)
712 {
713 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_PID_MASK) | ((u32PID << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
714 }
715
HAL_TSP_PidFlt_SelFltOutput(REG_PidFlt * pPidFilter,MS_U32 u32FltOutput)716 void HAL_TSP_PidFlt_SelFltOutput(REG_PidFlt *pPidFilter, MS_U32 u32FltOutput)
717 {
718 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_OUT_MASK) | (u32FltOutput & TSP_PIDFLT_OUT_MASK));
719 }
720
HAL_TSP_PidFlt_SelSecFlt(REG_PidFlt * pPidFilter,MS_U32 u32SecFltId)721 void HAL_TSP_PidFlt_SelSecFlt(REG_PidFlt *pPidFilter, MS_U32 u32SecFltId)
722 {
723 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
724 }
725
HAL_TSP_PidFlt_PVREnable(REG_PidFlt * pPidFilter)726 void HAL_TSP_PidFlt_PVREnable(REG_PidFlt *pPidFilter)
727 {
728 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) | TSP_PIDFLT_PVR_ENABLE));
729 }
730
731
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFilter,MS_U32 u32FltType)732 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFilter, MS_U32 u32FltType)
733 {
734 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, (HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~TSP_SECFLT_TYPE_MASK) | (u32FltType << TSP_SECFLT_TYPE_SHFT));
735 }
736
HAL_TSP_PidFlt_GetSecFlt(REG_PidFlt * pPidFilter)737 MS_U32 HAL_TSP_PidFlt_GetSecFlt(REG_PidFlt *pPidFilter)
738 {
739 return ((HAL_REG32_IndR((REG32 *)pPidFilter) & TSP_PIDFLT_SECFLT_MASK) >> TSP_PIDFLT_SECFLT_SHFT);
740 }
741
HAL_TSP_PidFlt_SelFltSource(REG_PidFlt * pPidFilter,MS_U32 u32FltSource)742 void HAL_TSP_PidFlt_SelFltSource(REG_PidFlt *pPidFilter, MS_U32 u32FltSource)
743 {
744 HAL_REG32_IndW((REG32 *)pPidFilter, (HAL_REG32_IndR((REG32 *)pPidFilter) & ~TSP_PIDFLT_IN_MASK) | (u32FltSource & TSP_PIDFLT_IN_MASK));
745 }
746
747 //--------------------------------------------------------------------------------------------------
748 // For section filter part
749 //--------------------------------------------------------------------------------------------------
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFilter)750 MS_U32 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFilter)
751 {
752 return (pSecFilter - (REG_SecFlt*)REG_SECFLT_BASE)>> 8; // div 0x100
753 }
754
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFilter)755 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFilter)
756 {
757 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
758 }
759
HAL_TSP_SecFlt_SetRmnCount(REG_SecFlt * pSecFilter,MS_U32 u32RmnCount)760 void HAL_TSP_SecFlt_SetRmnCount(REG_SecFlt *pSecFilter, MS_U32 u32RmnCount)
761 {
762 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_RMNCNT_MASK) |
763 ((u32RmnCount << TSP_SECFLT_RMNCNT_SHFT) & TSP_SECFLT_RMNCNT_MASK));
764 }
765
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFilter)766 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFilter)
767 {
768 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, 0);
769 }
770
771
HAL_TSP_SW_INT_STATUS(void)772 MS_U32 HAL_TSP_SW_INT_STATUS(void)
773 {
774 if (_bIsHK)
775 {
776 return _HAL_REG32_R(&_TspCtrl[0].SwInt_Stat);
777 }
778 else
779 {
780 MS_U32 u32SwIntStatus = (MS_U32)_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_M);
781 u32SwIntStatus |= ((_HAL_REG32_R(&_TspCtrl[0].SwInt_Stat1_H) & TSP_SWINT1_H_MASK) >> TSP_SWINT1_H_SHFT)<< 16;
782 return u32SwIntStatus;
783 }
784 }
785
786 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFilter,MS_U8 * pu8Mask)787 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFilter, MS_U8 *pu8Mask)
788 {
789 MS_U32 i;
790 MS_U32 u32Temp;
791 MS_U32 j;
792
793 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
794 {
795 j = (i<< 2);
796 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
797 HAL_REG32_IndW((REG32 *)&pSecFilter->Mask[i], u32Temp);
798 }
799 }
800
801 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFilter,MS_U8 * pu8NMask)802 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFilter, MS_U8 *pu8NMask)
803 {
804 MS_U32 u32FltId;
805 MS_U32 u32Temp;
806 REG_SecFlt* ptempSecFlt = &(_TspSec[0].Flt[31]);
807
808 u32Temp = (pu8NMask[0x0]) | (pu8NMask[0x1] << 8 ) | (pu8NMask[0x2] << 16 )| (pu8NMask[0x3] << 24);
809 HAL_REG32_IndW(&(ptempSecFlt->Match[0]), u32Temp);
810
811 u32Temp = (pu8NMask[0x4]) | (pu8NMask[0x5] << 8 ) | (pu8NMask[0x6] << 16 )| (pu8NMask[0x7] << 24);
812 HAL_REG32_IndW(&(ptempSecFlt->Match[1]), u32Temp);
813
814 u32Temp = (pu8NMask[0x8]) | (pu8NMask[0x9] << 8 ) | (pu8NMask[0xa] << 16 )| (pu8NMask[0xb] << 24);
815 HAL_REG32_IndW(&(ptempSecFlt->Match[2]), u32Temp);
816
817 u32Temp = (pu8NMask[0xc]) | (pu8NMask[0xd] << 8 ) | (pu8NMask[0xe] << 16 )| (pu8NMask[0xf] << 24);
818 HAL_REG32_IndW(&(ptempSecFlt->Match[3]), u32Temp);
819
820 u32FltId = (MS_U32)(pSecFilter - (REG_SecFlt*)REG_SECFLT_BASE);
821
822 //printf("[%s][%d] u32FltId %d\n", __FUNCTION__, __LINE__, (unsigned int)u32FltId);
823
824 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_NMATCH | u32FltId);
825
826 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
827 }
828
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFilter,MS_U8 * pu8Match)829 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFilter, MS_U8 *pu8Match)
830 {
831 MS_U32 i;
832 MS_U32 u32Temp;
833 MS_U32 j;
834
835 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
836 {
837 j = (i<< 2);
838 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
839 HAL_REG32_IndW((REG32 *)&pSecFilter->Match[i], u32Temp);
840 }
841 }
842
HAL_TSP_SecFlt_SetReqCount(REG_SecFlt * pSecFilter,MS_U32 u32ReqCount)843 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFilter, MS_U32 u32ReqCount)
844 {
845 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_REQCNT_MASK) |
846 ((u32ReqCount << TSP_SECFLT_REQCNT_SHFT) & TSP_SECFLT_REQCNT_MASK));
847 }
848
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFilter,MS_U32 u32SecFltMode)849 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFilter, MS_U32 u32SecFltMode)
850 {
851 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, (HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
852 }
853
HAL_TSP_SecFlt_GetCRC32(REG_SecFlt * pSecFilter)854 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFilter)
855 {
856 return HAL_REG32_IndR((REG32 *)&pSecFilter->CRC32);
857 }
858
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFilter)859 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFilter)
860 {
861 return ((HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
862 }
863
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFilter)864 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFilter)
865 {
866 return ((HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
867 }
868
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFilter)869 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFilter)
870 {
871 HAL_REG32_IndW((REG32 *)&pSecFilter->Ctrl, HAL_REG32_IndR((REG32 *)&pSecFilter->Ctrl) | TSP_SECFLT_PCRRST);
872 }
873
HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId)874 void HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId)
875 {
876 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_VER_RESET | u32SecFltId);
877 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
878 }
879
HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr)880 void HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr)
881 {
882 MS_PHY phyAddr = phyDataAddr - _HAL_TSP_MIU_OFFSET(phyDataAddr);
883 MS_U32 u32cmd = TSP_MCU_CMD_MEM_HIGH_ADDR | ((MS_U32)(phyAddr & 0xFFFF0000UL) >> 16UL);
884
885 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32cmd);
886 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
887
888 u32cmd = TSP_MCU_CMD_MEM_LOW_ADDR | ((MS_U32)(phyAddr & 0xFFFFUL));
889 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32cmd);
890 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
891 }
892
893
894 //--------------------------------------------------------------------------------------------------
895 // For section buffer part
896 //--------------------------------------------------------------------------------------------------
897 // To avoid SW read hidden HW byte enable information.
898 #define _TSP_SEC_BUF_ADDR_START(pSecFilter) (TSP_SECFLT_BUFSTART_MASK & HAL_REG32_IndR((REG32 *)&((pSecFilter)->BufStart)))
899
HAL_TSP_SecBuf_SetBuffer(REG_SecFlt * pSecBuf,MS_PHY phyStartAddr,MS_U32 u32BufSize)900 void HAL_TSP_SecBuf_SetBuffer(REG_SecFlt *pSecBuf, MS_PHY phyStartAddr, MS_U32 u32BufSize)
901 {
902 MS_PHY phyAddr = 0UL;
903
904 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyStartAddr);
905 phyAddr = phyStartAddr - _phySecBufMiuOffset;
906
907 HAL_REG32_IndW((REG32 *)&pSecBuf->BufStart, (MS_U32)phyAddr);
908 HAL_REG32_IndW((REG32 *)&pSecBuf->BufEnd, ((MS_U32)phyAddr + u32BufSize));
909 }
910
HAL_TSP_SecBuf_SetBufRead(REG_SecFlt * pSecBuf,MS_PHY phyReadAddr)911 void HAL_TSP_SecBuf_SetBufRead(REG_SecFlt *pSecBuf, MS_PHY phyReadAddr)
912 {
913 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyReadAddr);
914
915 HAL_REG32_IndW((REG32 *)&pSecBuf->BufRead, (MS_U32)(phyReadAddr-_phySecBufMiuOffset));
916 }
917
HAL_TSP_SecBuf_GetBufStart(REG_SecFlt * pSecBuf)918 MS_PHY HAL_TSP_SecBuf_GetBufStart(REG_SecFlt *pSecBuf)
919 {
920 return (((MS_PHY)_TSP_SEC_BUF_ADDR_START(pSecBuf) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
921 }
922
HAL_TSP_SecBuf_GetBufEnd(REG_SecFlt * pSecBuf)923 MS_PHY HAL_TSP_SecBuf_GetBufEnd(REG_SecFlt *pSecBuf)
924 {
925 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufEnd) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
926 }
927
HAL_TSP_SecBuf_GetBufCur(REG_SecFlt * pSecBuf)928 MS_PHY HAL_TSP_SecBuf_GetBufCur(REG_SecFlt *pSecBuf)
929 {
930 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufCur) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
931 }
932
HAL_TSP_SecBuf_ResetBuffer(REG_SecFlt * pSecBuf)933 void HAL_TSP_SecBuf_ResetBuffer(REG_SecFlt *pSecBuf)
934 {
935 HAL_REG32_IndW((REG32 *)&pSecBuf->BufCur, _TSP_SEC_BUF_ADDR_START(pSecBuf));
936 HAL_REG32_IndW((REG32 *)&pSecBuf->BufRead, _TSP_SEC_BUF_ADDR_START(pSecBuf));
937 HAL_REG32_IndW((REG32 *)&pSecBuf->BufWrite, _TSP_SEC_BUF_ADDR_START(pSecBuf));
938 }
939
HAL_TSP_SecBuf_GetBufRead(REG_SecFlt * pSecBuf)940 MS_PHY HAL_TSP_SecBuf_GetBufRead(REG_SecFlt *pSecBuf)
941 {
942 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufRead) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
943 }
944
HAL_TSP_SecBuf_GetBufWrite(REG_SecFlt * pSecBuf)945 MS_PHY HAL_TSP_SecBuf_GetBufWrite(REG_SecFlt *pSecBuf)
946 {
947 return (((MS_PHY)HAL_REG32_IndR((REG32 *)&pSecBuf->BufWrite) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
948 }
949
950 #undef _TSP_SEC_BUF_ADDR_START
951
HAL_TSP_SecBuf_SetBufRead_tmp(REG_SecFlt * pSecBuf,MS_PHY phyReadAddr)952 void HAL_TSP_SecBuf_SetBufRead_tmp(REG_SecFlt *pSecBuf, MS_PHY phyReadAddr)
953 {
954 _phySecBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyReadAddr);
955 HAL_REG32_IndW_tmp((REG32 *)&pSecBuf->BufRead, (MS_U32)(phyReadAddr-_phySecBufMiuOffset));
956 }
957
HAL_TSP_SecBuf_GetBufWrite_tmp(REG_SecFlt * pSecBuf)958 MS_PHY HAL_TSP_SecBuf_GetBufWrite_tmp(REG_SecFlt *pSecBuf)
959 {
960 return (((MS_PHY)HAL_REG32_IndR_tmp((REG32 *)&pSecBuf->BufWrite) & 0xFFFFFFFFUL) + _phySecBufMiuOffset);
961 }
962
963 //--------------------------------------------------------------------------------------------------
964 // For DMA part
965 //--------------------------------------------------------------------------------------------------
966 //[HW LIMIT][HW TODO] TsDma pause can not be access by TSP CPU
967 //[HW LIMIT][HW TODO] TsDma pause it hard to control because read/write in different register
968 //[HW LIMIT][HW TODO] When setting TsDma it should be disable interrupt
HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay)969 void HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay)
970 {
971 // Richard: the file in timer in Uranus is 24 bits.
972 // to simplify the process, writing 32 bits directly.
973 // HW will truncate the high 8 bits out, and use low 24 bits only (from Albert Lin)
974 _HAL_REG32_W(&_TspCtrl[0].TsFileIn_Timer, u32Delay);
975 }
976
HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr)977 void HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr)
978 {
979 _phyFIBufMiuOffset = _HAL_TSP_MIU_OFFSET(phyStreamAddr);
980 _HAL_REG32_W(&_TspCtrl[0].TsDma_Addr, (MS_U32)(phyStreamAddr-_phyFIBufMiuOffset));
981 }
982
HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize)983 MS_BOOL HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize)
984 {
985 if (u32StreamSize < 16) // t2 HW limite, CMQ had some problem while bufsize < 16
986 {
987 return FALSE;
988 }
989 _HAL_REG32_W(&_TspCtrl[0].TsDma_Size, u32StreamSize);
990 return TRUE;
991 }
992
HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl)993 void HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl)
994 {
995 // enable filein byte timer
996 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
997 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_BYTE_TIMER_EN));
998
999 _HAL_REG32_W(&_TspCtrl[0].TsDma_Ctrl_CmdQ, TSP_TSDMA_CTRL_START | (u32TsDmaCtrl & TSP_TSDMA_CTRL_PESMODE_MASK));
1000 }
1001
HAL_TSP_TsDma_Pause(void)1002 void HAL_TSP_TsDma_Pause(void)
1003 {
1004 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1005 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE));
1006 }
1007
HAL_TSP_TsDma_Resume(void)1008 void HAL_TSP_TsDma_Resume(void)
1009 {
1010 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1011 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE));
1012 }
1013
HAL_TSP_CmdQ_TsDma_GetState(void)1014 MS_U32 HAL_TSP_CmdQ_TsDma_GetState(void)
1015 {
1016 return (HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ), TSP_TSDMA_CTRL_START) |
1017 (MS_U32)(HAS_FLAG(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_PAUSE)));
1018 }
1019
HAL_TSP_CmdQ_EmptyCount(void)1020 MS_U32 HAL_TSP_CmdQ_EmptyCount(void)
1021 {
1022 return (TSP_CMDQ_SIZE - ((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_CNT_MASK)>>TSP_CMDQ_CNT_SHFT));
1023 }
1024
HAL_TSP_Get_CmdQFifoLevel(void)1025 MS_U8 HAL_TSP_Get_CmdQFifoLevel(void)
1026 {
1027 return (MS_U8)((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT);
1028 }
1029
HAL_TSP_SetCtrlMode(MS_U32 u32EngId,MS_U32 u32Mode,MS_U32 u32TsIfId)1030 void HAL_TSP_SetCtrlMode(MS_U32 u32EngId, MS_U32 u32Mode, MS_U32 u32TsIfId)
1031 {
1032 // Control bits:
1033 // TSP_CTRL_CPU_EN
1034 // TSP_CTRL_SW_RST
1035 // TSP_CTRL_MEM_DMA_EN
1036
1037 // for file in related setting
1038 if(u32Mode == 0)
1039 {
1040 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1041 (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl) & ~(TSP_CTRL_CPU_EN |
1042 TSP_CTRL_SW_RST |
1043 TSP_CTRL_TSFILE_EN)));
1044 HAL_TSP_filein_enable(FALSE);
1045 }
1046 else
1047 {
1048 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1049 (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl) & ~(TSP_CTRL_CPU_EN |
1050 TSP_CTRL_SW_RST |
1051 //TSP_CTRL_TSFILE_EN |
1052 //[URANUS] TSP_CTRL_CLK_GATING_DISABLE |
1053 // @FIXME: Richard ignore this at this stage
1054 0 )) | u32Mode);
1055
1056 if(HAS_FLAG(u32Mode, TSP_CTRL_TSFILE_EN))
1057 HAL_TSP_filein_enable(TRUE);
1058 }
1059
1060 if (TSP_IF_NUM > u32TsIfId)
1061 {
1062 _HAL_TSP_tsif_select(HAS_FLAG(u32Mode, (MS_U8)(u32TsIfId & 0xFF)));
1063 }
1064 }
1065
1066 //--------------------------------------------------------------------------------------------------
1067 // For PVR part
1068 //--------------------------------------------------------------------------------------------------
HAL_TSP_PVR_SetBuffer(MS_PHY phyBufStart0,MS_PHY phyBufStart1,MS_U32 u32BufSize0,MS_U32 u32BufSize1)1069 void HAL_TSP_PVR_SetBuffer(MS_PHY phyBufStart0, MS_PHY phyBufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1)
1070 {
1071 MS_PHY phyBufEnd;
1072
1073 _phyPVRBufMiuOffset[0] = _HAL_TSP_MIU_OFFSET(phyBufStart0);
1074
1075 // for buffer 0
1076 phyBufEnd= phyBufStart0+ u32BufSize0;
1077 _HAL_REG32_W(&_TspCtrl[0].TsRec_Head, ((MS_U32)(phyBufStart0-_phyPVRBufMiuOffset[0])>> MIU_BUS)); // 8 bytes unit
1078 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail, ((MS_U32)(phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS)); // 8 bytes unit
1079
1080 // for buffer 1
1081 phyBufEnd= phyBufStart1+ u32BufSize1;
1082 #define ADDR_PVR_HEAD20 (_virtRegBase+ 0x2a04)
1083 #define ADDR_PVR_HEAD21 (_virtRegBase+ 0x2a08)
1084 #define ADDR_PVR_MID20 (_virtRegBase+ 0x2a0c)
1085 #define ADDR_PVR_MID21 (_virtRegBase+ 0x2a10)
1086 #define ADDR_PVR_TAIL20 (_virtRegBase+ 0x2a14)
1087 #define ADDR_PVR_TAIL21 (_virtRegBase+ 0x2a18)
1088 REG16_T(ADDR_PVR_HEAD20)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF;
1089 REG16_T(ADDR_PVR_HEAD21)= (MS_U16)((phyBufStart1-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF;
1090 REG16_T(ADDR_PVR_TAIL20)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> MIU_BUS) & 0xFFFF;
1091 REG16_T(ADDR_PVR_TAIL21)= (MS_U16)((phyBufEnd-_phyPVRBufMiuOffset[0])>> (MIU_BUS+ 16)) & 0xFFFF;
1092 #undef ADDR_PVR_HEAD20
1093 #undef ADDR_PVR_HEAD21
1094 #undef ADDR_PVR_MID20
1095 #undef ADDR_PVR_MID21
1096 #undef ADDR_PVR_TAIL20
1097 #undef ADDR_PVR_TAIL21
1098
1099 // enable PVR ping pong buffer
1100 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1101 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_STR2MI_MIU_PINPON_EN));
1102
1103 // flush PVR buffer
1104 HAL_TSP_PVR_WaitFlush();
1105 }
1106
HAL_TSP_PVR_Enable(MS_BOOL bEnable)1107 void HAL_TSP_PVR_Enable(MS_BOOL bEnable)
1108 {
1109 //set burst len = 1
1110 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1111 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_burst_len_MASK));
1112
1113 // disable timeshift write protect -- it must enable while record/playback use the same buffer
1114 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1115 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP));
1116
1117 if (bEnable)
1118 {
1119 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1120 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE));
1121 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1122 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1123 }
1124 else
1125 {
1126 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1127 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_ENABLE));
1128 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1129 // RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1130 }
1131 }
1132
HAL_TSP_PVR_Reset(void)1133 void HAL_TSP_PVR_Reset(void)
1134 {
1135 // Richard: @FIXME:
1136 // Don't know PVR "reset" definition. call flush instead.
1137 HAL_TSP_PVR_WaitFlush();
1138 }
1139
HAL_TSP_PVR_All(MS_BOOL bPvrAll)1140 void HAL_TSP_PVR_All(MS_BOOL bPvrAll)
1141 {
1142 if (bPvrAll)
1143 {
1144 // bypass mode
1145 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1146 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1147 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1148 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN));
1149 }
1150 else
1151 {
1152 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1153 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1154 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1155 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_REG_REC_PID_EN));
1156 }
1157 }
1158
HAL_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD,MS_BOOL bEnable,MS_BOOL bRecAll)1159 void HAL_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD, MS_BOOL bEnable, MS_BOOL bRecAll)
1160 {
1161 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].reg15b4);
1162
1163 if(bBypassHD)
1164 u32data |= TSP_PVR_TS_HEADER;
1165 else
1166 u32data &= ~TSP_PVR_TS_HEADER;
1167
1168 if(bRecAll)
1169 {
1170 u32data |= TSP_REC_ALL_FILE;
1171 }
1172 else
1173 {
1174 u32data &= ~TSP_REC_ALL_FILE;
1175 }
1176
1177 if(bEnable)
1178 u32data |= TSP_PVR_FILEIN;
1179 else
1180 u32data &= ~TSP_PVR_FILEIN;
1181
1182 _HAL_REG32_W(&_TspCtrl[0].reg15b4, u32data);
1183 }
1184
HAL_TSP_PVR_Eng_IsEnabled(MS_U32 u32EngId)1185 MS_BOOL HAL_TSP_PVR_Eng_IsEnabled(MS_U32 u32EngId)
1186 {
1187 if(u32EngId == 0)
1188 {
1189 return ((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PVR_ENABLE) > 0);
1190 }
1191 else
1192 {
1193 return FALSE;
1194 }
1195 }
1196
HAL_TSP_LiveAB_En(MS_BOOL bPF_EN)1197 void HAL_TSP_LiveAB_En(MS_BOOL bPF_EN)
1198 {
1199 if (bPF_EN)
1200 {
1201 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_LIVEAB_SEL);
1202 }
1203 else
1204 {
1205 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_LIVEAB_SEL);
1206 }
1207 }
1208
HAL_TSP_IsLiveAB_Enable(void)1209 MS_BOOL HAL_TSP_IsLiveAB_Enable(void)
1210 {
1211 return ((_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & TSP_LIVEAB_SEL) != 0);
1212 }
1213
HAL_TSP_SetPKTSize(MS_U32 u32PKTSize)1214 void HAL_TSP_SetPKTSize(MS_U32 u32PKTSize)
1215 {
1216 if((u32PKTSize == 0x82) || (u32PKTSize == 0x86)) // RVU
1217 {
1218 printf("HAL_TSP_SetPKTSize: This chip not support RVU!\n"); // not support
1219 }
1220 else
1221 {
1222 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_ALT_TS_SIZE));
1223 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, (_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein)&~TSP_PKT_SIZE_MASK)|(TSP_PKT_SIZE_MASK&u32PKTSize));
1224 }
1225 }
1226
1227 // Set 1 to disable file-in timestamp block scheme, bypass timestamp
HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable)1228 void HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable)
1229 {
1230 if (!bEnable)
1231 {
1232 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_PKT192_BLK_DIS_FIN);
1233 }
1234 else
1235 {
1236 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_PKT192_BLK_DIS_FIN);
1237 }
1238 }
1239
1240
HAL_TSP_PVR_GetBufWrite(void)1241 MS_PHY HAL_TSP_PVR_GetBufWrite(void)
1242 {
1243 MS_PHY phyvalue;
1244
1245 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
1246 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD));
1247 phyvalue = (MS_PHY)(_HAL_REG32_R(&_TspCtrl[0].TsRec_WPtr)<< MIU_BUS) + _phyPVRBufMiuOffset[0];
1248 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
1249 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_STR2MI_WP_LD));
1250
1251 return phyvalue;
1252
1253 }
1254
HAL_TSP_PVR_WaitFlush(void)1255 void HAL_TSP_PVR_WaitFlush(void)
1256 {
1257 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1258 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH));
1259 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1260 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_FLUSH));
1261 }
1262
HAL_TSP_PVR_REC_FLT_Enable(MS_BOOL bEnable)1263 void HAL_TSP_PVR_REC_FLT_Enable(MS_BOOL bEnable)
1264 {
1265 if(bEnable)
1266 {
1267 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1268 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1269 }
1270 else
1271 {
1272 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1273 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PVR_PIDFLT_SEC));
1274 }
1275 }
1276
1277
1278 //--------------------------------------------------------------------------------------------------
1279 // For FW part
1280 //--------------------------------------------------------------------------------------------------
1281 /*
1282 void HAL_TSP_SetFwMsg(MS_U32 u32Mode)
1283 {
1284 _HAL_REG32_W(&_TspCtrl[0].Mcu_Msg, u32Mode);
1285 }
1286
1287 MS_U32 HAL_TSP_GetFwMsg(void)
1288 {
1289 return (_HAL_REG32_R(&_TspCtrl[0].Mcu_Msg));
1290 }
1291 */
1292
1293 static MS_U32 _u32FlowPadMap[2] = { 0x0, 0x0};
1294
1295 //--------------------------------------------------------------------------------------------------
1296 // For pad select part
1297 //--------------------------------------------------------------------------------------------------
HAL_TSP_SelPad(MS_U32 u32EngId,MS_U32 u32Flow,MS_U32 u32Pad)1298 void HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 u32Flow, MS_U32 u32Pad)
1299 {
1300
1301 MS_U32 u32Shft = 0;
1302
1303 MS_ASSERT(TSP_TS_PAD_NUM >= u32Pad);
1304
1305 if(u32Flow >= TSP_IF_NUM)
1306 {
1307 return;
1308 }
1309
1310 if (0 == u32Pad)
1311 {
1312 // internal demod
1313 u32Pad = TSP_MUX_INDEMOD;
1314 }
1315 else if(1 == u32Pad)
1316 {
1317 // external TS
1318 u32Pad = TSP_MUX_TS0;
1319
1320 if(_bTsPadUsed[0] == FALSE)
1321 {
1322 TSP_TOP_REG(REG_TOP_TS0_PE) = TSP_TOP_REG(REG_TOP_TS0_PE)| REG_TOP_TS0_PE_MASK;
1323 _bTsPadUsed[0] = TRUE;
1324 }
1325 }
1326 else
1327 {
1328 // external TS
1329 u32Pad = TSP_MUX_TS1;
1330
1331 if(_bTsPadUsed[1] == FALSE)
1332 {
1333 TSP_TOP_REG(REG_TOP_TS1_PE) = TSP_TOP_REG(REG_TOP_TS1_PE)| REG_TOP_TS1_PE_MASK;
1334 _bTsPadUsed[1] = TRUE;
1335 }
1336 }
1337 _u32FlowPadMap[u32Flow] = u32Pad;
1338
1339 if(u32Flow == 0)
1340 u32Shft= REG_TOP_TSN_MUX_TS0_SHIFT;
1341 else
1342 u32Shft = REG_TOP_TSN_MUX_TS1_SHIFT;
1343
1344 TSP_TOP_REG(REG_TOP_TSN_MUX) = (TSP_TOP_REG(REG_TOP_TSN_MUX) & ~(REG_TOP_TSN_MUX_MASK<< u32Shft)) | (u32Pad<< u32Shft);
1345
1346 }
1347
HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId,MS_U32 u32Flow,MS_BOOL bClkInv)1348 void HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bClkInv)
1349 {
1350 MS_U32 u32Clk = 0;
1351 MS_U32 u32Shft = 0;
1352
1353 if(u32Flow >= TSP_IF_NUM)
1354 {
1355 return;
1356 }
1357
1358 if(_u32FlowPadMap[u32Flow] == TSP_MUX_INDEMOD)
1359 u32Clk = TSP_CLK_INDEMOD;
1360 else if(_u32FlowPadMap[u32Flow] == TSP_MUX_TS1)
1361 u32Clk = TSP_CLK_TS1;
1362 else
1363 u32Clk = TSP_CLK_TS0;
1364
1365 if (bClkInv)
1366 {
1367 u32Clk |= TSP_CLK_INVERSE;
1368 }
1369
1370 u32Shft = (0 == u32Flow)? 0: 8;
1371 TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) & ~(REG_CLKGEN0_TSN_CLK_MASK<< u32Shft)) | (u32Clk<< u32Shft);
1372 }
1373
HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId,MS_BOOL bExtSync,MS_U32 u32Flow)1374 void HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId, MS_BOOL bExtSync, MS_U32 u32Flow)
1375 {
1376 REG32* pReg = NULL;
1377 MS_U32 u32ExtSync = 0;
1378
1379 if (0 == u32Flow)
1380 {
1381 pReg = &(_TspCtrl[0].Hw_Config0);
1382 u32ExtSync = TSP_HW_CFG0_TSIF0_EXTSYNC;
1383 }
1384 else if (1 == u32Flow)
1385 {
1386 pReg = &(_TspCtrl[0].Hw_Config2);
1387 u32ExtSync = TSP_HW_CFG2_TSIF1_EXTSYNC;
1388 }
1389 else
1390 {
1391 //ASSERT(0);
1392 return;
1393 }
1394
1395 if (bExtSync)
1396 {
1397 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32ExtSync));
1398 }
1399 else
1400 {
1401 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32ExtSync));
1402 }
1403 }
1404
HAL_TSP_SelPad_Parl(MS_U32 u32EngId,MS_BOOL bParl,MS_U32 u32Flow)1405 void HAL_TSP_SelPad_Parl(MS_U32 u32EngId, MS_BOOL bParl, MS_U32 u32Flow)
1406 {
1407 REG32* pReg = NULL;
1408 MS_U32 u32Parl = 0;
1409 MS_U32 u32Pad = 0;
1410 if (0 == u32Flow) // TS_IF0
1411 {
1412 pReg = &(_TspCtrl[0].Hw_Config0);
1413 u32Parl = TSP_HW_CFG0_TSIF0_PARL;
1414 }
1415 else if (1 == u32Flow) // TS_IF1
1416 {
1417 pReg = &(_TspCtrl[0].Hw_Config2);
1418 u32Parl = TSP_HW_CFG2_TSIF1_PARL;
1419 }
1420 else
1421 {
1422 //ASSERT(0);
1423 return;
1424 }
1425
1426 u32Pad = _u32FlowPadMap[u32Flow];
1427 if (bParl) // parallel
1428 {
1429 switch (u32Pad)
1430 {
1431 case TSP_MUX_TS0:
1432 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS0_CFG_MASK) | REG_TOP_TS_TS0_CFG_PARALLEL;
1433 break;
1434 case TSP_MUX_TS1:
1435 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS1_CFG_MASK) | REG_TOP_TS_TS1_CFG_PARALLEL;
1436 break;
1437 default:
1438 break;
1439 }
1440 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32Parl));
1441 }
1442 else // serial
1443 {
1444 switch (u32Pad)
1445 {
1446 case TSP_MUX_TS0:
1447 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS0_CFG_MASK) | REG_TOP_TS_TS0_CFG_SERIAL;
1448 break;
1449 case TSP_MUX_TS1:
1450 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~REG_TOP_TS_TS1_CFG_MASK) | REG_TOP_TS_TS1_CFG_SERIAL;
1451 break;
1452 default:
1453 break;
1454 }
1455 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32Parl));
1456 }
1457 }
1458
HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId,MS_U32 u32Flow,MS_BOOL bInvert)1459 void HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bInvert)
1460 {
1461 REG32* pReg = &(_TspCtrl[0].Hw_Config4);
1462 MS_U32 u32Invert = 0;
1463
1464 if(0 == u32Flow)
1465 {
1466 u32Invert = TSP_HW_CFG4_TS_DATA0_SWAP;
1467 }
1468 else if(1 == u32Flow)
1469 {
1470 u32Invert = TSP_HW_CFG4_TS_DATA1_SWAP;
1471 }
1472 else
1473 {
1474 return;
1475 }
1476
1477 if(bInvert)
1478 {
1479 _HAL_REG32_W(pReg, SET_FLAG1(_HAL_REG32_R(pReg), u32Invert));
1480 }
1481 else
1482 {
1483 _HAL_REG32_W(pReg, RESET_FLAG1(_HAL_REG32_R(pReg), u32Invert));
1484 }
1485 }
1486
HAL_TSP_GetCap(MS_U32 u32Cap,void * pData)1487 MS_BOOL HAL_TSP_GetCap(MS_U32 u32Cap, void* pData)
1488 {
1489 MS_BOOL bRet = TRUE;
1490
1491 switch (u32Cap)
1492 {
1493 case HAL_TSP_CAP_PID_FILTER_NUM:
1494 *((MS_U32*)pData) = TSP_PIDFLT_NUM_ALL;
1495 break;
1496 case HAL_TSP_CAP_SEC_FILTER_NUM:
1497 *((MS_U32*)pData) = TSP_SECFLT_NUM;
1498 break;
1499 case HAL_TSP_CAP_SEC_BUF_NUM:
1500 *((MS_U32*)pData) = TSP_SECBUF_NUM;
1501 break;
1502 case HAL_TSP_CAP_PVR_ENG_NUM:
1503 *((MS_U32*)pData) = TSP_PVR_IF_NUM;
1504 break;
1505 case HAL_TSP_CAP_PVR_FILTER_NUM:
1506 *((MS_U32*)pData) = TSP_PIDFLT1_NUM;
1507 break;
1508 case HAL_TSP_CAP_MMFI_AUDIO_FILTER_NUM:
1509 *((MS_U32*)pData) = TSP_MMFI_AUDIO_FILTER_NUM;
1510 break;
1511 case HAL_TSP_CAP_MMFI_V3D_FILTER_NUM:
1512 *((MS_U32*)pData) = TSP_MMFI_V3D_FILTER_NUM;
1513 break;
1514 case HAL_TSP_CAP_TSIF_NUM:
1515 *((MS_U32*)pData) = TSP_IF_NUM;
1516 break;
1517 case HAL_TSP_CAP_DEMOD_NUM:
1518 *((MS_U32*)pData) = TSP_DEMOD_NUM;
1519 break;
1520 case HAL_TSP_CAP_VFIFO_NUM:
1521 *((MS_U32*)pData) = TSP_VFIFO_NUM;
1522 break;
1523 case HAL_TSP_CAP_AFIFO_NUM:
1524 *((MS_U32*)pData) = TSP_AFIFO_NUM;
1525 break;
1526 case HAL_TSP_CAP_TS_PAD_NUM:
1527 *((MS_U32*)pData) = TSP_TS_PAD_NUM;
1528 break;
1529 case HAL_TSP_CAP_VQ_NUM:
1530 *((MS_U32*)pData) = TSP_VQ_NUM;
1531 break;
1532 case HAL_TSP_CAP_CA_FLT_NUM:
1533 *((MS_U32*)pData) = TSP_CA_FLT_NUM;
1534 break;
1535 case HAL_TSP_CAP_CA_KEY_NUM:
1536 *((MS_U32*)pData) = TSP_CA_KEY_NUM;
1537 break;
1538 case HAL_TSP_CAP_FW_ALIGN:
1539 *((MS_U32*)pData) = (1L << (MIU_BUS+TSP_DNLD_ADDR_ALI_SHIFT));
1540 break;
1541 case HAL_TSP_CAP_VQ_ALIGN:
1542 case HAL_TSP_CAP_SEC_BUF_ALIGN:
1543 case HAL_TSP_CAP_PVR_ALIGN:
1544 *((MS_U32*)pData) = (1L << MIU_BUS);
1545 break;
1546 case HAL_TSP_CAP_VQ_PITCH:
1547 *((MS_U32*)pData) = VQ_PACKET_UNIT_LEN;
1548 break;
1549 case HAL_TSP_CAP_PVRCA_PATH_NUM:
1550 *((MS_U32*)pData) = 1;
1551 break;
1552 case HAL_TSP_CAP_PVRCA0_FLT_RANGE:
1553 *((MS_U32*)pData) = TSP_SECFLT_NUM;
1554 *((MS_U32*)pData + 1) = TSP_SECFLT_NUM + TSP_PIDFLT1_NUM - 1;
1555 break;
1556 case HAL_TSP_CAP_PVRCA1_FLT_RANGE:
1557 case HAL_TSP_CAP_PVR1_FILTER_NUM:
1558 case HAL_TSP_CAP_SHAREKEY_FLT_RANGE:
1559 *((MS_U32*)pData) = 0;
1560 break;
1561 case HAL_TSP_CAP_HW_TYPE:
1562 *((MS_U32*)pData) = 0x00001001;
1563 break;
1564
1565 case HAL_TSP_CAP_HWPCR_SUPPORT:
1566 *((MS_U32*)pData) = 0;
1567 break;
1568
1569 case HAL_TSP_CAP_HWWP_SET_NUM:
1570 *((MS_U32*)pData) = TSP_WP_SET_NUM;
1571 break;
1572
1573 case HAL_TSP_CAP_DSCMB_ENG_NUM:
1574 *((MS_U32*)pData) = 1;
1575 break;
1576 case HAL_TSP_CAP_MAX_SEC_FLT_DEPTH:
1577 *((MS_U32*)pData) = TSP_SEC_FLT_DEPTH;
1578 break;
1579 case HAL_TSP_CAP_FW_BUF_SIZE:
1580 *((MS_U32*)pData) = TSP_FW_BUF_SIZE;
1581 break;
1582 case HAL_TSP_CAP_FW_BUF_RANGE:
1583 *((MS_U32*)pData) = TSP_FW_BUF_LOW_BUD;
1584 *((MS_U32*)pData+1) = TSP_FW_BUF_UP_BUD;
1585 break;
1586 case HAL_TSP_CAP_VQ_BUF_RANGE:
1587 *((MS_U32*)pData) = TSP_VQ_BUF_LOW_BUD;
1588 *((MS_U32*)pData+1) = TSP_VQ_BUF_UP_BUD;
1589 break;
1590 case HAL_TSP_CAP_SEC_BUF_RANGE:
1591 *((MS_U32*)pData) = TSP_SEC_BUF_LOW_BUD;
1592 *((MS_U32*)pData+1) = TSP_SEC_BUF_UP_BUD;
1593 break;
1594 case HAL_TSP_CAP_FIQ_NUM:
1595 *((MS_U32*)pData) = TSP_FIQ_NUM;
1596 break;
1597 default:
1598 *((MS_U32*)pData) = 0xFFFFFFFF;
1599 bRet = FALSE;
1600 break;
1601 }
1602 return bRet;
1603
1604 }
1605
HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable)1606 void HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable)
1607 {
1608 if(bEnable)
1609 {
1610 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1611 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | (TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV));
1612 }
1613 else
1614 {
1615 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1616 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~(TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV));
1617 }
1618 }
1619
HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId,MS_BOOL bEnable)1620 void HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId, MS_BOOL bEnable)
1621 {
1622 MS_U32 u32Flag[4] = {TSP_DUP_PKT_SKIP_VD, TSP_DUP_PKT_SKIP_AV, 0, TSP_DUP_PKT_SKIP_V3D};
1623
1624 if(u32StreamId == 2)
1625 return;
1626
1627 if(bEnable)
1628 {
1629 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1630 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | u32Flag[u32StreamId]);
1631 }
1632 else
1633 {
1634 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
1635 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~u32Flag[u32StreamId]);
1636 }
1637 }
1638
HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId,MS_U16 * pu16Pad,MS_U16 * pu16Clk,MS_BOOL * pbExtSync,MS_BOOL * pbParl)1639 MS_BOOL HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId, MS_U16* pu16Pad, MS_U16* pu16Clk, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
1640 {
1641 MS_U16 u16pad;
1642 MS_U32 u32data;
1643
1644 *pu16Pad = 0xFFFF;
1645 *pu16Clk = TSP_CLK_DISABLE;
1646 *pbExtSync = FALSE;
1647 *pbParl = FALSE;
1648
1649 u16pad = TSP_TOP_REG(REG_TOP_TSN_MUX);
1650
1651 switch(u8TsIfId)
1652 {
1653 case 0:
1654 u16pad >>= REG_TOP_TSN_MUX_TS0_SHIFT;
1655 *pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS0_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK;
1656 u32data = _HAL_REG32_R(&_TspCtrl[0].Hw_Config0);
1657 *pbExtSync = ((u32data & TSP_HW_CFG0_TSIF0_EXTSYNC) == TSP_HW_CFG0_TSIF0_EXTSYNC);
1658 *pbParl = ((u32data & TSP_HW_CFG0_TSIF0_PARL) == TSP_HW_CFG0_TSIF0_PARL);
1659 break;
1660 case 1:
1661 u16pad >>= REG_TOP_TSN_MUX_TS1_SHIFT;
1662 *pu16Clk = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSN_CLK) >> REG_CLKGEN0_TSN_CLK_TS1_SHIFT) & REG_CLKGEN0_TSN_CLK_MASK;
1663 u32data = _HAL_REG32_R(&_TspCtrl[0].Hw_Config2);
1664 *pbExtSync = ((u32data & TSP_HW_CFG2_TSIF1_EXTSYNC) == TSP_HW_CFG2_TSIF1_EXTSYNC);
1665 *pbParl = ((u32data & TSP_HW_CFG2_TSIF1_PARL) == TSP_HW_CFG2_TSIF1_PARL);
1666 break;
1667 default:
1668 return FALSE;
1669 }
1670
1671 *pu16Pad = u16pad & REG_TOP_TSN_MUX_MASK;
1672
1673 return TRUE;
1674 }
1675
HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId)1676 MS_BOOL HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId)
1677 {
1678 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].Idr_Read1);
1679
1680 switch (u32StreamId)
1681 {
1682 case 0: // return VFifo status
1683 return ((u32data & TSP_VD_FIFO_OVERFLOW) == TSP_VD_FIFO_OVERFLOW);
1684 case 1: // return AFifo 0 status
1685 return ((u32data & TSP_AU_FIFO_OVERFLOW) == TSP_AU_FIFO_OVERFLOW);
1686 case 3: // return V3D Fifo status
1687 return ((u32data & TSP_V3D_FIFO_OVERFLOW) == TSP_V3D_FIFO_OVERFLOW);
1688 default:
1689 return FALSE;
1690 }
1691 }
1692
1693 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
1694 // Macro function
1695 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
_HAL_TSP_FW_load(MS_PHY phyFwAddrPhys,MS_U32 u32FwSize,MS_BOOL bFwDMA,MS_BOOL bIQmem,MS_BOOL bDQmem)1696 static void _HAL_TSP_FW_load(
1697 MS_PHY phyFwAddrPhys,
1698 MS_U32 u32FwSize,
1699 MS_BOOL bFwDMA,
1700 MS_BOOL bIQmem,
1701 MS_BOOL bDQmem)
1702 {
1703 MS_U32 u32Value = 0x0;
1704
1705 // bDQmem is always true
1706 MS_ASSERT(bDQmem);
1707
1708 _phyOrLoadMiuOffset = _HAL_TSP_MIU_OFFSET(phyFwAddrPhys);
1709
1710 _HAL_REG32_W(&_TspCtrl2[0].Qmem_Config,
1711 SET_FLAG1(_HAL_REG32_R(&_TspCtrl2[0].Qmem_Config), TSP_TSP_SEL_SRAM));
1712
1713 // @FIXME: Richard: Only allow TSP FW running in DRAM at this first stage.
1714 // improve this afterward.
1715 MS_ASSERT(phyFwAddrPhys & TSP_CPU_BASE_ADDR_MASK);
1716 _HAL_REG32_W(&_TspCtrl[0].Cpu_Base, 0/*u32FwAddrPhys >> 3*/); // 16 bytes address unit
1717
1718 if (bFwDMA)
1719 {
1720 MS_U32 u32DnldCtrl = 0;
1721 MS_U32 u32DnldCtrl1 = 0;
1722 u32DnldCtrl = (MS_U32)(((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) & TSP_DNLD_ADDR_MASK;
1723 u32DnldCtrl1 = (MS_U32)((((phyFwAddrPhys-_phyOrLoadMiuOffset) >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT) & TSP_DNLD_ADDR_MASK1) >> TSP_DNLD_ADDR_SHFT1;
1724 printf("firmware 111 0x%08lx 0x%08lx 0x%08lx\n", (unsigned long)phyFwAddrPhys, (unsigned long)u32DnldCtrl1, (unsigned long)u32DnldCtrl);
1725
1726 u32DnldCtrl |= (_TSP_QMEM_SIZE << TSP_DNLD_NUM_SHFT);
1727
1728 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl, u32DnldCtrl);
1729 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2, (_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2) & ~(TSP_DNLD_ADDR_MASK1 >> TSP_DNLD_ADDR_SHFT1)) | u32DnldCtrl1);
1730 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1731 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE));
1732 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1733 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START));
1734 while (!HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_DONE));//printf(".");
1735 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1736 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE));
1737 }
1738
1739 _HAL_REG32_W(&_TspCtrl[0].Qmem_Imask, _TSP_QMEM_I_MASK);
1740
1741 if (bIQmem)
1742 {
1743 _HAL_REG32_W(&_TspCtrl[0].Qmem_Ibase,
1744 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Qmem_Ibase), _TSP_QMEM_I_ADDR_HIT));
1745 }
1746 else
1747 {
1748 _HAL_REG32_W(&_TspCtrl[0].Qmem_Ibase, _TSP_QMEM_I_ADDR_MISS);
1749 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1750 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_ICACHE_EN));
1751 }
1752
1753 u32Value = _HAL_REG32_R(&_TspCtrl[0].Qmem_Dmask) | _TSP_QMEM_D_MASK;
1754 _HAL_REG32_W(&_TspCtrl[0].Qmem_Dmask, u32Value);
1755
1756 u32Value = _HAL_REG32_R(&_TspCtrl[0].Qmem_Dbase) | _TSP_QMEM_D_ADDR_HIT;
1757 _HAL_REG32_W(&_TspCtrl[0].Qmem_Dbase, u32Value);
1758 }
1759
HAL_TSP_filein_enable(MS_BOOL b_enable)1760 void HAL_TSP_filein_enable(MS_BOOL b_enable)
1761 {
1762 // disable timeshift write protect -- it must enable while record/playback use the same buffer
1763 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1764 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILE_CHECK_WP));
1765
1766 // Richard: enable/disable file in timer as well
1767 // file in could only walk through pid filter set 0.
1768 if (b_enable)
1769 {
1770 // Set Data port enable for audio bypass
1771 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1772 // SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1773 //_HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1774 // SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_ENABLE| TSP_CTRL1_FILEIN_TIMER_ENABLE));
1775
1776 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1777 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
1778 }
1779 else
1780 {
1781 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1782 // RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1783 //_HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1784 // RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_FILEIN_ENABLE| TSP_CTRL1_FILEIN_TIMER_ENABLE));
1785
1786 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1787 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
1788 }
1789 //_HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1790 //RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1791 }
1792
_HAL_TSP_tsif_select(MS_U8 u8_tsif)1793 static void _HAL_TSP_tsif_select(MS_U8 u8_tsif)
1794 {
1795 if (u8_tsif == 1)
1796 {
1797 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1798 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
1799 }
1800 else
1801 {
1802 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1803 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
1804 }
1805 }
1806
1807 /*
1808 static void _HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 PadId)
1809 {
1810 if (PadId) // TS1
1811 {
1812 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1813 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_PAD1_SEL));
1814 }
1815 else // TS0
1816 {
1817 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl,
1818 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_PAD1_SEL));
1819 }
1820 }
1821 */
1822
HAL_TSP_PS_Path_Disable(void)1823 void HAL_TSP_PS_Path_Disable(void)
1824 {
1825 // set PS VID/AUD enable while video/audio/audio2 bypass mode
1826 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1827 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1828 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1829 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1830 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1831 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1832 }
1833
HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl)1834 void HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl)
1835 {
1836 switch (u32TsDmaCtrl)
1837 {
1838 case TSP_TSDMA_CTRL_VPES0:
1839 if((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PS_VID_EN) == 0)
1840 {
1841 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1842 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_AUD_EN));
1843 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1844 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1845
1846 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1847 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1848 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1849 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_VID_EN));
1850 }
1851 break;
1852 case TSP_TSDMA_CTRL_APES0:
1853 if((_HAL_REG32_R(&_TspCtrl[0].Hw_Config4) & TSP_HW_CFG4_PS_AUD_EN) == 0)
1854 {
1855 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1856 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_VID_EN));
1857 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1858 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1859
1860 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1861 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1862 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1863 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_PS_AUD_EN));
1864 }
1865 break;
1866 case TSP_TSDMA_CTRL_V3DPES0:
1867 if((_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2) & TSP_PS_VID3D_EN) == 0)
1868 {
1869 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1870 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1871
1872 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1873 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1874 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1875 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1876 }
1877 break;
1878 default:
1879 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1880 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), (TSP_HW_CFG4_PS_VID_EN|TSP_HW_CFG4_PS_AUD_EN)));
1881 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
1882 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PS_VID3D_EN));
1883 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
1884 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_DATA_PORT_EN));
1885 break;
1886 }
1887 }
1888
HAL_TSP_GetCtrlMode(MS_U32 u32EngId)1889 MS_U32 HAL_TSP_GetCtrlMode(MS_U32 u32EngId)
1890 {
1891 return (_HAL_REG32_R(&_TspCtrl[u32EngId].TSP_Ctrl));
1892 }
1893
HAL_TSP_DoubleBuf_En(MS_BOOL bBuf_Sel)1894 void HAL_TSP_DoubleBuf_En(MS_BOOL bBuf_Sel)
1895 {
1896 if (bBuf_Sel)
1897 {
1898 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | (TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_DESC));
1899 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~TSP_DOUBLE_BUF_SWITCH);
1900 }
1901 else
1902 {
1903 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE));
1904 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | (TSP_DOUBLE_BUF_SWITCH|TSP_DOUBLE_BUF_DESC));
1905 }
1906 //_HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | TSP_DOUBLE_BUF_DESC);
1907 }
1908
HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId,MS_BOOL bFlush)1909 void HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId, MS_BOOL bFlush)
1910 {
1911 MS_U32 u32Flag;
1912
1913 switch(u32StreamId)
1914 {
1915 case 0:
1916 u32Flag = TSP_RESET_VFIFO;
1917 break;
1918 case 1:
1919 u32Flag = TSP_RESET_AFIFO;
1920 break;
1921 case 3:
1922 u32Flag = TSP_RESET_VFIFO3D;
1923 break;
1924 default:
1925 return;
1926 }
1927 if (bFlush)
1928 {
1929 _HAL_REG32_W(&_TspCtrl[0].reg160C,
1930 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), u32Flag));
1931 }
1932 else
1933 {
1934 _HAL_REG32_W(&_TspCtrl[0].reg160C,
1935 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), u32Flag));
1936 }
1937 }
1938
1939 #define ADDR_AVFIFO_STATUS (_virtRegBase+ 0x2adc)
HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId)1940 MS_U32 HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId)
1941 {
1942 switch (u32StreamId)
1943 {
1944 case 0: // return VFifo status
1945 return (((REG16_T(ADDR_AVFIFO_STATUS))>>4)&0x0f);
1946 case 1: // return AFifo 0 status
1947 return (((REG16_T(ADDR_AVFIFO_STATUS))>>8)&0x0f);
1948 case 3: // return V3D Fifo status
1949 return (REG16_T(ADDR_AVFIFO_STATUS)&0x0f);
1950 default:
1951 return -1;
1952 }
1953 }
1954 #undef ADDR_AVFIFO_STATUS
1955
HAL_TSP_Ind_Enable(void)1956 void HAL_TSP_Ind_Enable(void)
1957 {
1958 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
1959 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
1960 }
1961
HAL_TSP_HW_INT_STATUS(void)1962 MS_U32 HAL_TSP_HW_INT_STATUS(void)
1963 {
1964 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat) & TSP_HWINT_STATUS_MASK);
1965 }
1966
HAL_TSP_SetBank(MS_VIRT u32NonPmBankAddr,MS_VIRT u32PmBankAddr)1967 void HAL_TSP_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr)
1968 {
1969 _virtRegBase = u32NonPmBankAddr;
1970 _TspCtrl = (REG_Ctrl*)(_virtRegBase + REG_CTRL_BASE);
1971 _TspCtrl2 = (REG_Ctrl2*)(_virtRegBase + REG_CTRL_MMFIBASE);
1972 _TspCtrl3 = (REG_Ctrl3*)(_virtRegBase + REG_CTRL_BASE_TS3);
1973 }
1974
HAL_TSP_Reset(MS_U32 u32EngId)1975 void HAL_TSP_Reset(MS_U32 u32EngId)
1976 {
1977 _HAL_REG32_W(&_TspCtrl[u32EngId].TSP_Ctrl, 0);
1978 }
1979
HAL_TSP_HwPatch(void)1980 void HAL_TSP_HwPatch(void)
1981 {
1982 _HAL_REG32_W(&_TspCtrl2[0].Qmem_Config,
1983 SET_FLAG1(_HAL_REG32_R(&_TspCtrl2[0].Qmem_Config), TSP_TSP_SEL_SRAM));
1984
1985 // To prevent the race condition of accessing section filter registers from HW/CPU.
1986 // It's a HW bug.
1987 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
1988 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_ISYNC_PATCH_EN));
1989
1990 // Bad initial value of TSP_CTRL1
1991 // Suppose Standby mode for TSP should NOT be enabled.
1992 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
1993 // Disable it by SW at this stage.
1994 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
1995 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_STANDBY));
1996
1997 // @FIXME: disable not match mask
1998 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
1999 _HAL_REG32_R(&_TspCtrl[0].reg15b4)|TSP_NMATCH_DIS);
2000
2001 // Jericho helps
2002 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2003 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), 0xFFFF0000));
2004 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2005 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), 0xBBBB0000));
2006
2007 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2008 #ifdef VQ_ENABLE
2009 _HAL_REG32_R(&_TspCtrl[0].reg160C)| (TSP_RM_DMA_GLITCH|TSP_DOUBLE_BUF_DESC));
2010 #else
2011 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RM_DMA_GLITCH));
2012 #endif
2013
2014 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2015 _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) |
2016 (TSP_SYSTIME_MODE_STC64|TSP_DUP_PKT_SKIP_VD|TSP_DUP_PKT_SKIP_V3D|TSP_DUP_PKT_SKIP_AV));
2017
2018 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2019 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PREVENT_OVF_META));
2020
2021 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
2022 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), (TSP_STR2MI_WP_LD|TSP_RM_OVERFLOW_GLITCH))); //improve pvr performance
2023
2024
2025 // Set match PID, default is AV FIFO
2026 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2027 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_AVPID_ST_AV));
2028
2029 // Set PUSI 3 byte mode for Audio
2030 _HAL_REG32_W(&_TspCtrl[0].HW2_Config3,
2031 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].HW2_Config3), TSP_PUSI_3BYTE_MODE));
2032
2033 // 2p sram setting
2034 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2035 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_HW_STANDBY_MODE));
2036 _HAL_REG32_W(&_TspCtrl3[0].Hw_Config,
2037 SET_FLAG1(_HAL_REG32_R(&_TspCtrl3[0].Hw_Config), TSP_PREVENT_SRAM_COLLISION));
2038
2039 // Set filein segment bit to 0
2040 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2041 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_PVR_CMD_QUEUE_ENABLE));
2042
2043 _HAL_REG16_W(&_TspCtrl2[0].HwCfg1,
2044 SET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg1), (AF_PKT_LOSS_BYTE_ECO|UPDATE_SCRAMBLE_PID_PUSI|NEW_OVERFLOW_MODE|FIX_PINPON_SYNC_IN_ECO)));
2045
2046 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0, _HAL_REG16_R(&_TspCtrl2[0].HwCfg0) | (PREVENT_SRAM_COLLISION|MASK_SCR_VID_EN|MASK_SCR_VID_3D_EN|MASK_SCR_AUD_EN));
2047
2048 _HAL_REG16_W(&_TspCtrl2[0].HwCfg2, _HAL_REG16_R(&_TspCtrl2[0].HwCfg2) | REG_RST_CC_MODE);
2049
2050 //_HAL_REG32_W(&_TspCtrl3[0].Hw_ECO, _HAL_REG32_R(&_TspCtrl3[0].Hw_ECO) | TSP_TIMESTAMP_RING | TSP_LPCR_RING);
2051 //_HAL_REG32_W(&_TspCtrl3[0].Hw_Semaphore1, _HAL_REG32_R(&_TspCtrl3[0].Hw_Semaphore1) | TSP_TIMESTAMP_ECO);
2052
2053
2054 //VQ parameters
2055 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, (_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL) & ~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK) | (0x0C << TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT));
2056 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, (_HAL_REG32_R(&_TspCtrl[0].VQ1_Config) & ~TSP_VQ1_FORCEFIRE_CNT_1K_MASK) | (0x0C << TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT));
2057 }
2058
HAL_TSP_DoubleBuf_Disable(void)2059 void HAL_TSP_DoubleBuf_Disable(void)
2060 {
2061
2062 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2063 #ifdef VQ_ENABLE
2064 _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_SWITCH));
2065 #else
2066 _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~(TSP_DOUBLE_BUF_EN|TSP_BLK_DISABLE|TSP_DOUBLE_BUF_SWITCH|TSP_DOUBLE_BUF_DESC));
2067 #endif
2068 }
2069
2070 // Default value of low bound is 0, default value of up bound is 0xFFFFFFFF, means no protection
2071 // If set both low bound and up bound to be 0, means protection all
2072 // The range can be written: phyStartAddr <= x <= phyEndAddr
2073 // Protection range: x > phyEndAddr && x < phyStartAddr
HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable,MS_PHY phyStartAddr,MS_PHY phyEndAddr)2074 void HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr)
2075 {
2076 MS_U32 lbnd1_8;
2077 MS_U32 ubnd1_8;
2078 MS_U32 lbnd9_24;
2079 MS_U32 ubnd9_24;
2080 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(phyStartAddr);
2081
2082 if (bEnable)
2083 {
2084 if(phyStartAddr == phyEndAddr)
2085 phyStartAddr += (1UL << MIU_BUS);
2086 else
2087 phyEndAddr -= (1UL << MIU_BUS);
2088
2089 phyStartAddr -= phyMiuOffset;
2090 phyEndAddr -= phyMiuOffset;
2091
2092 lbnd1_8 = (MS_U32)((phyStartAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) & 0x00FFUL;
2093 lbnd9_24 = (MS_U32)(((phyStartAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) >> 8UL) & 0xFFFFUL;
2094 ubnd1_8 = (MS_U32)((phyEndAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) & 0x00FFUL;
2095 ubnd9_24 = (MS_U32)(((phyEndAddr >> MIU_BUS) >> TSP_ORZ_DMAW_BND_ALT_SHIFT) >> 8UL) & 0xFFFFUL;
2096
2097 _HAL_REG32_W(&_TspCtrl[0].reg16C0, (_HAL_REG32_R(&_TspCtrl[0].reg16C0) & ~(TSP_ORZ_DMAW_LBND_LSB8)) | lbnd1_8);
2098 _HAL_REG32_W(&_TspCtrl[0].ORZ_DMAW, (_HAL_REG32_R(&_TspCtrl[0].ORZ_DMAW) & ~(TSP_ORZ_DMAW_LBND)) | lbnd9_24);
2099 _HAL_REG32_W(&_TspCtrl[0].reg16C0, (_HAL_REG32_R(&_TspCtrl[0].reg16C0) & ~(TSP_ORZ_DMAW_UBND_LSB8)) | (ubnd1_8 << TSP_ORZ_DMAW_UBND_LSB8_SHIFT));
2100 _HAL_REG32_W(&_TspCtrl[0].ORZ_DMAW, (_HAL_REG32_R(&_TspCtrl[0].ORZ_DMAW) & ~(TSP_ORZ_DMAW_UBND)) | (ubnd9_24 << TSP_ORZ_DMAW_UBND_SHIFT));
2101
2102 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) | TSP_ORZ_DMAW_PROT_EN);
2103 }
2104 else
2105 {
2106 _HAL_REG32_W(&_TspCtrl[0].reg160C, _HAL_REG32_R(&_TspCtrl[0].reg160C) & ~TSP_ORZ_DMAW_PROT_EN);
2107 }
2108 }
2109
2110 //--------------------------------------------------------------------------------------------------
2111 // For STC part
2112 //--------------------------------------------------------------------------------------------------
HAL_TSP_Stc_ctrl(MS_U32 u32EngId,MS_U32 u32Sync)2113 void HAL_TSP_Stc_ctrl(MS_U32 u32EngId, MS_U32 u32Sync)
2114 {
2115 /////////////Set STC control by HK////////////////
2116 // select synth from chip top : bit 1 -> 0 -> controlled by HK
2117 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
2118
2119 // set HK STC synth CW
2120 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2121 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = (u32Sync & 0xFFFF);
2122 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = (u32Sync >> 16) & 0xFFFF;
2123
2124 // set STC synth
2125 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2126 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
2127 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
2128
2129 /////////////Set STC control by TSP////////////////
2130 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
2131 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
2132
2133 // set TSP STC synth CW
2134 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
2135 HAL_REG32_IndW((REG32 *)(0x0021024c<<1), u32Sync);
2136
2137 // t2 , t3 had no 0x0021025c, it was add after t4, synthesizer enable
2138 HAL_REG32_IndW((REG32 *)(0x0021025c<<1), HAL_REG32_IndR((REG32 *)(0x0021025c<<1))| 0x01);
2139 HAL_REG32_IndW((REG32 *)(0x0021025c<<1), HAL_REG32_IndR((REG32 *)(0x0021025c<<1))& ~0x01);
2140 }
2141
HAL_TSP_STC_Update_Disable(MS_U32 u32EngId,MS_BOOL bDisable)2142 void HAL_TSP_STC_Update_Disable(MS_U32 u32EngId, MS_BOOL bDisable)
2143 {
2144 if(bDisable)
2145 {
2146 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2147 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_cnt_33b_ld));
2148 }
2149 else
2150 {
2151 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2152 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_cnt_33b_ld));
2153 }
2154 }
2155
HAL_TSP_GetSTC(MS_U32 u32EngId)2156 MS_U32 HAL_TSP_GetSTC(MS_U32 u32EngId)
2157 {
2158 if(HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_SYSTIME_MODE_STC64))
2159 {
2160 MS_U32 u32temp;
2161
2162 u32temp = (_HAL_REG32_R(&_TspCtrl[0].TsRec_Tail2_Pcr1) & TSP_PCR1_L16_MASK) >> TSP_PCR1_L16_SHFT;
2163 u32temp |= ((_HAL_REG32_R(&_TspCtrl[0].Pcr1) & 0xFFFF) << 16);
2164 return u32temp ;
2165 }
2166 else
2167 {
2168 return HAL_REG32_IndR((REG32 *)(0x00210244<< 1));
2169 }
2170 }
2171
HAL_TSP_GetSTC_32(MS_U32 u32EngId)2172 MS_U32 HAL_TSP_GetSTC_32(MS_U32 u32EngId)
2173 {
2174 if(HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_SYSTIME_MODE_STC64))
2175 {
2176 MS_U32 u32temp;
2177
2178 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr1) >> 16)& 0xFFFF;
2179 u32temp |= (((_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & TSP_PCR64_H16_MASK) & 0xFFFF) << 16);
2180 return u32temp ;
2181 }
2182 else
2183 {
2184 return (HAL_REG32_IndR((REG32 *)(0x00210248<< 1)) & 0x01);
2185 }
2186 }
2187
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)2188 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
2189 {
2190 if (bEnable)
2191 {
2192 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) | TSP_SYSTIME_MODE_STC64);
2193 }
2194 else
2195 {
2196 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein, _HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein) & ~TSP_SYSTIME_MODE_STC64);
2197 }
2198 }
2199
HAL_TSP_SetSTC(MS_U32 u32EngId,MS_U32 u32STC,MS_U32 u32STC_32)2200 void HAL_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC, MS_U32 u32STC_32)
2201 {
2202 if(HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_SYSTIME_MODE_STC64))
2203 {
2204 MS_U32 u32temp;
2205
2206 u32temp = ((u32STC & 0xFFFF) << TSP_PCR1_L16_SHFT) |
2207 (_HAL_REG32_R(&_TspCtrl[0].TsRec_Tail2_Pcr1) & ~TSP_PCR1_L16_MASK);
2208 _HAL_REG32_W(&_TspCtrl[0].TsRec_Tail2_Pcr1, u32temp);
2209
2210 u32temp = ((u32STC >> 16) & 0xFFFF) | ((u32STC_32 & 0xFFFF) << 16);
2211 _HAL_REG32_W(&_TspCtrl[0].Pcr1, u32temp);
2212
2213 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_PCR64_H16_MASK) | ((u32STC_32 >> 16) & TSP_PCR64_H16_MASK);
2214 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32temp);
2215 }
2216 else
2217 {
2218 HAL_REG32_IndW((REG32 *)(0x00210244<< 1), u32STC);
2219 HAL_REG32_IndW((REG32 *)(0x00210248<< 1), u32STC_32 & 0x01);
2220 }
2221 }
2222
HAL_TSP_SetSTCOffset(MS_U32 u32EngId,MS_U32 u32Offset,MS_BOOL bAdd)2223 MS_BOOL HAL_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd)
2224 {
2225 #if 0
2226 MS_U32 u32opt = ((MS_U32)bAdd & 0xFF) << TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT;
2227
2228 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Offset);
2229 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_SET_STC_OFFSET | u32opt | u32EngId);
2230
2231 while(_HAL_REG32_R(&_TspCtrl[0].MCU_Cmd) != 0);
2232
2233 return TRUE;
2234
2235 #endif
2236
2237 return FALSE;
2238 }
2239
2240
2241 #if 0
2242 void HAL_TSP_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32)
2243 {
2244 if(HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_SYSTIME_MODE_STC64))
2245 {
2246 MS_U32 u32temp;
2247
2248 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr1) & ~ 0xFFFF0000) | ((u32STC_32 & 0xFFFF) << 16);
2249 _HAL_REG32_W(&_TspCtrl[0].Pcr1, u32temp);
2250 u32temp = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_PCR64_H16_MASK) | ((u32STC_32 >> 16) & TSP_PCR64_H16_MASK);
2251 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32temp);
2252 }
2253 else
2254 {
2255 HAL_REG32_IndW((REG32 *)(0x00210248<< 1), u32STC_32 & 0x01);
2256 }
2257 }
2258 #endif
2259
HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId,MS_U32 u32STC)2260 void HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId, MS_U32 u32STC)
2261 {
2262 _HAL_REG32_W(&_TspCtrl[0].Pcr.ML, u32STC);
2263 }
2264
HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId,MS_U32 u32STC_32)2265 void HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32)
2266 {
2267 _HAL_REG32L_W(&_TspCtrl[0].Pcr.H32, u32STC_32 & 0x01);
2268 }
2269
HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId)2270 MS_U32 HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId)
2271 {
2272 return (_HAL_REG32_R(&_TspCtrl[0].Pcr.ML));
2273 }
2274
HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId)2275 MS_U32 HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId)
2276 {
2277 return (_HAL_REG32L_R(&_TspCtrl[0].Pcr.H32) & 0x01);
2278 }
2279
HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_U8 u8Opt)2280 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Opt)
2281 {
2282 MS_U32 i = 0;
2283 MS_U32 u32Enable = 0;
2284 MS_U32 u32Cmd = 0;
2285
2286 if(u8Opt & HAL_TSP_STC_UPDATE_HK)
2287 {
2288 u32Enable = 1;
2289 }
2290 if(u8Opt & HAL_TSP_STC_UPDATE_UPDATEONCE)
2291 {
2292 u32Cmd = TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE;
2293 }
2294
2295 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Enable);
2296
2297 if (u8Eng == 0)
2298 {
2299 u32Cmd |= TSP_MCU_CMD_CTRL_STC_UPDATE;
2300 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32Cmd);
2301 }
2302 else
2303 {
2304 return FALSE;
2305 }
2306
2307 while (i< 4)
2308 {
2309 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2310 {
2311 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2312 return TRUE;
2313 }
2314 i++;
2315 _delay();
2316 }
2317 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2318 return FALSE;
2319 }
HAL_TSP_GetPcr(MS_U32 u32EngId,MS_U32 * pu32Pcr_32,MS_U32 * pu32Pcr)2320 MS_BOOL HAL_TSP_GetPcr(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr)
2321 {
2322 MS_U32 i = 0;
2323
2324 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2325 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2326 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_PCR_GET);
2327 while (i< 4)
2328 {
2329 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2330 {
2331 *pu32Pcr = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2332 *pu32Pcr_32 = _HAL_REG32_R(&_TspCtrl[0].MCU_Data1);
2333 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2334 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2335 return ((0!= *pu32Pcr) || (0!= *pu32Pcr_32))? TRUE: FALSE;
2336 }
2337 i++;
2338 _delay();
2339 }
2340 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2341 return FALSE;
2342 }
2343
HAL_TSP_CmdQ_IsEmpty(void)2344 MS_BOOL HAL_TSP_CmdQ_IsEmpty(void)
2345 {
2346 if (_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_EMPTY)
2347 {
2348 return TRUE;
2349 }
2350 return FALSE;
2351 }
2352
HAL_TSP_Int_Disable(MS_U32 u32Mask)2353 void HAL_TSP_Int_Disable(MS_U32 u32Mask)
2354 {
2355 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2356 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)(u32Mask>>8)));
2357 }
2358
HAL_TSP_Int_Enable(MS_U32 u32Mask)2359 void HAL_TSP_Int_Enable(MS_U32 u32Mask)
2360 {
2361 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2362 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)(u32Mask>>8)));
2363 }
2364
HAL_TSP_Int_ClearSw(void)2365 void HAL_TSP_Int_ClearSw(void)
2366 {
2367 if (_bIsHK)
2368 {
2369 _HAL_REG32_W(&_TspCtrl[0].SwInt_Stat, 0);
2370 }
2371 else
2372 {
2373 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_M, 0);
2374 _HAL_REG32_W(&_TspCtrl[0].SwInt_Stat1_H,
2375 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].SwInt_Stat1_H), TSP_SWINT1_H_MASK));
2376 }
2377 }
2378
HAL_TSP_Int_ClearHw(MS_U32 u32Mask)2379 void HAL_TSP_Int_ClearHw(MS_U32 u32Mask)
2380 {
2381 _HAL_REG16_W(&_TspCtrl[0].HwInt_Stat,
2382 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].HwInt_Stat)|0xFF00, (MS_U16)u32Mask));
2383 }
2384
HAL_TSP_CmdQ_CmdCount(void)2385 MS_U32 HAL_TSP_CmdQ_CmdCount(void)
2386 {
2387 return (((_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_CMDQ_CNT_MASK)>>TSP_CMDQ_CNT_SHFT));
2388 }
2389
HAL_TSP_CmdQ_TsDma_Reset(void)2390 void HAL_TSP_CmdQ_TsDma_Reset(void)
2391 {
2392 _HAL_REG32_W(&_TspCtrl[0].TsDma_Ctrl_CmdQ, 0);
2393 }
2394
HAL_TSP_CmdQ_Reset(void)2395 MS_BOOL HAL_TSP_CmdQ_Reset(void)
2396 {
2397 int ii = 0;
2398 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2399 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_CMDQ_RESET));
2400 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2401 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_CMDQ_RESET));
2402
2403 //reset the last data that hw is excuting --> HW new design
2404 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0,
2405 SET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg0), TSP_TSIFCFG_WB_FSM_RESET));
2406
2407 //check R done
2408 for(ii = 0; ii < 100; ii++)
2409 {
2410 if(_HAL_REG32_R(&_TspCtrl[0].TsDma_Ctrl_CmdQ) & TSP_TSDMA_RDONE)
2411 {
2412 break;
2413 }
2414 MsOS_DelayTask(1);
2415 }
2416
2417 _HAL_REG16_W(&_TspCtrl2[0].HwCfg0,
2418 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl2[0].HwCfg0), TSP_TSIFCFG_WB_FSM_RESET));
2419
2420 if(ii == 100)
2421 {
2422 printf("%s, wait fine in reset timeout\n", __FUNCTION__);
2423 return FALSE;
2424 }
2425
2426 //rst_ts_fin
2427 _HAL_REG32_W(&_TspCtrl[0].reg160C, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2428 _HAL_REG32_W(&_TspCtrl[0].reg160C, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2429
2430 return TRUE;
2431 }
2432
HAL_TSP_WbDmaEnable(MS_BOOL bEnable)2433 void HAL_TSP_WbDmaEnable(MS_BOOL bEnable)
2434 {
2435 if (bEnable)
2436 {
2437 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2438 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2439 }
2440 else
2441 {
2442 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2443 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2444 }
2445 }
2446
2447 // u32TSSrc: 0 -> TS0, 1 -> File
2448 // u32GroupId: 0 -> filter0~filter31
HAL_TSP_Scmb_Status(MS_U32 u32TSSrc,MS_U32 u32GroupId,MS_U32 u32PidFltId)2449 MS_U32 HAL_TSP_Scmb_Status(MS_U32 u32TSSrc, MS_U32 u32GroupId, MS_U32 u32PidFltId)
2450 {
2451 MS_U32 u32PIDFltMask = u32PidFltId;
2452 MS_U32 u32ScmbSts = 0;
2453
2454 if(u32PidFltId != 0xFFFFFFFF)
2455 {
2456 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
2457 }
2458
2459 if (u32TSSrc == 0)
2460 {
2461 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2462 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld));
2463
2464 u32ScmbSts = HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsPidScmbStatTsin), u32PIDFltMask);
2465
2466 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2467 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_ts_ld));
2468 }
2469 else
2470 {
2471 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2472 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_fi_ld));
2473
2474 u32ScmbSts = HAS_FLAG(_HAL_REG32_R(&_TspCtrl[0].TsPidScmbStatFile), u32PIDFltMask);
2475
2476 _HAL_REG32_W(&_TspCtrl[0].reg15b4,
2477 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg15b4), TSP_match_pid_scr_fi_ld));
2478 }
2479
2480 if(u32PIDFltMask != 0xFFFFFFFF)
2481 {
2482 u32ScmbSts = ((u32ScmbSts > 0) ? 1: 0);
2483 }
2484
2485 return u32ScmbSts;
2486
2487 }
2488 #if 0
2489 void HAL_TSP_CPU_SetBase(MS_U32 u32Addr, MS_U32 u32Size)
2490 {
2491 #if (!LINUX_TEST)
2492 // TSP FW running in QMEM
2493 _HAL_TSP_FW_load(u32Addr, u32Size, TRUE, TRUE, TRUE);
2494 #else
2495 // only for linux
2496 // @FIXME: abstract this later
2497 void* pBuf = NULL;
2498 MS_U32 u32PhysAddr = 0;
2499
2500 #if 0
2501 if (NULL == (pBuf = MsOS_AllocateMemory (u32Size, gs32NonCachedPoolID)))
2502 {
2503 MS_ASSERT(0);
2504 }
2505
2506 memcpy(pBuf, (void*)u32Addr, u32Size);
2507 u32PhysAddr = (MS_U32)VA2PA(pBuf);
2508 printf("firmware 0x%08x 0x%08x\n", (MS_U32)pBuf, u32Addr);
2509 _HAL_TSP_FW_load(u32PhysAddr, u32Size, TRUE, TRUE, TRUE);
2510 MsOS_FreeMemory(pBuf, gs32NonCachedPoolID);
2511 #else
2512 if (NULL == (pBuf = MsOS_AllocateMemory (72*1024*1024, gs32NonCachedPoolID)))
2513 {
2514 MS_ASSERT(0);
2515 }
2516 u32PhysAddr = 60*1024*1024;
2517 memcpy(PA2KSEG1(u32PhysAddr), (void*)u32Addr, u32Size);
2518 printf("firmware 0x%08x 0x%08x\n", (MS_U32)PA2KSEG1(u32PhysAddr), u32PhysAddr);
2519 _HAL_TSP_FW_load(u32PhysAddr, u32Size, TRUE, TRUE, TRUE);
2520 MsOS_FreeMemory(pBuf, gs32NonCachedPoolID);
2521 #endif
2522 #endif
2523 }
2524 #else
HAL_TSP_CPU_SetBase(MS_PHY phyAddr,MS_U32 u32Size)2525 void HAL_TSP_CPU_SetBase(MS_PHY phyAddr, MS_U32 u32Size)
2526 {
2527 printf("[%s][%d] load firmware (address, size) = (0x%08lx, 0x%08lx)\n", __FUNCTION__, __LINE__, (unsigned long)phyAddr, (unsigned long)u32Size);
2528 _HAL_TSP_FW_load(phyAddr, u32Size, TRUE, TRUE, TRUE);
2529 }
2530
2531 #endif // #if 0
2532
HAL_TSP_Alive(void)2533 MS_BOOL HAL_TSP_Alive(void)
2534 {
2535 MS_U32 i = 0;
2536 MS_U32 u32Data;
2537
2538 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2539 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_ALIVE);
2540 while (i< 4)
2541 {
2542 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2543 {
2544 u32Data = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2545 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2546 return (TSP_MCU_DATA_ALIVE == u32Data)? TRUE: FALSE;
2547 }
2548 i++;
2549 _delay();
2550 }
2551 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2552 return FALSE;
2553 }
2554
HAL_TSP_SetOwner(REG_SecFlt * pSecFilter,MS_BOOL bOwner)2555 void HAL_TSP_SetOwner(REG_SecFlt* pSecFilter, MS_BOOL bOwner)
2556 {
2557 MS_U32 u32HkId;
2558
2559 if (_bIsHK)
2560 {
2561 u32HkId = (bOwner)? 0: 1;
2562 }
2563 else
2564 {
2565 u32HkId = (bOwner)? 1: 0;
2566 }
2567 HAL_REG32_IndW((REG32 *)&pSecFilter->RmnReqCnt, (HAL_REG32_IndR((REG32 *)&pSecFilter->RmnReqCnt) & ~TSP_SECFLT_OWNER_MASK) |
2568 ((u32HkId << TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK));
2569 }
2570
HAL_TSP_FileIn_Set(MS_BOOL bset)2571 void HAL_TSP_FileIn_Set(MS_BOOL bset)
2572 {
2573 if (bset)
2574 {
2575 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2576 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_FILEIN192_EN));
2577 }
2578 else
2579 {
2580 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2581 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_FILEIN192_EN));
2582 }
2583 }
2584
HAL_TSP_ResetTimeStamp(void)2585 void HAL_TSP_ResetTimeStamp(void)
2586 {
2587 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2588 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2589 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2590 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_TIMESTAMP_RESET));
2591 }
2592
HAL_TSP_GetPVRTimeStamp(void)2593 MS_U32 HAL_TSP_GetPVRTimeStamp(void)
2594 {
2595 MS_U32 u32lpcr;
2596
2597 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2598 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_RLD));
2599 u32lpcr = _HAL_REG32_R(&_TspCtrl[0].LPcr1);
2600 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2601 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_RLD));
2602
2603 return u32lpcr;
2604 }
2605
HAL_TSP_SetPVRTimeStamp(MS_U32 u32Stamp)2606 void HAL_TSP_SetPVRTimeStamp(MS_U32 u32Stamp)
2607 {
2608 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2609 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_WLD));
2610 _HAL_REG32_W(&_TspCtrl[0].LPcr1,u32Stamp);
2611 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2612 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR1_WLD));
2613 }
2614
HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId,MS_U32 u32ClkSrc)2615 MS_BOOL HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId, MS_U32 u32ClkSrc)
2616 {
2617 if(u32ClkSrc == 0x0) // 90K
2618 {
2619 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2620 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PVR1_CLK_STAMP_27_EN));
2621 }
2622 else // 27M
2623 {
2624 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2625 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_PVR1_CLK_STAMP_27_EN));
2626 }
2627 return TRUE;
2628 }
2629
HAL_TSP_GetPlayBackTimeStamp(void)2630 MS_U32 HAL_TSP_GetPlayBackTimeStamp(void)
2631 {
2632 MS_U32 u32lpcr;
2633
2634 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2635 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_RLD));
2636 u32lpcr = _HAL_REG32_R(&_TspCtrl[0].LPcr2);
2637 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2638 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_RLD));
2639
2640 return u32lpcr;
2641 }
2642
HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp)2643 void HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp)
2644 {
2645 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2646 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_WLD));
2647 _HAL_REG32_W(&_TspCtrl[0].LPcr2,u32Stamp);
2648 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2649 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_LPCR2_WLD));
2650 }
2651
HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id,MS_U32 u32ClkSrc)2652 MS_BOOL HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id, MS_U32 u32ClkSrc)
2653 {
2654 if(u32ClkSrc == 0x0) // 90K
2655 {
2656 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2657 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_TSIF0_CLK_STAMP_27_EN));
2658 }
2659 else // 27M
2660 {
2661 _HAL_REG32_W(&_TspCtrl[0].Dnld_Ctrl2,
2662 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Dnld_Ctrl2), TSP_TSIF0_CLK_STAMP_27_EN));
2663 }
2664 return TRUE;
2665 }
2666
HAL_TSP_GetFileInTimeStamp(void)2667 MS_U32 HAL_TSP_GetFileInTimeStamp(void)
2668 {
2669 return _HAL_REG32_R(&_TspCtrl[0].TimeStamp_FileIn);
2670 }
2671
HAL_TSP_GetFilinReadAddr(MS_PHY * pphyReadAddr)2672 MS_BOOL HAL_TSP_GetFilinReadAddr(MS_PHY* pphyReadAddr)
2673 {
2674 *pphyReadAddr = ((MS_PHY)_HAL_REG32_R(&_TspCtrl[0].TsFileIn_RPtr) << MIU_BUS) + _phyFIBufMiuOffset;
2675
2676 return TRUE;
2677 }
2678
HAL_TSP_SetDMABurstLen(MS_U32 u32Len)2679 void HAL_TSP_SetDMABurstLen(MS_U32 u32Len)
2680 {
2681 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2682 _HAL_REG32_R(&_TspCtrl[0].Hw_Config4) | ((u32Len<<TSP_HW_DMA_MODE_SHIFT)&TSP_HW_DMA_MODE_MASK));
2683 _HAL_REG32_W(&_TspCtrl[0].PktChkSizeFilein,
2684 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].PktChkSizeFilein), TSP_SEC_DMA_BURST_EN));
2685 }
2686
HAL_TSP_PVR_PacketMode(MS_BOOL bSet)2687 void HAL_TSP_PVR_PacketMode(MS_BOOL bSet)
2688 {
2689 if (bSet)
2690 {
2691 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2692 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RECORD192_EN));
2693 }
2694 else
2695 {
2696 _HAL_REG32_W(&_TspCtrl[0].reg160C,
2697 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].reg160C), TSP_RECORD192_EN));
2698 }
2699 }
2700
HAL_ResetAll(void)2701 void HAL_ResetAll(void)
2702 {
2703 printf("Reset ALL registers\n");
2704 //_HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2705 // SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_CPU_EN));
2706 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2707 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2708 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2709 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2710 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2711 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
2712
2713 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2714 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2715 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2716 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2717 _HAL_REG32_W(&_TspCtrl[0].TSP_Ctrl,
2718 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].TSP_Ctrl), TSP_CTRL_SW_RST));
2719 }
2720
2721
2722 #define CKG_TS0_TS1 0x16A0UL //0x28
2723 #define CLK_TS0_DISABLE 0x0001UL
2724 #define CLK_TS0_INVERT 0x0002UL
2725 #define CLK_TS0_CLK_MASK 0x001CUL
2726 #define CLK_TS1_DISABLE 0x0100UL
2727 #define CLK_TS1_INVERT 0x0200UL
2728 #define CLK_TS1_CLK_MASK 0x1C00UL
2729 #define CKG_TSP_STC0 0x16A8UL //0x2a
2730 #define CLK_TSP_DISABLE 0x0001UL
2731 #define CLK_TSP_INVERT 0x0002UL
2732 #define CLK_TSP_CLK_MASK 0x000CUL
2733 #define CLK_PAR_DISABLE 0x0010UL
2734 #define CLK_PAR_INVERT 0x0020UL
2735 #define CLK_PAR_CLK_MASK 0x0040UL
2736 #define CLK_PAR_CLK_192 0x0040UL
2737 #define CLK_STC_DISABLE 0x0100UL
2738 #define CLK_STC_INVERT 0x0200UL
2739 #define CLK_STC_CLK_MASK 0x0C00UL
2740 #define CKG_TSP_STAMP 0x16ACUL //0x2b
2741 #define CLK_SYN_STC0_MASK 0x0007UL
2742 #define CLK_SYN_STC0_432M 0x0001UL
2743 #define CLK_STAM_DISABLE 0x0100UL
2744 #define CLK_STAM_INVERT 0x0200UL
2745 #define CLK_STAM_CLK_MASK 0x0C00UL
2746 #define CKG2_TSP_TS_SAMPLE 0x1464UL //0x019
2747 #define CKG2_TSP_TS_SAMPLE_DISABLE 0x0010UL
2748 #define CKG2_TSP_TS_SAMPLE_INVERT 0x0020UL
2749 #define CKG2_TSP_TS_SAMPLE_CLK_MASK 0x00C0UL
2750 #define CHIP_TSP_BOOT_CLK_SEL 0x3D68 //0x5a
2751 #define CHIP_TSP_BOOT_CLK_SEL_MASK 0x0020
2752
HAL_TSP_PowerCtrl(MS_BOOL bOn)2753 void HAL_TSP_PowerCtrl(MS_BOOL bOn)
2754 {
2755 if (bOn)
2756 {
2757 //Set PE Pad
2758 //TSP_TOP_REG(REG_TOP_TS0_PE) |= REG_TOP_TS0_PE_MASK;
2759
2760 // Enable TSP Clock
2761 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2762 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_TSP_DISABLE|CLK_TSP_INVERT|CLK_TSP_CLK_MASK)));
2763
2764 // Enable CLK_PARSER clock
2765 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2766 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_DISABLE|CLK_PAR_INVERT|CLK_PAR_CLK_MASK)));
2767 //Set CLK_PARSER_192
2768 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2769 SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_PAR_CLK_192)));
2770
2771 //TSP select SRAM
2772 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CHIP_TSP_BOOT_CLK_SEL)), CHIP_TSP_BOOT_CLK_SEL_MASK));
2773
2774 //Select SRAM
2775 _HAL_REG32_W(&(_TspCtrl2[0].Qmem_Config), SET_FLAG1(_HAL_REG32_R(&(_TspCtrl2[0].Qmem_Config)), TSP_TSP_SEL_SRAM));
2776
2777 // Enable TS0 clock
2778 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),
2779 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|CLK_TS0_CLK_MASK)));
2780
2781 // Enable TS1 clock
2782 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1),
2783 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|CLK_TS1_CLK_MASK)));
2784
2785 // Set SYN_STC to be 432MHz
2786 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),
2787 SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_SYN_STC0_432M));
2788
2789 // Enable STC clock
2790 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0),
2791 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), (CLK_STC_DISABLE|CLK_STC_INVERT|CLK_STC_CLK_MASK)));
2792
2793 // Enable TIMESTAMP clock
2794 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP),
2795 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INVERT|CLK_STAM_CLK_MASK)));
2796
2797 // Enable Sample clock
2798 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE),
2799 RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), (CKG2_TSP_TS_SAMPLE_DISABLE|CKG2_TSP_TS_SAMPLE_INVERT|CKG2_TSP_TS_SAMPLE_CLK_MASK)));
2800
2801 }
2802 else
2803 {
2804 // Disable TSP clock
2805 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_TSP_DISABLE));
2806
2807 // Disable TS0 clock
2808 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), CLK_TS0_DISABLE));
2809
2810 // Disable TS1 clock
2811 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TS0_TS1)), CLK_TS1_DISABLE));
2812
2813 // Disable STC clock
2814 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_STC_DISABLE));
2815
2816 // Disable CLK_PARSER clock
2817 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STC0)), CLK_PAR_DISABLE));
2818
2819 // Disable TIMESTAMP clock
2820 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG_TSP_STAMP)), CLK_STAM_DISABLE));
2821
2822 // Disable Sample clock
2823 _HAL_REG32L_W((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_virtRegBase+CKG2_TSP_TS_SAMPLE)), CKG2_TSP_TS_SAMPLE_DISABLE));
2824
2825 //Reset PE Pad
2826 if(_bTsPadUsed[0] == TRUE)
2827 {
2828 TSP_TOP_REG(REG_TOP_TS0_PE) &= ~REG_TOP_TS0_PE_MASK;
2829 _bTsPadUsed[0] = FALSE;
2830 }
2831 else if(_bTsPadUsed[1] == TRUE)
2832 {
2833 TSP_TOP_REG(REG_TOP_TS1_PE) &= ~REG_TOP_TS1_PE_MASK;
2834 _bTsPadUsed[1] = FALSE;
2835 }
2836
2837 }
2838 }
2839
2840 #undef CKG_TS0_TS1
2841 #undef CLK_TS0_DISABLE
2842 #undef CLK_TS0_INVERT
2843 #undef CLK_TS0_CLK_MASK
2844 #undef CKG_TSP_STC0
2845 #undef CLK_TSP_DISABLE
2846 #undef CLK_TSP_INVERT
2847 #undef CLK_TSP_CLK_MASK
2848 #undef CLK_PAR_DISABLE
2849 #undef CLK_PAR_INVERT
2850 #undef CLK_PAR_CLK_MASK
2851 #undef CLK_PAR_CLK_192
2852 #undef CLK_STC_DISABLE
2853 #undef CLK_STC_INVERT
2854 #undef CLK_STC_CLK_MASK
2855 #undef CKG_TSP_STAMP
2856 #undef CLK_SYN_STC0_MASK
2857 #undef CLK_SYN_STC0_432M
2858 #undef CLK_STAM_DISABLE
2859 #undef CLK_STAM_INVERT
2860 #undef CLK_STAM_CLK_MASK
2861 #undef CKG2_TSP_TS_SAMPLE
2862 #undef CKG2_TSP_TS_SAMPLE_DISABLE
2863 #undef CKG2_TSP_TS_SAMPLE_INVERT
2864 #undef CKG2_TSP_TS_SAMPLE_CLK_MASK
2865 #undef CHIP_TSP_BOOT_CLK_SEL
2866 #undef CHIP_TSP_BOOT_CLK_SEL_MASK
2867
2868
HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel)2869 MS_U32 HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel)
2870 {
2871 _HAL_REG32_W(&_TspCtrl[0].PKT_CNT, TSP_DBG_SEL_MASK&(u32dbgsel<<TSP_DBG_SEL_SHIFT));
2872 return (_HAL_REG32_R(&_TspCtrl[0].TSP_Debug)&TSP_DEBUG_MASK);
2873 }
2874
HAL_TSP_Enable_ValidSync_Dectect(void)2875 void HAL_TSP_Enable_ValidSync_Dectect(void)
2876 {
2877 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2878 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_VALID_FALLING_DETECT));
2879 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
2880 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_SYNC_RISING_DETECT));
2881 }
2882
HAL_Reset_WB(void)2883 void HAL_Reset_WB(void)
2884 {
2885 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2886 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2887 _HAL_REG32_W(&_TspCtrl[0].Hw_Config0,
2888 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config0), TSP_HW_CFG0_WB_DMA_RESET));
2889 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2890 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2891 _HAL_REG16_W(&_TspCtrl[0].TSP_Ctrl1,
2892 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].TSP_Ctrl1), TSP_CTRL1_DMA_RST));
2893 }
2894
HAL_TSP_Get_FW_VER(void)2895 MS_U32 HAL_TSP_Get_FW_VER(void)
2896 {
2897 MS_U32 i = 0;
2898 MS_U32 u32Data = 0;
2899
2900 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2901 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_VERSION_GET);
2902 while (i< 4)
2903 {
2904 if (0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2905 {
2906 u32Data = _HAL_REG32_R(&_TspCtrl[0].MCU_Data0);
2907 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2908 return u32Data;
2909 }
2910 i++;
2911 _delay();
2912 }
2913 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2914 return u32Data;
2915 }
2916
HAL_TSP_Check_FW_VER(void)2917 MS_BOOL HAL_TSP_Check_FW_VER(void)
2918 {
2919 MS_U32 u32FWVer;
2920
2921 u32FWVer = HAL_TSP_Get_FW_VER();
2922 if((u32FWVer >> 16) != TSP_FW_DEVICE_ID)
2923 {
2924 printf("\nWarning: TSP FW not match!! FW version: 0x%08x\n\n", (unsigned int)u32FWVer);
2925 return FALSE;
2926 }
2927
2928 return TRUE;
2929 }
2930
HAL_TSP_SetFwDbgMem(MS_PHY phyAddr,MS_U32 u32Size)2931 MS_BOOL HAL_TSP_SetFwDbgMem(MS_PHY phyAddr, MS_U32 u32Size)
2932 {
2933 MS_U32 i = 0;
2934
2935 if(IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_1_ADDR, OPENRISC_IP_1_ADDR + OPENRISC_IP_1_SIZE) ||
2936 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_2_ADDR, OPENRISC_IP_2_ADDR + OPENRISC_IP_2_SIZE) ||
2937 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_IP_3_ADDR, OPENRISC_IP_3_ADDR + OPENRISC_IP_3_SIZE) ||
2938 IsCover(phyAddr, phyAddr + u32Size, OPENRISC_QMEM_ADDR, OPENRISC_QMEM_ADDR + OPENRISC_QMEM_SIZE))
2939 {
2940 printf("[%s][%d] invalid physical address 0x%x\n", __FUNCTION__, __LINE__, (unsigned int)phyAddr);
2941 return FALSE;
2942 }
2943 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, phyAddr);
2944 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, u32Size);
2945 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DBG_MEM);
2946 while(i<4)
2947 {
2948 if(0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2949 {
2950 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2951 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2952 return TRUE;
2953 }
2954 i++;
2955 _delay();
2956 }
2957 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2958 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2959 _HAL_REG32_W(&_TspCtrl[0].MCU_Data1, 0);
2960
2961 return FALSE;
2962 }
2963
HAL_TSP_SetFwDbgWord(MS_U32 u32Word)2964 MS_BOOL HAL_TSP_SetFwDbgWord(MS_U32 u32Word)
2965 {
2966 MS_U32 i = 0;
2967
2968 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, u32Word);
2969 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DBG_WORD);
2970 while(i<4)
2971 {
2972 if(0 == _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd))
2973 {
2974 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2975 return TRUE;
2976 }
2977 i++;
2978 _delay();
2979 }
2980 _HAL_REG32_W(&_TspCtrl[0].MCU_Data0, 0);
2981 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, 0);
2982 return FALSE;
2983 }
2984
2985 //0: VQ0, 1: VQ_file
HAL_TSP_SetVQBuffer(MS_PHY phyBaseAddr,MS_U32 u32BufLen)2986 void HAL_TSP_SetVQBuffer(MS_PHY phyBaseAddr, MS_U32 u32BufLen)
2987 {
2988 MS_PHY phyAddr = phyBaseAddr;
2989 MS_U32 u32Size = 0, u32OneBufSize = 0, u32temp = 0;
2990 MS_PHY phyVqBufOffset = _HAL_TSP_MIU_OFFSET(phyBaseAddr);
2991
2992 u32OneBufSize = ((u32BufLen >> MIU_BUS) / TSP_VQ_NUM) << MIU_BUS; //miu alignment
2993 u32Size = u32OneBufSize / TSP_VQ_PITCH;
2994
2995 _HAL_REG32_W(&(_TspCtrl[0].VQ0_BASE), (MS_U32)((phyAddr-phyVqBufOffset) >> MIU_BUS));
2996 u32temp = (u32Size << TSP_VQ0_SIZE_192PK_SHIFT) | (_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL) & ~TSP_VQ0_SIZE_192PK_MASK);
2997 _HAL_REG32_W(&(_TspCtrl[0].VQ0_CTRL), u32temp);
2998
2999 phyAddr += u32OneBufSize;
3000 _HAL_REG32_W(&(_TspCtrl[0].VQ1_Base), (MS_U32)((phyAddr-phyVqBufOffset) >> MIU_BUS));
3001 u32temp = (u32Size << TSP_VQ1_SIZE_192BYTE_SHIFT) | (_HAL_REG32_R(&_TspCtrl[0].VQ1_Size) & ~TSP_VQ1_SIZE_192BYTE_MASK);
3002 _HAL_REG32_W(&(_TspCtrl[0].VQ1_Size), u32temp);
3003 }
3004
HAL_TSP_VQueue_Enable(MS_BOOL bEnable)3005 void HAL_TSP_VQueue_Enable(MS_BOOL bEnable)
3006 {
3007 if (bEnable)
3008 {
3009 // Reset VQ before VQ enable.
3010 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3011 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3012
3013 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3014 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3015
3016 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3017 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS), (TSP_VQ0_EN|TSP_VQ_FILE_EN|TSP_VQ_PINGPONG_EN)));
3018 }
3019 else
3020 {
3021 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3022 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS), (TSP_VQ0_EN|TSP_VQ_FILE_EN|TSP_VQ_PINGPONG_EN)));
3023 }
3024
3025 }
3026
HAL_TSP_VQueue_Reset(void)3027 void HAL_TSP_VQueue_Reset(void)
3028 {
3029 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3030 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3031 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3032 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_RESET));
3033
3034 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3035 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3036 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3037 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_RESET));
3038 }
3039
HAL_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable)3040 void HAL_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable)
3041 {
3042 if (bEnable)
3043 {
3044 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3045 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_OVERFLOW_INT_EN));
3046 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3047 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_OVF_INT_EN));
3048
3049 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3050 SET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L)|0xFF00 , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8));
3051 }
3052 else
3053 {
3054 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL,
3055 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL), TSP_VQ0_OVERFLOW_INT_EN));
3056 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3057 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].VQ1_Config), TSP_VQ1_OVF_INT_EN));
3058
3059 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3060 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) , TSP_HWINT2_VQ_OVERFLOW_STATUS >> 8));
3061 }
3062 }
3063
HAL_TSP_VQueue_Clr_OverflowInt(void)3064 void HAL_TSP_VQueue_Clr_OverflowInt(void)
3065 {
3066 MS_U32 u32data = _HAL_REG32_R(&_TspCtrl[0].VQ0_CTRL);
3067
3068 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, u32data | TSP_VQ0_CLR_OVERFLOW_INT);
3069 _HAL_REG32_W(&_TspCtrl[0].VQ0_CTRL, u32data & ~TSP_VQ0_CLR_OVERFLOW_INT);
3070
3071 u32data = _HAL_REG32_R(&_TspCtrl[0].VQ1_Config);
3072 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, u32data | TSP_VQ1_CLR_OVF_INT);
3073 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config, u32data & ~TSP_VQ1_CLR_OVF_INT);
3074
3075 _HAL_REG16_W(&_TspCtrl[0].SwInt_Stat1_L,
3076 RESET_FLAG1(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L), TSP_HWINT2_VQ_OVERFLOW_STATUS));
3077 }
3078
HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len)3079 void HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len)
3080 {
3081 MS_U32 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN1;
3082
3083 switch(u8req_len)
3084 {
3085 case 1:
3086 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN1;
3087 break;
3088 case 2:
3089 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN2;
3090 break;
3091 case 4:
3092 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN4;
3093 break;
3094 case 8:
3095 u32Value = TSP_REQ_VQ_RX_THRESHOLD_LEN8;
3096 break;
3097 default:
3098 break;
3099 }
3100
3101 _HAL_REG32_W(&_TspCtrl[0].VQ0_STATUS,
3102 (_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS) & ~TSP_REQ_VQ_RX_THRESHOLD_MASKE) | u32Value);
3103
3104
3105 _HAL_REG32_W(&_TspCtrl[0].VQ1_Config,
3106 (_HAL_REG32_R(&_TspCtrl[0].VQ1_Config) & ~TSP_VQ1_WR_THRESHOLD_MASK) | u32Value);
3107 }
3108
HAL_TSP_VQ_INT_STATUS(void)3109 MS_U32 HAL_TSP_VQ_INT_STATUS(void)
3110 {
3111 return (MS_U32)(_HAL_REG16_R(&_TspCtrl[0].SwInt_Stat1_L) & TSP_HWINT2_VQ_OVERFLOW_STATUS);
3112 }
3113
HAL_TSP_Get_VQStatus(void)3114 MS_U32 HAL_TSP_Get_VQStatus(void)
3115 {
3116 return (_HAL_REG32_R(&_TspCtrl[0].VQ0_STATUS) & TSP_VQ0_STATUS_MASK);
3117 }
3118
HAL_TSP_GetPidFltReg(MS_U32 u32EngId,MS_U32 u32PidFltId)3119 REG_PidFlt* HAL_TSP_GetPidFltReg(MS_U32 u32EngId, MS_U32 u32PidFltId)
3120 {
3121 return (&(_TspPid[u32EngId].Flt[u32PidFltId]));
3122 }
3123
HAL_TSP_Read_DropPktCnt(MS_U16 * pu16ADropCnt,MS_U16 * pu16VDropCnt)3124 MS_BOOL HAL_TSP_Read_DropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt)
3125 {
3126 return FALSE;
3127 }
3128
HAL_TSP_TSIF0_Enable(MS_BOOL bEnable)3129 void HAL_TSP_TSIF0_Enable(MS_BOOL bEnable)
3130 {
3131 if (bEnable)
3132 {
3133 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3134 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
3135 }
3136 else
3137 {
3138 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3139 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF0_ENABLE));
3140 }
3141 }
3142
HAL_TSP_TSIF1_Enable(MS_BOOL bEnable)3143 void HAL_TSP_TSIF1_Enable(MS_BOOL bEnable)
3144 {
3145 if (bEnable)
3146 {
3147 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3148 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
3149 }
3150 else
3151 {
3152 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3153 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_CFG4_TSIF1_ENABLE));
3154 }
3155 }
3156
3157 // (Section DMA + PVR) , total 5 set
3158 // Default value of low bound is 0, default value of up bound is 0xFFFFFFFF, means no protection
3159 // If set both low bound and up bound to be 0, means protection all
3160 // MIU bus is 4, Max MIU address is 512MB, should append 1 zero
3161 // The range can be written: u32StartAddr <= x < u32EndAddr
3162 // Protection range: x >= u32EndAddr && x < u32StartAddr
HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable,MS_PHY * pphyStartAddr,MS_PHY * pphyEndAddr)3163 void HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY* pphyStartAddr, MS_PHY* pphyEndAddr)
3164 {
3165 MS_U32 u32value;
3166 MS_U32 u32lbnd, u32ubnd;
3167
3168 if (bEnable)
3169 {
3170 if(pphyStartAddr[0] == pphyEndAddr[0])
3171 pphyEndAddr[0] += (1UL << MIU_BUS);
3172
3173 u32lbnd = (MS_U32)(((pphyStartAddr[0]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[0])) >> MIU_BUS) >> TSP_DMAW_BND_ALI_SHIFT) & TSP_DMAW_LBND_LSB8;
3174 u32ubnd = (MS_U32)((((pphyEndAddr[0]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[0])) >> MIU_BUS) >> TSP_DMAW_BND_ALI_SHIFT) & TSP_DMAW_LBND_LSB8) << TSP_DMAW_UBND_LSB8_SHIFT;
3175 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16C4) & ~(TSP_DMAW_LBND_LSB8|TSP_DMAW_UBND_LSB8));
3176 _HAL_REG32_W(&_TspCtrl[0].reg16C4, u32value);
3177 u32lbnd = (MS_U32)(((pphyStartAddr[0]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[0])) >> MIU_BUS) >> TSP_DMAWP_BND_ALI_SHIFT) & TSP_DMAWP_LBND_MASK;
3178 u32ubnd = (MS_U32)((((pphyEndAddr[0]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[0])) >> MIU_BUS) >> TSP_DMAWP_BND_ALI_SHIFT) & TSP_DMAWP_HBND_MASK) << TSP_DMAWP_HBND_SHFT;
3179 u32value = u32lbnd + u32ubnd;
3180 _HAL_REG32_W(&_TspCtrl[0].TSP_DMAWP_BND, u32value);
3181
3182 if(pphyStartAddr[1] == pphyEndAddr[1])
3183 pphyStartAddr[1] += (1UL << MIU_BUS);
3184
3185 u32lbnd = (MS_U32)(((pphyStartAddr[1]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[1])) >> MIU_BUS) >> TSP_DMAW1_BND_ALI_SHIFT) & TSP_DMAW1_LBND_LSB8;
3186 u32ubnd = (MS_U32)((((pphyEndAddr[1]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[1])) >> MIU_BUS) >> TSP_DMAW1_BND_ALI_SHIFT) & TSP_DMAW1_LBND_LSB8) << TSP_DMAW1_UBND_LSB8_SHIFT;
3187 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16C8) & ~(TSP_DMAW1_LBND_LSB8|TSP_DMAW1_UBND_LSB8));
3188 _HAL_REG32_W(&_TspCtrl[0].reg16C8, u32value);
3189 u32lbnd = (MS_U32)(((pphyStartAddr[1]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[1])) >> MIU_BUS) >> TSP_DMAW1_ALI_SHIFT) & TSP_DMAW1_LBND_MASK1;
3190 u32ubnd = (MS_U32)((((pphyEndAddr[1]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[1])) >> MIU_BUS) >> TSP_DMAW1_ALI_SHIFT) & TSP_DMAW1_UBND_MASK1) << TSP_DMAW1_UBND_SHIFT1;
3191 u32value = u32lbnd + u32ubnd;
3192 _HAL_REG32_W(&_TspCtrl[0].DMAW1_1, u32value);
3193
3194 if(pphyStartAddr[2] == pphyEndAddr[2])
3195 pphyStartAddr[2] += (1UL << MIU_BUS);
3196
3197 u32lbnd = (MS_U32)(((pphyStartAddr[2]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[2])) >> MIU_BUS) >> TSP_DMAW2_BND_ALI_SHIFT) & TSP_DMAW2_LBND_LSB8;
3198 u32ubnd = (MS_U32)((((pphyEndAddr[2]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[2])) >> MIU_BUS) >> TSP_DMAW2_BND_ALI_SHIFT) & TSP_DMAW2_LBND_LSB8) << TSP_DMAW2_UBND_LSB8_SHIFT;
3199 u32value = u32lbnd + u32ubnd+ (_HAL_REG32_R(&_TspCtrl[0].reg16CC) & ~(TSP_DMAW2_LBND_LSB8|TSP_DMAW2_UBND_LSB8));
3200 _HAL_REG32_W(&_TspCtrl[0].reg16CC, u32value);
3201 u32lbnd = (MS_U32)(((pphyStartAddr[2]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[2])) >> MIU_BUS) >> TSP_DMAW2_ALI_SHIFT) & TSP_DMAW2_LBND_MASK1;
3202 u32ubnd = (MS_U32)((((pphyEndAddr[2]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[2])) >> MIU_BUS) >> TSP_DMAW2_ALI_SHIFT) & TSP_DMAW2_UBND_MASK1) << TSP_DMAW2_UBND_SHIFT1;
3203 u32value = u32lbnd + u32ubnd;
3204 _HAL_REG32_W(&_TspCtrl[0].DMAW2_1, u32value);
3205
3206 if(pphyStartAddr[3] == pphyEndAddr[3])
3207 pphyStartAddr[3] += (1UL << MIU_BUS);
3208
3209 u32lbnd = (MS_U32)(((pphyStartAddr[3]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[3])) >> MIU_BUS) >> TSP_DMAW3_BND_ALI_SHIFT) & TSP_DMAW3_LBND_MASK;
3210 u32ubnd = (MS_U32)(((pphyEndAddr[3]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[3])) >> MIU_BUS) >> TSP_DMAW3_BND_ALI_SHIFT) & TSP_DMAW3_UBND_MASK;
3211 _HAL_REG32_W(&_TspCtrl[0].DMAW3_LBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW3_LBND) & ~TSP_DMAW3_LBND_MASK) | u32lbnd);
3212 _HAL_REG32_W(&_TspCtrl[0].DMAW3_UBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW3_UBND) & ~TSP_DMAW3_UBND_MASK) | u32ubnd);
3213
3214 if(pphyStartAddr[4] == pphyEndAddr[4])
3215 pphyStartAddr[4] += (1UL << MIU_BUS);
3216
3217 u32lbnd = (MS_U32)(((pphyStartAddr[4]-_HAL_TSP_MIU_OFFSET(pphyStartAddr[4])) >> MIU_BUS) >> TSP_DMAW4_BND_ALI_SHIFT) & TSP_DMAW4_LBND_MASK;
3218 u32ubnd = (MS_U32)(((pphyEndAddr[4]-_HAL_TSP_MIU_OFFSET(pphyEndAddr[4])) >> MIU_BUS) >> TSP_DMAW4_BND_ALI_SHIFT) & TSP_DMAW4_UBND_MASK;
3219 _HAL_REG32_W(&_TspCtrl[0].DMAW4_LBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW4_LBND) & ~TSP_DMAW4_LBND_MASK) | u32lbnd);
3220 _HAL_REG32_W(&_TspCtrl[0].DMAW4_UBND, (_HAL_REG32_R(&_TspCtrl[0].DMAW4_UBND) & ~TSP_DMAW4_UBND_MASK) | u32ubnd);
3221
3222 _HAL_REG32_W(&_TspCtrl[0].reg15b4, _HAL_REG32_R(&_TspCtrl[0].reg15b4) | TSP_DMAW_PROTECT_EN);
3223 }
3224 else
3225 {
3226 _HAL_REG32_W(&_TspCtrl[0].reg15b4, _HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_DMAW_PROTECT_EN);
3227 }
3228 }
3229
HAL_TSP_MOBF_Set_PVRKey(MS_U32 u32Key0,MS_U32 u32Key1)3230 MS_BOOL HAL_TSP_MOBF_Set_PVRKey(MS_U32 u32Key0, MS_U32 u32Key1)
3231 {
3232 _HAL_REG32_W(&_TspCtrl[0].MOBF_PVR_KEY, (_HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_MOBF_PVR_KEY0_MASK) | ((u32Key0 << TSP_MOBF_PVR_KEY0_SHIFT) & TSP_MOBF_PVR_KEY0_MASK));
3233 _HAL_REG32_W(&_TspCtrl[0].MOBF_PVR_KEY, (_HAL_REG32_R(&_TspCtrl[0].reg15b4) & ~TSP_MOBF_PVR_KEY1_MASK) | ((u32Key0 << TSP_MOBF_PVR_KEY1_SHIFT) & TSP_MOBF_PVR_KEY1_MASK));
3234 return TRUE;
3235 }
3236
HAL_TSP_MOBF_Set_FileinKey(MS_U32 u32Key)3237 MS_BOOL HAL_TSP_MOBF_Set_FileinKey(MS_U32 u32Key)
3238 {
3239 MS_U32 u32Data = 0;
3240
3241 u32Data = (_HAL_REG32_R(&_TspCtrl[0].Pcr64_H) & ~TSP_MOBF_FILE_KEY0_L_MASK) |
3242 ((u32Key << TSP_MOBF_FILE_KEY0_L_SHIFT) & TSP_MOBF_FILE_KEY0_L_MASK);
3243 _HAL_REG32_W(&_TspCtrl[0].Pcr64_H, u32Data);
3244 return TRUE;
3245 }
3246
HAL_TSP_MOBF_Filein_Enable(MS_BOOL bEnable)3247 MS_BOOL HAL_TSP_MOBF_Filein_Enable(MS_BOOL bEnable)
3248 {
3249 return FALSE;
3250 }
3251
HAL_TSP_MOBF_PVR_Enable(MS_BOOL bEnable)3252 MS_BOOL HAL_TSP_MOBF_PVR_Enable(MS_BOOL bEnable)
3253 {
3254 return FALSE;
3255 }
3256
HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)3257 MS_BOOL HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable)
3258 {
3259 if (bEnable)
3260 {
3261 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3262 SET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_BD_AUDIO_EN));
3263 }
3264 else
3265 {
3266 _HAL_REG32_W(&_TspCtrl[0].Hw_Config4,
3267 RESET_FLAG1(_HAL_REG32_R(&_TspCtrl[0].Hw_Config4), TSP_HW_BD_AUDIO_EN));
3268 }
3269
3270 return TRUE;
3271 }
3272
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)3273 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
3274 {
3275 switch (u32Cmd)
3276 {
3277 default:
3278 return FALSE;
3279 }
3280
3281 return TRUE;
3282 }
3283
HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId)3284 MS_U8 HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId)
3285 {
3286 MS_U32 u32Value = TSP_MCU_CMD_SCMSTS_GET | (MS_U32)(u8FltId & 0xFF);
3287
3288 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32Value);
3289 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3290 return (MS_U8)(_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3291 }
3292
HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId)3293 MS_U8 HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId)
3294 {
3295 MS_U32 u32Value = TSP_MCU_CMD_SCMSTS_GET | (MS_U32)(u8FltId & 0xFF);
3296
3297 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, u32Value);
3298 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3299 return (MS_U8)(_HAL_REG32_R(&_TspCtrl[0].MCU_Data0) >> 8);
3300 }
3301
3302 //-------------------------------------------------------------------------------
3303 // @u16Mode : TSP_DEBUG_MODE_DIS_CONT => discontinuous packet count
3304 // TSP_DEBUG_MODE_DROP_COUNT => drop packet count
3305 // @u16Src : TBD
3306 // @u16Fifo : TBD
3307 //-------------------------------------------------------------------------------
_HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE u16Mode,TSP_DEBUG_SRC TspSrc,TSP_DEBUG_FIFO TspFifo)3308 static MS_U32 _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE u16Mode, TSP_DEBUG_SRC TspSrc, TSP_DEBUG_FIFO TspFifo)
3309 {
3310 REG16* pReg = NULL;
3311 MS_U16 u16Mask = 0;
3312 MS_U16 u16Shft = 0;
3313 MS_U16 u16Cfg = 0;
3314
3315 switch (TspSrc)
3316 {
3317 case TSP_DEBUG_SRC_TS0: // TS0
3318 pReg = &(_TspCtrl2[0].PktCnt_TS0);
3319 break;
3320 case TSP_DEBUG_SRC_TS1: // TS1
3321 pReg = &(_TspCtrl2[0].PktCnt_TS1);
3322 break;
3323 case TSP_DEBUG_SRC_FILE: // FILE
3324 pReg = &(_TspCtrl2[0].PktCnt_File);
3325 break;
3326 default:
3327 return 0;
3328 }
3329
3330 switch (TspFifo)
3331 {
3332 case TSP_DEBUG_FIFO_VIDEO: // VIDEO
3333 u16Mask = DISCONTI_CNT_VIDEO_MASK;
3334 u16Shft = DISCONTI_CNT_VIDEO_SHFT;
3335 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2; // discontinuous packet count : drop packet count
3336 break;
3337 case TSP_DEBUG_FIFO_AUDIO: // AUDIO
3338 u16Mask = DISCONTI_CNT_AUDIO_MASK;
3339 u16Shft = DISCONTI_CNT_AUDIO_SHFT;
3340 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2;
3341 break;
3342 case TSP_DEBUG_FIFO_VIDEO3D: // VIDEO3D
3343 u16Mask = DISCONTI_CNT_V3D_MASK;
3344 u16Shft = DISCONTI_CNT_V3D_SHFT;
3345 u16Cfg = (u16Mode == TSP_DEBUG_MODE_DIS_CONT) ? TSP_HW_CFG_0 : TSP_HW_CFG_2;
3346 break;
3347 default:
3348 return 0;
3349 }
3350
3351 _HAL_REG16_W(&(_TspCtrl2[0].HwCfg1),
3352 (_HAL_REG16_R(&(_TspCtrl2[0].HwCfg1)) & ~HW_INFO_SRC_MODE_MASK) | u16Cfg);
3353
3354 return (MS_U32)(_HAL_REG16_R(pReg) & u16Mask) >> u16Shft;
3355 }
3356
3357 //-------------------------------------------------------------------------------
3358 // @ u16Src : TBD
3359 // @ u16Fifo : TBD
3360 // @ return value : 0 ~ 15
3361 //-------------------------------------------------------------------------------
HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info * TspDisconPktCntInfo)3362 MS_U32 HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info* TspDisconPktCntInfo)
3363 {
3364 if(TspDisconPktCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3365 {
3366 // Set the clear source
3367 if(TspDisconPktCntInfo->TspSrc == TSP_DEBUG_SRC_TS0)
3368 {
3369 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3370 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_0<<TSP_CLR_SRC_SHIFT));
3371 }
3372 else if(TspDisconPktCntInfo->TspSrc == TSP_DEBUG_SRC_FILE)
3373 {
3374 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3375 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_FILE<<TSP_CLR_SRC_SHIFT));
3376 }
3377
3378 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3379 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) | (TSP_DISCONTI_VD_CLR | TSP_DISCONTI_V3D_CLR | TSP_DISCONTI_AUD_CLR));
3380 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3381 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~(TSP_DISCONTI_VD_CLR | TSP_DISCONTI_V3D_CLR | TSP_DISCONTI_AUD_CLR));
3382 }
3383 return _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE_DIS_CONT, TspDisconPktCntInfo->TspSrc, TspDisconPktCntInfo->TspFifo);
3384 }
3385
3386 //-------------------------------------------------------------------------------
3387 // @ u16Src : TBD
3388 // @ u16Fifo : TBD
3389 // @ return value : 0 ~ 15
3390 //-------------------------------------------------------------------------------
HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info * TspDropCntInfo)3391 MS_U32 HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info* TspDropCntInfo)
3392 {
3393 if(TspDropCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3394 {
3395 // Set the clear source
3396 if(TspDropCntInfo->TspSrc == TSP_DEBUG_SRC_TS0)
3397 {
3398 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3399 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_0<<TSP_CLR_SRC_SHIFT));
3400 }
3401 else if(TspDropCntInfo->TspSrc == TSP_DEBUG_SRC_FILE)
3402 {
3403 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3404 (_HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~TSP_CLR_SRC_MASK) | (TSP_CLR_SRC_PIDFLT_FILE<<TSP_CLR_SRC_SHIFT));
3405 }
3406
3407 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3408 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) | (TSP_DUP_PKT_CNT_CLR));
3409 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl1),
3410 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl1)) & ~(TSP_DUP_PKT_CNT_CLR));
3411 }
3412 return _HAL_TSP_Get_PktCnt(TSP_DEBUG_MODE_DROP_CONT, TspDropCntInfo->TspSrc, TspDropCntInfo->TspFifo);
3413 }
3414
3415 //-------------------------------------------------------------------------------
3416 // @u16Tsif : TBD
3417 // @ return value : 0 ~ 15
3418 //-------------------------------------------------------------------------------
HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info * TspLockCntInfo)3419 MS_U32 HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info* TspLockCntInfo)
3420 {
3421 if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3422 {
3423 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3424 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_CLR_LOCKED_PKT_CNT));
3425 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3426 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_CLR_LOCKED_PKT_CNT));
3427 }
3428 else if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_ENABLE)
3429 {
3430 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3431 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_DIS_LOCKED_PKT_CNT));
3432 }
3433 else if(TspLockCntInfo->TspCmd == TSP_DEBUG_CMD_DISABLE)
3434 {
3435 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3436 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_DIS_LOCKED_PKT_CNT));
3437 }
3438
3439 switch (TspLockCntInfo->TspTsif)
3440 {
3441 case TSP_DEBUG_TSIF0: // TS0
3442 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].LockPktCnt)) & TS0_LOCK_CNT_MASK) >> TS0_LOCK_CNT_SHFT;
3443 case TSP_DEBUG_TSIF1: // TS1
3444 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].LockPktCnt)) & TS1_LOCK_CNT_MASK) >> TS1_LOCK_CNT_SHFT;
3445 default:
3446 return 0;
3447 }
3448 }
3449
3450 //-------------------------------------------------------------------------------
3451 // @ u16Fifo : TBD
3452 // @ return value : 0 ~ 15
3453 //-------------------------------------------------------------------------------
HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info * TspAVCntInfo)3454 MS_U32 HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info* TspAVCntInfo)
3455 {
3456 if(TspAVCntInfo->TspCmd == TSP_DEBUG_CMD_CLEAR)
3457 {
3458 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3459 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) | (TSP_CLR_AV_PKT_CNT));
3460 _HAL_REG32_W(&(_TspCtrl[0].DbgInfo_Ctrl),
3461 _HAL_REG32_R(&(_TspCtrl[0].DbgInfo_Ctrl)) & ~(TSP_CLR_AV_PKT_CNT));
3462 }
3463
3464 switch (TspAVCntInfo->TspFifo)
3465 {
3466 case TSP_DEBUG_FIFO_VIDEO: // VIDEO
3467 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].AVPktCnt)) & VIDEO_PKT_CNT_MASK) >> VIDEO_PKT_CNT_SHFT;
3468 case TSP_DEBUG_FIFO_AUDIO: // AUDIO
3469 return (MS_U32)(_HAL_REG16_R(&(_TspCtrl2[0].AVPktCnt)) & AUDIO_PKT_CNT_MASK) >> AUDIO_PKT_CNT_SHFT;
3470 default:
3471 return 0;
3472 }
3473 }
3474
3475
HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc)3476 MS_U32 HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc)
3477 {
3478 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_TEI_COUNT_GET | u32PktSrc);
3479 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3480 return (_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3481 }
3482
HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc)3483 MS_BOOL HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc)
3484 {
3485 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_TEI_COUNT_GET | TSP_MCU_CMD_TEI_COUNT_OPTION_RESET | u32PktSrc);
3486 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3487 return TRUE;
3488 }
3489
HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId)3490 MS_U32 HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId)
3491 {
3492 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DISCONT_COUNT_GET | u32FltId);
3493 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3494 return (_HAL_REG32_R(&_TspCtrl[0].MCU_Data0));
3495 }
3496
HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId)3497 MS_BOOL HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId)
3498 {
3499 _HAL_REG32_W(&_TspCtrl[0].MCU_Cmd, TSP_MCU_CMD_DISCONT_COUNT_GET | TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET | u32FltId);
3500 while (0 != _HAL_REG32_R(&_TspCtrl[0].MCU_Cmd));
3501 return TRUE;
3502 }
3503
HAL_TSP_SetPacketMode(MS_U32 u32TSIf,MS_U32 u32PktMode)3504 MS_BOOL HAL_TSP_SetPacketMode(MS_U32 u32TSIf, MS_U32 u32PktMode)
3505 {
3506 return FALSE;
3507 }
3508
HAL_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID,MS_U8 u8SyncByte)3509 MS_BOOL HAL_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID, MS_U8 u8SyncByte)
3510 {
3511 return FALSE;
3512 }
3513
HAL_TSP_MOBF_Set_PVRKey_EX(MS_U32 u32PvrEng,MS_U32 u32Key0,MS_U32 u32Key1)3514 void HAL_TSP_MOBF_Set_PVRKey_EX(MS_U32 u32PvrEng, MS_U32 u32Key0, MS_U32 u32Key1)
3515 {
3516 return;
3517 }
3518
3519