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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // file halTSP.h 97 // @brief Transport Stream Processer (TSP) HAL 98 // @author MStar Semiconductor,Inc. 99 //////////////////////////////////////////////////////////////////////////////////////////////////// 100 #ifndef __HAL_TSP_H__ 101 #define __HAL_TSP_H__ 102 103 #include "MsCommon.h" 104 105 #include "regTSP.h" 106 107 //-------------------------------------------------------------------------------------------------- 108 // Driver Compiler Option 109 //-------------------------------------------------------------------------------------------------- 110 #define TSP_HWPCR_BY_HK 0 //Tuning STC by driver side 111 #define TSP_AUDIO3_AUDIO4_SUPPORT 1 //Support AUDIO3 & AUDIO4 FIFO 112 //-------------------------------------------------------------------------------------------------- 113 // TSP Hardware Abstraction Layer 114 //-------------------------------------------------------------------------------------------------- 115 // TSP Register 116 #define _TspPid ((REG_Pid*)(REG_PIDFLT_L_BASE)) 117 #define _TspPid_H ((REG_Pid*)(REG_PIDFLT_H_BASE)) 118 119 #define _TspSec1 ((REG_Sec*)(REG_SECFLT_BASE1)) 120 121 #define TSP_HW_CFG_0 0x00 122 #define TSP_HW_CFG_1 0x01 123 #define TSP_HW_CFG_2 0x10 124 #define TSP_HW_CFG_3 0x11 125 126 /// TSP debug mode type 127 typedef enum 128 { 129 TSP_DEBUG_MODE_DIS_CONT, ///< Select dis-continue packet count mode 130 TSP_DEBUG_MODE_DROP_CONT, ///< Select drop packet count mode 131 } TSP_DEBUG_MODE; 132 133 typedef enum 134 { 135 TSP_DEBUG_SRC_TS0, ///< TSP input from TS0 interface 136 TSP_DEBUG_SRC_TS1, ///< TSP input from TS1 interface 137 TSP_DEBUG_SRC_TS2, ///< TSP input from TS2 interface 138 TSP_DEBUG_SRC_FILE, ///< TSP input from filein 139 } TSP_DEBUG_SRC; 140 141 typedef enum 142 { 143 TSP_DEBUG_FIFO_VIDEO, ///< TSP output to Video FIFO 144 TSP_DEBUG_FIFO_AUDIO, ///< TSP output to Audio FIFO 145 TSP_DEBUG_FIFO_VIDEO3D, ///< TSP output to Video3D FIFO 146 TSP_DEBUG_FIFO_AUDIOB, ///< TSP output to AudioB FIFO 147 } TSP_DEBUG_FIFO; 148 149 typedef enum 150 { 151 TSP_DEBUG_PKT_DEMUX_0, 152 TSP_DEBUG_PKT_DEMUX_0_FILE, 153 TSP_DEBUG_PKT_DEMUX_1, 154 TSP_DEBUG_PKT_DEMUX_2, 155 TSP_DEBUG_MMFI0, 156 TSP_DEBUG_MMFI1, 157 } TSP_DEBUG_FIFO_SRC; 158 159 typedef enum 160 { 161 TSP_DEBUG_TSIF0, ///< TSP output to Video FIFO 162 TSP_DEBUG_TSIF1, ///< TSP output to Audio FIFO 163 TSP_DEBUG_TSIF2, 164 TSP_DEBUG_TSIFFI, 165 } TSP_DEBUG_TSIF; 166 167 typedef enum 168 { 169 TSP_DEBUG_CMD_NONE, ///< TSP debug table cmd: do nothing 170 TSP_DEBUG_CMD_CLEAR, ///< TSP debug table cmd: clear 171 TSP_DEBUG_CMD_ENABLE, ///< TSP debug table cmd: enable 172 TSP_DEBUG_CMD_DISABLE, ///< TSP debug table cmd: disable 173 } TSP_DEBUG_CMD; 174 175 typedef enum 176 { 177 TSP_CLR_SRC_PIDFLT_0 = 0x1, ///< TSP debug table clear source: pidflt 0 178 TSP_CLR_SRC_PIDFLT_FILE = 0x2, ///< TSP debug table clear source: pidflt file 179 } TSP_DEBUG_CLR_SRC; 180 181 //---------------------------------- 182 /// DMX debug table information structure 183 //---------------------------------- 184 typedef struct 185 { 186 TSP_DEBUG_CMD TspCmd; 187 TSP_DEBUG_SRC TspSrc; 188 TSP_DEBUG_FIFO TspFifo; 189 } TSP_DisconPktCnt_Info, TSP_DropPktCnt_Info; 190 191 typedef struct 192 { 193 TSP_DEBUG_CMD TspCmd; 194 TSP_DEBUG_TSIF TspTsif; 195 } TSP_LockPktCnt_info; 196 197 typedef struct 198 { 199 TSP_DEBUG_CMD TspCmd; 200 TSP_DEBUG_FIFO TspFifo; 201 TSP_DEBUG_FIFO_SRC TspFifoSrc; 202 } TSP_AVPktCnt_info; 203 204 //-------------------------------------------------------------------------------------------------- 205 // Macro of bit operations 206 //-------------------------------------------------------------------------------------------------- 207 #define HAS_FLAG(flag, bit) ((flag) & (bit)) 208 #define SET_FLAG(flag, bit) ((flag)|= (bit)) 209 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 210 #define SET_FLAG1(flag, bit) ((flag)| (bit)) 211 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 212 213 // define NULL function 214 #define HAL_TSP_SecFlt_SelSecBuf(u32EngId, u32SecFltId, u32BufId, bEnable) 215 #define HAL_TSP_SecFlt_SetEcmIdx(u32EngId, u32SecFltId, u32EcmIdx) 216 #define HAL_TSP_SecFlt_ResetEmmIdx(u32EngId, u32SecFltId) 217 #define HAL_TSP_SelAudOut(u32EngId) 218 219 //AV FIFO Enum 220 #define TSP_FIFO_AU 0 221 #define TSP_FIFO_AUB 1 222 #define TSP_FIFO_V3D 2 223 #define TSP_FIFO_VD 3 224 #define TSP_FIFO_AUC 4 225 #define TSP_FIFO_AUD 5 226 227 //TSP IF Source Enum 228 #define TSP_SRC_FROM_TSIF0_LIVE 0x00000001 229 #define TSP_SRC_FROM_TSIF0_FILE 0x00000002 230 #define TSP_SRC_FROM_TSIF1 0x00000003 231 #define TSP_SRC_FROM_TSIF2 0x00000004 232 #define TSP_SRC_FROM_MMFI0 0x00000006 233 #define TSP_SRC_FROM_MMFI1 0x00000007 234 235 //TSP Packet Demux Enum 236 #define TSP_PKTDMX_NONE 0x00000000 237 #define TSP_PKTDMX0_LIVE 0x00000002 238 #define TSP_PKTDMX0_FILE 0x00000004 239 #define TSP_PKTDMX1 0x00000008 240 #define TSP_PKTDMX2 0x00000010 241 242 243 //////////////////////////////////////////////// 244 // HAL API 245 //////////////////////////////////////////////// 246 247 //enum of Capcbility item 248 #define HAL_TSP_CAP_PID_FILTER_NUM 0x00000000 249 #define HAL_TSP_CAP_SEC_FILTER_NUM 0x00000001 250 #define HAL_TSP_CAP_SEC_BUF_NUM 0x00000002 251 #define HAL_TSP_CAP_PVR_ENG_NUM 0x00000003 252 #define HAL_TSP_CAP_PVR_FILTER_NUM 0x00000004 253 #define HAL_TSP_CAP_PVR1_FILTER_NUM 0x00000005 254 #define HAL_TSP_CAP_MMFI0_FILTER_NUM 0x00000006 255 #define HAL_TSP_CAP_MMFI1_FILTER_NUM 0x00000007 256 #define HAL_TSP_CAP_TSIF_NUM 0x00000008 257 #define HAL_TSP_CAP_DEMOD_NUM 0x00000009 258 #define HAL_TSP_CAP_TS_PAD_NUM 0x0000000a 259 #define HAL_TSP_CAP_VQ_NUM 0x0000000b 260 #define HAL_TSP_CAP_CA_FLT_NUM 0x0000000c 261 #define HAL_TSP_CAP_CA_KEY_NUM 0x0000000d 262 #define HAL_TSP_CAP_FW_ALIGN 0x0000000e 263 #define HAL_TSP_CAP_VQ_ALIGN 0x0000000f 264 #define HAL_TSP_CAP_VQ_PITCH 0x00000010 265 #define HAL_TSP_CAP_SEC_BUF_ALIGN 0x00000011 266 #define HAL_TSP_CAP_PVR_ALIGN 0x00000012 267 #define HAL_TSP_CAP_PVRCA_PATH_NUM 0x00000013 268 #define HAL_TSP_CAP_SHAREKEY_FLT_RANGE 0x00000014 269 #define HAL_TSP_CAP_CA0_FLT_RANGE 0x00000015 270 #define HAL_TSP_CAP_CA1_FLT_RANGE 0x00000016 271 #define HAL_TSP_CAP_CA2_FLT_RANGE 0x00000017 272 #define HAL_TSP_CAP_SHAREKEY_FLT1_RANGE 0x00000018 273 #define HAL_TSP_CAP_SHAREKEY_FLT2_RANGE 0x00000019 274 #define HAL_TSP_CAP_HW_TYPE 0x0000001a 275 #define HAL_TSP_CAP_VFIFO_NUM 0x0000001c 276 #define HAL_TSP_CAP_AFIFO_NUM 0x0000001d 277 #define HAL_TSP_CAP_HWPCR_SUPPORT 0x0000001e 278 #define HAL_TSP_CAP_PCRFLT_START_IDX 0x0000001f 279 #define HAL_TSP_CAP_HWWP_SET_NUM 0x00000020 280 #define HAL_TSP_CAP_DSCMB_ENG_NUM 0x00000021 281 #define HAL_TSP_CAP_MERGESTR_NUM 0x00000022 282 #define HAL_TSP_CAP_MAX_SEC_FLT_DEPTH 0x00000023 283 #define HAL_TSP_CAP_FW_BUF_SIZE 0x00000024 284 #define HAL_TSP_CAP_FW_BUF_RANGE 0x00000025 285 #define HAL_TSP_CAP_VQ_BUF_RANGE 0x00000026 286 #define HAL_TSP_CAP_SEC_BUF_RANGE 0x00000027 287 #define HAL_TSP_CAP_FIQ_NUM 0x00000028 288 289 290 //STC update Control Parameters define 291 #define HAL_TSP_STC_UPDATE_FW 0x00 292 #define HAL_TSP_STC_UPDATE_HK 0x01 293 #define HAL_TSP_STC_UPDATE_UPDATEONCE 0x02 294 295 //S2P Clock Option 296 #define HAL_S2P_CLK_OPT_NONE 0x00000000 297 #define HAL_S2P_CLK_OPT_INVERT 0x00000001 298 #define HAL_S2P_CLK_OPT_NON_INVERT 0x00000002 299 300 //[LEGACY] //[OBSOLETE] 301 extern MS_BOOL _bIsHK; 302 //[LEGACY] //[OBSOLETE] 303 304 MS_BOOL HAL_TSP_GetCap(MS_U32 u32Cap, void* pData); 305 MS_BOOL HAL_TSP_Alive(void); 306 void HAL_TSP_HW_Lock_Init(void); 307 void HAL_TSP_HW_Lock_Release(void); 308 void HAL_TSP_SetPKTSize(MS_U32 u32PKTSize); 309 void HAL_TSP_SetOwner(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_BOOL bOwner); 310 MS_BOOL HAL_TSP_TTX_IsAccess(MS_U32 u32Try); 311 void HAL_TSP_TTX_UnlockAccess(void); 312 313 void HAL_ResetAll(void); 314 void HAL_TSP_PowerCtrl(MS_BOOL bOn); 315 void HAL_TSP_SaveFltState(void); 316 void HAL_TSP_RestoreFltState(void); 317 void HAL_TSP_Enable_ValidSync_Dectect(void); 318 void HAL_Reset_WB(void); 319 MS_BOOL HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_U32* pu32StartAddr, MS_U32* pu32EndAddr); 320 void HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_U32 u32StartAddr, MS_U32 u32EndAddr); 321 322 void HAL_TSP_ORAcess_Optimize(MS_BOOL bEnable); 323 void HAL_TSP_Reset(MS_U32 u32EngId); 324 void HAL_TSP_SetBank(MS_U32 u32BankAddr, MS_U32 u32PMBankAddr); 325 void HAL_TSP_WbDmaEnable(MS_BOOL bEnable); 326 void HAL_TSP_HwPatch(void); 327 void HAL_TSP_CPU_SetBase(MS_U32 u32Addr, MS_U32 u32Size); 328 void HAL_TSP_SetCtrlMode(MS_U32 u32EngId, MS_U32 u32Mode, MS_U32 u32TsIfId); 329 MS_U32 HAL_TSP_GetCtrlMode(MS_U32 u32EngId); 330 331 void HAL_TSP_Ind_Enable(void); 332 MS_U32 HAL_TSP_Scmb_Status(MS_U32 u32TSSrc, MS_U32 u32GroupId, MS_U32 u32PidFltId); 333 334 void HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable); 335 void HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId, MS_BOOL bEnable); 336 void HAL_TSP_TEI_RemoveErrorPkt(MS_U32 u32PktType, MS_BOOL bEnable); 337 MS_BOOL HAL_TSP_DupPktCnt_Clear(void); 338 MS_BOOL HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable); 339 340 void HAL_TSP_Int_ClearSw(void); 341 void HAL_TSP_Int_ClearHw(MS_U32 u32Mask); 342 void HAL_TSP_Int_ClearHw2(MS_U32 u32Mask); 343 void HAL_TSP_Int_Enable(MS_U32 u32Mask); 344 void HAL_TSP_Int_Disable(MS_U32 u32Mask); 345 void HAL_TSP_Int2_Enable(MS_U32 u32Mask); 346 void HAL_TSP_Int2_Disable(MS_U32 u32Mask); 347 MS_U32 HAL_TSP_HW_INT_STATUS(void); 348 MS_U32 HAL_TSP_HW_INT2_STATUS(void); 349 MS_U32 HAL_TSP_SW_INT_STATUS(void); 350 351 MS_BOOL HAL_TSP_TsOutPadCfg(MS_U32 u32OutPad, MS_U32 u32OutPadMode, MS_U32 u32InPad, MS_BOOL bInParallel); 352 void HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 u32Flow, MS_U32 u32Pad, MS_BOOL bParl); 353 void HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bClkInv); 354 void HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId, MS_BOOL bExtSync, MS_U32 u32Flow); 355 void HAL_TSP_SelPad_Parl(MS_U32 u32EngId, MS_BOOL bParl, MS_U32 u32Flow); 356 MS_BOOL HAL_TSP_TsOuOutClockPhase(MS_U16 u16OutPad, MS_U16 u16Val, MS_BOOL bEnable, MS_U32 u32S2pOpt); 357 void HAL_TSP_TSOut_En(MS_BOOL bEnable); 358 MS_BOOL HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId, MS_U16* pu16Pad, MS_U16* pu16Clk, MS_BOOL* pbExtSync, MS_BOOL* pbParl); 359 void HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bInvert); 360 void HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId, MS_BOOL bFlush); 361 MS_U32 HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId); 362 void HAL_TSP_AVFIFO_Src_Select(MS_U32 u32Fifo, MS_U32 u32Src); 363 void HAL_TSP_AVFIFO_Block_Disable(MS_U32 u32Fifo, MS_BOOL bDisable); 364 MS_BOOL HAL_TSP_TSIF_Enable(MS_U8 u8_tsif, MS_BOOL bEnable); 365 void HAL_TSP_SelMatchPidSrc(MS_U32 u32Src); 366 MS_BOOL HAL_TSP_PidFlt_Src_Select(MS_U32 u32Src); 367 368 369 void HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId, MS_U32 u32STC); 370 void HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32); 371 MS_U32 HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId); 372 MS_U32 HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId); 373 MS_U32 HAL_TSP_CmdQ_CmdCount(void); 374 MS_BOOL HAL_TSP_CmdQ_Reset(void); 375 void HAL_TSP_CmdQ_TsDma_SetAddr(MS_U32 u32StreamAddr); 376 MS_BOOL HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize); 377 void HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl); 378 MS_U32 HAL_TSP_CmdQ_TsDma_GetState(void); 379 MS_U32 HAL_TSP_CmdQ_EmptyCount(void); 380 void HAL_TSP_CmdQ_TsDma_Reset(void); 381 MS_BOOL HAL_TSP_CmdQ_IsEmpty(void); 382 void HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay); 383 void HAL_TSP_TsDma_Pause(void); 384 void HAL_TSP_TsDma_Resume(void); 385 MS_U8 HAL_TSP_Get_CmdQFifoLevel(void); 386 387 void HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable); 388 void HAL_TSP_filein_enable(MS_BOOL b_enable); 389 void HAL_TSP_FileIn_Set(MS_BOOL bset); 390 void HAL_TSP_ResetTimeStamp(void); 391 MS_U32 HAL_TSP_GetPlayBackTimeStamp(void); 392 void HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp); 393 void HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id, MS_U32 u32ClkSrc); 394 MS_U32 HAL_TSP_GetFileInTimeStamp(void); 395 MS_BOOL HAL_TSP_GetFilinReadAddr(MS_PHYADDR* pu32ReadAddr); 396 void HAL_TSP_SetDMABurstLen(MS_U32 u32Len); 397 398 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); //T12 new 399 void HAL_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC, MS_U32 u32STC_32); 400 void HAL_TSP_Stc_ctrl(MS_U32 u32EngId, MS_U32 u32Sync); 401 MS_U32 HAL_TSP_GetSTCSynth(MS_U32 u32EngId); 402 //void HAL_TSP_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32); 403 void HAL_TSP_STC_Update_Disable(MS_U32 u32EngId, MS_BOOL bDisable); 404 MS_U32 HAL_TSP_GetSTC(MS_U32 u32EngId); 405 MS_U32 HAL_TSP_GetSTC_32(MS_U32 u32EngId); 406 MS_BOOL HAL_TSP_SelectSTCEng(MS_U32 u32FltSrc, MS_U32 u32Eng); 407 MS_BOOL HAL_TSP_GetPcr(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr); 408 MS_BOOL HAL_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd); 409 MS_BOOL HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId); 410 void HAL_TSP_HWPcr_SetSrcId(MS_U32 u32EngId, MS_U32 u32SrcId); 411 void HAL_TSP_HWPcr_SelSrc(MS_U32 u32EngId, MS_U32 u32Src); 412 void HAL_TSP_HWPcr_Reset(MS_U32 u32EngId, MS_BOOL bReset); 413 void HAL_TSP_HWPcr_Int_Enable(MS_U32 u32EngId, MS_BOOL bEnable); 414 void HAL_TSP_HWPcr_Read(MS_U32 u32EngId, MS_U32 *pu32Pcr, MS_U32 *pu32Pcr_32); 415 416 //MS_U32 HAL_TSP_PidFltId(MS_U32 u32PidType); 417 void HAL_TSP_PidFlt_SetPid(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32PID); 418 void HAL_TSP_PidFlt_SelFltOutput(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32FltOutput); 419 void HAL_TSP_PidFlt_SelSecFlt(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32SecFltId); 420 MS_U32 HAL_TSP_PidFlt_GetSecFlt(MS_U32 u32EngId, MS_U32 u32PidFltId); 421 MS_U32 HAL_TSP_PidFlt_GetPid(MS_U32 u32EngId, MS_U32 u32PidFltId); 422 MS_U32 HAL_TSP_PidFlt_GetFltOutput(MS_U32 u32EngId, MS_U32 u32PidFltId); 423 void HAL_TSP_PidFlt_SelFltSource(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32FltSource); 424 void HAL_TSP_PidFlt_SetFltSrcStreamID(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32SrcStrId); 425 426 void HAL_TSP_PidFlt_SetHWPcrPid(MS_U32 u32EngId, MS_U32 u32PID); 427 MS_U32 HAL_TSP_PidFlt_GetHWPcrPid(MS_U32 u32EngId); 428 void HAL_TSP_PidFlt_HWPcrFlt_Enable(MS_U32 u32EngId, MS_BOOL bEnable); 429 430 void HAL_TSP_SecBuf_ResetBuffer(MS_U32 u32EngId, MS_U32 u32SecBufId); 431 void HAL_TSP_SecFlt_ResetState(MS_U32 u32EngId, MS_U32 u32SecFltId); 432 void HAL_TSP_SecFlt_SetType(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32FltType); 433 void HAL_TSP_SecFlt_SetRmnCount(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32RmnCount); 434 void HAL_TSP_SecFlt_ClrCtrl(MS_U32 u32EngId, MS_U32 u32SecFltId); 435 void HAL_TSP_SecFlt_SetMask(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8Mask); 436 void HAL_TSP_SecFlt_SetNMask(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8NMask); 437 void HAL_TSP_SecFlt_SetMatch(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8Match); 438 void HAL_TSP_SecFlt_SetReqCount(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32ReqCount); 439 MS_U32 HAL_TSP_SecFlt_GetMode(MS_U32 u32EngId, MS_U32 u32SecFltId); 440 void HAL_TSP_SecFlt_PcrReset(MS_U32 u32EngId, MS_U32 u32SecFltId); 441 void HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId); 442 void HAL_TSP_SecFlt_SetDataAddr(MS_U32 u32DataAddr); 443 444 MS_U32 HAL_TSP_SecBuf_GetBufRead(MS_U32 u32EngId, MS_U32 u32SecBufId); 445 MS_U32 HAL_TSP_SecBuf_GetBufWrite(MS_U32 u32EngId, MS_U32 u32SecBufId); 446 void HAL_TSP_SecBuf_SetBuffer(MS_U32 u32EngId, MS_U32 u32SecBufId, MS_U32 u32StartAddr, MS_U32 u32BufSize); 447 void HAL_TSP_SecBuf_SetBufRead(MS_U32 u32EngId, MS_U32 u32SecBufId, MS_U32 u32ReadAddr); 448 MS_U32 HAL_TSP_SecBuf_GetBufStart(MS_U32 u32EngId, MS_U32 u32SecBufId); 449 MS_U32 HAL_TSP_SecBuf_GetBufEnd(MS_U32 u32EngId, MS_U32 u32SecBufId); 450 MS_U32 HAL_TSP_SecBuf_GetBufCur(MS_U32 u32EngId, MS_U32 u32SecBufId); 451 void HAL_TSP_SecFlt_SetMode(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32SecFltMode); 452 MS_U32 HAL_TSP_SecFlt_GetCRC32(MS_U32 u32EngId, MS_U32 u32SecFltId); 453 MS_U32 HAL_TSP_SecFlt_GetState(MS_U32 u32EngId, MS_U32 u32SecFltId); 454 void HAL_TSP_SecBuf_SetBufRead_tmp(MS_U32 u32EngId, MS_U32 u32SecBufId, MS_U32 u32ReadAddr); 455 MS_U32 HAL_TSP_SecBuf_GetBufWrite_tmp(MS_U32 u32EngId, MS_U32 u32SecBufId); 456 457 void HAL_TSP_PVR_SetBuffer(MS_U8 u8PVRId, MS_U32 u32BufStart0, MS_U32 u32BufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1); 458 void HAL_TSP_PVR_Enable(MS_U8 u8PVRId, MS_BOOL bEnable); 459 void HAL_TSP_PVR_Reset(MS_U8 u8PVRId); 460 void HAL_TSP_PVR_All(MS_U8 u8PVRId, MS_BOOL bPvrAll, MS_BOOL bWithNull, MS_BOOL bOldMode); 461 MS_U32 HAL_TSP_PVR_GetBufWrite(MS_U8 u8PVRId); 462 void HAL_TSP_PVR_WaitFlush(MS_U8 u8PVRId); 463 void HAL_TSP_PVR_BypassHeader_En(MS_U8 u8PVRId, MS_BOOL bBypassHD); 464 void HAL_TSP_PVR_Src_Select(MS_U8 u8PVRId, MS_U32 u32Src); 465 MS_U32 HAL_TSP_PVR_StartingEngs_Get(MS_U32 u32PktDmxSrc); 466 MS_BOOL HAL_TSP_PVR_IsEnabled(MS_U32 u32EngId); 467 MS_BOOL HAL_TSP_PVR_Alignment_Enable(MS_U8 u8PVRId, MS_BOOL bEnable); 468 MS_BOOL HAL_TSP_PVR_ForceSync_Enable(MS_U8 u8PVRId, MS_BOOL bEnable); 469 void HAL_TSP_PVR_PacketMode(MS_U8 u8PVRId, MS_BOOL bSet); 470 MS_BOOL HAL_TSP_PVR_Fifo_Block_Disable(MS_U8 u8PVRId, MS_BOOL bDisable); 471 MS_U32 HAL_TSP_GetPVRTimeStamp(MS_U8 u8PVRId); 472 void HAL_TSP_SetPVRTimeStamp(MS_U8 u8PVRId, MS_U32 u32Stamp); 473 void HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId, MS_U32 u32ClkSrc); 474 475 MS_BOOL HAL_TSP_Read_DropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt); 476 void HAL_TSP_TSIF0_Enable(MS_BOOL bEnable); 477 void HAL_TSP_TSIF1_Enable(MS_BOOL bEnable); 478 void HAL_TSP_TSIFFI_SrcSelect(MS_BOOL bFileMode); 479 480 MS_U32 HAL_REG32_IndR(REG32 *reg); 481 void HAL_REG32_IndW(REG32 *reg, MS_U32 value); 482 483 // void HAL_TSP_SetFwMsg(MS_U32 u32Mode); 484 // MS_U32 HAL_TSP_GetFwMsg(void); 485 void HAL_TSP_ISR_SAVE_ALL(void); 486 void HAL_TSP_ISR_RESTORE_ALL(void); 487 void HAL_TSP_PS_Path_Disable(void); 488 void HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl); 489 void HAL_TSP_CSA_Set_ScrmPath(MS_U8 u8EngId, MS_U32 u32ScrmPath); 490 MS_U32 HAL_TSP_CSA_Get_ScrmPath(MS_U8 u8EngId); 491 MS_BOOL HAL_TSP_CSA_Set_CACtrl(MS_U8 u8EngId, MS_U8 u8SrcTSIF, MS_U32 u32Dst); 492 MS_BOOL HAL_TSP_CSA_Get_CACtrl(MS_U8 u8EngId, MS_U8* pu8SrcTSIF, MS_U32* pu32Dst); 493 494 MS_U32 HAL_TSP_Get_FW_VER(void); 495 MS_BOOL HAL_TSP_Check_FW_VER(void); 496 MS_BOOL HAL_TSP_SetFwDbgMem(MS_PHYADDR phyAddr, MS_U32 u32Size); 497 MS_BOOL HAL_TSP_SetFwDbgWord(MS_U32 u32Word); 498 MS_U32 HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel); 499 MS_U8 HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId); 500 MS_U8 HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId); 501 502 //------- VQ Funcions ----------------------------------------------------------- 503 void HAL_TSP_SetVQBuffer(MS_U8 u8VQId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 504 void HAL_TSP_VQueue_Enable(MS_BOOL bEnable); 505 void HAL_TSP_VQueue_Reset(MS_U8 u8VQId); 506 void HAL_TSP_VQueue_OverflowInt_En(MS_U8 u8VQId, MS_BOOL bEnable); 507 void HAL_TSP_VQueue_Clr_OverflowInt(MS_U8 u8VQId); 508 void HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len); 509 MS_U32 HAL_TSP_Get_VQStatus(void); 510 void HAL_TSP_VQBlock_Disable(MS_U8 u8VQId, MS_BOOL bDisable); 511 //----------------------------------------------------------------------------- 512 513 //------------------ MOBF Functions --------------- 514 //--- decrypt address must be the same as encrypt address ------ 515 void HAL_TSP_MOBF_Select(MS_U8 u8Model, MS_U8 u8MobfIndex0, MS_U8 u8MobfIndex1); 516 //--------------------------------------------------------- 517 518 // ------------------------------------------------------------- 519 // Common api for mode setting 520 // u32Cmd[31]: 0 -> public cmd, 1 -> private cmd 521 // ------------------------------------------------------------- 522 // HAL_CMD_ONEWAY : Oneway record enable, 1-> Rec scrmable stream disable, 2 -> PVR oneway, 4 -> LoadFW oneway 523 // ------------------------------------------------------------- 524 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 525 #define HAL_CMD_ONEWAY 0x80000001 //u32Config0: 1-> Rec SCM stream disable , 2->OnewayPVRPort, 4->OnewayFW; u32Config1,pData: Don't care 526 527 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Opt); 528 529 // ------------------------------------------------------------- 530 // Debug table 531 // ------------------------------------------------------------- 532 MS_U32 HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info* TspDisconPktCntInfo); 533 MS_U32 HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info* TspDropCntInfo); 534 MS_U32 HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info* TspLockCntInfo); 535 MS_U32 HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info* TspAVCntInfo); 536 537 MS_U32 HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc); 538 MS_BOOL HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc); 539 MS_U32 HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId); 540 MS_BOOL HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId); 541 542 // ------------------------------------------------------------- 543 // Merge Stream 544 // ------------------------------------------------------------- 545 MS_BOOL HAL_TSP_Set_Sync_Byte(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SyncByte, MS_BOOL bSet); 546 MS_BOOL HAL_TSP_Set_Src_Id(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SrcId, MS_BOOL bSet); 547 548 // ATS Calibration API 549 MS_BOOL HAL_TSP_Set_ATS_AdjPeriod(MS_U16 u16Value); 550 MS_BOOL HAL_TSP_Set_ATS_AdjEnable(MS_BOOL bEnable); 551 MS_BOOL HAL_TSP_Set_ATS_AdjOffset(MS_BOOL bIncreased, MS_U16 u16Offset); 552 MS_BOOL HAL_TSP_DropScmbPkt(MS_U32 u32StreamId,MS_BOOL bEnable); 553 554 555 556 #endif // #ifndef __HAL_TSP_H__ 557