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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSO_REG_H_ 103 #define _TSO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TSO_ENGINE_NUM (1) 137 #define TSO_PIDFLT_NUM (64) 138 #define TSO_REP_PIDFLT_NUM (16) 139 #define TSO_TSIF_NUM (2) 140 #define TSO_FILE_IF_NUM (1) 141 #define TSO_SVQ_UNIT_SIZE (208) 142 143 #define TSO_PIDFLT_NUM_ALL TSO_PIDFLT_NUM 144 145 #define TSO_PID_NULL 0x1FFF 146 147 #define TSO_MIU_BUS 4 148 149 //------------------------------------------------------------------------------------------------- 150 // Harware Capability 151 //------------------------------------------------------------------------------------------------- 152 153 #define TSO_IN_MUX_TS0 0x0 154 #define TSO_IN_MUX_TS1 0x1 155 #define TSO_IN_MUX_TS2 0x2 156 #define TSO_IN_MUX_TSDEMOD 0x7 157 #define TSO_IN_MUX_MEM 0x8 158 159 #define TSO_CLKIN_TS0 0x00 160 #define TSO_CLKIN_TS1 0x04 161 #define TSO_CLKIN_TS2 0x08 162 #define TSO_CLKIN_DMD 0x1C 163 164 //--------------- u16ClkOutDivSrcSel ------------- 165 #define TSO_OUT_DIV_DMPLLDIV5 0x0000 // dmplldiv5 = 844/5 = 172.8MHz 166 #define TSO_OUT_DIV_DMPLLDIV3 0x0001 // dmplldiv3 = 844/3 = 288MHz 167 168 // Note: 169 // DVB-T dmplldiv5 / 2 (11+1) = 7.2 MHz 170 // DVB-C dmplldiv5 / 2 (11+1) = 7.2 MHz 171 // ATSC dmplldiv5 / 2 (11+1) = 7.2 MHz 172 // ISDB-T dmplldiv_3 / 2 (17+1) = 8 MHz 173 174 //---------------- u16ClkOutSel --------------- 175 #define TSO_OUT_DIV2 0x0000 // Must also select div src and set div num 176 #define TSO_OUT_62MHz 0x0400 177 #define TSO_OUT_54MHz 0x0800 178 #define TSO_OUT_PTSO_OUT 0x0C00 //live-in 179 #define TSO_OUT_PTSO_OUT_DIV8 0x1000 //live-in 180 #define TSO_OUT_27MHz 0x1400 181 #define TSO_OUT_DEMOD_P 0x1C00 //live-in 182 183 //--------------- u16PreTsoOutSel ------------- 184 #define TSO_PRE_OUT_TS0IN 0x0000 185 #define TSO_PRE_OUT_TS1IN 0x0001 186 #define TSO_PRE_OUT_TS2IN 0x0002 187 #define TSO_PRE_OUT_DEMDOIN 0x0003 188 189 //------------------------------------------------------------------------------------------------- 190 // Type and Structure 191 //------------------------------------------------------------------------------------------------- 192 193 #define REG_PIDFLT_BASE (0x00210000 << 1) // Fit the size of REG32 194 195 #define REG_CTRL_BASE_TSO (0x27400) // 0x113A 196 #define REG_CTRL_BASE_TSO1 (0x47A00) // 0x123D 197 198 199 typedef struct _REG32 200 { 201 volatile MS_U16 L; 202 volatile MS_U16 empty_L; 203 volatile MS_U16 H; 204 volatile MS_U16 empty_H; 205 } REG32; 206 207 typedef struct _REG16 208 { 209 volatile MS_U16 data; 210 volatile MS_U16 _resv; 211 } REG16; 212 213 typedef REG32 REG_PidFlt; 214 215 // PID 216 #define TSO_PIDFLT_PID_MASK 0x00001FFF 217 #define TSO_PIDFLT_PID_SHFT 0 218 219 // Channel source 220 #define TSO_PIDFLT_IN_SHIFT 13 221 #define TSO_PIDFLT_IN_MASK 0x0000E000 222 #define TSO_PIDFLT_IN_CH0 0x00002000 223 #define TSO_PIDFLT_IN_CH5 0x0000A000 224 #define TSO_PIDFLT_IN_CH6 0x0000C000 225 226 typedef struct _REG_Pid 227 { // Index(word) CPU(byte) Default 228 REG_PidFlt Flt[TSO_PIDFLT_NUM]; 229 } REG_Pid; 230 231 232 typedef struct _REG_Ctrl_TSO 233 { 234 //---------------------------------------------- 235 // 0xBF802A00 MIPS direct access 236 //---------------------------------------------- 237 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 238 239 REG16 SW_RSTZ; // 0xbf827400 0x00 240 #define TSO_SW_RSTZ_DISABLE 0x0001 241 #define TSO_SW_RSTZ_CLK_STAMP 0x0002 242 #define TSO_SW_RSTZ_WB1 0x0200 243 #define TSO_SW_RSTZ_WB_DMA1 0x0400 244 #define TSO_SW_RSTZ_CMDQ 0x1000 245 #define TSO_SW_RSTZ_WB 0x2000 246 #define TSO_SW_RSTZ_WB_DMA 0x4000 247 #define TSO_SW_RSTZ_TS_FIN 0x8000 248 #define TSO_SW_RSTZ_ALL 0x00FE 249 250 REG16 SW_RSTZ1; // 0xbf827404 0x01 251 #define TSO_SW_RSTZ1_CH_IF1 0x0001 252 #define TSO_SW_RSTZ1_CH_IF5 0x0010 253 #define TSO_SW_RSTZ1_ALL 0x0031 254 255 REG32 _xbf827408_740c; // 0xbf827408~0xbf82740c 0x02~03 256 257 REG16 TSO_CH0_IF1_CFG0; // 0xbf827410 0x04 258 #define TSO_PKT_SIZE_CHK_LIVE_MASK 0x00FF 259 #define TSO_PIDFLT_PKT_SIZE_MASK 0xFF00 260 #define TSO_PIDFLT_PKT_SIZE_SHIFT 8 261 262 REG16 TSO_CH0_IF1_CFG1; // 0xbf827414 0x05 263 REG16 TSO_CH0_IF1_CFG2; // 0xbf827418 0x06 264 #define TSO_CHCFG_P_SEL 0x0001 265 #define TSO_CHCFG_EXT_SYNC_SEL 0x0002 266 #define TSO_CHCFG_TS_SIN_C0 0x0004 267 #define TSO_CHCFG_TS_SIN_C1 0x0008 268 #define TSO_CHCFG_PIDFLT_REC_ALL 0x0010 // bypass all packets 269 #define TSO_CHCFG_PIDFLT_REC_NULL 0x0020 // bypass NULL packets 270 #define TSO_CHCFG_PIDFLT_OVF_INT_EN 0x0040 271 #define TSO_CHCFG_PIDFLT_OVF_CLR 0x0080 272 #define TSO_CHCFG_FORCE_SYNC_BYTE 0x0100 273 #define TSO_CHCFG_SKIP_TEI_PKT 0x0200 274 #define TSO_CHCFG_DIS_LOCKED_PKT_CNT 0x0400 275 #define TSO_CHCFG_CLR_LOCKED_PKT_CNT 0x0800 276 #define TSO_CHCFG_TRC_CLK_LD_DIS 0x1000 277 #define TSO_CHCFG_TRC_CLK_CLR 0x2000 278 REG16 TSO_CH0_IF1_CFG3; // 0xbf82741c 0x07 279 280 REG16 _xbf827420_744c[12]; // 0xbf827420~0xbf82744c 0x08~13 281 282 REG16 TSO_CH0_IF5_CFG0; // 0xbf827450 0x14 283 REG16 TSO_CH0_IF5_CFG1; // 0xbf827454 0x15 284 REG16 TSO_CH0_IF5_CFG2; // 0xbf827458 0x16 285 REG16 TSO_CH0_IF5_CFG3; // 0xbf82745c 0x17 286 287 REG16 _xbf827460_746c[4]; // 0xbf827460~0xbf82746c 0x18~0x1b 288 289 REG16 TSO_CFG0; // 0xbf827470 0x1c //s2p_Cfg 290 REG16 TSO_CFG1; // 0xbf827474 0x1d 291 #define TSO_CFG1_TSO_OUT_EN 0x0001 292 #define TSO_CFG1_TSO_TSIF1_EN 0x0002 293 #define TSO_CFG1_TSO_TSIF5_EN 0x0020 294 #define TSO_CFG1_CLK_TRC_SEL_MASK 0x0E00 295 #define TSO_CFG1_PKT_LOCK_CLR 0x2000 296 #define TSO_CFG1_NULL_EN 0x4000 297 #define TSO_CFG1_PKT_PARAM_LD 0x8000 298 299 REG16 TSO_CFG2; // 0xbf827478 0x1e 300 #define TSO_CFG2_VALID_BYTECNT_MASK 0x00FF 301 #define TSO_CFG2_INVALID_BYTECNT_MASK 0xFF00 302 #define TSO_CFG2_VALID_BYTECNT_SHIFT 0 303 #define TSO_CFG2_INVALID_BYTECNT_SHIFT 8 304 305 REG16 TSO_CFG3; // 0xbf82747c 0x1f 306 307 REG32 REP_PidFlt[16]; // 0xbf827480~0xbf8274F8 0x20~0x3e 308 #define REP_PIDFLT_ORG_PID_MASK 0x00001FFF 309 #define REP_PIDFLT_SRC_MASK 0x0000E000 310 #define REP_PIDFLT_SRC_SHIFT 13 311 #define REP_PIDFLT_SRC_CH1 0x00002000 312 #define REP_PIDFLT_SRC_CH5 0x0000A000 313 #define REP_PIDFLT_SRC_CH6 0x0000C000 314 #define REP_PIDFLT_NEW_PID_MASK 0x01FFF000 315 #define REP_PIDFLT_NEW_PID_SHIFT 16 316 #define REP_PIDFLT_REPLACE_EN 0x80000000 317 318 REG16 TSO_CLR_BYTE_CNT; // 0xbf827500 0x40 319 #define TSO_CLR_BYTE_CNT_1 0x0000 320 #define TSO_CLR_BYTE_CNT_5 0x0004 321 322 REG32 TSO_SYSTIMESTAMP; // 0xbf827504~0xbf827508 0x41~42 323 324 REG16 TSO_CFG4; // 0xbf82750c 0x43 325 #define TSO_CFG4_LOCK_RET_SYS_TIMESTAMP 0x0001 326 #define TSO_CFG4_ENABLE_SYS_TIMESTAMP 0x0002 327 #define TSO_CFG4_SET_SYS_TIMESTAMP 0x0004 328 #define TSO_CFG4_SET_TIMESTAMP_BASE_MASK 0x0008 329 #define TSO_CFG4_SET_TIMESTAMP_90K 0x0000 330 #define TSO_CFG4_SET_TIMESTAMP_27M 0x0008 331 #define TSO_CFG4_PIDTABLE_SRAM_SD_EN 0x0010 332 #define TSO_CFG4_NULL_PKT_ID_MASK 0xF000 333 334 REG16 TSO_CFG5; // 0xbf82750c 0x44 335 #define TSO_CFG5_WIRE_MODE_EN_1 0x0001 336 #define TSO_CFG5_WIRE_MODE_EN_5 0x0010 337 338 REG32 TSO_INDR_ADDR; // 0xbf82750c~0xbf827510 0x45~0x46 339 REG32 TSO_INDR_WDATA; // 0xbf827514~0xbf827518 0x47~0x48 340 REG16 TSO_INDR_RDATA; // 0xbf82751c 0x49 341 REG16 TSO_INDR_CTRL ; // 0xbf827520 0x4a 342 #define TSO_INDIR_W_ENABLE 0x0001 343 #define TSO_INDIR_R_ENABLE 0x0002 344 345 REG16 TSO_STATUS; // 0xbf827524 0x4b 346 347 REG16 TSO_FI_TIMER[1]; // 0xbf827528 0x4c 348 349 REG16 _xbf82752c; // 0xbf82752c 0x4d 350 351 REG16 TSO_STATUS1; // 0xbf827530 0x4e 352 #define TSO_PIDFLT_OVF_EVER_TSIF0 0x0001 353 #define TSO_PIDFLT_OVF_EVER_TSIF5 0x0010 354 355 REG16 _xbf827534_7568[12]; // 0xbf827534~0xbf827568 0x4f~0x5a 356 357 REG16 TSO_TRACE_HIGH; // 0xbf82756c 0x5b 358 REG16 TSO_TRACE_LOW; // 0xbf827570 0x5c 359 REG16 TSO_TRACE_1t; // 0xbf827574 0x5d 360 361 REG16 TSO_BLOCK_SIZE_DB; // 0xbf827578 0x5e 362 REG16 TSO_BLOCK_OPT_DB; // 0xbf82757c 0x5f 363 364 REG32 TSO_Filein_raddr; // 0xbf827580~0xbf827584 0x60-0x61 365 REG32 TSO_Filein_rNum; // 0xbf827588~0xbf82758c 0x62-0x63 366 REG16 TSO_Filein_Ctrl; // 0xbf827590 0x64 367 #define TSO_FILEIN_CTRL_MASK 0x0003 368 #define TSO_FILEIN_RSTART 0x0001 369 #define TSO_FILEIN_ABORT 0x0002 370 #define TSO_FILEIN_MOBF_IDX_MASK 0x1F00 371 #define TSO_FILEIN_MOBF_IDX_SHIFT 8 372 #define TSO_FILEIN_RIU_TSO_NS 0x2000 373 374 REG16 _xbf827594_75a4[5]; // 0xbf827594~0xbf8275a4 0x65-0x69 375 376 REG16 TSO_PKT_CNT_SEL; // 0xbf8275a8 0x6a 377 #define TSO_PKT_CNT_SEL_MASK 0x000F 378 #define TSO_PKT_CNT_LOCKED_CNT_MASK 0x00F0 379 #define TSO_PKT_CNT_DBG_MASK 0xFF00 380 381 REG16 TSO_PKT_CHKSIZE_FI; // 0xbf8275ac 0x6b 382 #define TSO_PKT_CHKSIZE_FI_MASK 0x00FF 383 384 REG32 TSO_LPCR2[1]; // 0xbf8275b0~ 0xbf8275b4 0x6c~0x6d 385 386 REG32 _xbf8275b8_75bc; // 0xbf8275b8~ 0xbf8275bc 0x6e~0x6f 387 388 REG32 TSO_TIMESTAMP[1]; // 0xbf8275c0~ 0xbf8275c4 0x70~0x71 389 390 REG32 _xbf8275c8_75cc; // 0xbf8275c8~ 0xbf8275cc 0x72~0x73 391 392 REG32 TSO_TSO2MI_RADDR[1]; // 0xbf8275d0~ 0xbf8275d4 0x74~0x75 393 394 REG32 _xbf8275d8_75dc; // 0xbf8275d8~ 0xbf8275dc 0x76~0x77 395 396 REG16 TSO_CMDQ_STATUS; // 0xbf8275e0 0x78 397 #define TSO_CMDQ_SIZE 8 398 #define TSO_CMDQ_STS_WCNT_MASK 0x000F 399 #define TSO_CMDQ_STS_WLEVEL_MASK 0x0030 400 #define TSO_CMDQ_STS_FIFO_FULL 0x0040 401 #define TSO_CMDQ_STS_FIFO_EMPTY 0x0080 402 403 REG16 TSO_FILE_CFG[1]; // 0xbf8275e4 0x79 404 #define TSO_FICFG_TSO2MI_RPRI 0x0001 405 #define TSO_FICFG_MEM_TSDATA_ENDIAN 0x0002 406 #define TSO_FICFG_MEM_TS_W_ORDER 0x0004 407 #define TSO_FICFG_LPCR2_WLD 0x0008 408 #define TSO_FICFG_LPCR2_LD 0x0010 409 #define TSO_FICFG_DIS_MIU_RQ 0x0020 410 #define TSO_FICFG_RADDR_READ 0x0040 411 #define TSO_FICFG_TS_DATAPORT_SEL 0x0080 412 #define TSO_FICFG_TSO_FILEIN 0x0100 413 #define TSO_FICFG_TIMER_ENABLE 0x0200 414 #define TSO_FICFG_PKT192_BLK_DISABLE 0x0400 415 #define TSO_FICFG_PKT192_ENABLE 0x0800 416 #define TSO_FICFG_FILE_SEGMENT 0x1000 417 #define TSO_FICFG_CLK_TIMESTAMP_SEL_MASK 0x2000 418 #define TSO_FICFG_CLK_TIMESTAMP_27M 0x2000 419 #define TSO_FICFG_CLK_TIMESTAMP_90K 0x0000 420 421 REG16 _xbf8275e8; // 0xbf8275e8 x7a 422 423 REG16 TSO_Interrupt; // 0xbf8275ec 0x7b 424 #define TSO_INT_ENABLE_MASK 0x00FF 425 #define TSO_INT_STATUS_MASK 0xFF00 426 #define TSO_INT_DMA_DONE 0x0001 427 #define TSO_INT_DMA_DONE1 0x0002 428 #define TSO_INT_TRCCLK_UPDATE 0x0004 429 430 REG16 TSO_Interrupt1; // 0xbf8275f0 0x7c 431 #define TSO_INT1_ENABLE_MASK 0x00FF 432 #define TSO_INT1_STATUS_MASK 0xFF00 433 #define TSO_INT1_PIDFLT1_OVF 0x0001 434 #define TSO_INT1_PIDFLT5_OVF 0x0010 435 436 REG32 TSO_DBG; // 0xbf8275f4~0xbf8275f8 0x7d~0x7e 437 REG16 TSO_DBG_SEL; // 0xbf8275fc 0x7f 438 439 } REG_Ctrl_TSO; 440 441 typedef struct _REG_Ctrl_TSO1 442 { 443 //---------------------------------------------- 444 // 0xBF802A00 MIPS direct access 445 //---------------------------------------------- 446 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 447 448 REG16 TSO_PRE_HEADER1_CFG0; // 0xbf847A00 0x00 449 #define TSO_PRE_HD1_CFG0_LOCAL_STRID_MASK 0x00FF 450 451 REG16 TSO_PRE_HEADER1_CFG1; // 0xbf847A04 0x01 452 REG16 TSO_PRE_HEADER1_CFG2; // 0xbf847A08 0x02 453 REG16 TSO_PRE_HEADER1_CFG3; // 0xbf847A0c 0x03 454 455 REG16 _xbf827a10_7a3c[12]; // 0xbf847A10~0xbf847A3c 0x04~0x0f 456 457 REG16 TSO_PRE_HEADER5_CFG0; // 0xbf847A40 0x10 458 REG16 TSO_PRE_HEADER5_CFG1; // 0xbf847A44 0x11 459 REG16 TSO_PRE_HEADER5_CFG2; // 0xbf847A48 0x12 460 REG16 TSO_PRE_HEADER5_CFG3; // 0xbf847A4c 0x13 461 462 REG16 _xbf827a50_7a5c[4]; // 0xbf847A50~0xbf847A5c 0x14~0x17 463 464 REG32 TSO_SVQ1_BASE; // 0xbf847A50~0xbf847A54 0x18~0x19 465 REG16 TSO_SVQ1_SIZE; // 0xbf847A58 0x1a //unit:200byte/pkt 466 REG16 TSO_SVQ1_TX_CFG; // 0xbf847A5c 0x1b 467 #define TSO_SVQ_TX_CFG_WR_THRESHOLD_MASK 0x000F 468 #define TSO_SVQ_TX_CFG_PRI_THRESHOLD_MASK 0x00F0 469 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK 0x0F00 470 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT 8UL 471 #define TSO_SVQ_TX_CFG_TX_RESET 0x1000 472 #define TSO_SVQ_TX_CFG_OVF_INT_EN 0x2000 473 #define TSO_SVQ_TX_CFG_OVF_CLR 0x4000 474 #define TSO_SVQ_TX_CFG_SVQ_EN 0x8000 475 476 REG16 _xbf827a60_7a9c[12]; // 0xbf847A60~0xbf847A9c 0x1c~0x27 477 478 REG32 TSO_SVQ5_BASE; // 0xbf847Aa0~0xbf847Aa4 0x28~0x29 479 REG16 TSO_SVQ5_SIZE; // 0xbf847Aa8 0x2a //unit:200byte/pkt 480 REG16 TSO_SVQ5_TX_CFG; // 0xbf847Aac 0x2b 481 482 REG16 _xbf827ab0_7abc[4]; // 0xbf847Ab0~0xbfbc7Abc 0x2c~0x2f 483 484 REG16 TSO_SVQ_RX_CFG; // 0xbf847Ac0 0x30 485 #define TSO_SVQ_RX_CFG_MODE_MASK 0x0003 486 #define TSO_SVQ_RX_CFG_MODE_OPENCBL 0x0000 487 #define TSO_SVQ_RX_CFG_MODE_CIPL 0x0001 488 #define TSO_SVQ_RX_CFG_MODE_192PKT 0x0002 489 #define TSO_SVQ_RX_CFG_RD_THRESHOLD_MASK 0x001C 490 #define TSO_SVQ_RX_CFG_ARBMODE_MASK 0x0060 491 #define TSO_SVQ_RX_CFG_ARBMODE_RUNROBIN 0x0000 492 #define TSO_SVQ_RX_CFG_ARBMODE_FIXPRI 0x0020 493 #define TSO_SVQ_RX_CFG_ARBMODE_DYMPRI 0x0040 494 #define TSO_SVQ_RX_CFG_DRAM_SD_ENABLE 0x0080 495 #define TSO_SVQ_RX_CFG_SVQ_FORCE_RESET 0x0100 496 #define TSO_SVQ_RX_CFG_SVQ_MIU_NS 0x0200 497 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK 0x7C00 498 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_SHIFT 10 499 #define TSO_SVQ_RX_CFG_SVQ_DYN_PRI 0x8000 500 501 REG16 TSO_SVQ_RX_PRI[2]; // 0xbf847Ac4~0xbf847Acc 0x31~0x32 502 #define TSO_SVQ_RX_NUM 6 503 #define TSO_SVQ_RX_PRI_MASK 0xFF 504 #define TSO_SVQ_RX_PRI_SHIFT 8 505 506 REG16 _xbf827acc; // 0xbf847Acc 0x33 507 508 REG32 TSO_SVQ_STATUS; // 0xbf847Ad0~0xbf847Ad4 0x34~0x35 509 #define TSO_SVQ_STS_MASK 0x000F 510 #define TSO_SVQ1_STS_SHIFT 0 511 #define TSO_SVQ5_STS_SHIFT 16 512 #define TSO_SVQ_STS_EVER_FULL 0x0001 513 #define TSO_SVQ_STS_EVER_OVF 0x0002 514 #define TSO_SVQ_STS_EMPTY 0x0004 515 #define TSO_SVQ_STS_BUSY 0x0008 516 517 REG32 TSO_SVQ_STATUS2; // 0xbf847Ad8~0xbf847Adc 0x36~0x37 518 #define TSO_SVQ_STS2_MASK 0x000F 519 #define TSO_SVQ1_STS2_SHIFT 0 520 #define TSO_SVQ5_STS2_SHIFT 16 521 #define TSO_SVQ_STS2_TXFIFO_WLEVEL_MASK 0x000C 522 #define TSO_SVQ_STS2_TXFIFO_FULL 0x0002 523 #define TSO_SVQ_STS2_TXFIFO_EMPTY 0x0001 524 525 REG32 TSO_DELTA; // 0xbf847Ae0~0xbf847Ae4 0x38~0x39 526 527 REG16 TSO_DELTA_CFG; // 0xbf847Ae8 0x3a 528 #define TSO_DELTA_CFG_SEL_CH_MASK 0x0007 529 #define TSO_DELTA_CFG_DELTA_CLR 0x0008 530 #define TSO_DELTA_CFG_MAX_ID_MASK 0x0700 531 #define TSO_DELTA_CFG_MAX_ID_SHIFT 8 532 533 } REG_Ctrl_TSO1; 534 535 536 #endif // _TSO_REG_H_ 537 538