1 //<MStar Software>
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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halTSO.c
97 // @brief TS I/O HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "halTSO.h"
101 #include "halCHIP.h"
102
103 //--------------------------------------------------------------------------------------------------
104 // Driver Compiler Option
105 //--------------------------------------------------------------------------------------------------
106 #define TSP_HAL_REG_SAFE_MODE 1 // Register protection access between 1 task and 1+ ISR
107
108 //-------------------------------------------------------------------------------------------------
109 // Local Structures
110 //-------------------------------------------------------------------------------------------------
111 typedef struct _HalTSO_OutPad
112 {
113 MS_U16 u16OutPad[TSO_ENGINE_NUM];
114 MS_U16 u16TSCfgOld[TSO_ENGINE_NUM];
115 MS_U16 u16TSOutModeOld[TSO_ENGINE_NUM];
116 } HalTSO_OutPad;
117
118 //--------------------------------------------------------------------------------------------------
119 // TSP Hardware Abstraction Layer
120 //--------------------------------------------------------------------------------------------------
121 static REG_Ctrl_TSO* _TSOCtrl = NULL;
122 static REG_Ctrl_TSO1* _TSOCtrl1 = NULL;
123
124
125 static MS_VIRT _virtTSORegBase = 0;
126 static MS_PHY _phyTSOFiMiuOffset[TSO_FILE_IF_NUM] = {[0 ... (TSO_FILE_IF_NUM-1)] = 0UL};
127 static MS_PHY _phyTSOVQiMiuOffset = 0U;
128
129 static HalTSO_OutPad _stOutPadCtrl;
130
131 //[NOTE] Jerry
132 // Some register has write order, for example, writing PCR_L will disable PCR counter
133 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
134 #define _HAL_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
135 (reg)->H = ((value) >> 16); } while(0)
136
137 #define _HAL_REG16_W(reg, value) (reg)->data = (value);
138
139 //--------------------------------------------------------------------------------------------------
140 // Macro of bit operations
141 //--------------------------------------------------------------------------------------------------
142 #define HAS_FLAG(flag, bit) ((flag) & (bit))
143 #define SET_FLAG(flag, bit) ((flag)|= (bit))
144 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit)))
145 #define SET_FLAG1(flag, bit) ((flag)| (bit))
146 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit)))
147
148 #define TSO_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x6600 + ((addr)<<2))))
149 #define REG_CLKGEN1_TSO_IN 0x22
150 #define REG_CLKGEN0_TSO_TRACE_MASK 0x000F
151 #define REG_CLKGEN1_TSO_TRACE_DISABLE 0x0001
152 #define REG_CLKGEN1_TSO_TRACE_INVERT 0x0002
153 #define REG_CLKGEN1_TSO_TRACE_216M 0x0000
154 #define REG_CLKGEN1_TSO_TRACE_SAMPLE_MASK 0x00F0
155 #define REG_CLKGEN1_TSO_TRACE_SAMPLE_DISABLE 0x0010
156 #define REG_CLKGEN1_TSO_TRACE_SAMPLE_INVERT 0x0020
157 #define REG_CLKGEN1_TSO_TRACE_SAMPLE_216 0x0000
158 #define REG_CLKGEN1_TSO_IN_MASK 0x1F00
159 #define REG_CLKGEN1_TSO_IN_SHIFT 8
160 #define REG_CLKGEN1_TSO_IN_DISABLE 0x0100
161 #define REG_CLKGEN1_TSO_IN_INVERT 0x0200
162 // bit[12:8] -> 0: disable clock
163 // 1: invert clock
164 // bit [12:10] -> 000: Sel TS0 Clk
165 // 001: Sel TS1 Clk
166 // 010: Sel TS2 Clk
167 // 011: Sel Demod Clk
168 #define REG_CLKGEN1_TSO1_IN 0x23
169 #define REG_CLKGEN1_TSO1_IN_MASK 0x1F00
170 #define REG_CLKGEN1_TSO1_IN_SHIFT 8
171 #define REG_CLKGEN1_TSO1_IN_DISABLE 0x0100
172 #define REG_CLKGEN1_TSO1_IN_INVERT 0x0200
173 // bit[12:8] -> 0: disable clock
174 // 1: invert clock
175 // bit [12:10] -> 000: Sel TS0 Clk
176 // 001: Sel TS1 Clk
177 // 010: Sel TS2 Clk
178 // 011: Sel Demod Clk
179 #define REG_CLKGEN1_TSO_OUT_PHASE 0x24
180 #define REG_CLKGEN1_TSO_OUT_DIVNUM_MASK 0x001F
181 #define REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_MASK 0x1F00
182 #define REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_SHIFT 8
183 #define REG_CLKGEN1_TSO_OUT_CLK 0x25
184 #define REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK 0x0001
185 // bit[0] -> 0: CLK_DMPLLDIV5
186 // 1: CLK_DMPLLDIV3
187 #define REG_CLKGEN1_TSO_OUT_INV 0x0002
188 #define REG_CLKGEN1_TSO_OUT_PHASE_TUN_ENABLE 0x0004
189 #define REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_MASK 0x0070
190 #define REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_SHIFT 4
191 #define REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_TS0 0x0000
192 #define REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_TS1 0x0010
193 #define REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_TS2 0x0020
194
195 #define REG_CLKGEN0_TSO_OUT_CLK_MASK 0x1F00
196 #define REG_CLKGEN1_TSO_OUT_CLK_DISABLE 0x0100
197 #define REG_CLKGEN1_TSO_OUT_CLK_INVERT 0x0200
198 // bit[12:8] -> 0: disable clock
199 // 1: invert clock
200 // bit [4:2] -> 000: TSO_OUT_DIV2 (clock/2N+1)
201 // 001: 62MHz
202 // 010: 54MHz
203 // 011: clk_p_tso_out (live in)
204 // 100: clk_p_tso_out_div8 (live in)
205 // 101: 27MHz
206 // 111: clk_demod_ts_p
207
208 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x3c00 + ((addr)<<2))))
209 #define REG_TOP_TS_OUT_MODE 0x51 //For ts1 out configure
210 #define REG_TOP_TS_OUT_MODE_MASK 0x0100
211 #define REG_TOP_TS1_OUT_MODE_TSO 0x0100
212
213 //#define REG_TOP_TS_TS0TS1_CFG_MASK 0x07
214 #define REG_TOP_TSCONFIG 0x51
215 #define REG_TOP_TS0CFG_SHIFT 9
216 #define REG_TOP_TS_TS0_CFG_MASK 0x03
217 #define REG_TOP_TS_TS0_PARALL_IN 1
218 #define REG_TOP_TS_TS0_SERIAL_IN 2
219
220 #define REG_TOP_TS1CFG_SHIFT 11
221 #define REG_TOP_TS_TS1_CFG_MASK 0x07
222 #define REG_TOP_TS_TS1_PARALL_IN 1
223 #define REG_TOP_TS_TS1_PARALL_OUT 2
224 #define REG_TOP_TS_TS1_SERIAL_IN 3
225
226 #define REG_TOP_TS2CONFIG 0x54
227 #define REG_TOP_TS2CFG_SHIFT 4
228 #define REG_TOP_TS_TS2_CFG_MASK 0x03
229 #define REG_TOP_TS_TS2_PARALL_IN 1
230 #define REG_TOP_TS_TS2_SERIAL_IN 2
231 #define REG_TOP_TSCFG_DISABLE_PAD 0
232
233
234
235
236 #define TSP_TSP5_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0xc7600 + ((addr)<<2))))
237 #define REG_TSP5_TSOIN_MUX 0x13
238 #define REG_TSP5_TSOIN_MUX_MASK 0x000F
239 #define REG_TSP5_TSOIN0_MUX_SHIFT 0
240 #define REG_TSP5_TSOIN1_MUX_SHIFT 4
241 #define REG_TSP5_TSOOUT_MUX 0x15
242 #define REG_TSP5_TSOOUT_MUX_MASK 0x000F
243 #define REG_TSP5_TSOOUT_MUX_TSO 0x0000
244 #define REG_TSP5_TSOOUT_MUX_S2P0 0x0001
245
246 #define TSP_TS_SAMPLE_REG(addr) (*((volatile MS_U16*)(_virtTSORegBase + 0x21600 + ((addr)<<2))))
247 #define REG_TSO_OUT_CLK_SEL 0x30
248 #define REG_TSO_OUT_CLK_SEL_MASK 1
249 #define REG_TSO_OUT_TSO 0x0000
250 #define REG_TSO_OUT_S2P 0x0001
251
252
253 #if 0
254 #define TSO_MIUDIG0_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x0C00 + ((addr)<<2))))
255 #define TSO_MIUDIG1_REG(addr) (*((volatile MS_U16*)(_u32TSORegBase + 0x2400 + ((addr)<<2))))
256 #define REG_MIUDIG_MIU_SEL1 0x79
257 #define REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK 0x0080
258 #endif
259 //--------------------------------------------------------------------------------------------------
260 // Implementation
261 //--------------------------------------------------------------------------------------------------
_HAL_REG32_R(REG32 * reg)262 static MS_U32 _HAL_REG32_R(REG32 *reg)
263 {
264 MS_U32 value = 0;
265 value = (reg)->H << 16;
266 value |= (reg)->L;
267 return value;
268 }
269
_HAL_REG16_R(REG16 * reg)270 static MS_U16 _HAL_REG16_R(REG16 *reg)
271 {
272 MS_U16 value = 0;
273 value = (reg)->data;
274 return value;
275 }
276
_HAL_TSO_MIU_OFFSET(MS_PHY Phyaddr)277 static MS_PHY _HAL_TSO_MIU_OFFSET(MS_PHY Phyaddr)
278 {
279 #ifdef HAL_MIU2_BASE
280 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
281 return ((MS_PHY)HAL_MIU2_BASE & 0xFFFFFFFFUL);
282 else
283 #endif //HAL_MIU2_BASE
284 #ifdef HAL_MIU1_BASE
285 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
286 return ((MS_PHY)HAL_MIU1_BASE & 0xFFFFFFFFUL);
287 else
288 #endif //HAL_MIU1_BASE
289 return ((MS_PHY)HAL_MIU0_BASE & 0xFFFFFFFFUL);
290 }
291
HAL_TSO_SetBank(MS_VIRT virtBankAddr)292 void HAL_TSO_SetBank(MS_VIRT virtBankAddr)
293 {
294 _virtTSORegBase = virtBankAddr;
295 _TSOCtrl = (REG_Ctrl_TSO*)(_virtTSORegBase+ REG_CTRL_BASE_TSO);
296 _TSOCtrl1 = (REG_Ctrl_TSO1*)(_virtTSORegBase+ REG_CTRL_BASE_TSO1);
297 }
298
HAL_TSO_REG32_IndR(REG32 * reg)299 static MS_U32 HAL_TSO_REG32_IndR(REG32 *reg)
300 {
301 MS_U32 u32tmp;
302 MS_VIRT virtReg = (MS_VIRT)reg;
303
304 u32tmp = ((MS_U32)virtReg)>> 1UL;
305
306 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address
307 _HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_INDIR_R_ENABLE)); // set command
308
309 u32tmp = ((MS_U32)_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_RDATA))) & 0xFFFFUL; // get read value
310
311 return u32tmp;
312 }
313
HAL_TSO_REG32_IndW(REG32 * reg,MS_U32 value)314 static void HAL_TSO_REG32_IndW(REG32 *reg, MS_U32 value)
315 {
316 MS_VIRT virtReg = (MS_VIRT)reg;
317 MS_U32 u32tmp = 0;
318
319 u32tmp = ((MS_U32)virtReg)>> 1;
320
321 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_ADDR), u32tmp); // set address
322 _HAL_REG32_W(&(_TSOCtrl->TSO_INDR_WDATA), value); // set write value
323 _HAL_REG16_W(&(_TSOCtrl->TSO_INDR_CTRL) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_INDR_CTRL)), TSO_INDIR_W_ENABLE)); // set command
324 }
325
326 //
327 // General API
328 //
HAL_TSO_Init(void)329 void HAL_TSO_Init(void)
330 {
331 MS_U8 u8ii = 0;
332
333 //select MIU0, and 128bit MIU bus
334 #if 0
335 TSO_MIUDIG0_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
336 TSO_MIUDIG1_REG(REG_MIUDIG_MIU_SEL1) &= ~REG_MIUDIG_MIU_SEL1_TSO_SEL_MASK; //select miu0
337 TSP_TOP_REG(REG_TOP_MIU_GP1_i64) =
338 (TSP_TOP_REG(REG_TOP_MIU_GP1_i64) & ~REG_TOP_MIU_GP1_i64_TSO_MASK) | REG_TOP_MIU_GP1_i64_TSO_128BIT_CLIENT;
339 #endif
340
341 for(u8ii = 0; u8ii < (MS_U8)TSO_ENGINE_NUM; u8ii++)
342 {
343 _stOutPadCtrl.u16OutPad[u8ii] = 0;
344 _stOutPadCtrl.u16TSCfgOld[u8ii] = 0;
345 _stOutPadCtrl.u16TSOutModeOld[u8ii] = 0;
346 }
347
348 //reset
349 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL);
350 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL);
351 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), 0);
352 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_DISABLE);
353
354 //default local stream id
355 _HAL_REG16_W(&(_TSOCtrl1->TSO_PRE_HEADER1_CFG0), 0x47);
356 _HAL_REG16_W(&(_TSOCtrl1->TSO_PRE_HEADER5_CFG0), 0x47);
357
358 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_MODE_MASK) | TSO_SVQ_RX_CFG_MODE_CIPL);
359
360 // Set SVQ FIFO timeout value
361 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ1_TX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ1_TX_CFG)) & ~TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK) | (0x0C << TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT));
362 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ5_TX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ5_TX_CFG)) & ~TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK) | (0x0C << TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT));
363 }
364
HAL_TSO_Reset_All(MS_U8 u8Eng)365 void HAL_TSO_Reset_All(MS_U8 u8Eng)
366 {
367 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), TSO_SW_RSTZ1_ALL);
368 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_ALL);
369
370 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ1), 0);
371 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), TSO_SW_RSTZ_DISABLE);
372 }
373
HAL_TSO_Reset(MS_U8 u8Eng)374 void HAL_TSO_Reset(MS_U8 u8Eng)
375 {
376 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) & ~TSO_SW_RSTZ_DISABLE);
377 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), _HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) | TSO_SW_RSTZ_DISABLE);
378 }
379
HAL_TSO_Reset_SubItem(MS_U8 u8Eng,MS_U16 u16RstItem)380 void HAL_TSO_Reset_SubItem(MS_U8 u8Eng, MS_U16 u16RstItem)
381 {
382 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) | u16RstItem));
383 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), (_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)) & ~u16RstItem));
384 }
385
HAL_TSO_HWInt_Enable(MS_U8 u8Eng,MS_BOOL bEnable,MS_U16 u16init)386 void HAL_TSO_HWInt_Enable(MS_U8 u8Eng, MS_BOOL bEnable, MS_U16 u16init)
387 {
388 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt));
389
390 if(bEnable)
391 {
392 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (u16data | u16init));
393 }
394 else
395 {
396 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (u16data & ~u16init));
397 }
398 }
399
HAL_TSO_HWInt_Clear(MS_U8 u8Eng,MS_U16 u16Int)400 void HAL_TSO_HWInt_Clear(MS_U8 u8Eng, MS_U16 u16Int)
401 {
402 _HAL_REG16_W(&(_TSOCtrl->TSO_Interrupt), (_HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt)) & ~u16Int));
403 }
404
HAL_TSO_HWInt_Status(MS_U8 u8Eng)405 MS_U16 HAL_TSO_HWInt_Status(MS_U8 u8Eng)
406 {
407 return (_HAL_REG16_R(&(_TSOCtrl->TSO_Interrupt)) & TSO_INT_STATUS_MASK);
408 }
409
HAL_TSO_Recover_TSOutMode(MS_U8 u8Eng)410 void HAL_TSO_Recover_TSOutMode(MS_U8 u8Eng)
411 {
412 switch(_stOutPadCtrl.u16OutPad[u8Eng])
413 {
414 case HAL_TSOOUT_MUX_TS1:
415 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~(REG_TOP_TS_TS1_CFG_MASK<<REG_TOP_TS1CFG_SHIFT)) | _stOutPadCtrl.u16TSCfgOld[u8Eng];
416 TSP_TOP_REG(REG_TOP_TS_OUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUT_MODE) & ~REG_TOP_TS_OUT_MODE_MASK) | _stOutPadCtrl.u16TSOutModeOld[u8Eng];
417 break;
418 default:
419 return;
420 }
421 }
422
HAL_TSO_OutPad(MS_U8 u8Eng,MS_U16 * pu16OutPad,MS_BOOL bSet)423 MS_BOOL HAL_TSO_OutPad(MS_U8 u8Eng, MS_U16* pu16OutPad,MS_BOOL bSet)
424 {
425 if(bSet)
426 {
427 switch(*pu16OutPad)
428 {
429 case HAL_TSOOUT_MUX_TS1:
430 _stOutPadCtrl.u16OutPad[u8Eng] = *pu16OutPad;
431 _stOutPadCtrl.u16TSCfgOld[u8Eng] = TSP_TOP_REG(REG_TOP_TSCONFIG) & (REG_TOP_TS_TS1_CFG_MASK << REG_TOP_TS1CFG_SHIFT);
432 _stOutPadCtrl.u16TSOutModeOld[u8Eng] = TSP_TOP_REG(REG_TOP_TS_OUT_MODE) & REG_TOP_TS_OUT_MODE_MASK;
433 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~(REG_TOP_TS_TS1_CFG_MASK << REG_TOP_TS1CFG_SHIFT));
434 TSP_TOP_REG(REG_TOP_TS_OUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUT_MODE) & ~REG_TOP_TS_OUT_MODE_MASK) | REG_TOP_TS1_OUT_MODE_TSO;
435 TSP_TSP5_REG(REG_TSP5_TSOOUT_MUX) = (TSP_TSP5_REG(REG_TSP5_TSOOUT_MUX) & ~REG_TSP5_TSOOUT_MUX_MASK) | REG_TSP5_TSOOUT_MUX_TSO;
436 TSP_TS_SAMPLE_REG(REG_TSO_OUT_CLK_SEL) = ((TSP_TS_SAMPLE_REG(REG_TSO_OUT_CLK_SEL) & ~REG_TSO_OUT_CLK_SEL_MASK) | REG_TSO_OUT_TSO); //tso out
437 break;
438 default:
439 return FALSE;
440 }
441 }
442 else
443 {
444 *pu16OutPad = HAL_TSOOUT_MUX_TS1; // only ts1 1p out
445 }
446
447 return TRUE;
448
449 }
450
HAL_TSO_SelPad(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16InPadSel,MS_BOOL bParallel)451 MS_BOOL HAL_TSO_SelPad(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16InPadSel, MS_BOOL bParallel)
452 {
453 MS_U16 u16RegMask, u16RegShift;
454 MS_U16 u16data = 0;
455
456 //printf("[%s] %d, %d, %x, %d\n", __FUNCTION__, (int)u8Eng, (int)u8TsIf, u16InPadSel, (int)bParallel);
457
458 switch(u8TsIf)
459 {
460 case HAL_TSO_TSIF_LIVE1:
461 u16RegShift = REG_TSP5_TSOIN0_MUX_SHIFT;
462 break;
463 case HAL_TSO_TSIF_LIVE2:
464 u16RegShift = REG_TSP5_TSOIN1_MUX_SHIFT;
465 break;
466 default:
467 return FALSE;
468 }
469
470 switch(u16InPadSel)
471 {
472 case TSO_IN_MUX_TS0:
473 u16RegMask = REG_TOP_TS_TS0_CFG_MASK << REG_TOP_TS0CFG_SHIFT;
474 if(bParallel)
475 {
476 u16data = REG_TOP_TS_TS0_PARALL_IN << REG_TOP_TS0CFG_SHIFT;
477 }
478 else
479 {
480 u16data = REG_TOP_TS_TS0_SERIAL_IN << REG_TOP_TS0CFG_SHIFT;
481 }
482 break;
483 case TSO_IN_MUX_TS1:
484 u16RegMask = REG_TOP_TS_TS1_CFG_MASK << REG_TOP_TS1CFG_SHIFT;
485 if(bParallel)
486 {
487 u16data = REG_TOP_TS_TS1_PARALL_IN << REG_TOP_TS1CFG_SHIFT;
488 }
489 else
490 {
491 u16data = REG_TOP_TS_TS1_SERIAL_IN << REG_TOP_TS1CFG_SHIFT;
492 }
493 break;
494 case TSO_IN_MUX_TS2:
495 u16RegMask = REG_TOP_TS_TS2_CFG_MASK << REG_TOP_TS2CFG_SHIFT;
496 if(bParallel)
497 {
498 u16data = REG_TOP_TS_TS2_PARALL_IN << REG_TOP_TS2CFG_SHIFT;
499 }
500 else
501 {
502 u16data = REG_TOP_TS_TS2_SERIAL_IN << REG_TOP_TS2CFG_SHIFT;
503 }
504 break;
505 case TSO_IN_MUX_TSDEMOD:
506 TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) = (TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) & ~(REG_TSP5_TSOIN_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift);
507 return TRUE;
508
509 default:
510 return FALSE;
511 }
512
513 TSP_TOP_REG(REG_TOP_TSCONFIG) = (TSP_TOP_REG(REG_TOP_TSCONFIG) & ~u16RegMask) | u16data;
514
515 TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) = (TSP_TSP5_REG(REG_TSP5_TSOIN_MUX) & ~(REG_TSP5_TSOIN_MUX_MASK << u16RegShift)) | (u16InPadSel << u16RegShift);
516
517 // ts1_pad & ts3_pad can for output mode
518 //TSP_TOP_REG(REG_TOP_TS_CONFIG) &= ~REG_TOP_TS1_CONFIG_MASK;
519 //TSP_TOP_REG(REG_TOP_TS_OUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUT_MODE) & ~REG_TOP_TS_OUT_MODE_MASK) | REG_TOP_TS_OUT_MODE_TSO;
520
521 return TRUE;
522 }
523
HAL_TSO_Set_InClk(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 u16ClkSel,MS_BOOL bClkInvert,MS_BOOL bEnable)524 MS_BOOL HAL_TSO_Set_InClk(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16 u16ClkSel, MS_BOOL bClkInvert, MS_BOOL bEnable)
525 {
526 MS_U16 u16Reg, u16RegMask, u16RegShift;
527 MS_U16 u16value = 0;
528
529 //printf("[%s] %d, u8TsIf %x, u16ClkSel %d, %d, %d\n", __FUNCTION__, (int)u8Eng, (int)u8TsIf, u16ClkSel, (int)bClkInvert, (int)bEnable);
530
531 switch(u8TsIf)
532 {
533 case HAL_TSO_TSIF_LIVE1:
534 u16Reg = REG_CLKGEN1_TSO_IN;
535 u16RegMask = REG_CLKGEN1_TSO_IN_MASK;
536 u16RegShift = REG_CLKGEN1_TSO_IN_SHIFT;
537 u16value = TSO_CLKGEN1_REG(u16Reg) & ~u16RegMask;
538 break;
539 case HAL_TSO_TSIF_LIVE2:
540 u16Reg = REG_CLKGEN1_TSO1_IN;
541 u16RegMask = REG_CLKGEN1_TSO1_IN_MASK;
542 u16RegShift = REG_CLKGEN1_TSO1_IN_SHIFT;
543 u16value = TSO_CLKGEN1_REG(u16Reg) & ~u16RegMask;
544 break;
545 default:
546 return FALSE;
547 }
548
549 //printf("[%s] u16RegMask %x, u16RegShift %d\n", __FUNCTION__, u16RegMask, u16RegShift);
550
551 if(!bEnable)
552 {
553 u16value |= (REG_CLKGEN1_TSO_IN_DISABLE << u16RegShift);
554 }
555 else
556 {
557 if(u16ClkSel > TSO_CLKIN_DMD)
558 {
559 return FALSE;
560 }
561
562 u16value |= (u16ClkSel << u16RegShift);
563 if(bClkInvert)
564 {
565 u16value |= (REG_CLKGEN1_TSO1_IN_INVERT << u16RegShift);
566 }
567 }
568
569 //printf("u16value %x\n", u16value);
570
571 switch(u8TsIf)
572 {
573 case HAL_TSO_TSIF_LIVE1:
574 TSO_CLKGEN1_REG(u16Reg) = u16value;
575 break;
576 case HAL_TSO_TSIF_LIVE2:
577 TSO_CLKGEN1_REG(u16Reg) = u16value;
578 break;
579 default:
580 return FALSE;
581 }
582
583 return TRUE;
584 }
585
HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng,MS_U8 u8TsIf,MS_U16 * pu16Pad,MS_BOOL * pbClkInvert,MS_BOOL * pbExtSync,MS_BOOL * pbParl)586 MS_BOOL HAL_TSO_GetInputTSIF_Status(MS_U8 u8Eng, MS_U8 u8TsIf, MS_U16* pu16Pad, MS_BOOL* pbClkInvert, MS_BOOL* pbExtSync, MS_BOOL* pbParl)
587 {
588
589 MS_U16 u16Reg, u16RegMask, u16RegShift;
590 MS_U16 u16data = 0;
591 REG16* reg16 = 0;
592
593 // Set pad mux
594 switch(u8TsIf)
595 {
596 case HAL_TSO_TSIF_LIVE1:
597 u16Reg = REG_TSP5_TSOIN_MUX;
598 u16RegMask = REG_TSP5_TSOIN_MUX_MASK << REG_TSP5_TSOIN0_MUX_SHIFT;
599 u16RegShift = REG_TSP5_TSOIN0_MUX_SHIFT;
600 break;
601 case HAL_TSO_TSIF_LIVE2:
602 u16Reg = REG_TSP5_TSOIN_MUX;
603 u16RegMask = REG_TSP5_TSOIN_MUX_MASK << REG_TSP5_TSOIN1_MUX_SHIFT;
604 u16RegShift = REG_TSP5_TSOIN1_MUX_SHIFT;
605 break;
606 default:
607 return FALSE;
608 }
609
610 *pu16Pad = (TSP_TOP_REG(u16Reg) & u16RegMask) >> u16RegShift;
611
612 switch(u8TsIf)
613 {
614 case HAL_TSO_TSIF_LIVE1:
615 u16data = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) & REG_CLKGEN1_TSO_IN_MASK) >> REG_CLKGEN1_TSO_IN_SHIFT;
616 reg16 = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
617 break;
618 case HAL_TSO_TSIF_LIVE2:
619 u16data = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO1_IN) & REG_CLKGEN1_TSO1_IN_MASK) >> REG_CLKGEN1_TSO1_IN_SHIFT;
620 reg16 = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
621 break;
622 default:
623 return FALSE;
624 }
625
626 *pbExtSync = ((_HAL_REG16_R(reg16) & TSO_CHCFG_EXT_SYNC_SEL) == TSO_CHCFG_EXT_SYNC_SEL);
627 *pbParl = ((_HAL_REG16_R(reg16) & TSO_CHCFG_P_SEL) == TSO_CHCFG_P_SEL);
628 *pbClkInvert = ((u16data & REG_CLKGEN1_TSO1_IN_INVERT) == REG_CLKGEN1_TSO1_IN_INVERT);
629
630 return TRUE;
631
632 }
633
HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng,MS_U16 u16PadSel,MS_BOOL bSet,HalTSOOutClk * pstOutClkSet)634 MS_BOOL HAL_TSO_OutClk_DefSelect(MS_U8 u8Eng, MS_U16 u16PadSel, MS_BOOL bSet, HalTSOOutClk* pstOutClkSet)
635 {
636 if((u16PadSel == 0xFFFF) || (bSet == TRUE))
637 {
638 return FALSE; //not support yet
639 }
640
641 switch(u16PadSel)
642 {
643 case HAL_TSOIN_MUX_TS0:
644 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
645 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS0IN;
646 break;
647 case HAL_TSOIN_MUX_TS1:
648 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
649 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS1IN;
650 break;
651 case HAL_TSOIN_MUX_TS2:
652 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT;
653 pstOutClkSet->u16PreTsoOutClk = HAL_PRE_TSO_OUT_SEL_TS2IN;
654 break;
655 case HAL_TSOIN_MUX_TSDEMOD0:
656 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD;
657 break;
658 case HAL_TSOIN_MUX_MEM:
659 pstOutClkSet->u16OutClk = HAL_TSO_OUT_SEL_TSO_OUT_DIV2N;
660 pstOutClkSet->u16OutDivSrc = HAL_TSO_OUT_DIV_SEL_172M_2N;
661 pstOutClkSet->u16OutDivNum = 0x0F; //default: 172.8/2(15+1) = 5.4M
662 break;
663 default:
664 return FALSE;
665 }
666
667 return TRUE;
668 }
669
670 // default: dmplldiv5 / 2 (11+1) = 7.2 MHz
671 // default: dmplldiv_3 / 2 (17+1) = 8 MHz
HAL_TSO_OutputClk(MS_U8 u8Eng,HalTSOOutClk * pstOutClkSet,MS_BOOL bSet)672 void HAL_TSO_OutputClk(MS_U8 u8Eng, HalTSOOutClk* pstOutClkSet, MS_BOOL bSet)
673 {
674 if(bSet == TRUE)
675 {
676 if(pstOutClkSet->bEnable == FALSE)
677 {
678 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE);
679 return;
680 }
681
682 switch(pstOutClkSet->u16OutClk)
683 {
684 case HAL_TSO_OUT_SEL_TSO_OUT_DIV2N:
685 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), TRUE);
686 break;
687 case HAL_TSO_OUT_SEL_TSO_OUT_27MHz:
688 case HAL_TSO_OUT_SEL_TSO_OUT_62MHz:
689 case HAL_TSO_OUT_SEL_TSO_OUT_54MHz:
690 case HAL_TSO_OUT_SEL_TSO_OUT_FROM_DEMOD:
691 break;
692 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT:
693 case HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8:
694 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), TRUE);
695 break;
696 default:
697 return;
698 }
699
700 HAL_TSO_Set_TSOOut_Phase_Tune(u8Eng, 0, FALSE); //default -> no phase tuning
701 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), TRUE); //alyays need TSO out clock
702 }
703 else
704 {
705 HAL_TSO_OutClk(u8Eng, &(pstOutClkSet->u16OutClk), &(pstOutClkSet->bClkInvert), &(pstOutClkSet->bEnable), FALSE);
706 if(pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_DIV2N)
707 {
708 HAL_TSO_TSOOutDiv(u8Eng, &(pstOutClkSet->u16OutDivSrc), &(pstOutClkSet->u16OutDivNum), FALSE);
709 }
710 else if((pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT) || (pstOutClkSet->u16OutClk == HAL_TSO_OUT_SEL_TSO_OUT_PTSOOUT_DIV8))
711 {
712 HAL_TSO_PreTsoOutClk(u8Eng, &(pstOutClkSet->u16PreTsoOutClk), FALSE);
713 }
714 }
715 }
716
HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng,MS_U16 u16ClkOutPhase,MS_BOOL bPhaseEnable)717 MS_BOOL HAL_TSO_Set_TSOOut_Phase_Tune(MS_U8 u8Eng, MS_U16 u16ClkOutPhase, MS_BOOL bPhaseEnable)
718 {
719 MS_U16 u16value = 0;
720
721 if(!bPhaseEnable)
722 {
723 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) &= ~REG_CLKGEN1_TSO_OUT_PHASE_TUN_ENABLE;
724 }
725 else
726 {
727 u16value = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) & ~REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_MASK)
728 | (u16ClkOutPhase << REG_CLKGEN1_TSO_OUT_PH_TUN_NUM_SHIFT);
729
730 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) = u16value;
731 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) |= REG_CLKGEN1_TSO_OUT_PHASE_TUN_ENABLE;
732 }
733
734 return TRUE;
735 }
736
HAL_TSO_PreTsoOutClk(MS_U8 u8Eng,MS_U16 * pu16PreTsoOutSel,MS_BOOL bSet)737 MS_BOOL HAL_TSO_PreTsoOutClk(MS_U8 u8Eng, MS_U16* pu16PreTsoOutSel, MS_BOOL bSet)
738 {
739 if(bSet == TRUE)
740 {
741 if(*pu16PreTsoOutSel > HAL_PRE_TSO_OUT_SEL_TS2IN)
742 {
743 return FALSE;
744 }
745
746 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) =
747 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_MASK) | (*pu16PreTsoOutSel << REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_SHIFT);
748 }
749 else
750 {
751 *pu16PreTsoOutSel = (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & (REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_MASK)) >> REG_CLKGEN1_TSO_OUT_PRE_OUTCLK_SHIFT;
752 }
753
754 return TRUE;
755 }
756
HAL_TSO_TSOOutDiv(MS_U8 u8Eng,MS_U16 * pu16ClkOutDivSrcSel,MS_U16 * pu16ClkOutDivNum,MS_BOOL bSet)757 MS_BOOL HAL_TSO_TSOOutDiv(MS_U8 u8Eng, MS_U16* pu16ClkOutDivSrcSel, MS_U16* pu16ClkOutDivNum,MS_BOOL bSet)
758 {
759
760 //clock source for clock divide
761 if(bSet == TRUE)
762 {
763 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) =
764 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN1_TSO_TRACE_216M;
765
766 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) =
767 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK) | *pu16ClkOutDivSrcSel;
768
769 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) =
770 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) & ~REG_CLKGEN1_TSO_OUT_DIVNUM_MASK) | *pu16ClkOutDivNum;
771 }
772 else
773 {
774 *pu16ClkOutDivSrcSel = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & REG_CLKGEN0_TSO_OUT_DIV_SEL_MASK;
775 *pu16ClkOutDivNum = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_PHASE) & REG_CLKGEN1_TSO_OUT_DIVNUM_MASK;
776 }
777 return TRUE;
778 }
779
HAL_TSO_OutClk(MS_U8 u8Eng,MS_U16 * pu16ClkOutSel,MS_BOOL * pbClkInvert,MS_BOOL * pbEnable,MS_BOOL bSet)780 MS_BOOL HAL_TSO_OutClk(MS_U8 u8Eng, MS_U16* pu16ClkOutSel, MS_BOOL* pbClkInvert, MS_BOOL* pbEnable,MS_BOOL bSet)
781 {
782
783 MS_U16 u16Clk = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~REG_CLKGEN0_TSO_OUT_CLK_MASK;
784
785 if(bSet == TRUE)
786 {
787 if(!*pbEnable)
788 {
789 u16Clk |= REG_CLKGEN1_TSO_OUT_CLK_DISABLE;
790 }
791 else
792 {
793 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) =
794 (TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_IN) & ~REG_CLKGEN0_TSO_TRACE_MASK) | REG_CLKGEN1_TSO_TRACE_216M;
795
796 u16Clk |= *pu16ClkOutSel;
797
798 if(*pbClkInvert)
799 u16Clk |= REG_CLKGEN1_TSO_OUT_CLK_INVERT;
800 }
801 printf("[%s]u16Clk=0x%x\n\n",__FUNCTION__,u16Clk);
802 TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) = u16Clk;
803 }
804 else
805 {
806 *pbEnable = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_CLK_DISABLE;
807 *pbClkInvert = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & REG_CLKGEN1_TSO_OUT_CLK_INVERT;
808 *pu16ClkOutSel = TSO_CLKGEN1_REG(REG_CLKGEN1_TSO_OUT_CLK) & ~(REG_CLKGEN1_TSO_OUT_CLK_INVERT | REG_CLKGEN1_TSO_OUT_CLK_DISABLE);
809 }
810
811 return TRUE;
812 }
813
814 // ------------------------------------------------------
815 // APIS
816 //-------------------------------------------------------
HAL_TSO_Flt_SetPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16PID)817 void HAL_TSO_Flt_SetPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16PID)
818 {
819 MS_U32 u32value;
820 REG_PidFlt* pidReg = &(_TsoPid[u8Eng].Flt[u16FltId]);
821
822 u32value = (HAL_TSO_REG32_IndR((REG32 *)pidReg) & ~TSO_PIDFLT_PID_MASK) | (((MS_U32)u16PID << TSO_PIDFLT_PID_SHFT) & TSO_PIDFLT_PID_MASK);
823 HAL_TSO_REG32_IndW((REG32 *)pidReg, u32value);
824 }
825
HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng,MS_U16 u16FltId,MS_U16 u16InputSrc)826 void HAL_TSO_Flt_SetInputSrc(MS_U8 u8Eng, MS_U16 u16FltId, MS_U16 u16InputSrc)
827 {
828 MS_U32 u32value;
829 REG_PidFlt* pidReg = &(_TsoPid[u8Eng].Flt[u16FltId]);
830
831 u32value = (HAL_TSO_REG32_IndR((REG32 *)pidReg) & ~TSO_PIDFLT_IN_MASK) | (u16InputSrc << TSO_PIDFLT_IN_SHIFT);
832 HAL_TSO_REG32_IndW((REG32 *)pidReg, u32value);
833 }
834
HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng,MS_U16 u16FltId,MS_U8 u8TsIf,MS_U16 u16OldPid,MS_U16 u16NewPid)835 MS_BOOL HAL_TSO_ReplaceFlt_SetPktPid(MS_U8 u8Eng, MS_U16 u16FltId, MS_U8 u8TsIf, MS_U16 u16OldPid, MS_U16 u16NewPid)
836 {
837 REG32 *pReg = 0;
838 MS_U32 u32data = (((MS_U32)u16OldPid) & REP_PIDFLT_ORG_PID_MASK) | (((MS_U32)u8TsIf) << REP_PIDFLT_SRC_SHIFT) |
839 ((((MS_U32)u16NewPid) << REP_PIDFLT_NEW_PID_SHIFT) & REP_PIDFLT_NEW_PID_MASK);
840 pReg = &(_TSOCtrl->REP_PidFlt[u16FltId]);
841 _HAL_REG32_W(pReg, u32data);
842
843 return TRUE;
844 }
845
HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng,MS_U16 u16FltId,MS_BOOL bEnable)846 MS_BOOL HAL_TSO_ReplaceFlt_Enable(MS_U8 u8Eng, MS_U16 u16FltId, MS_BOOL bEnable)
847 {
848 if(bEnable)
849 {
850 _HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), SET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u16FltId])), REP_PIDFLT_REPLACE_EN));
851 }
852 else
853 {
854 _HAL_REG32_W(&(_TSOCtrl->REP_PidFlt[u16FltId]), RESET_FLAG1(_HAL_REG32_R(&(_TSOCtrl->REP_PidFlt[u16FltId])), REP_PIDFLT_REPLACE_EN));
855 }
856
857 return TRUE;
858 }
859
HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng,MS_PHY phyAddr)860 void HAL_TSO_Set_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng, MS_PHY phyAddr)
861 {
862 _phyTSOFiMiuOffset[u8FileEng] = _HAL_TSO_MIU_OFFSET(phyAddr);
863
864 if(u8FileEng == 0)
865 {
866 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_raddr), (MS_U32)(phyAddr-_phyTSOFiMiuOffset[u8FileEng]));
867 }
868 }
869
HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32len)870 void HAL_TSO_Set_Filein_ReadLen(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32len)
871 {
872 if(u8FileEng == 0)
873 {
874 _HAL_REG32_W(&(_TSOCtrl->TSO_Filein_rNum), u32len);
875 }
876 }
877
HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng,MS_U8 u8FileEng)878 MS_PHY HAL_TSO_Get_Filein_ReadAddr(MS_U8 u8Eng, MS_U8 u8FileEng)
879 {
880 MS_PHY phyvalue = 0;
881
882 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) | TSO_FICFG_RADDR_READ);
883 phyvalue = ((MS_PHY)_HAL_REG32_R(&(_TSOCtrl->TSO_TSO2MI_RADDR[u8FileEng])) & 0xFFFFFFFFUL) << TSO_MIU_BUS;
884 phyvalue += _phyTSOFiMiuOffset[u8FileEng];
885 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) & ~TSO_FICFG_RADDR_READ);
886 return phyvalue;
887 }
888
HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16ctrl)889 void HAL_TSO_Set_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16ctrl)
890 {
891 if(u8FileEng == 0)
892 {
893 _HAL_REG16_W(&(_TSOCtrl->TSO_Filein_Ctrl), (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl)) & ~TSO_FILEIN_CTRL_MASK) | u16ctrl);
894 }
895 }
896
HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng,MS_U8 u8FileEng)897 MS_U16 HAL_TSO_Get_Filein_Ctrl(MS_U8 u8Eng, MS_U8 u8FileEng)
898 {
899 if(u8FileEng == 0)
900 {
901 return (_HAL_REG16_R(&(_TSOCtrl->TSO_Filein_Ctrl)) & TSO_FILEIN_CTRL_MASK);
902 }
903
904 return 0;
905 }
906
HAL_TSO_Set_Filein_MOBFKey(MS_U8 u8FileEng,MS_U32 u32Key,MS_BOOL bSecured)907 MS_BOOL HAL_TSO_Set_Filein_MOBFKey(MS_U8 u8FileEng, MS_U32 u32Key, MS_BOOL bSecured)
908 {
909 MS_U16 u16data = (bSecured ? TSO_FILEIN_RIU_TSO_NS : 0);
910 REG16* pReg = &(_TSOCtrl->TSO_Filein_Ctrl);
911
912 if((_HAL_REG16_R(pReg) & (TSO_FILEIN_RSTART|TSO_FILEIN_ABORT)) != 0)
913 {
914 return FALSE;
915 }
916
917 u16data |= ((MS_U16)(u32Key << TSO_FILEIN_MOBF_IDX_SHIFT) & TSO_FILEIN_MOBF_IDX_MASK);
918 _HAL_REG16_W(pReg, u16data)
919
920 return TRUE;
921 }
922
HAL_TSO_Filein_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)923 MS_BOOL HAL_TSO_Filein_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
924 {
925 MS_U16 u16ChIf = TSO_CFG1_TSO_TSIF5_EN;
926
927 if(bEnable)
928 {
929 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf));
930 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
931 SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_SEGMENT|TSO_FICFG_TS_DATAPORT_SEL));
932 }
933 else
934 {
935 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16ChIf));
936 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
937 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_TSO_FILEIN|TSO_FICFG_FILE_SEGMENT|TSO_FICFG_TS_DATAPORT_SEL));
938 }
939
940 return TRUE;
941 }
942
HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)943 void HAL_TSO_FileinTimer_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
944 {
945 if(bEnable)
946 {
947 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) | TSO_FICFG_TIMER_ENABLE);
948 }
949 else
950 {
951 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng])) & ~TSO_FICFG_TIMER_ENABLE);
952 }
953 }
954
HAL_TSO_Filein_Rate(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U16 u16timer)955 void HAL_TSO_Filein_Rate(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U16 u16timer)
956 {
957 _HAL_REG16_W(&(_TSOCtrl->TSO_FI_TIMER[u8FileEng]), u16timer);
958 }
959
HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)960 void HAL_TSO_Filein_192Mode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
961 {
962 if(bEnable)
963 {
964 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE));
965 }
966 else
967 {
968 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
969 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_ENABLE));
970 }
971 }
972
HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng,MS_U8 u8FileEng,MS_BOOL bEnable)973 void HAL_TSO_Filein_192BlockMode_Enable(MS_U8 u8Eng, MS_U8 u8FileEng, MS_BOOL bEnable)
974 {
975 if(bEnable)
976 {
977 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
978 RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE));
979 }
980 else
981 {
982 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]),
983 SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_FILE_CFG[u8FileEng]), TSO_FICFG_PKT192_BLK_DISABLE));
984 }
985 }
986
HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng,MS_U8 u8FileEng)987 MS_U16 HAL_TSO_CmdQ_FIFO_Get_WRCnt(MS_U8 u8Eng, MS_U8 u8FileEng)
988 {
989 MS_U16 u16Shift = 0;
990
991 return ((_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_WCNT_MASK);
992 }
993
HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng,MS_U8 u8FileEng)994 MS_BOOL HAL_TSO_CmdQ_FIFO_IsFull(MS_U8 u8Eng, MS_U8 u8FileEng)
995 {
996 MS_U16 u16Shift = 0;
997
998 return (MS_BOOL)((_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_FIFO_FULL);
999 }
1000
HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng,MS_U8 u8FileEng)1001 MS_BOOL HAL_TSO_CmdQ_FIFO_IsEmpty(MS_U8 u8Eng, MS_U8 u8FileEng)
1002 {
1003 MS_U16 u16Shift = 0;
1004
1005 return (MS_BOOL)((_HAL_REG16_R(&(_TSOCtrl->TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_FIFO_EMPTY);
1006 }
1007
HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng,MS_U8 u8FileEng)1008 MS_U8 HAL_TSO_CmdQ_FIFO_Get_WRLevel(MS_U8 u8Eng, MS_U8 u8FileEng)
1009 {
1010 MS_U16 u16Shift = 0;
1011
1012 return (MS_U8)((_HAL_REG16_R(&(_TSOCtrl[u8Eng].TSO_CMDQ_STATUS)) >> u16Shift) & TSO_CMDQ_STS_WLEVEL_MASK);
1013 }
1014
HAL_TSO_CmdQ_Reset(MS_U8 u8Eng,MS_U8 u8FileEng)1015 MS_BOOL HAL_TSO_CmdQ_Reset(MS_U8 u8Eng, MS_U8 u8FileEng)
1016 {
1017 MS_U16 u16data = TSO_SW_RSTZ_CMDQ;
1018
1019 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1020 _HAL_REG16_W(&(_TSOCtrl->SW_RSTZ), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->SW_RSTZ)), u16data));
1021 return TRUE;
1022 }
1023
HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16ValidBlockCnt)1024 void HAL_TSO_RW_ValidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16ValidBlockCnt)
1025 {
1026 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG2));
1027
1028 if(bWrite)
1029 {
1030 u16data &= ~TSO_CFG2_VALID_BYTECNT_MASK;
1031 u16data |= (*pu16ValidBlockCnt << TSO_CFG2_VALID_BYTECNT_SHIFT);
1032 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG2), u16data);
1033
1034 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1035 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1036 }
1037 else
1038 {
1039 *pu16ValidBlockCnt = (u16data & TSO_CFG2_VALID_BYTECNT_MASK) >> TSO_CFG2_VALID_BYTECNT_SHIFT;
1040 }
1041 }
1042
HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16InvalidBlockCnt)1043 void HAL_TSO_RW_InvalidBlock_Count(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16InvalidBlockCnt)
1044 {
1045 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG2));
1046
1047 if(bWrite)
1048 {
1049 u16data &= ~TSO_CFG2_INVALID_BYTECNT_MASK;
1050 u16data |= (*pu16InvalidBlockCnt << TSO_CFG2_INVALID_BYTECNT_SHIFT);
1051 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG2), u16data);
1052
1053 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1054 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1055 }
1056 else
1057 {
1058 *pu16InvalidBlockCnt = u16data & TSO_CFG2_INVALID_BYTECNT_MASK;
1059 }
1060 }
1061
HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng,MS_BOOL bWrite,MS_U16 * pu16PktSize)1062 void HAL_TSO_RW_OutputPktSize(MS_U8 u8Eng, MS_BOOL bWrite, MS_U16 *pu16PktSize)
1063 {
1064 if(bWrite)
1065 {
1066 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG3), *pu16PktSize);
1067 }
1068 else
1069 {
1070 *pu16PktSize = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG3));
1071 }
1072
1073 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1074 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&_TSOCtrl->TSO_CFG1), TSO_CFG1_PKT_PARAM_LD));
1075 }
1076
HAL_TSO_LPcr2_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U32 u32lpcr2)1077 void HAL_TSO_LPcr2_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U32 u32lpcr2)
1078 {
1079 MS_U16 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]));
1080
1081 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp | TSO_FICFG_LPCR2_WLD);
1082 _HAL_REG32_W(&(_TSOCtrl->TSO_LPCR2[u8FileEng]), u32lpcr2);
1083 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp);
1084 }
1085
HAL_TSO_LPcr2_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1086 MS_U32 HAL_TSO_LPcr2_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1087 {
1088 MS_U32 u32temp = 0;
1089 MS_U16 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]));
1090
1091 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), ((u16temp & ~TSO_FICFG_LPCR2_WLD)|TSO_FICFG_LPCR2_LD));
1092 u32temp = _HAL_REG32_R(&_TSOCtrl->TSO_LPCR2[u8FileEng]);
1093 _HAL_REG16_W(&(_TSOCtrl->TSO_FILE_CFG[u8FileEng]), u16temp);
1094
1095 return u32temp;
1096 }
1097
HAL_TSO_TimeStamp_Get(MS_U8 u8Eng,MS_U8 u8FileEng)1098 MS_U32 HAL_TSO_TimeStamp_Get(MS_U8 u8Eng, MS_U8 u8FileEng)
1099 {
1100 return _HAL_REG32_R(&(_TSOCtrl->TSO_TIMESTAMP[u8FileEng]));
1101 }
1102
HAL_TSO_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8If,MS_U8 u8size)1103 MS_BOOL HAL_TSO_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8If, MS_U8 u8size)
1104 {
1105 MS_U16 u16data = 0;
1106
1107 if(u8If == HAL_TSO_TSIF_LIVE1)
1108 {
1109 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CH0_IF1_CFG0)) & ~TSO_PKT_SIZE_CHK_LIVE_MASK;
1110 _HAL_REG16_W(&(_TSOCtrl->TSO_CH0_IF1_CFG0), u16data | (MS_U16)u8size);
1111 }
1112 else if((u8If == HAL_TSO_TSIF_LIVE2) || (u8If == HAL_TSO_TSIF_FILE1))
1113 {
1114 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CH0_IF5_CFG0)) & ~TSO_PKT_SIZE_CHK_LIVE_MASK;
1115 _HAL_REG16_W(&(_TSOCtrl->TSO_CH0_IF5_CFG0), u16data | (MS_U16)u8size);
1116 }
1117 else
1118 {
1119 return FALSE;
1120 }
1121
1122 return TRUE;
1123 }
1124
HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng,MS_U8 u8FileEng,MS_U8 u8size)1125 void HAL_TSO_Filein_PktChkSize_Set(MS_U8 u8Eng, MS_U8 u8FileEng, MS_U8 u8size)
1126 {
1127 MS_U16 u16temp = 0, u16shift = 0;
1128
1129 u16temp = _HAL_REG16_R(&(_TSOCtrl->TSO_PKT_CHKSIZE_FI)) & ~(TSO_PKT_CHKSIZE_FI_MASK << u16shift);
1130 u16temp |= (((MS_U16)(u8size & 0xFF)) << u16shift);
1131
1132 _HAL_REG16_W(&(_TSOCtrl->TSO_PKT_CHKSIZE_FI), u16temp);
1133 }
1134
HAL_TSO_Cfg1_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL bEnable)1135 void HAL_TSO_Cfg1_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL bEnable)
1136 {
1137 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG1));
1138
1139 if(bEnable)
1140 {
1141 u16data |= u16CfgItem;
1142 }
1143 else
1144 {
1145 u16data &= ~u16CfgItem;
1146 }
1147
1148 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), u16data);
1149 }
1150
HAL_TSO_Cfg4_Enable(MS_U8 u8Eng,MS_U16 u16CfgItem,MS_BOOL bEnable)1151 void HAL_TSO_Cfg4_Enable(MS_U8 u8Eng, MS_U16 u16CfgItem, MS_BOOL bEnable)
1152 {
1153 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl->TSO_CFG4));
1154
1155 if(bEnable)
1156 {
1157 u16data |= u16CfgItem;
1158 }
1159 else
1160 {
1161 u16data &= ~u16CfgItem;
1162 }
1163
1164 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4), u16data);
1165 }
1166
HAL_TSO_ChIf_Enable(MS_U8 u8Eng,MS_U8 u8ChIf,MS_BOOL bEnable)1167 MS_BOOL HAL_TSO_ChIf_Enable(MS_U8 u8Eng, MS_U8 u8ChIf, MS_BOOL bEnable)
1168 {
1169 MS_U16 u16data = 0;
1170
1171 if(u8Eng > 0)
1172 {
1173 return FALSE;
1174 }
1175
1176 switch(u8ChIf)
1177 {
1178 case HAL_TSO_TSIF_LIVE1:
1179 u16data = TSO_CFG1_TSO_TSIF1_EN;
1180 break;
1181 case HAL_TSO_TSIF_LIVE2:
1182 u16data = TSO_CFG1_TSO_TSIF5_EN;
1183 break;
1184 default:
1185 return FALSE;
1186 }
1187
1188 if(bEnable)
1189 {
1190 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16data));
1191 }
1192 else
1193 {
1194 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG1), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)), u16data));
1195 }
1196
1197 return FALSE;
1198
1199 }
1200
HAL_TSO_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 u16Cfg,MS_BOOL bEnable)1201 MS_BOOL HAL_TSO_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16 u16Cfg, MS_BOOL bEnable)
1202 {
1203 REG16* pReg = NULL;
1204
1205 if(u8Eng > 0)
1206 {
1207 return FALSE;
1208 }
1209
1210 switch(u8ChIf)
1211 {
1212 case HAL_TSO_TSIF_LIVE1:
1213 pReg = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
1214 break;
1215 case HAL_TSO_TSIF_LIVE2:
1216 pReg = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
1217 break;
1218 default:
1219 return FALSE;
1220 }
1221
1222 if(bEnable)
1223 {
1224 _HAL_REG16_W(pReg, SET_FLAG1(_HAL_REG16_R(pReg), u16Cfg));
1225 }
1226 else
1227 {
1228 _HAL_REG16_W(pReg, RESET_FLAG1(_HAL_REG16_R(pReg), u16Cfg));
1229 }
1230
1231 return TRUE;
1232 }
1233
HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Cfg,MS_BOOL * pbEnable)1234 MS_BOOL HAL_TSO_Get_ChIf_Cfg(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Cfg, MS_BOOL *pbEnable)
1235 {
1236 REG16* pReg = NULL;
1237 MS_U16 u16data = 0;
1238
1239 *pu16Cfg = 0;
1240 *pbEnable = FALSE;
1241
1242 if(u8Eng > 0)
1243 {
1244 return FALSE;
1245 }
1246
1247 switch(u8ChIf)
1248 {
1249 case HAL_TSO_TSIF_LIVE1:
1250 pReg = &(_TSOCtrl->TSO_CH0_IF1_CFG2);
1251 break;
1252 case HAL_TSO_TSIF_LIVE2:
1253 pReg = &(_TSOCtrl->TSO_CH0_IF5_CFG2);
1254 break;
1255 default:
1256 return FALSE;
1257 }
1258
1259 *pu16Cfg = _HAL_REG16_R(pReg);
1260
1261 switch(u8ChIf)
1262 {
1263 case HAL_TSO_TSIF_LIVE1:
1264 u16data = TSO_CFG1_TSO_TSIF1_EN;
1265 break;
1266 case HAL_TSO_TSIF_LIVE2:
1267 u16data = TSO_CFG1_TSO_TSIF5_EN;
1268 break;
1269 default:
1270 return FALSE;
1271 }
1272
1273 *pbEnable = ((_HAL_REG16_R(&(_TSOCtrl->TSO_CFG1)) & u16data) == u16data);
1274
1275 return TRUE;
1276
1277 }
1278
1279
HAL_TSO_SVQBuf_Set(MS_U8 u8Eng,MS_U8 u8ChIf,MS_PHY phyBufAddr,MS_U32 u32BufSize)1280 MS_BOOL HAL_TSO_SVQBuf_Set(MS_U8 u8Eng, MS_U8 u8ChIf, MS_PHY phyBufAddr, MS_U32 u32BufSize)
1281 {
1282 REG32* p32Reg = NULL;
1283 REG16* p16Reg = NULL;
1284 REG16* p16RegCfg = NULL;
1285 MS_U32 u32addr = 0;
1286
1287 _phyTSOVQiMiuOffset = _HAL_TSO_MIU_OFFSET(phyBufAddr);
1288 u32addr = (MS_U32)(phyBufAddr - _phyTSOVQiMiuOffset);
1289
1290 if(u8Eng > 0)
1291 {
1292 return FALSE;
1293 }
1294
1295 switch(u8ChIf)
1296 {
1297 case HAL_TSO_TSIF_LIVE1:
1298 p32Reg = &(_TSOCtrl1->TSO_SVQ1_BASE);
1299 p16Reg = &(_TSOCtrl1->TSO_SVQ1_SIZE);
1300 p16RegCfg = &(_TSOCtrl1->TSO_SVQ1_TX_CFG);
1301 break;
1302 case HAL_TSO_TSIF_LIVE2:
1303 p32Reg = &(_TSOCtrl1->TSO_SVQ5_BASE);
1304 p16Reg = &(_TSOCtrl1->TSO_SVQ5_SIZE);
1305 p16RegCfg = &(_TSOCtrl1->TSO_SVQ5_TX_CFG);
1306 break;
1307 default:
1308 return FALSE;
1309 }
1310
1311 _HAL_REG32_W(p32Reg, u32addr >> TSO_MIU_BUS);
1312 _HAL_REG16_W(p16Reg , u32BufSize/TSO_SVQ_UNIT_SIZE);
1313
1314 // Reset SVQ
1315 _HAL_REG16_W(p16RegCfg , SET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_TX_RESET));
1316 _HAL_REG16_W(p16RegCfg , RESET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_TX_RESET));
1317
1318 _HAL_REG16_W(p16RegCfg, SET_FLAG1(_HAL_REG16_R(p16RegCfg), TSO_SVQ_TX_CFG_SVQ_EN));
1319
1320 return TRUE;
1321 }
1322
HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng,MS_U8 u8ChIf)1323 MS_BOOL HAL_TSO_ChIf_ClrByteCnt(MS_U8 u8Eng, MS_U8 u8ChIf)
1324 {
1325 MS_U16 u16data = 0;
1326
1327 switch(u8ChIf)
1328 {
1329 case HAL_TSO_TSIF_LIVE1:
1330 u16data = TSO_CLR_BYTE_CNT_1;
1331 break;
1332 case HAL_TSO_TSIF_LIVE2:
1333 u16data = TSO_CLR_BYTE_CNT_5;
1334 break;
1335 default:
1336 return FALSE;
1337 }
1338
1339
1340 _HAL_REG16_W(&(_TSOCtrl->TSO_CLR_BYTE_CNT), SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CLR_BYTE_CNT)), u16data));
1341 _HAL_REG16_W(&(_TSOCtrl->TSO_CLR_BYTE_CNT), RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CLR_BYTE_CNT)), u16data));
1342
1343 return TRUE;
1344 }
1345
HAL_TSO_LocalStreamID(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U8 * pu8StrID,MS_BOOL beSet)1346 MS_BOOL HAL_TSO_LocalStreamID(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U8* pu8StrID, MS_BOOL beSet)
1347 {
1348 REG16* p16Reg = NULL;
1349
1350 if(beSet == FALSE)
1351 {
1352 *pu8StrID = 0xFF;
1353 }
1354
1355 if(u8Eng > 0)
1356 {
1357 return FALSE;
1358 }
1359
1360 switch(u8ChIf)
1361 {
1362 case HAL_TSO_TSIF_LIVE1:
1363 p16Reg = &(_TSOCtrl1->TSO_PRE_HEADER1_CFG0);
1364 break;
1365 case HAL_TSO_TSIF_LIVE2:
1366 p16Reg = &(_TSOCtrl1->TSO_PRE_HEADER5_CFG0);
1367 break;
1368 default:
1369 return FALSE;
1370 }
1371
1372 if(beSet == TRUE)
1373 {
1374 _HAL_REG16_W(p16Reg , (MS_U16)(*pu8StrID) & 0xFF);
1375 }
1376 else
1377 {
1378 *pu8StrID = (MS_U8)(_HAL_REG16_R(p16Reg) & 0xFF);
1379 }
1380
1381 return TRUE;
1382
1383 }
1384
HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng,MS_U8 u8ChIf)1385 MS_BOOL HAL_TSO_SVQ_TX_Reset(MS_U8 u8Eng, MS_U8 u8ChIf)
1386 {
1387 REG16* p16Reg = NULL;
1388
1389 if(u8Eng > 0)
1390 {
1391 return FALSE;
1392 }
1393
1394 switch(u8ChIf)
1395 {
1396 case HAL_TSO_TSIF_LIVE1:
1397 p16Reg = &(_TSOCtrl1->TSO_SVQ1_TX_CFG);
1398 break;
1399 case HAL_TSO_TSIF_LIVE2:
1400 p16Reg = &(_TSOCtrl1->TSO_SVQ5_TX_CFG);
1401 break;
1402 default:
1403 return FALSE;
1404 }
1405
1406 _HAL_REG16_W(p16Reg , SET_FLAG1(_HAL_REG16_R(p16Reg), TSO_SVQ_TX_CFG_TX_RESET));
1407 _HAL_REG16_W(p16Reg , RESET_FLAG1(_HAL_REG16_R(p16Reg), TSO_SVQ_TX_CFG_TX_RESET));
1408
1409 return TRUE;
1410
1411 }
1412
HAL_TSO_Set_SVQRX_MOBFKey(MS_U8 u8Eng,MS_U32 u32Key,MS_BOOL bSecured)1413 MS_BOOL HAL_TSO_Set_SVQRX_MOBFKey(MS_U8 u8Eng, MS_U32 u32Key, MS_BOOL bSecured)
1414 {
1415 MS_U16 u16data = _HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK;
1416
1417 u16data |= ((MS_U16)(u32Key << TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_SHIFT) & TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK);
1418
1419 if(bSecured)
1420 {
1421 u16data |= TSO_SVQ_RX_CFG_SVQ_MIU_NS;
1422 }
1423 else
1424 {
1425 u16data &= ~TSO_SVQ_RX_CFG_SVQ_MIU_NS;
1426 }
1427
1428 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), u16data);
1429
1430 return TRUE;
1431 }
1432
HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng,MS_U16 u16mode)1433 MS_BOOL HAL_TSO_Set_SVQRX_PktMode(MS_U8 u8Eng, MS_U16 u16mode)
1434 {
1435 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_MODE_MASK) | u16mode);
1436
1437 return TRUE;
1438 }
1439
HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng,MS_U16 u16mode,MS_U16 * pu16SvqRxPri)1440 MS_BOOL HAL_TSO_Set_SVQRX_ArbitorMode(MS_U8 u8Eng, MS_U16 u16mode, MS_U16 *pu16SvqRxPri)
1441 {
1442 MS_U8 u8ii = 0, u8jj = 0;
1443 MS_U16 u16shift = 0;
1444
1445 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_CFG), (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_CFG)) & ~TSO_SVQ_RX_CFG_ARBMODE_MASK) | u16mode);
1446
1447 if(u16mode != TSO_SVQ_RX_CFG_ARBMODE_FIXPRI)
1448 {
1449 return TRUE;
1450 }
1451
1452 for(u8ii = 0; u8ii < TSO_SVQ_RX_NUM; u8ii++)
1453 {
1454 u8jj = u8ii >> 1;
1455 u16shift = ((u8ii % 2) ? TSO_SVQ_RX_PRI_SHIFT: 0);
1456
1457 _HAL_REG16_W(&(_TSOCtrl1->TSO_SVQ_RX_PRI[u8jj]),
1458 (_HAL_REG16_R(&(_TSOCtrl1->TSO_SVQ_RX_PRI[u8jj])) & ~(TSO_SVQ_RX_PRI_MASK << u16shift)) | (pu16SvqRxPri[u8ii] << u16shift));
1459 }
1460
1461 return TRUE;
1462 }
1463
HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng,MS_U32 u32systime)1464 MS_BOOL HAL_TSO_Set_SVQ_LocalSysTimestamp(MS_U8 u8Eng, MS_U32 u32systime)
1465 {
1466 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_SYS_TIMESTAMP));
1467 _HAL_REG32_W(&(_TSOCtrl->TSO_SYSTIMESTAMP), u32systime);
1468 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_SYS_TIMESTAMP));
1469
1470 return FALSE;
1471 }
1472
HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U16 * pu16Status)1473 MS_BOOL HAL_TSO_Get_SVQ_Status(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U16* pu16Status)
1474 {
1475 MS_U32 u32data = 0;
1476 MS_U32 u32Shift = 0;
1477
1478 *pu16Status = 0;
1479
1480 if(u8Eng > 0)
1481 {
1482 return FALSE;
1483 }
1484
1485 u32data = _HAL_REG32_R(&(_TSOCtrl1->TSO_SVQ_STATUS));
1486
1487 switch(u8ChIf)
1488 {
1489 case HAL_TSO_TSIF_LIVE1:
1490 u32Shift = 0;
1491 break;
1492 case HAL_TSO_TSIF_LIVE2:
1493 u32Shift = 16;
1494 break;
1495 default:
1496 return FALSE;
1497 }
1498
1499 *pu16Status = ((MS_U16)(u32data >> u32Shift) & TSO_SVQ_STS_MASK);
1500
1501 return TRUE;
1502
1503 }
1504
HAL_TSO_GetDelayTime_PreHd2Output(MS_U8 u8Eng,MS_U8 u8ChIf,MS_U32 * pu32time)1505 MS_BOOL HAL_TSO_GetDelayTime_PreHd2Output(MS_U8 u8Eng, MS_U8 u8ChIf, MS_U32 *pu32time)
1506 {
1507 *pu32time = 0;
1508
1509 if(u8Eng > 0)
1510 {
1511 return FALSE;
1512 }
1513
1514 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)), TSO_DELTA_CFG_DELTA_CLR));
1515 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)), TSO_DELTA_CFG_DELTA_CLR));
1516
1517 _HAL_REG16_W(&(_TSOCtrl1->TSO_DELTA_CFG) ,
1518 (_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)) & ~TSO_DELTA_CFG_SEL_CH_MASK) | u8ChIf);
1519
1520 *pu32time = _HAL_REG32_R(&(_TSOCtrl1->TSO_DELTA));
1521
1522 return TRUE;
1523 }
1524
HAL_TSO_Get_MaxDelta_ChId(MS_U8 u8Eng,MS_U8 * pu8ChIf)1525 MS_BOOL HAL_TSO_Get_MaxDelta_ChId(MS_U8 u8Eng, MS_U8 *pu8ChIf)
1526 {
1527 *pu8ChIf = 0xFF;
1528
1529 *pu8ChIf = (MS_U8)((_HAL_REG16_R(&(_TSOCtrl1->TSO_DELTA_CFG)) & TSO_DELTA_CFG_MAX_ID_MASK) >> TSO_DELTA_CFG_MAX_ID_SHIFT);
1530
1531 return TRUE;
1532 }
1533
HAL_TSO_Sel_LocalSysStampClkBase(MS_U8 u8Eng,MS_U16 u16ClkBase)1534 MS_BOOL HAL_TSO_Sel_LocalSysStampClkBase(MS_U8 u8Eng, MS_U16 u16ClkBase)
1535 {
1536 if(u16ClkBase == HAL_TSO_TIMESTAMP_27M)
1537 {
1538 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , SET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_TIMESTAMP_27M));
1539 }
1540 else
1541 {
1542 _HAL_REG16_W(&(_TSOCtrl->TSO_CFG4) , RESET_FLAG1(_HAL_REG16_R(&(_TSOCtrl->TSO_CFG4)), TSO_CFG4_SET_TIMESTAMP_BASE_MASK));
1543 }
1544
1545 return TRUE;
1546 }
1547
1548
1549
1550