1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSP.h 98 // Description: Transport Stream Processor (TSP) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSP_REG_H_ 103 #define _TSP_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 132 133 134 //-------------------------------------------------------------------------------------------------- 135 // Global Definition 136 //-------------------------------------------------------------------------------------------------- 137 #define TS_PACKET_SIZE 188UL 138 139 //-------------------------------------------------------------------------------------------------- 140 // Compliation Option 141 //-------------------------------------------------------------------------------------------------- 142 143 //[CMODEL][FWTSP] 144 // When enable, interrupt will not lost, CModel will block next packet 145 // and FwTSP will block until interrupt status is clear by MIPS. 146 // (For firmware and cmodel only) 147 #define TSP_DBG_SAFE_MODE_ENABLE 0 148 149 //------------------------------------------------------------------------------------------------- 150 // Harware Capability 151 //------------------------------------------------------------------------------------------------- 152 #define TSP_PIDFLT_NUM 32UL 153 #define TSP_PIDFLT1_NUM 16UL 154 #define TSP_PVR_IF_NUM 1UL 155 #define TSP_MMFI_AUDIO_FILTER_NUM 2UL 156 #define TSP_MMFI_V3D_FILTER_NUM 1UL 157 #define TSP_IF_NUM 2UL 158 #define TSP_DEMOD_NUM 1UL 159 #define TSP_VFIFO_NUM 2UL 160 #define TSP_AFIFO_NUM 1UL 161 #define TSP_TS_PAD_NUM 2UL 162 #define TSP_VQ_NUM 2UL 163 #define TSP_CA_FLT_NUM 16UL 164 #define TSP_CA_KEY_NUM 8UL 165 #define TSP_VQ_PITCH 192UL 166 /***************************************************/ 167 168 #define TSP_ENGINE_NUM (1UL) 169 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM+ TSP_PIDFLT1_NUM) 170 #define TSP_SECFLT_NUM (TSP_PIDFLT_NUM) 171 #define TSP_SECBUF_NUM (TSP_SECFLT_NUM) 172 #define TSP_FILTER_DEPTH (16UL) 173 174 #define TSP_SECFLT_NUM_All (TSP_SECFLT_NUM) 175 176 #define TSP_WP_SET_NUM (5UL) 177 178 #define DSCMB_FLT_START_ID (16UL) 179 #define DSCMB_FLT_END_ID (31UL) 180 #define DSCMB_FLT_NUM (16UL) 181 182 #define DSCMB_FLT_SHAREKEY_START_ID (0UL) 183 #define DSCMB_FLT_SHAREKEY_END_ID (0UL) 184 #define DSCMB_FLT_SHAREKEY_NUM (0UL) 185 186 #define DSCMB_FLT_NUM_ALL (DSCMB_FLT_NUM+DSCMB_FLT_SHAREKEY_NUM) 187 188 189 //PAD MUX definition 190 #define TSP_MUX_TS0 0UL 191 #define TSP_MUX_TS1 1UL 192 #define TSP_MUX_INDEMOD 7UL 193 194 //Clk source definition 195 #define TSP_CLK_DISABLE 0x01UL 196 #define TSP_CLK_INVERSE 0x02UL 197 #define TSP_CLK_TS0 0x00UL 198 #define TSP_CLK_TS1 0x04UL 199 #define TSP_CLK_INDEMOD 0x1CUL 200 #define CLKGEN0_TSP_CLK_MASK 0x1CUL 201 202 #define TSP_FW_DEVICE_ID 0x31UL 203 204 #define STC_SYNTH_NUM 1UL 205 #define STC_SYNTH_DEFAULT 0x28000000UL 206 207 #define DRAM_SIZE (0x40000000UL) 208 #define TSP_FW_BUF_SIZE (0x4000UL) 209 #define TSP_FW_BUF_LOW_BUD 0UL 210 #define TSP_FW_BUF_UP_BUD DRAM_SIZE 211 212 #define TSP_VQ_BUF_LOW_BUD 0UL 213 #define TSP_VQ_BUF_UP_BUD DRAM_SIZE 214 215 #define TSP_SEC_BUF_LOW_BUD 0UL 216 #define TSP_SEC_BUF_UP_BUD DRAM_SIZE 217 #define TSP_SEC_FLT_DEPTH 32UL 218 #define TSP_FIQ_NUM 0UL 219 220 //QMEM Setting 221 #define _TSP_QMEM_I_MASK 0xffff8000UL //total: 0x4000 222 #define _TSP_QMEM_I_ADDR_HIT 0x00000000UL 223 #define _TSP_QMEM_I_ADDR_MISS 0xffffffffUL 224 #define _TSP_QMEM_D_MASK 0xffff8000UL 225 #define _TSP_QMEM_D_ADDR_HIT 0x00000000UL 226 #define _TSP_QMEM_D_ADDR_MISS 0xffffffffUL 227 #define _TSP_QMEM_SIZE 0x1000UL // 16K bytes, 32bit aligment //0x4000 228 229 //------------------------------------------------------------------------------------------------- 230 // Type and Structure 231 //------------------------------------------------------------------------------------------------- 232 233 // Software 234 #define REG_PIDFLT_BASE (0x00210000UL << 1UL) // Fit the size of REG32 235 #define REG_SECFLT_BASE (0x00211000UL << 1UL) // Fix the size of REG32 236 237 #define REG_CTRL_BASE (0x2A00UL) // 0xBF800000+(1500/2)*4 238 #define REG_CTRL_BASE_TS3 (0xC1400UL) // 0xBF800000+(60A00/2)*4 239 #define REG_CTRL_MMFIBASE (0x3900UL) // 0xBF800000+(1C80/2)*4 (TSP2: debug table) 240 241 typedef struct _REG32 242 { 243 volatile MS_U16 L; 244 volatile MS_U16 empty_L; 245 volatile MS_U16 H; 246 volatile MS_U16 empty_H; 247 } REG32; 248 249 typedef struct _REG32_L 250 { 251 volatile MS_U32 data; 252 volatile MS_U32 _resv; 253 } REG32_L; 254 255 typedef struct _REG16 256 { 257 volatile MS_U16 u16data; 258 volatile MS_U16 _null; 259 } REG16; 260 261 typedef REG32 REG_PidFlt; 262 263 // PID 264 #define TSP_PIDFLT_PID_MASK 0x00001FFFUL 265 #define TSP_PIDFLT_PID_SHFT 0UL 266 267 // Section filter Id 268 #define TSP_PIDFLT_SECFLT_MASK 0x001F0000UL // [20:16] secflt id 269 #define TSP_PIDFLT_SECFLT_SHFT 16UL 270 #define TSP_PIDFLT_SECFLT_NULL 0x1FUL // software usage 271 272 // AF/Sec/Video/Audio/Audio-second 273 #define TSP_PIDFLT_OUT_MASK 0x09e02000UL 274 #define TSP_PIDFLT_OUT_SECFLT_AF 0x00002000UL 275 #define TSP_PIDFLT_OUT_NONE 0x00000000UL 276 #define TSP_PIDFLT_OUT_SECFLT 0x00200000UL 277 #define TSP_PIDFLT_OUT_VFIFO 0x00400000UL 278 #define TSP_PIDFLT_OUT_AFIFO 0x00800000UL 279 #define TSP_PIDFLT_OUT_AFIFO2 0x01000000UL 280 #define TSP_PIDFLT_OUT_VFIFO3D 0x08000000UL 281 282 // File/Live 283 #define TSP_PIDFLT_IN_MASK 0x02000000UL 284 #define TSP_PIDFLT_IN_LIVE 0x00000000UL 285 #define TSP_PIDFLT_IN_FILE 0x02000000UL 286 287 // note, this bit is only useful for PVR pure pid 288 // use SEC/VIDEO/AUDIO flag is identical to PVR a certain PID 289 #define TSP_PIDFLT_PVR_ENABLE 0x04000000UL 290 291 typedef struct _REG_SecFlt 292 { 293 REG32 Ctrl; 294 // SW flag 295 #define TSP_SECFLT_TYPE_MASK 0x01000007UL 296 #define TSP_SECFLT_TYPE_SHFT 0UL 297 #define TSP_SECFLT_TYPE_SEC 0x00000000UL 298 #define TSP_SECFLT_TYPE_PES 0x00000001UL 299 #define TSP_SECFLT_TYPE_PKT 0x00000002UL 300 #define TSP_SECFLT_TYPE_PCR 0x00000003UL 301 #define TSP_SECFLT_TYPE_TTX 0x00000004UL 302 #define TSP_SECFLT_TYPE_VER 0x00000005UL 303 #define TSP_SECFLT_TYPE_EMM 0x00000006UL 304 #define TSP_SECFLT_TYPE_ECM 0x00000007UL 305 #define TSP_SECFLT_TYPE_SEC_NO_PUSI 0x01000000UL 306 // for TSP_SECFLT_TYPE_PCR 307 #define TSP_SECFLT_PCRRST 0x00000010UL 308 309 // for 310 // TSP_SECFLT_TYPE_SEC 311 // TSP_SECFLT_TYPE_PES 312 // TSP_SECFLT_TYPE_PKT 313 // TSP_SECFLT_TYPE_TTX 314 // TSP_SECFLT_TYPE_OAD 315 #define TSP_SECFLT_MODE_MASK 0x00000030UL // software implementation 316 #define TSP_SECFLT_MODE_SHFT 4UL 317 #define TSP_SECFLT_MODE_CONTI 0x0UL 318 #define TSP_SECFLT_MODE_ONESHOT 0x1UL 319 #define TSP_SECFLT_MODE_CRCCHK 0x2UL 320 #define TSP_SECFLT_MODE_PESSCMCHK 0x3UL //Only for PES type checking SCMB status 321 322 //[NOTE] update section filter 323 // It's not suggestion user update section filter control register 324 // when filter is enable. There may be race condition. Be careful. 325 #define TSP_SECFLT_STATE_MASK 0x000000C0UL // software implementation 326 #define TSP_SECFLT_STATE_SHFT 6UL 327 #define TSP_SECFLT_STATE_OVERFLOW 0x1UL 328 #define TSP_SECFLT_STATE_DISABLE 0x2UL 329 330 REG32 Match[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 331 REG32 Mask[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 332 REG32 BufStart; 333 #define TSP_SECFLT_BUFSTART_MASK 0xFFFFFFFFUL 334 REG32 BufEnd; 335 REG32 BufRead; 336 REG32 BufWrite; 337 REG32 BufCur; 338 339 REG32 RmnReqCnt; 340 #define TSP_SECFLT_OWNER_MASK 0x80000000UL 341 #define TSP_SECFLT_OWNER_SHFT 31UL 342 #define TSP_SECFLT_REQCNT_MASK 0x7FFF0000UL 343 #define TSP_SECFLT_REQCNT_SHFT 16UL 344 #define TSP_SECFLT_RMNCNT_MASK 0x0000FFFFUL 345 #define TSP_SECFLT_RMNCNT_SHFT 0UL 346 347 REG32 CRC32; 348 REG32 NMatch[TSP_FILTER_DEPTH/sizeof(MS_U32)]; 349 REG32 _x50[12]; // (0x210080-0x210050)/4 350 } REG_SecFlt; 351 352 353 typedef struct _REG_Stc 354 { 355 REG32 ML; 356 REG32_L H32; 357 } REG_Stc; 358 359 360 typedef struct _REG_Pid 361 { // Index(word) CPU(byte) Default 362 REG_PidFlt Flt[TSP_PIDFLT_NUM_ALL]; 363 } REG_Pid; 364 365 366 typedef struct _REG_Sec 367 { // Index(word) CPU(byte) Default 368 REG_SecFlt Flt[TSP_SECFLT_NUM]; 369 } REG_Sec; 370 371 372 typedef struct _REG_Ctrl 373 { 374 //---------------------------------------------- 375 // 0xBF802A00 MIPS direct access 376 //---------------------------------------------- 377 // Index(word) CPU(byte) MIPS(0x1500/2+index)*4 378 // only 24 bits supported in PVR address. 8 bytes address 379 REG32 TsRec_Head20; // 0xbf802a00 0x00 //oneway/rw protect 380 #define TSP_HW_PVR_BUF_HEAD20_MASK 0xFFFF0000UL 381 #define TSP_HW_PVR_BUF_HEAD20_SHFT 16UL 382 REG32 TsRec_Head21_Mid20; // 0xbf802a08 0x02 383 #define TSP_HW_PVR_BUF_HEAD21_MASK 0x0000FFFFUL 384 #define TSP_HW_PVR_BUF_HEAD21_SHFT 0UL 385 #define TSP_HW_PVR_BUF_MID20_MASK 0xFFFF0000UL 386 #define TSP_HW_PVR_BUF_MID20_SHFT 16UL 387 REG32 TsRec_Mid21_Tail20; // 0xbf802a10 0x04 388 #define TSP_HW_PVR_BUF_MID21_MASK 0x0000FFFFUL 389 #define TSP_HW_PVR_BUF_MID21_SHFT 0UL 390 #define TSP_HW_PVR_BUF_TAIL20_MASK 0xFFFF0000UL 391 #define TSP_HW_PVR_BUF_TAIL20_SHFT 16UL 392 REG32 TsRec_Tail2_Pcr1; // 0xbf802a18 0x06 393 #define TSP_HW_PVR_BUF_TAIL21_MASK 0x0000FFFFUL 394 #define TSP_HW_PVR_BUF_TAIL21_SHFT 0UL 395 #define TSP_PCR1_L16_MASK 0xFFFF0000UL 396 #define TSP_PCR1_L16_SHFT 16UL 397 REG32 Pcr1; // 0xbf802a20 0x08 398 #define TSP_PCR64_MID32_MASK 0xFFFFFFFFUL //PCR64 Middle 64 399 #define TSP_PCR64_MID32_SHFT 0UL 400 REG32 Pcr64_H; // 0xbf802a28 0x0A 401 #define TSP_PCR64_H16_MASK 0x0000FFFFUL 402 #define TSP_PCR64_H16_SHFT 0UL 403 #define TSP_MOBF_FILE_KEY0_L_MASK 0x001F0000UL //decrypt key 404 #define TSP_MOBF_FILE_KEY0_L_SHIFT 16UL 405 406 REG32 _xbf802a30; //_xbf802a30 0x0C 407 408 REG32 DbgInfo_Ctrl; //_xbf802a38 0x0E 409 #define TSP_DIS_LOCKED_PKT_CNT 0x10000000UL 410 #define TSP_CLR_LOCKED_PKT_CNT 0x20000000UL 411 #define TSP_CLR_AV_PKT_CNT 0x40000000UL 412 413 REG32 _xbf802a40_xbf802a78[8]; // 0xbf802a40-- 0xbf802a78 (0x10 ~ 0x1E) 414 REG32 Pkt_CacheW0; // 0xbf802a80 0x20 415 REG32 Pkt_CacheW1; // 0xbf802a88 0x22 416 REG32 Pkt_CacheW2; // 0xbf802a90 0x24 417 REG32 Pkt_CacheW3; // 0xbf802a98 0x26 418 REG32_L Pkt_CacheIdx; // 0xbf802aa0 0x28 419 REG32 Pkt_DMA; // 0xbf802aa8 0x2a 420 #define TSP_SEC_DMAFIL_NUM_MASK 0x000000FFUL 421 #define TSP_SEC_DMAFIL_NUM_SHIFT 0UL 422 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 423 #define TSP_SEC_DMASRC_OFFSET_SHIFT 8UL 424 #define TSP_SEC_DMASRC_OFFSET_MASK 0x0000FF00UL 425 #define TSP_SEC_DMADES_LEN_MASK 0x00FF0000UL 426 #define TSP_SEC_DMADES_LEN_SHIFT 16UL 427 REG32 Hw_Config0; // 0xbf802ab0 0x2c : HW_Config0~3 (0x2c~0x2d) 428 #define TSP_HW_CFG0_DATA_PORT_EN 0x00000001UL 429 #define TSP_HW_CFG0_TSIFO_SERL 0x00000000UL 430 #define TSP_HW_CFG0_TSIF0_PARL 0x00000002UL 431 #define TSP_HW_CFG0_TSIF0_EXTSYNC 0x00000004UL 432 #define TSP_HW_CFG0_TSIF0_TS_BYPASS 0x00000008UL 433 #define TSP_HW_CFG0_TSIF0_VPID_BYPASS 0x00000010UL 434 #define TSP_HW_CFG0_TSIF0_APID_BYPASS 0x00000020UL 435 #define TSP_HW_CFG0_WB_DMA_RESET 0x00000040UL 436 437 #define TSP_HW_CFG0_PACKET_BUF_SIZE_MASK 0x0000FF00UL 438 #define TSP_HW_CFG0_PACKET_BUF_SIZE_SHIFT 8UL 439 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_MASK 0x00FF0000UL 440 #define TSP_HW_CFG0_PACKET_PIDFLT0_SIZE_SHIFT 16UL 441 #define TSP_HW_CFG0_PACKET_SIZE_MASK 0xFF000000UL 442 #define TSP_HW_CFG0_PACKET_SIZE_SHFT 24UL 443 444 REG32 TSP_DBG_PORT; // 0xbf802ab8 0x2e 445 #define TSP_DBG_FILTER_MATCH0_MASK 0x000000FFUL 446 #define TSP_DBG_FILTER_MATCH0_SHIFT 0UL 447 #define TSP_DBG_FILTER_MATCH1_MASK 0x0000FF00UL 448 #define TSP_DBG_FILTER_MATCH1_SHIFT 8UL 449 #define TSP_DNG_DATA_MASK 0x00FF0000UL 450 #define TSP_DNG_DATA_SHIFT 16UL 451 REG_Stc Pcr; // 0xbf802ac0 0x30 & 0x32 452 453 REG32 Pkt_Info; // 0xbf802ad0 0x34 454 #define TSP_APID_L_MASK 0x000000FFUL 455 #define TSP_APID_L_SHIFT 0UL 456 #define TSP_APID_H_MASK 0x00001F00UL 457 #define TSP_APID_H_SHIFT 8UL 458 #define TSP_PKT_PID_8_12_CP_MASK 0x001F0000UL 459 #define TSP_PKT_PID_8_12_CP_SHIFT 16UL 460 #define TSP_PKT_PRI_MASK 0x00200000UL 461 #define TSP_PKT_PRI_SHIFT 21UL 462 #define TSP_PKT_PLST_MASK 0x00400000UL 463 #define TSP_PKT_PLST_SHIFT 22UL 464 #define TSP_PKT_ERR 0x00800000UL 465 466 REG32 Pkt_Info2; // 0xbf802ad8 0x36 467 #define TSP_PKT_INFO_CC_MASK 0x0000000FUL 468 #define TSP_PKT_INFO_CC_SHFT 0UL 469 #define TSP_PKT_INFO_ADPCNTL_MASK 0x00000030UL 470 #define TSP_PKT_INFO_ADPCNTL_SHFT 4UL 471 #define TSP_PKT_INFO_SCMB 0x000000C0UL 472 #define TSP_PKT_INFO_SCMB_SHFT 6UL 473 #define TSP_PKT_PID_0_7_CP_MASK 0x0000FF00UL 474 #define TSP_PKT_PID_0_7_CP_SHIFT 8UL 475 476 REG32 SwInt_Stat; // 0xbf802ae0 0x38 477 #define TSP_SWINT_INFO_SEC_MASK 0x000000FFUL 478 #define TSP_SWINT_INFO_SEC_SHFT 0UL 479 #define TSP_SWINT_INFO_ENG_MASK 0x0000FF00UL 480 #define TSP_SWINT_INFO_ENG_SHFT 8UL 481 #define TSP_SWINT_STATUS_CMD_MASK 0x7FFF0000UL 482 #define TSP_SWINT_STATUS_CMD_SHFT 16UL 483 #define TSP_SWINT_STATUS_SEC_RDY 0x0001UL 484 #define TSP_SWINT_STATUS_REQ_RDY 0x0002UL 485 #define TSP_SWINT_STATUS_BUF_OVFLOW 0x0006UL 486 #define TSP_SWINT_STATUS_SEC_CRCERR 0x0007UL 487 #define TSP_SWINT_STATUS_SEC_ERROR 0x0008UL 488 #define TSP_SWINT_STATUS_SYNC_LOST 0x0010UL 489 #define TSP_SWINT_STATUS_PKT_OVRUN 0x0020UL 490 #define TSP_SWINT_STATUS_DEBUG 0x0030UL 491 #define TSP_SWINT_CMD_DMA_PAUSE 0x0100UL 492 #define TSP_SWINT_CMD_DMA_RESUME 0x0200UL 493 494 #define TSP_SWINT_STATUS_SEC_GROUP 0x000FUL 495 #define TSP_SWINT_STATUS_GROUP 0x00FFUL 496 #define TSP_SWINT_CMD_GROUP 0x7F00UL 497 #define TSP_SWINT_CMD_STC_UPD 0x0400UL 498 499 #define TSP_SWINT_CTRL_FIRE 0x80000000UL 500 501 REG32 TsDma_Addr; // 0xbf802ae8 0x3a //oneway/rw protect 502 // only 24 bits available for filein length 503 REG32 TsDma_Size; // 0xbf802af0 0x3c 504 REG32 TsDma_Ctrl_CmdQ; // 0xbf802af8 0x3e 505 // file in control 506 #define TSP_TSDMA_CTRL_START 0x00000001UL 507 #define TSP_TSDMA_RDONE 0x00000002UL 508 #define TSP_TSDMA_CTRL_INIT_TRUST_MCU 0x00000004UL 509 #define TSP_TSDMA_CTRL_PESMODE_MASK 0x0000001CUL 510 #define TSP_TSDMA_CTRL_VPES0 0x00000004UL 511 #define TSP_TSDMA_CTRL_APES0 0x00000008UL 512 #define TSP_TSDMA_CTRL_V3DPES0 0x00000020UL //not used 513 #define TSP_TSDMA_STAT_ABORT 0x00000080UL 514 // CmdQ 515 #define TSP_CMDQ_CNT_MASK 0x001F0000UL 516 #define TSP_CMDQ_CNT_SHFT 16UL 517 #define TSP_CMDQ_FULL 0x00400000UL 518 #define TSP_CMDQ_EMPTY 0x00800000UL 519 #define TSP_CMDQ_SIZE 16UL 520 #define TSP_CMDQ_WR_LEVEL_MASK 0x03000000UL 521 #define TSP_CMDQ_WR_LEVEL_SHFT 24UL 522 523 REG32 MCU_Cmd; // 0xbf802b00 0x40 524 #define TSP_MCU_CMD_MASK 0xFF000000UL 525 #define TSP_MCU_CMD_NULL 0x00000000UL 526 #define TSP_MCU_CMD_ALIVE 0x01000000UL 527 #define TSP_MCU_CMD_NMATCH 0x02000000UL 528 #define TSP_MCU_CMD_NMATCH_FLT_MASK 0x000000FFUL 529 #define TSP_MCU_CMD_NMATCH_FLT_SHFT 0x00000000UL 530 #define TSP_MCU_CMD_PCR_GET 0x03000000UL 531 #define TSP_MCU_CMD_VER_RESET 0x04000000UL 532 #define TSP_MCU_CMD_VER_RESET_FLT_MASK 0x000000FFUL 533 #define TSP_MCU_CMD_VER_RESET_FLT_SHFT 0x00000000UL 534 #define TSP_MCU_CMD_MEM_HIGH_ADDR 0x05000000UL 535 #define TSP_MCU_CMD_MEM_LOW_ADDR 0x06000000UL 536 #define TSP_MCU_CMD_MEM_ADDR_SHFT 0x00000000UL 537 #define TSP_MCU_CMD_MEM_ADDR_MASK 0x0000FFFFUL 538 #define TSP_MCU_CMD_VERSION_GET 0x07000000UL 539 #define TSP_MCU_CMD_DBG_MEM 0x08000000UL 540 #define TSP_MCU_CMD_DBG_WORD 0x09000000UL 541 #define TSP_MCU_CMD_SCMSTS_GET 0x0B000000UL 542 #define TSP_MCU_CMD_CTRL_STC_UPDATE 0x0C000000UL 543 #define TSP_MCU_CMD_CTRL_STC1_UPDATE 0x0D000000UL 544 #define TSP_MCU_CMD_CTRL_STC_UPDATE_OPTION_MASK 0x00FF0000UL 545 #define TSP_MCU_CMD_CTRL_STC_UPDATE_ONCE 0x00010000UL 546 #define TSP_MCU_CMD_TEI_COUNT_GET 0x0E000000UL 547 #define TSP_MCU_CMD_TEI_COUNT_SRC_MASK 0x0000FFFFUL 548 #define TSP_MCU_CMD_TEI_COUNT_SRC_LIVE 0x00000000UL 549 #define TSP_MCU_CMD_TEI_COUNT_SRC_FILE 0x00000001UL 550 #define TSP_MCU_CMD_TEI_COUNT_OPTION_MASK 0x00FF0000UL 551 #define TSP_MCU_CMD_TEI_COUNT_OPTION_RESET 0x00800000UL 552 #define TSP_MCU_CMD_DISCONT_COUNT_GET 0x0F000000UL 553 #define TSP_MCU_CMD_DISCONT_COUNT_FLT_MASK 0x0000FFFFUL 554 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_MASK 0x00FF0000UL 555 #define TSP_MCU_CMD_DISCONT_COUNT_OPTION_RESET 0x00800000UL 556 #define TSP_MCU_CMD_SET_STC_OFFSET 0x10000000UL 557 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_MASK 0x00FF0000UL 558 #define TSP_MCU_CMD_SET_STC_OFFSET_OPTION_SHIFT 16UL 559 // #define TSP_MSG_FW_STC_NOSYNC 0x00000001 560 // #define TSP_MSG_FW_STC1_NOSYNC 0x00000002 //[reserved] 561 562 REG32 Hw_Config2; // 0xbf802b08 0x42 563 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_MASK 0x000000FFUL 564 #define TSP_HW_CFG2_PACKET_CHK_SIZE1_SHFT 0UL 565 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_MASK 0x0000FF00UL 566 #define TSP_HW_CFG2_PACKET_SYNCBYTE1_SHFT 8UL 567 #define TSP_HW_CFG2_PACKET_SIZE1_MASK 0x00FF0000UL 568 #define TSP_HW_CFG2_PACKET_SIZE1_SHFT 16UL 569 #define TSP_HW_CFG2_TSIF1_SERL 0x00000000UL 570 #define TSP_HW_CFG2_TSIF1_PARL 0x01000000UL 571 #define TSP_HW_CFG2_TSIF1_EXTSYNC 0x02000000UL 572 #define TSP_HW_CFG2_TS_DATAPORT_EN1 0x04000000UL 573 #define TSP_HW_CFG2_TS_FILE_IN1 0x08000000UL 574 #define TSP_HW_CFG2_TSIF1_TS_BYPASS 0x10000000UL 575 #define TSP_HW_CFG2_TSIF1_VPID_BYPASS 0x20000000UL 576 #define TSP_HW_CFG2_TSIF1_APID_BYPASS 0x40000000UL 577 #define TSP_PIDFLT_SEL_PID0 0x00000000UL 578 #define TSP_PIDFLT_SEL_PID1 0x80000000UL 579 580 REG32 Hw_Config4; // 0xbf802b10 0x44 581 #define TSP_HW_CFG4_PVR_PIDFLT_SEC 0x00000001UL 582 #define TSP_HW_CFG4_PVR_ENABLE 0x00000002UL 583 #define TSP_HW_CFG4_PVR_ENDIAN_BIG 0x00000004UL // 1: record TS to MIU with big endian 584 // 0: record TS to MIU with little endian 585 #define TSP_HW_CFG4_TSIF1_ENABLE 0x00000008UL // 1: enable ts interface 1 and vice versa 586 #define TSP_HW_CFG4_PVR_FLUSH 0x00000010UL // 1: str2mi_wadr <- str2mi_miu_head 587 #define TSP_HW_CFG4_PVRBUF_BYTEORDER_BIG 0x00000020UL // Byte order of 8-byte recoding buffer to MIU. 588 #define TSP_HW_CFG4_PVR_PAUSE 0x00000040UL 589 #define TSP_HW_CFG4_MEMTSDATA_ENDIAN_BIG 0x00000080UL // 32-bit data byte order read from 8x64 FIFO when playing file. 590 591 #define TSP_HW_CFG4_TSIF0_ENABLE 0x00000100UL // 1: enable ts interface 0 and vice versa 592 #define TSP_VALID_FALLING_DETECT 0x00000200UL // Reset bit count when data valid signal of TS interface is low. 593 #define TSP_SYNC_RISING_DETECT 0x00000400UL // Reset bit count on the rising sync signal of TS interface. 594 #define TSP_HW_CFG4_TS_DATA0_SWAP 0x00000800UL // Set 1 to swap the bit order of TS0 DATA bus 595 #define TSP_HW_CFG4_TS_DATA1_SWAP 0x00001000UL // Set 1 to swap the bit order of TS1 DATA bus 596 #define TSP_HW_BD_AUDIO_EN 0x00002000UL 597 #define TSP_HW_TSP2OUTAEON_INT_EN 0x00004000UL // Set 1 to force interrupt to outside AEON 598 #define TSP_HW_HK_INT_FORCE 0x00008000UL // Set 1 to force interrupt to HK_MCU 599 #define TSP_HW_CFG4_BYTE_ADDR_DMA 0x000E0000UL // prevent from byte enable bug 600 #define TSP_HW_CFG4_ALT_TS_SIZE 0x00010000UL // enable TS packets in 204 mode 601 #define TSP_HW_DMA_MODE_MASK 0x00300000UL // Section filter DMA mode, 2'b00: Single.2'b01: Burst 2 bytes.2'b10: Burst 4 bytes.2'b11: Burst 8 bytes. 602 #define TSP_HW_DMA_MODE_SHIFT 20UL 603 #define TSP_HW_CFG4_PS_VID_EN 0x00800000UL // program stream video enable 604 #define TSP_HW_CFG4_PS_AUD_EN 0x01000000UL // program stream audio enable 605 #define TSP_HW_CFG4_APES_ERR_RM_E 0x04000000UL // Set 1 to enable removing APES error packet 606 #define TSP_HW_CFG4_VPES_ERR_RM_EN 0x08000000UL // Set 1 to enable removing VPES error packet 607 #define TSP_HW_CFG4_SEC_ERR_RM_EN 0x10000000UL // Set 1 to enable removing section error packet 608 #define TSP_HW_CFG4_ISYNC_PATCH_EN 0x80000000UL // Set 1 to enable the patch of internal sync in "tsif" 609 610 REG32 NOEA_PC; // 0xbf802b18 0x46 611 REG32 Idr_Ctrl_Addr0; // 0xbf802b20 0x48 612 #define TSP_IDR_START 0x00000001UL 613 #define TSP_IDR_READ 0x00000000UL 614 #define TSP_IDR_WRITE 0x00000002UL 615 #define TSP_IDR_WR_ENDIAN_BIG 0x00000004UL 616 #define TSP_IDR_WR_ADDR_AUTO_INC 0x00000008UL // Set 1 to enable address auto-increment after finishing read/write 617 #define TSP_IDR_WDAT0_TRIG_EN 0x00000010UL // WDAT0_TRIG_EN 618 #define TSP_IDR_MCUWAIT 0x00000020UL 619 #define TSP_IDR_SOFT_RST 0x00000080UL // Set 1 to soft-reset the IND32 module 620 #define TSP_IDR_AUTO_INC_VAL_MASK 0x00000F00UL 621 #define TSP_IDR_AUTO_INC_VAL_SHIFT 8UL 622 #define TSP_IDR_ADDR_MASK0 0xFFFF0000UL 623 #define TSP_IDR_ADDR_SHFT0 16UL 624 REG32 Idr_Addr1_Write0; // 0xbf802b28 0x4a 625 #define TSP_IDR_ADDR_MASK1 0x0000FFFFUL 626 #define TSP_IDR_ADDR_SHFT1 0UL 627 #define TSP_IDR_WRITE_MASK0 0xFFFF0000UL 628 #define TSP_IDR_WRITE_SHFT0 16UL 629 REG32 Idr_Write1_Read0; // 0xbf802b30 0x4c 630 #define TSP_IDR_WRITE_MASK1 0x0000FFFFUL 631 #define TSP_IDR_WRITE_SHFT1 0UL 632 #define TSP_IDR_READ_MASK0 0xFFFF0000UL 633 #define TSP_IDR_READ_SHFT0 16UL 634 REG32 Idr_Read1; // 0xbf802b38 0x4e 635 #define TSP_IDR_READ_MASK1 0x0000FFFFUL 636 #define TSP_IDR_READ_SHFT1 0UL 637 #define TSP_V3D_FIFO_OVERFLOW 0x00200000UL 638 #define TSP_VD_FIFO_OVERFLOW 0x08000000UL 639 #define TSP_AU_FIFO_OVERFLOW 0x20000000UL 640 641 // only 25 bits supported in PVR address. 8 bytes address 642 REG32 TsRec_Head; // 0xbf802b40 0x50 //oneway/rw protect 643 REG32 TsRec_Mid; // 0xbf802b48 0x52 644 REG32 TsRec_Tail; // 0xbf802b50 0x54 645 REG32 TsRec_WPtr; // 0xbf802b58 0x56 646 647 REG32 TSP_DMAWP_BND; // 0xbf802b60 0x58 648 #define TSP_DMAWP_BND_ALI_SHIFT 10UL 649 #define TSP_DMAWP_LBND_MASK 0x0000FFFFUL 650 #define TSP_DMAWP_LBND_SHFT 0UL 651 #define TSP_DMAWP_HBND_MASK 0x0000FFFFUL 652 #define TSP_DMAWP_HBND_SHFT 16UL 653 654 REG32 reg15b4; // 0xbf802b68 0x5a 655 #define TSP_VQ_DMAW_PROTECT_EN 0x00000001UL 656 #define TSP_DMAW_PROTECT_EN 0x00000002UL 657 #define TSP_DMAW_ERRST_CLR 0x00000004UL // Set 1 to clear the error status of DMA write out of bound 658 #define TSP_PVR_TS_HEADER 0x00000008UL // Set 1 to bypass TS header in PIDFLT0 record 659 #define TSP_PVR_FILEIN 0x00000010UL // Set 1 to enable recoding through PIDFLT0 660 #define TSP_REC_ALL_TS 0x00000020UL // Set 1 to enable recoding TS from broadcast source in PIDFLT0 661 #define TSP_REC_ALL_FILE 0x00000040UL // Set 1 to enable recoding TS from file input source in PIDFLT0 662 #define TSP_AVFIFO_RD_EN 0x00000080UL // 0: AFIFO and VFIFO read are connected to MVD and MAD, 1: AFIFO and VFIFO read are controlled by registers (0x15B5[2:0]) 663 #define TSP_AVFIFO_RD 0x00000100UL // If AVFIFO_RD_EN is 1, set to 1, then set to 0 would issue a read strobe to AFIFO or VFIFO 664 #define TSP_AVFIFO_SEL_VIDEO 0x00000000UL 665 #define TSP_AVFIFO_SEL_AUDIO 0x00000200UL 666 #define TSP_NMATCH_DIS 0x00000800UL // Set 1 to disable not match compare function 667 #define TSP_REC_DATA_INV_EN 0x00001000UL // Set 1 to enable data payload invert for PVR record 668 #define TSP_PLY_FILE_INV_EN 0x00002000UL // Set 1 to enable data payload invert in pidflt0 file path 669 #define TSP_PLY_TS_INV_EN 0x00004000UL // Set 1 to enable data payload invert in pidflt0 TS path 670 #define TSP_BYTE_TIMER_EN 0x00008000UL // Set 1 to enable byte timer in ts_if0 TS path 671 #define TSP_STR2MI_MIU_PINPON_EN 0x00010000UL // Set 1 to enable MIU addresses with pinpon mode 672 #define TSP_REG_REC_PID_EN 0x00020000UL // Set 1 to record max 24 pid and ignore a/v/sec/adp flag. 673 #define TSP_TEI_SKIPE_PKT_PID0 0x00040000UL // Set 1 to skip error packets in pidflt0 TS path 674 #define TSP_TEI_SKIPE_PKT_FILE 0x00080000UL // Set 1 to skip error packets in pidflt0 file path 675 #define TSP_TEI_SKIPE_PKT_PID1 0x00100000UL // Set 1 to skip error packets in pidflt1 TS path 676 #define TSP_cnt_33b_ld 0x01000000UL // Set 1 to load cnt_33b 677 #define TSP_force_syncbyte 0x02000000UL // Set 1 to force sync byte (8'h47) in ts_if0 and ts_if1 path. 678 #define TSP_serial_ext_sync_1t 0x04000000UL // Set 1 to detect serial-in sync without 8-cycle mode 679 #define TSP_burst_len_MASK 0x18000000UL // 00,01: burst length = 4; 10,11: burst length = 1 680 #define TSP_burst_len_SHIFT 27UL 681 #define TSP_match_pid_num_ld 0x20000000UL // Set 1 to load match pid number 682 #define TSP_match_pid_scr_ts_ld 0x40000000UL // Set 1 to load match pid number with scramble information from FILE PIDFLT 683 #define TSP_match_pid_scr_fi_ld 0x80000000UL // Set 1 to load match pid number with scramble information from TS PIDFLT 684 685 REG32 TSP_MATCH_PID_NUM; // 0xbf802b70 0x5c 686 REG32 TSP_IWB_WAIT; // 0xbf802b78 0x5e // Wait count settings for IWB when TSP CPU i-cache is enabled. 687 688 REG32 Cpu_Base; // 0xbf802b80 0x60 //oneway/rw protect 689 #define TSP_CPU_BASE_ADDR_MASK 0x03FFFFFFUL 690 REG32 Qmem_Ibase; // 0xbf802b88 0x62 691 REG32 Qmem_Imask; // 0xbf802b90 0x64 692 REG32 Qmem_Dbase; // 0xbf802b98 0x66 693 REG32 Qmem_Dmask; // 0xbf802ba0 0x68 694 695 REG32 TSP_Debug; // 0xbf802ba8 0x6a 696 #define TSP_DEBUG_MASK 0x00FFFFFFUL 697 698 REG32 TsFileIn_WPtr; // 0xbf802bb0 0x6c, bit0~bit24 699 REG32 TsFileIn_RPtr; // 0xbf802bb8 0x6e 700 REG32 TsFileIn_Timer; // 0xbf802bc0 0x70 701 REG32 TsFileIn_Head; // 0xbf802bc8 0x72, bit0~bit24 702 REG32 TsFileIn_Mid; // 0xbf802bd0 0x74 703 REG32 TsFileIn_Tail; // 0xbf802bd8 0x76 704 705 REG32 Dnld_Ctrl; // 0xbf802be0 0x78, miu address 706 #define TSP_DNLD_ADDR_MASK 0x0000FFFFUL 707 #define TSP_DNLD_ADDR_SHFT 0UL 708 #define TSP_DNLD_ADDR_ALI_SHIFT 4UL //Bit [11:4] of DMA_RADDR[19:0] 709 #define TSP_DNLD_NUM_MASK 0xFFFF0000UL 710 #define TSP_DNLD_NUM_SHFT 16UL 711 712 REG32 TSP_Ctrl; // 0xbf802be8 0x7a 713 #define TSP_CTRL_CPU_EN 0x00000001UL 714 #define TSP_CTRL_SW_RST 0x00000002UL 715 #define TSP_CTRL_DNLD_START 0x00000004UL 716 #define TSP_CTRL_DNLD_DONE 0x00000008UL // see 0x78 for related information 717 #define TSP_CTRL_TSFILE_EN 0x00000010UL 718 #define TSP_CTRL_R_PRIO 0x00000020UL 719 #define TSP_CTRL_W_PRIO 0x00000040UL 720 #define TSP_CTRL_IF0_PAD_SHIFT 7UL 721 #define TSP_CTRL_IF0_PAD0_SEL 0x00000000UL 722 #define TSP_CTRL_IF0_PAD1_SEL 0x00000080UL 723 #define TSP_CTRL_ICACHE_EN 0x00000100UL 724 #define TSP_CTRL_CPU2MI_R_PRIO 0x00000400UL 725 #define TSP_CTRL_CPU2MI_W_PRIO 0x00000800UL 726 #define TSP_CTRL_I_EL 0x00000000UL 727 #define TSP_CTRL_I_BL 0x00001000UL 728 #define TSP_CTRL_D_EL 0x00000000UL 729 #define TSP_CTRL_D_BL 0x00002000UL 730 731 REG32 PKT_CNT; // 0xbf802bf0 0x7c 732 #define TSP_PKT_CNT_MASK 0x000000FFUL 733 #define TSP_DBG_SEL_MASK 0xFFFF0000UL 734 #define TSP_DBG_SEL_SHIFT 16UL 735 736 REG16 HwInt_Stat; // 0xbf802bf8 0x7e 737 #define TSP_HWINT_STATUS_MASK 0xFF00UL // Tsp2hk_int enable bits. 738 #define TSP_HWINT_TSP_PVR_TAIL0_STATUS 0x0100UL 739 #define TSP_HWINT_TSP_PVR_MID0_STATUS 0x0200UL 740 #define TSP_HWINT_TSP_PVR_TAIL1_STATUS 0x0100UL 741 #define TSP_HWINT_TSP_PVR_MID1_STATUS 0x0200UL 742 #define TSP_HWINT_TSP_HK_INT_FORCE_STATUS 0x0400UL 743 #define TSP_HWINT_TSP_FILEIN_MID_INT_STATUS 0x0800UL 744 #define TSP_HWINT_TSP_FILEIN_TAIL_INT_STATUS 0x1000UL 745 #define TSP_HWINT_TSP_SW_INT_STATUS 0x2000UL 746 #define TSP_HWINT_TSP_DMA_READ_DONE 0x4000UL 747 #define TSP_HWINT_TSP_AV_PKT_ERR 0x8000UL 748 749 #define TSP_HWINT_HW_PVR_MASK (TSP_HWINT_TSP_PVR_TAIL0_STATUS|TSP_HWINT_TSP_PVR_TAIL1_STATUS) 750 #define TSP_HWINT_ALL (TSP_HWINT_TSP_SW_INT_STATUS|TSP_HWINT_HW_PVR_MASK) 751 752 REG16 TSP_Ctrl1; // 0xbf802bfc 0x7f 753 #define TSP_CTRL1_FILEIN_TIMER_ENABLE 0x0001UL 754 #define TSP_CTRL1_TSP_FILE_NON_STOP 0x0002UL //Set 1 to enable TSP file data read without timer check 755 #define TSP_CTRL1_FILEIN_PAUSE 0x0004UL 756 #define TSP_CTRL1_FILE_CHECK_WP 0x0008UL 757 #define TSP_CTRL1_FILE_CHECK_WP_8x8 0x0040UL // Select read threshold when playing back TS file to be at least 8x8 bytes 758 #define TSP_CTRL1_STANDBY 0x0080UL 759 #define TSP_CTRL1_INT2NOEA 0x0100UL 760 #define TSP_CTRL1_FILEIN_ENABLE 0x0200UL 761 #define TSP_CTRL1_FORCE_XIU_WRDY 0x0400UL 762 #define TSP_CTRL1_CMDQ_RESET 0x0800UL 763 #define TSP_CTRL1_DLEND_EN 0x1000UL // Set 1 to enable little-endian mode in TSP CPU 764 #define TSP_CTRL1_PVR_CMD_QUEUE_ENABLE 0x2000UL 765 #define TSP_CTRL1_FILE_WP_LOAD 0x4000UL 766 #define TSP_CTRL1_DMA_RST 0x8000UL 767 768 //---------------------------------------------- 769 // 0xBF802C00 MIPS direct access 770 //---------------------------------------------- 771 REG32 MCU_Data0; // 0xbf802c00 0x00 772 #define TSP_MCU_DATA_ALIVE TSP_MCU_CMD_ALIVE 773 774 REG32 LPcr1; // 0xbf802c08 0x02 775 REG32 LPcr2; // 0xbf802c10 0x04 776 REG32 reg160C; // 0xbf802c18 0x06 777 #define TSP_LPCR1_WLD 0x00000001UL // Set 1 to load LPCR1 value 778 #define TSP_LPCR1_RLD 0x00000002UL // Set 1 to read LPCR1 value (Default: 1) 779 #define TSP_LPCR2_WLD 0x00000004UL // Set 1 to load LPCR2 value 780 #define TSP_LPCR2_RLD 0x00000008UL // Set 1 to read LPCR2 value (Default: 1) 781 #define TSP_RECORD192_EN 0x00000010UL // 160C bit(5)enable TS packets with 192 bytes on record mode 782 #define TSP_FILEIN192_EN 0x00000020UL // 160C bit(5)enable TS packets with 192 bytes on file-in mode 783 #define TSP_DOUBLE_BUF_EN 0x00000040UL // tsin->pinpon filein->single 784 #define TSP_ORZ_DMAW_PROT_EN 0x00000080UL // 160C bit(7) open RISC DMA write protection 785 #define TSP_CLR_PIDFLT_BYTE_CNT 0x00000100UL // Clear pidflt0_file byte counter 786 #define TSP_WATCH_DOG_EN 0x00000200UL // Set 1 to count watch dog and release blocking scheme on second section interface when meeting timeout 787 #define TSP_BLK_DISABLE 0x00000400UL // Disable blocking scheme for second section interface 788 #define TSP_DOUBLE_BUF_SWITCH 0x00000800UL // tsin->single filein->pinpon 789 #define TSP_DOUBLE_BUF_DESC 0x00004000UL // 160d bit(6) remove buffer limitation 790 #define TSP_TIMESTAMP_RESET 0x00008000UL // 160d bit(7) reset timestamp 791 #define TSP_DIS_MIU_RQ 0x00100000UL // Disable miu R/W request for reset TSP usage 792 #define TSP_GDMA2WBSRAM_EN 0x00200000UL // Enable GDMA bridge for boot from SPI 793 #define TSP_GDMA2WBSRAM_ENDIAN_BIG 0x00400000UL // Byte order of 4-byte GDMA to QMEM. 794 #define TSP_RM_DMA_GLITCH 0x00800000UL // Fix sec_dma overflow glitch 795 #define TSP_RESET_VFIFO 0x01000000UL // Reset VFIFO -- ECO Done 796 #define TSP_RESET_AFIFO 0x02000000UL // Reset AFIFO -- ECO Done 797 #define TSP_RESET_VFIFO3D 0x20000000UL 798 #define TSP_REG_RESET_GDMA 0x04000000UL // Set 1 to reset GDMA bridge 799 #define TSP_CLR_ALL_FLT_MATCH 0x08000000UL // Set 1 to clean all flt_match in a packet 800 801 REG32 PktChkSizeFilein; // 0xbf802c20 0x08 802 #define TSP_PKT_SIZE_MASK 0x000000FFUL 803 #define TSP_PKT192_BLK_DIS_FIN 0x00000100UL // Set 1 to disable file-in timestamp block scheme 804 #define TSP_AV_CLR 0x00000200UL // Clear AV FIFO overflow flag and in/out counter 805 #define TSP_HW_STANDBY_MODE 0x00000400UL // Set 1 to disable all SRAM in TSP for low power mode automatically 806 #define TSP_LIVEAB_SEL 0x00010000UL // switch tsif1 to filein 807 #define TSP_CNT_34B_DEFF_EN 0x00020000UL // Switch STC DIFF Mode (Output STC+DIFF to MVD and MAD) 808 #define TSP_DMA_OVERFLOW_MET_SEL 0x00040000UL 809 #define TSP_SYSTIME_MODE_STC64 0x00080000UL 810 #define TSP_SEC_DMA_BURST_EN 0x00800000UL 811 #define TSP_DUP_PKT_SKIP_VD 0x02000000UL 812 #define TSP_DUP_PKT_SKIP_V3D 0x04000000UL 813 #define TSP_DUP_PKT_SKIP_AV 0x08000000UL 814 815 REG32 Dnld_Ctrl2; // 0xbf802c28 0x0a 816 #define TSP_DNLD_ADDR_MASK1 0x001F0000UL 817 #define TSP_DNLD_ADDR_SHFT1 16UL 818 #define TSP_BLK_AF_SCRMB_BIT 0x00000400UL // Set 1 to block update pids to scrmb when the there are only AF in the pkt 819 #define TSP_TSIF0_CLK_STAMP_27_EN 0x00000100UL 820 #define TSP_PVR1_CLK_STAMP_27_EN 0x00000200UL 821 #define TSP_CMQ_WORD_EN 0x00400000UL // Set 1 to access CMDQ related registers in word. 822 #define TSP_NEW_WARB_BURST_MODE_DIS 0x00800000UL 823 #define TSP_V3D_PID_BYPASS 0x08000000UL 824 #define TSP_AVPID_ST_SEL 0x20000000UL 825 #define TSP_AVPID_ST_AV 0x20000000UL 826 #define TSP_AVPID_ST_AU2V3D 0x00000000UL 827 #define TSP_PS_VID3D_EN 0x40000000UL 828 #define TSP_PREVENT_OVF_META 0x80000000UL 829 830 REG32 TsPidScmbStatTsin; // 0xbf802c30 0x0c 831 REG32 TsPidScmbStatFile; // 0xbf802c38 0x0e 832 REG32 _xbf802c40_xbf802c70[7]; // 0xbf802c40-0xbf802c70 0x10-0x1C -reserved 833 834 REG32 DbgInfo_Ctrl1; //0xbf802c78 0x1E 835 #define TSP_CLR_SRC_MASK 0x00070000UL 836 #define TSP_CLR_SRC_SHIFT 16UL 837 #define TSP_CLR_DISCINT_SRC_CH0 0x00010000UL 838 #define TSP_CLR_DISCINT_SRC_CHFILE 0x00020000UL 839 #define TSP_DISCONTI_VD_CLR 0x00080000UL 840 #define TSP_DISCONTI_V3D_CLR 0x00100000UL 841 #define TSP_DISCONTI_AUD_CLR 0x00200000UL 842 #define TSP_SRAM_COLLISION_CLR 0x02000000UL 843 844 REG32 VQ0_BASE; // 0x3a2c80 0x20 845 #define TSP_VQ0_BASE_MASK 0x03FFFFFFUL 846 REG32 VQ0_CTRL; // 0x3a2c88 0x22 847 #define TSP_VQ0_SIZE_192PK_MASK 0x0000FFFFUL 848 #define TSP_VQ0_SIZE_192PK_SHIFT 0UL 849 #define TSP_VQ0_WR_THRESHOLD_MASK 0x000F0000UL 850 #define TSP_VQ0_WR_THRESHOLD_SHIFT 16UL 851 #define TSP_VQ0_PRIORTY_THRESHOLD_MASK 0x00F00000UL 852 #define TSP_VQ0_PRIORTY_THRESHOL_SHIFT 20UL 853 #define TSP_VQ0_FORCE_FIRE_CNT_1K_MASK 0x0F000000UL 854 #define TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT 24UL 855 #define TSP_VQ0_RESET 0x10000000UL 856 #define TSP_VQ0_OVERFLOW_INT_EN 0x40000000UL // Enable the interrupt for overflow happened on Virtual Queue path 857 #define TSP_VQ0_CLR_OVERFLOW_INT 0x80000000UL // Clear the interrupt and the overflow flag 858 REG32 VQ0_STATUS; // 0x3a2c90 0x24 859 #define TSP_VQ0_STATUS_MASK 0x0000FFFFUL 860 #define TSP_VQ0_STATUS_SHIFT 0UL 861 #define TSP_VQ0_EN 0x00010000UL 862 #define TSP_REQ_VQ_RX_THRESHOLD_MASKE 0x00060000UL 863 #define TSP_REQ_VQ_RX_THRESHOLD_SHIFT 17UL 864 #define TSP_REQ_VQ_RX_THRESHOLD_LEN1 0x00000000UL 865 #define TSP_REQ_VQ_RX_THRESHOLD_LEN2 0x00020000UL 866 #define TSP_REQ_VQ_RX_THRESHOLD_LEN4 0x00040000UL 867 #define TSP_REQ_VQ_RX_THRESHOLD_LEN8 0x00060000UL 868 #define TSP_VQ_FILE_EN 0x00100000UL 869 #define TSP_VQ_PINGPONG_EN 0x00200000UL 870 871 REG32 _xbf802c98_xbf802ce0[10]; // 0xbf802c98-0xbf802ce0 0x26-0x38 -reserved 872 REG32 DMAW1_1; // 0xbf802ce8 0x3a 873 #define TSP_DMAW1_ALI_SHIFT 10UL 874 #define TSP_DMAW1_LBND_MASK1 0x0000FFFFUL 875 #define TSP_DMAW1_LBND_SHIFT1 0UL 876 #define TSP_DMAW1_UBND_MASK1 0x0000FFFFUL 877 #define TSP_DMAW1_UBND_SHIFT1 16UL 878 REG32 DMAW2_1; // 0xbf802cf0 0x3c 879 #define TSP_DMAW2_ALI_SHIFT 10UL 880 #define TSP_DMAW2_LBND_MASK1 0x0000FFFFUL 881 #define TSP_DMAW2_LBND_SHIFT1 0UL 882 #define TSP_DMAW2_UBND_MASK1 0x0000FFFFUL 883 #define TSP_DMAW2_UBND_SHIFT1 16UL 884 REG32 ORZ_DMAW; // 0xbf802cf8 0x3e 885 #define TSP_ORZ_ALI_SHIFT 2UL 886 #define TSP_ORZ_DMAW_LBND 0x0000ffffUL 887 #define TSP_ORZ_DMAW_UBND 0xffff0000UL 888 #define TSP_ORZ_DMAW_UBND_SHIFT 16UL 889 890 REG32_L CA_CTRL; // 0xbf802d00 0x40 891 #define TSP_CA_CTRL_MASK 0x000000ffUL 892 #define TSP_CA_INPUT_TSIF0_LIVEIN 0x00000001UL 893 #define TSP_CA_INPUT_TSIF0_FILEIN 0x00000002UL 894 #define TSP_CA_INPUT_TSIF1 0x00000004UL 895 #define TSP_CA_AVPAUSE 0x00000008UL 896 #define TSP_CA_OUTPUT_PLAY_LIVE 0x00000010UL 897 #define TSP_CA_OUTPUT_PLAY_FILE 0x00000020UL 898 #define TSP_CA_OUTPUT_REC 0x00000040UL 899 900 REG32 REG_ONEWAY; // 0xbf802d08 0x42 901 #define TSP_ONEWAY_REC_DISABLE 0x00000001UL //Disable record descrambled stream 902 #define TSP_ONEWAY_PVR_PORT 0x00000002UL //PVR buffer registers are oneway 903 #define TSP_ONEWAY_FW_PORT 0x00000004UL //Orz fw buffer registers are oneway 904 #define TSP_ONEWAY_QMEM_PORT 0x00000008UL //QMEM registers are oneway 905 906 REG32 _xbf802d10_xbf802d48[8]; // 0xbf802d10 -0xbf802d48 0x44-0x52 -reserved 907 REG32 MOBF_PVR_KEY; // 0xbf802d50 0x54 908 #define TSP_MOBF_PVR_KEY0_MASK 0x00FF0000UL 909 #define TSP_MOBF_PVR_KEY0_SHIFT 16UL 910 #define TSP_MOBF_PVR_KEY1_MASK 0xFF000000UL 911 #define TSP_MOBF_PVR_KEY1_SHIFT 24UL 912 913 REG32 VQ1_Base; // 0xbf802d58 0x56 914 915 REG32 _xbf802d60_xbf802d68[2]; // 0xbf802d60 -0xbf802d68 0x58 -0x5a -reserved 916 917 REG32 VQ1_Size; // 0xbf802d70 0x5C 918 #define TSP_VQ1_SIZE_192BYTE_MASK 0xffff0000UL 919 #define TSP_VQ1_SIZE_192BYTE_SHIFT 16UL 920 921 REG32 VQ1_Config; // 0xbf802d78 0x5e 922 #define TSP_VQ1_WR_THRESHOLD_MASK 0x0000000FUL 923 #define TSP_VQ1_WR_THRESHOLD_SHIFT 0UL 924 #define TSP_VQ1_PRI_THRESHOLD_MASK 0x000000F0UL 925 #define TSP_VQ1_PRI_THRESHOLD_SHIFT 4UL 926 #define TSP_VQ1_FORCEFIRE_CNT_1K_MASK 0x00000F00UL 927 #define TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT 8UL 928 #define TSP_VQ1_RESET 0x00001000UL 929 #define TSP_VQ1_OVF_INT_EN 0x00004000UL 930 #define TSP_VQ1_CLR_OVF_INT 0x00008000UL 931 932 REG32 reg16C0; // 0xbf802d80 0x60 933 #define TSP_ORZ_DMAW_LBND_LSB8 0x000000ffUL 934 #define TSP_ORZ_DMAW_UBND_LSB8 0x0000ff00UL 935 #define TSP_ORZ_DMAW_UBND_LSB8_SHIFT 8UL 936 #define TSP_ORZ_DMAW_BND_ALT_SHIFT 2UL 937 #define TSP_TS_WATCH_DOG_MASK 0xFFFF0000UL 938 #define TSP_TS_WATCH_DOG_SHIFT 16UL 939 940 REG32 reg16C4; // 0xbf802d88 0x62 941 #define TSP_DMAW_BND_ALI_SHIFT 2UL 942 #define TSP_DMAW_LBND_LSB8 0x000000ffUL 943 #define TSP_DMAW_UBND_LSB8 0x0000ff00UL 944 #define TSP_DMAW_UBND_LSB8_SHIFT 8UL 945 REG32 reg16C8; // 0xbf802d90 0x64 946 #define TSP_DMAW1_BND_ALI_SHIFT 2UL 947 #define TSP_DMAW1_LBND_LSB8 0x000000ffUL 948 #define TSP_DMAW1_UBND_LSB8 0x0000ff00UL 949 #define TSP_DMAW1_UBND_LSB8_SHIFT 8UL 950 REG32 reg16CC; // 0xbf802d98 0x66 951 #define TSP_DMAW2_BND_ALI_SHIFT 2UL 952 #define TSP_DMAW2_LBND_LSB8 0x000000ffUL 953 #define TSP_DMAW2_UBND_LSB8 0x0000ff00UL 954 #define TSP_DMAW2_UBND_LSB8_SHIFT 8UL 955 REG32 _xbf802da0_xbf802da8[2]; // 0xbf802da0 -0xbf802da8 0x68-0x6a -reserved 956 REG16 SwInt_Stat1_L; // 0xbf802dB0 0x6c 957 #define TSP_HWINT2_EN_MASK 0x00FFUL 958 #define TSP_HWINT2_STATUS_MASK 0xFF00UL 959 #define TSP_HWINT2_STATUS_SHIFT 8UL 960 #define TSP_HWINT2_DMA_WPR_STATUS 0x0100UL 961 #define TSP_HWINT2_ORZ_WPR_STATUS 0x0200UL 962 #define TSP_HWINT2_VQ_OVERFLOW_STATUS 0x1000UL 963 964 REG16 SwInt_Stat1_M; 965 REG32 SwInt_Stat1_H; // 0xbf802dB8 0x6e 966 #define TSP_SWINT1_H_SHFT 0UL 967 #define TSP_SWINT1_H_MASK 0x0000FFFFUL 968 969 REG32 TimeStamp_FileIn; // 0xbf802dC0 0x70 970 971 REG32 HW2_Config3; // 0xbf802dC0 0x72 972 #define TSP_RM_OVERFLOW_GLITCH 0x00000008UL 973 #define TSP_DUP_PKT_CNT_CLR 0x00000040UL 974 #define TSP_REC_AT_SYNC_DIS 0x00000100UL 975 #define TSP_PVR_ALIGN_EN 0x00000200UL 976 #define TSP_FORCE_SYNC_EN 0x00000400UL 977 #define TSP_DMA_FLUSH_EN 0x00040000UL 978 #define TSP_STR2MI_WP_LD 0x00080000UL 979 #define TSP_CLR_SEC_DMAW_OVERFLOW 0x10000000UL 980 #define TSP_PUSI_3BYTE_MODE 0x40000000UL // set 1 to set pusi flag only in first 3 byte of the payload 981 982 REG32 DMAW3_LBND; // 0xbf802dC0 0x74, MIU Address 3 of the lower bound of DMA write protection when REG15B4[1] is 1 983 REG32 DMAW3_UBND; // 0xbf802dC0 0x76, MIU Address 3 of the upper bound of DMA write protection when REG15B4[1] is 1 984 #define TSP_DMAW3_BND_ALI_SHIFT 2UL 985 #define TSP_DMAW3_LBND_MASK 0x00FFFFFFUL 986 #define TSP_DMAW3_UBND_MASK 0x00FFFFFFUL 987 REG32 DMAW4_LBND; // 0xbf802dC0 0x78, MIU Address 4 of the lower bound of DMA write protection when REG15B4[1] is 1 988 REG32 DMAW4_UBND; // 0xbf802dC0 0x7a, MIU Address 4 of the upper bound of DMA write protection when REG15B4[1] is 1 989 #define TSP_DMAW4_BND_ALI_SHIFT 2UL 990 #define TSP_DMAW4_LBND_MASK 0x00FFFFFFUL 991 #define TSP_DMAW4_UBND_MASK 0x00FFFFFFUL 992 REG32 MCU_Data1; // 0xbf802dC0 0x7C 993 } REG_Ctrl; 994 995 // TSP part 2 996 typedef struct _REG_Ctrl2 997 { 998 REG16 Overflow0; // 0xbf803900 0x40 999 #define AFIFO_EVER_OVERFLOW 0x0020UL 1000 #define VFIFO_EVER_OVERFLOW 0x0080UL 1001 #define V3DFIFO_EVER_OVERFLOW 0x0100UL 1002 #define PVR_1_EVER_OVERFLOW 0x0200UL 1003 #define VQ_TX0_EVER_OVERFLOW 0x1000UL 1004 #define VQ_TX1_EVER_OVERFLOW 0x2000UL 1005 1006 REG16 Overflow1; // 0xbf803904 0x41 1007 #define SEC_PINGPONG_EVER_OVERFLOW 0x0001UL 1008 #define SEC_SINGLE_EVER_OVERFLOW 0x0002UL 1009 #define SEC_DMAW_OVERFLOW 0x0004UL 1010 1011 REG16 FifoStatus; // 0xbf803908 0x42 1012 #define AFIFO_STATUS_MASK 0x000FUL 1013 #define AFIFO_STATUS_SHFT 0UL 1014 #define VFIFO_STATUS_MASK 0x0F00UL 1015 #define VFIFO_STATUS_SHFT 8UL 1016 #define V3DFIFO_STATUS_MASK 0xF000UL 1017 #define V3DFIFO_STATUS_SHFT 12UL 1018 1019 REG16 PvrFifoStatus; // 0xbf80390C 0x43 1020 #define PVR_1_STATUS_MASK 0x000FUL 1021 #define PVR_1_STATUS_SHFT 0UL 1022 1023 REG16 VQTxFifoStatus; // 0xbf803910 0x44 1024 #define VQ_TX0_STATUS_MASK 0x000FUL 1025 #define VQ_TX0_STATUS_SHFT 0UL 1026 #define VQ_TX1_STATUS_MASK 0x0F00UL 1027 #define VQ_TX1_STATUS_SHFT 8UL 1028 1029 REG16 PktCnt_TS0; // 0xbf803914 0x45 1030 REG16 PktCnt_TS1; // 0xbf803918 0x46 1031 REG16 PktCnt_TS2; // 0xbf80391C 0x47 1032 REG16 PktCnt_File; // 0xbf803920 0x48 1033 #define DISCONTI_CNT_AUDIO_MASK 0x000FUL 1034 #define DISCONTI_CNT_AUDIO_SHFT 0UL 1035 #define DISCONTI_CNT_VIDEO_MASK 0x0F00UL 1036 #define DISCONTI_CNT_VIDEO_SHFT 8UL 1037 #define DISCONTI_CNT_V3D_MASK 0xF000UL 1038 #define DISCONTI_CNT_V3D_SHFT 12UL 1039 1040 #define DROP_CNT_AUDIO_MASK 0x000FUL 1041 #define DROP_CNT_AUDIO_SHFT 0UL 1042 #define DROP_CNT_VIDEO_MASK 0x0F00UL 1043 #define DROP_CNT_VIDEO_SHFT 8UL 1044 #define DROP_CNT_V3D_MASK 0xF000UL 1045 #define DROP_CNT_V3D_SHFT 12UL 1046 1047 REG16 LockPktCnt; // 0xbf803924 0x49 1048 #define TS0_LOCK_CNT_MASK 0x000FUL 1049 #define TS0_LOCK_CNT_SHFT 0UL 1050 #define TS1_LOCK_CNT_MASK 0x00F0UL 1051 #define TS1_LOCK_CNT_SHFT 4UL 1052 #define TSCB_LOCK_CNT_MASK 0xF000UL 1053 #define TSCB_LOCK_CNT_SHFT 12UL 1054 1055 REG16 AVPktCnt; // 0xbf803928 0x4A 1056 #define VIDEO_PKT_CNT_MASK 0x000FUL 1057 #define VIDEO_PKT_CNT_SHFT 0UL 1058 #define AUDIO_PKT_CNT_MASK 0x00F0UL 1059 #define AUDIO_PKT_CNT_SHFT 4UL 1060 1061 1062 REG16 PktErrStatus; // 0xbf80392C 0x4B 1063 REG16 PidMatched0; // 0xbf803930 0x4C 1064 REG16 PidMatched1; // 0xbf803934 0x4D 1065 REG16 PidMatched2; // 0xbf803938 0x4E 1066 REG16 PidMatched3; // 0xbf80393C 0x4F 1067 1068 REG16 Sram_Collision; // 0xbf803940 0x50 1069 1070 REG16 dummy_0x51_0x6F[0x70-0x51]; // 0xbf803998 0x51 ~6F 1071 1072 REG32 Qmem_Config; // 0xbf8039FC 0x70 1073 #define TSP_QMEM_DBG_MODE 0x00000001UL 1074 #define TSP_TSP_SEL_SRAM 0x00000002UL 1075 #define TSP_QMEM_DBG_RADDR 0xFFFF0000UL 1076 1077 REG32 Qmem_Dbg_Rd; // 0xbf8039FC 0x72 1078 1079 REG16 dummy_0x74_0x76[0x77-0x74]; // 0xbf803998 0x74 ~77 1080 1081 REG16 HwCfg0; // 0x77 1082 #define TSP_TSIFCFG_WB_FSM_RESET 0x0001UL 1083 #define TSP_TSIFCFG_WB_FSM_RESET_FINISH 0x0002UL 1084 1085 #define MASK_SCR_VID_EN 0x0004UL 1086 #define MASK_SCR_VID_3D_EN 0x0008UL 1087 #define MASK_SCR_AUD_EN 0x0010UL 1088 #define MASK_SCR_PVR1_EN 0x0040UL 1089 #define PREVENT_SRAM_COLLISION 0x0080UL 1090 1091 #define TSP_3WIRE_SERIAL_MODE_MASK 0x0300UL //set 1 to enable 3 wire serial in mode: Combine valid and clk.Valid always 1 and gated clk when no data in 1092 #define TSP_3WIRE_SERIAL_TSIF0 0x0100UL 1093 #define TSP_3WIRE_SERIAL_TSIF1 0x0200UL 1094 1095 REG16 HwCfg1; // 0x78 1096 #define NEW_OVERFLOW_MODE 0x0001UL 1097 #define AF_PKT_LOSS_BYTE_ECO 0x0004UL // reg_adp_sel_sync_byte_cnt_out_en .issue befor:use section mode get AF only pkt may loss one byte 1098 #define FIX_PINPON_SYNC_IN_ECO 0x0008UL // if enable, overflow flag will be clear after dma_abort and buffer not full. if disable, overflow flag will be clear once buffer un-full. 1099 #define DMA_WADDR_INC_NEW_MODE 0x0010UL // default 0 1100 #define DIS_CNT_INC_BY_PAYLOAD 0x0040UL 1101 #define UPDATE_SCRAMBLE_PID_PUSI 0x0080UL 1102 REG16 dummy_0x79_0x7E[0x7f-0x79]; 1103 REG16 HwCfg2; // 0xbf8039FC 0x7F 1104 #define HW_INFO_SRC_MODE_MASK 0x0003UL 1105 #define REG_SRC_SEL 0x0001UL 1106 #define REG_DROP_PKT_MODE 0x0002UL 1107 #define REG_RST_CC_MODE 0x0004UL 1108 1109 } REG_Ctrl2; 1110 1111 // TSP part 3 1112 typedef struct _REG_Ctrl3 1113 { 1114 REG32 ReSample_Config; // 0xbf8C1400 0x00 1115 #define TSP_RESAMPLE_EN 0x00000001UL 1116 #define TSP_TS_SOURCE_MASK 0x00000006UL 1117 #define TSP_RETURN_STATUS 0x0000FFF8UL 1118 #define TSP_RESAMPLE_CTRL 0xFFFF0000UL 1119 1120 REG32 Clk_Phase; // 0xbf8C1408 0x02 1121 #define TSP_CLK_PHASE 0x000000FFUL 1122 #define TSP_CLK_PHASE_DIFF 0x0000FF00UL 1123 #define TSP_MIN_CLK 0x00FF0000UL 1124 #define TSP_MAX_CLK 0x00FF0000UL 1125 1126 REG32 MaxMin_SyncValid; // 0xbf8C1410 0x04 1127 #define TSP_MIN_SYNC 0x000000FFUL 1128 #define TSP_MAX_SYNC 0x0000FF00UL 1129 #define TSP_MIN_VALID 0x00FF0000UL 1130 #define TSP_MAX_VALID 0xFF000000UL 1131 1132 REG32 MaxMin_dat0dat1; // 0xbf8C1418 0x06 1133 #define TSP_MIN_DAT0 0x000000FFUL 1134 #define TSP_MAX_DAT0 0x0000FF00UL 1135 #define TSP_MIN_DAT1 0x00FF0000UL 1136 #define TSP_MAX_DAT1 0xFF000000UL 1137 1138 REG32 MaxMin_dat2dat3; // 0xbf8C1420 0x08 1139 #define TSP_MIN_DAT2 0x000000FFUL 1140 #define TSP_MAX_DAT2 0x0000FF00UL 1141 #define TSP_MIN_DAT3 0x00FF0000UL 1142 #define TSP_MAX_DAT3 0xFF000000UL 1143 1144 REG32 MaxMin_dat4dat5; // 0xbf8C1428 0x0A 1145 #define TSP_MIN_DAT4 0x000000FFUL 1146 #define TSP_MAX_DAT4 0x0000FF00UL 1147 #define TSP_MIN_DAT5 0x00FF0000UL 1148 #define TSP_MAX_DAT5 0xFF000000UL 1149 1150 REG32 MaxMin_dat6dat7; // 0xbf8C1430 0x0C 1151 #define TSP_MIN_DAT6 0x000000FFUL 1152 #define TSP_MAX_DAT6 0x0000FF00UL 1153 #define TSP_MIN_DAT7 0x00FF0000UL 1154 #define TSP_MAX_DAT7 0xFF000000UL 1155 1156 REG32 _xbf8C1438_xbf8C1478[9]; // 0xbf8C1438 - 0xbf8C1478 0x0E-0x1E -reserved 1157 1158 REG32 Hw_Semaphore0; // 0xbf8C1480 0x20 1159 #define TSP_HW_SEMAPHORE0 0x0000FFFFUL 1160 #define TSP_HW_SEMAPHORE1 0xFFFF0000UL 1161 1162 REG32 Hw_Semaphore1; // 0xbf8C1488 0x22 1163 #define TSP_HW_SEMAPHORE2 0x0000FFFFUL 1164 #define TSP_TIMESTAMP_ECO 0x04000000UL 1165 REG32 Hw_Config; // 0xbf8C1490 0x24 1166 #define TSP_3WIRE_SERIAL_MODE 0x00FF0000UL 1167 #define TSP_PREVENT_SRAM_COLLISION 0x01000000UL 1168 #define TSP_INIT_TIMESTAMP_FILEIN 0x00010000UL 1169 #define TSP_INIT_TIMESTAMP_MMFI0 0x00020000UL 1170 #define TSP_INIT_TIMESTAMP_MMFI1 0x00040000UL 1171 REG32 Hw_FI_Timestamp; // 0xbf8C1492 0x26 1172 REG32 Hw_MMFI0_Timestamp; // 0x28 1173 REG32 Hw_MMFI1_Timestamp; // 0x2A 1174 REG32 Hw_ECO; // 0x2C 1175 #define TSP_TIMESTAMP_RING 0x00000001UL 1176 #define TSP_LPCR_RING 0x00000002UL 1177 1178 } REG_Ctrl3; 1179 1180 // Firmware status 1181 #define TSP_FW_STATE_MASK 0xFFFF0000UL 1182 #define TSP_FW_STATE_LOAD 0x00010000UL 1183 #define TSP_FW_STATE_ENG_OVRUN 0x00020000UL 1184 #define TSP_FW_STATE_ENG1_OVRUN 0x00040000UL //[reserved] 1185 #define TSP_FW_STATE_IC_ENABLE 0x01000000UL 1186 #define TSP_FW_STATE_DC_ENABLE 0x02000000UL 1187 #define TSP_FW_STATE_IS_ENABLE 0x04000000UL 1188 #define TSP_FW_STATE_DS_ENABLE 0x08000000UL 1189 1190 // TSP AEON specific IP address 1191 #define OPENRISC_IP_1_ADDR 0x00200000UL 1192 #define OPENRISC_IP_1_SIZE 0x00020000UL 1193 #define OPENRISC_IP_2_ADDR 0x90000000UL 1194 #define OPENRISC_IP_2_SIZE 0x00010000UL 1195 #define OPENRISC_IP_3_ADDR 0x40080000UL 1196 #define OPENRISC_IP_3_SIZE 0x00020000UL 1197 #define OPENRISC_QMEM_ADDR 0x00000000UL 1198 #define OPENRISC_QMEM_SIZE 0x00003000UL 1199 1200 #endif // _TSP_REG_H_ 1201 1202