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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // file halTSP.h 97 // @brief Transport Stream Processer (TSP) HAL 98 // @author MStar Semiconductor,Inc. 99 //////////////////////////////////////////////////////////////////////////////////////////////////// 100 #ifndef __HAL_TSP_H__ 101 #define __HAL_TSP_H__ 102 103 #include "MsCommon.h" 104 105 #include "regTSP.h" 106 107 //-------------------------------------------------------------------------------------------------- 108 // Driver Compiler Option 109 //-------------------------------------------------------------------------------------------------- 110 111 //-------------------------------------------------------------------------------------------------- 112 // TSP Hardware Abstraction Layer 113 //-------------------------------------------------------------------------------------------------- 114 115 // TSP Register 116 #define _TspPid ((REG_Pid*)(REG_PIDFLT_BASE)) 117 #define _TspSec ((REG_Sec*)(REG_SECFLT_BASE)) 118 119 #define TSP_HW_CFG_0 0x00 120 #define TSP_HW_CFG_1 0x01 121 #define TSP_HW_CFG_2 0x10 122 #define TSP_HW_CFG_3 0x11 123 124 /// TSP debug mode type 125 typedef enum 126 { 127 TSP_DEBUG_MODE_DIS_CONT, ///< Select dis-continue packet count mode 128 TSP_DEBUG_MODE_DROP_CONT, ///< Select drop packet count mode 129 } TSP_DEBUG_MODE; 130 131 typedef enum 132 { 133 TSP_DEBUG_SRC_TS0, ///< TSP input from TS0 interface 134 TSP_DEBUG_SRC_TS1, ///< TSP input from TS1 interface 135 TSP_DEBUG_SRC_TS2, ///< TSP input from TS2 interface 136 TSP_DEBUG_SRC_FILE, ///< TSP input from filein 137 TSP_DEBUG_SRC_TSCB, ///< TSP input from TSCB 138 } TSP_DEBUG_SRC; 139 140 typedef enum 141 { 142 TSP_DEBUG_FIFO_VIDEO, ///< TSP output to Video FIFO 143 TSP_DEBUG_FIFO_AUDIO, ///< TSP output to Audio FIFO 144 TSP_DEBUG_FIFO_VIDEO3D, ///< TSP output to Video3D FIFO 145 TSP_DEBUG_FIFO_AUDIOB, ///< TSP output to AudioB FIFO 146 } TSP_DEBUG_FIFO; 147 148 typedef enum 149 { 150 TSP_DEBUG_PKT_DEMUX_0, 151 TSP_DEBUG_PKT_DEMUX_0_FILE, 152 TSP_DEBUG_PKT_DEMUX_1, 153 TSP_DEBUG_PKT_DEMUX_2, 154 TSP_DEBUG_MMFI0, 155 TSP_DEBUG_MMFI1, 156 } TSP_DEBUG_FIFO_SRC; 157 158 typedef enum 159 { 160 TSP_DEBUG_TSIF0, ///< TSP output to Video FIFO 161 TSP_DEBUG_TSIF1, ///< TSP output to Audio FIFO 162 TSP_DEBUG_TSIFCB, ///< TSP output to Video3D FIFO 163 } TSP_DEBUG_TSIF; 164 165 typedef enum 166 { 167 TSP_DEBUG_CMD_NONE, ///< TSP debug table cmd: do nothing 168 TSP_DEBUG_CMD_CLEAR, ///< TSP debug table cmd: clear 169 TSP_DEBUG_CMD_ENABLE, ///< TSP debug table cmd: enable 170 TSP_DEBUG_CMD_DISABLE, ///< TSP debug table cmd: disable 171 } TSP_DEBUG_CMD; 172 173 typedef enum 174 { 175 TSP_CLR_SRC_PIDFLT_0 = 0x1, ///< TSP debug table clear source: pidflt 0 176 TSP_CLR_SRC_PIDFLT_FILE = 0x2, ///< TSP debug table clear source: pidflt file 177 } TSP_DEBUG_CLR_SRC; 178 179 //---------------------------------- 180 /// DMX debug table information structure 181 //---------------------------------- 182 typedef struct 183 { 184 TSP_DEBUG_CMD TspCmd; 185 TSP_DEBUG_SRC TspSrc; 186 TSP_DEBUG_FIFO TspFifo; 187 } TSP_DisconPktCnt_Info, TSP_DropPktCnt_Info; 188 189 typedef struct 190 { 191 TSP_DEBUG_CMD TspCmd; 192 TSP_DEBUG_TSIF TspTsif; 193 } TSP_LockPktCnt_info; 194 195 typedef struct 196 { 197 TSP_DEBUG_CMD TspCmd; 198 TSP_DEBUG_FIFO TspFifo; 199 TSP_DEBUG_FIFO_SRC TspFifoSrc; 200 } TSP_AVPktCnt_info; 201 202 //-------------------------------------------------------------------------------------------------- 203 // Macro of bit operations 204 //-------------------------------------------------------------------------------------------------- 205 #define HAS_FLAG(flag, bit) ((flag) & (bit)) 206 #define SET_FLAG(flag, bit) ((flag)|= (bit)) 207 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 208 #define SET_FLAG1(flag, bit) ((flag)| (bit)) 209 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 210 211 // define NULL function 212 #define HAL_TSP_SecFlt_SelSecBuf(pSecFilter, u32BufId, bEnable) 213 #define HAL_TSP_SecFlt_SetEcmIdx(pSecFilter, u32EcmIdx) 214 #define HAL_TSP_SecFlt_ResetEmmIdx(pSecFilter) 215 #define HAL_TSP_SelAudOut(u32EngId) 216 217 //////////////////////////////////////////////// 218 // HAL API 219 //////////////////////////////////////////////// 220 221 #define HAL_TSP_CAP_PID_FILTER_NUM 0x00000000 222 #define HAL_TSP_CAP_SEC_FILTER_NUM 0x00000001 223 #define HAL_TSP_CAP_SEC_BUF_NUM 0x00000002 224 #define HAL_TSP_CAP_PVR_ENG_NUM 0x00000003 225 #define HAL_TSP_CAP_PVR_FILTER_NUM 0x00000004 226 #define HAL_TSP_CAP_PVR1_FILTER_NUM 0x00000005 227 #define HAL_TSP_CAP_MMFI_AUDIO_FILTER_NUM 0x00000006 228 #define HAL_TSP_CAP_MMFI_V3D_FILTER_NUM 0x00000007 229 #define HAL_TSP_CAP_TSIF_NUM 0x00000008 230 #define HAL_TSP_CAP_DEMOD_NUM 0x00000009 231 #define HAL_TSP_CAP_TS_PAD_NUM 0x0000000a 232 #define HAL_TSP_CAP_VQ_NUM 0x0000000b 233 #define HAL_TSP_CAP_CA_FLT_NUM 0x0000000c 234 #define HAL_TSP_CAP_CA_KEY_NUM 0x0000000d 235 #define HAL_TSP_CAP_FW_ALIGN 0x0000000e 236 #define HAL_TSP_CAP_VQ_ALIGN 0x0000000f 237 #define HAL_TSP_CAP_VQ_PITCH 0x00000010 238 #define HAL_TSP_CAP_SEC_BUF_ALIGN 0x00000011 239 #define HAL_TSP_CAP_PVR_ALIGN 0x00000012 240 #define HAL_TSP_CAP_PVRCA_PATH_NUM 0x00000013 241 #define HAL_TSP_CAP_SHAREKEY_FLT_RANGE 0x00000014 242 #define HAL_TSP_CAP_PVRCA0_FLT_RANGE 0x00000015 243 #define HAL_TSP_CAP_PVRCA1_FLT_RANGE 0x00000016 244 #define HAL_TSP_CAP_HW_TYPE 0x0000001a 245 #define HAL_TSP_CAP_VFIFO_NUM 0x0000001c 246 #define HAL_TSP_CAP_AFIFO_NUM 0x0000001d 247 #define HAL_TSP_CAP_HWPCR_SUPPORT 0x0000001e 248 #define HAL_TSP_CAP_PCRFLT_START_IDX 0x0000001f 249 #define HAL_TSP_CAP_HWWP_SET_NUM 0x00000020 250 #define HAL_TSP_CAP_DSCMB_ENG_NUM 0x00000021 251 #define HAL_TSP_CAP_MERGESTR_NUM 0x00000022 252 #define HAL_TSP_CAP_MAX_SEC_FLT_DEPTH 0x00000023 253 #define HAL_TSP_CAP_FW_BUF_SIZE 0x00000024 254 #define HAL_TSP_CAP_FW_BUF_RANGE 0x00000025 255 #define HAL_TSP_CAP_VQ_BUF_RANGE 0x00000026 256 #define HAL_TSP_CAP_SEC_BUF_RANGE 0x00000027 257 #define HAL_TSP_CAP_FIQ_NUM 0x00000028 258 259 260 //STC update Control Parameters define 261 #define HAL_TSP_STC_UPDATE_FW 0x00 262 #define HAL_TSP_STC_UPDATE_HK 0x01 263 #define HAL_TSP_STC_UPDATE_UPDATEONCE 0x02 264 265 266 //[LEGACY] //[OBSOLETE] 267 extern MS_BOOL _bIsHK; 268 //[LEGACY] //[OBSOLETE] 269 270 void HAL_TSP_Stc_ctrl(MS_U32 u32EngId, MS_U32 u32Sync); 271 void HAL_TSP_Reset(MS_U32 u32EngId); 272 void HAL_TSP_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr); 273 void HAL_TSP_Int_Disable(MS_U32 u32Mask); 274 MS_U32 HAL_TSP_CmdQ_CmdCount(void); 275 MS_BOOL HAL_TSP_CmdQ_Reset(void); 276 void HAL_TSP_WbDmaEnable(MS_BOOL bEnable); 277 void HAL_TSP_HwPatch(void); 278 void HAL_TSP_CPU_SetBase(MS_PHY phyAddr, MS_U32 u32Size); 279 void HAL_TSP_SetCtrlMode(MS_U32 u32EngId, MS_U32 u32Mode, MS_U32 u32TsIfId); 280 void HAL_TSP_Int_ClearSw(void); 281 void HAL_TSP_Int_ClearHw(MS_U32 u32Mask); 282 void HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay); 283 void HAL_TSP_Int_Enable(MS_U32 u32Mask); 284 MS_U32 HAL_TSP_GetCtrlMode(MS_U32 u32EngId); 285 void HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable); 286 void HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId, MS_BOOL bEnable); 287 MS_BOOL HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId, MS_U16* pu16Pad, MS_U16* pu16Clk, MS_BOOL* pbExtSync, MS_BOOL* pbParl); 288 MS_BOOL HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId); 289 290 void HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 u32Flow, MS_U32 u32Pad); 291 void HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bClkInv); 292 void HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId, MS_BOOL bExtSync, MS_U32 u32Flow); 293 void HAL_TSP_SelPad_Parl(MS_U32 u32EngId, MS_BOOL bParl, MS_U32 u32Flow); 294 void HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bInvert); 295 void HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId, MS_BOOL bFlush); 296 MS_U32 HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId); 297 void HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId, MS_U32 u32STC); 298 void HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32); 299 MS_U32 HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId); 300 MS_U32 HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId); 301 void HAL_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC, MS_U32 u32STC_32); 302 MS_BOOL HAL_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd); 303 //void HAL_TSP_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32); 304 void HAL_TSP_STC_Update_Disable(MS_U32 u32EngId, MS_BOOL bDisable); 305 MS_U32 HAL_TSP_GetSTC(MS_U32 u32EngId); 306 MS_U32 HAL_TSP_GetSTC_32(MS_U32 u32EngId); 307 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 308 MS_BOOL HAL_TSP_GetPcr(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr); 309 //MS_U32 HAL_TSP_PidFltId(MS_U32 u32PidType); 310 void HAL_TSP_PidFlt_SetPid(REG_PidFlt *pPidFilter, MS_U32 u32PID); 311 void HAL_TSP_PidFlt_SelFltOutput(REG_PidFlt *pPidFilter, MS_U32 u32FltOutput); 312 void HAL_TSP_PidFlt_SelSecFlt(REG_PidFlt *pPidFilter, MS_U32 u32SecFltId); 313 void HAL_TSP_PidFlt_PVREnable(REG_PidFlt *pPidFilter); 314 315 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFilter, MS_U32 u32FltType); 316 MS_U32 HAL_TSP_PidFlt_GetSecFlt(REG_PidFlt *pPidFilter); 317 MS_U32 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFilter); 318 void HAL_TSP_SecBuf_ResetBuffer(REG_SecFlt *pSecBuf); 319 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFilter); 320 void HAL_TSP_SecFlt_SetRmnCount(REG_SecFlt *pSecFilter, MS_U32 u32RmnCount); 321 MS_U32 HAL_TSP_HW_INT_STATUS(void); 322 MS_U32 HAL_TSP_SW_INT_STATUS(void); 323 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFilter); 324 MS_U32 HAL_TSP_Scmb_Status(MS_U32 u32TSSrc, MS_U32 u32GroupId, MS_U32 u32PidFltId); 325 MS_PHY HAL_TSP_SecBuf_GetBufRead(REG_SecFlt *pSecBuf); 326 MS_PHY HAL_TSP_SecBuf_GetBufWrite(REG_SecFlt *pSecBuf); 327 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFilter); 328 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFilter, MS_U8 *pu8Mask); 329 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFilter, MS_U8 *pu8NMask); 330 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFilter, MS_U8 *pu8Match); 331 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFilter, MS_U32 u32ReqCount); 332 void HAL_TSP_SecBuf_SetBuffer(REG_SecFlt *pSecBuf, MS_PHY phyStartAddr, MS_U32 u32BufSize); 333 void HAL_TSP_SecBuf_SetBufRead(REG_SecFlt *pSecBuf, MS_PHY phyReadAddr); 334 MS_PHY HAL_TSP_SecBuf_GetBufStart(REG_SecFlt *pSecBuf); 335 MS_PHY HAL_TSP_SecBuf_GetBufEnd(REG_SecFlt *pSecBuf); 336 MS_PHY HAL_TSP_SecBuf_GetBufCur(REG_SecFlt *pSecBuf); 337 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFilter, MS_U32 u32SecFltMode); 338 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFilter); 339 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFilter); 340 void HAL_TSP_PVR_SetBuffer(MS_PHY phyBufStart0, MS_PHY phyBufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1); 341 void HAL_TSP_PVR_Enable(MS_BOOL bEnable); 342 void HAL_TSP_PVR_Reset(void); 343 void HAL_TSP_PVR_All(MS_BOOL bPvrAll); 344 MS_PHY HAL_TSP_PVR_GetBufWrite(void); 345 void HAL_TSP_PVR_WaitFlush(void); 346 void HAL_TSP_PVR_Filein_Enable(MS_BOOL bBypassHD, MS_BOOL bEnable, MS_BOOL bRecAll); 347 void HAL_TSP_PVR_REC_FLT_Enable(MS_BOOL bEnable); 348 MS_BOOL HAL_TSP_PVR_Eng_IsEnabled(MS_U32 u32EngId); 349 350 void HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr); 351 MS_BOOL HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize); 352 void HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl); 353 void HAL_TSP_TsDma_Pause(void); 354 void HAL_TSP_TsDma_Resume(void); 355 MS_U32 HAL_TSP_CmdQ_TsDma_GetState(void); 356 MS_U32 HAL_TSP_CmdQ_EmptyCount(void); 357 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFilter); 358 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFilter); 359 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFilter); 360 void HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId); 361 void HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr); 362 363 void HAL_TSP_Ind_Enable(void); 364 void HAL_TSP_CmdQ_TsDma_Reset(void); 365 MS_BOOL HAL_TSP_CmdQ_IsEmpty(void); 366 MS_U8 HAL_TSP_Get_CmdQFifoLevel(void); 367 368 // void HAL_TSP_SetFwMsg(MS_U32 u32Mode); 369 // MS_U32 HAL_TSP_GetFwMsg(void); 370 void HAL_TSP_ISR_SAVE_ALL(void); 371 void HAL_TSP_ISR_RESTORE_ALL(void); 372 MS_U32 HAL_REG32_IndR(REG32 *reg); 373 void HAL_REG32_IndW(REG32 *reg, MS_U32 value); 374 void HAL_TSP_PS_Path_Disable(void); 375 void HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl); 376 void HAL_TSP_DoubleBuf_En(MS_BOOL bBuf_Sel); 377 void HAL_TSP_DoubleBuf_Disable(void); 378 void HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr); 379 void HAL_TSP_CSA_Set_ScrmPath(MS_U32 u32ScrmPath); 380 MS_U32 HAL_TSP_CSA_Get_ScrmPath(void); 381 void HAL_TSP_PidFlt_SelFltSource(REG_PidFlt *pPidFilter, MS_U32 u32FltSource); 382 void HAL_TSP_LiveAB_En(MS_BOOL bPF_EN); 383 MS_BOOL HAL_TSP_IsLiveAB_Enable(void); 384 385 void HAL_TSP_Scmb_Detect(MS_BOOL bEnable); 386 void HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable); 387 388 MS_BOOL HAL_TSP_GetCap(MS_U32 u32Cap, void* pData); 389 390 MS_BOOL HAL_TSP_Alive(void); 391 void HAL_TSP_HW_Lock_Init(void); 392 void HAL_TSP_HW_Lock_Release(void); 393 void HAL_TSP_SetPKTSize(MS_U32 u32PKTSize); 394 void HAL_TSP_SetOwner(REG_SecFlt* pSecFlt, MS_BOOL bOwner); 395 MS_BOOL HAL_TSP_TTX_IsAccess(MS_U32 u32Try); 396 void HAL_TSP_TTX_UnlockAccess(void); 397 398 void HAL_TSP_filein_enable(MS_BOOL b_enable); 399 void HAL_TSP_FileIn_Set(MS_BOOL bset); 400 void HAL_TSP_ResetTimeStamp(void); 401 MS_U32 HAL_TSP_GetPVRTimeStamp(void); 402 void HAL_TSP_SetPVRTimeStamp(MS_U32 u32Stamp); 403 MS_BOOL HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId, MS_U32 u32ClkSrc); 404 405 MS_U32 HAL_TSP_GetPlayBackTimeStamp(void); 406 void HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp); 407 MS_BOOL HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id, MS_U32 u32ClkSrc); 408 409 MS_U32 HAL_TSP_GetFileInTimeStamp(void); 410 MS_BOOL HAL_TSP_GetFilinReadAddr(MS_PHY* pphyReadAddr); 411 void HAL_TSP_SetDMABurstLen(MS_U32 u32Len); 412 void HAL_TSP_PVR_PacketMode(MS_BOOL bSet); 413 void HAL_ResetAll(void); 414 void HAL_TSP_PowerCtrl(MS_BOOL bOn); 415 void HAL_TSP_SecBuf_SetBufRead_tmp(REG_SecFlt *pSecBuf, MS_PHY pRehyadAddr); 416 MS_PHY HAL_TSP_SecBuf_GetBufWrite_tmp(REG_SecFlt *pSecBuf); 417 MS_U32 HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel); 418 419 void HAL_TSP_SetVQBuffer(MS_PHY phyBaseAddr, MS_U32 u32BufLen); 420 void HAL_TSP_VQueue_Enable(MS_BOOL bEnable); 421 void HAL_TSP_VQueue_Reset(void); 422 void HAL_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable); 423 void HAL_TSP_VQueue_Clr_OverflowInt(void); 424 MS_U32 HAL_TSP_VQ_INT_STATUS(void); 425 void HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len); 426 MS_U32 HAL_TSP_Get_VQStatus(void); 427 428 void HAL_TSP_SaveFltState(void); 429 void HAL_TSP_RestoreFltState(void); 430 void HAL_TSP_Enable_ValidSync_Dectect(void); 431 void HAL_Reset_WB(void); 432 MS_U8 HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId); 433 MS_U8 HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId); 434 void HAL_TSP_Set_AVPAUSE(MS_BOOL bSet); 435 MS_U32 HAL_TSP_Get_FW_VER(void); 436 MS_BOOL HAL_TSP_Check_FW_VER(void); 437 MS_BOOL HAL_TSP_SetFwDbgMem(MS_PHY phyAddr, MS_U32 u32Size); 438 MS_BOOL HAL_TSP_SetFwDbgWord(MS_U32 u32Word); 439 440 REG_PidFlt* HAL_TSP_GetPidFltReg(MS_U32 u32EngId, MS_U32 u32PidFltId); 441 MS_BOOL HAL_TSP_Read_DropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt); 442 void HAL_TSP_TSIF0_Enable(MS_BOOL bEnable); 443 void HAL_TSP_TSIF1_Enable(MS_BOOL bEnable); 444 void HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY* pphyStartAddr, MS_PHY* pphyEndAddr); 445 446 MS_BOOL HAL_TSP_MOBF_Set_PVRKey(MS_U32 u32Key0, MS_U32 u32Key1); 447 MS_BOOL HAL_TSP_MOBF_Set_FileinKey(MS_U32 u32Key); 448 MS_BOOL HAL_TSP_MOBF_Filein_Enable(MS_BOOL bEnable); 449 MS_BOOL HAL_TSP_MOBF_PVR_Enable(MS_BOOL bEnable); 450 451 MS_BOOL HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable); 452 453 // ------------------------------------------------------------- 454 // Common api for mode setting 455 // u32Cmd[31]: 0 -> public cmd, 1 -> private cmd 456 // ------------------------------------------------------------- 457 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 458 459 // ------------------------------------------------------------- 460 // Debug table 461 // ------------------------------------------------------------- 462 MS_U32 HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info* TspDisconPktCntInfo); 463 MS_U32 HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info* TspDropCntInfo); 464 MS_U32 HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info* TspLockCntInfo); 465 MS_U32 HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info* TspAVCntInfo); 466 467 MS_U32 HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc); 468 MS_BOOL HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc); 469 MS_U32 HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId); 470 MS_BOOL HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId); 471 472 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Opt); 473 474 MS_BOOL HAL_TSP_SetPacketMode(MS_U32 u32TSIf, MS_U32 u32PktMode); 475 MS_BOOL HAL_TSP_SetMergeStrSyncByte(MS_U32 u32SrcID, MS_U8 u8SyncByte); 476 void HAL_TSP_MOBF_Set_PVRKey_EX(MS_U32 u32PvrEng, MS_U32 u32Key0, MS_U32 u32Key1); 477 478 479 #endif // #ifndef __HAL_TSP_H__ 480