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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // file halTSP.h 97 // @brief Transport Stream Processer (TSP) HAL 98 // @author MStar Semiconductor,Inc. 99 //////////////////////////////////////////////////////////////////////////////////////////////////// 100 #ifndef __HAL_TSP_H__ 101 #define __HAL_TSP_H__ 102 103 #include "MsCommon.h" 104 105 #include "regTSP.h" 106 107 //-------------------------------------------------------------------------------------------------- 108 // Driver Compiler Option 109 //-------------------------------------------------------------------------------------------------- 110 #define TSP_HWPCR_BY_HK 0UL //Tuning STC by driver side 111 #define TSP_AUDIO3_AUDIO4_SUPPORT 0UL //Support AUDIO3 & AUDIO4 FIFO 112 113 //-------------------------------------------------------------------------------------------------- 114 // TSP Hardware Abstraction Layer 115 //-------------------------------------------------------------------------------------------------- 116 // TSP Register 117 #define _TspPid ((REG_Pid*)(REG_PIDFLT_L_BASE)) 118 #define _TspPid_H ((REG_Pid*)(REG_PIDFLT_H_BASE)) 119 120 #define _TspPid_Ext ((REG_Pid*)(REG_PIDFLT_L_EXT_BASE)) 121 #define _TspPid_Ext_H ((REG_Pid*)(REG_PIDFLT_H_EXT_BASE)) 122 123 #define _TspSec1 ((REG_Sec*)(REG_SECFLT_BASE1)) 124 #define _TspSec2 ((REG_Sec*)(REG_SECFLT_BASE2)) 125 126 #define TSP_HW_CFG_0 0x00UL 127 #define TSP_HW_CFG_1 0x01UL 128 #define TSP_HW_CFG_2 0x10UL 129 #define TSP_HW_CFG_3 0x11UL 130 131 /// TSP debug mode type 132 typedef enum 133 { 134 TSP_DEBUG_MODE_DIS_CONT, ///< Select dis-continue packet count mode 135 TSP_DEBUG_MODE_DROP_CONT, ///< Select drop packet count mode 136 } TSP_DEBUG_MODE; 137 138 typedef enum 139 { 140 TSP_DEBUG_SRC_TS0, ///< TSP input from TS0 interface 141 TSP_DEBUG_SRC_TS1, ///< TSP input from TS1 interface 142 TSP_DEBUG_SRC_TS2, ///< TSP input from TS2 interface 143 TSP_DEBUG_SRC_FILE, ///< TSP input from filein 144 } TSP_DEBUG_SRC; 145 146 typedef enum 147 { 148 TSP_DEBUG_FIFO_VIDEO, ///< TSP output to Video FIFO 149 TSP_DEBUG_FIFO_AUDIO, ///< TSP output to Audio FIFO 150 TSP_DEBUG_FIFO_VIDEO3D, ///< TSP output to Video3D FIFO 151 TSP_DEBUG_FIFO_AUDIOB, ///< TSP output to AudioB FIFO 152 } TSP_DEBUG_FIFO; 153 154 typedef enum 155 { 156 TSP_DEBUG_PKT_DEMUX_0, 157 TSP_DEBUG_PKT_DEMUX_0_FILE, 158 TSP_DEBUG_PKT_DEMUX_1, 159 TSP_DEBUG_PKT_DEMUX_2, 160 TSP_DEBUG_MMFI0, 161 TSP_DEBUG_MMFI1, 162 } TSP_DEBUG_FIFO_SRC; 163 164 typedef enum 165 { 166 TSP_DEBUG_TSIF0, ///< TSP output to Video FIFO 167 TSP_DEBUG_TSIF1, ///< TSP output to Audio FIFO 168 TSP_DEBUG_TSIF2, 169 TSP_DEBUG_TSIFFI, 170 } TSP_DEBUG_TSIF; 171 172 typedef enum 173 { 174 TSP_DEBUG_CMD_NONE, ///< TSP debug table cmd: do nothing 175 TSP_DEBUG_CMD_CLEAR, ///< TSP debug table cmd: clear 176 TSP_DEBUG_CMD_ENABLE, ///< TSP debug table cmd: enable 177 TSP_DEBUG_CMD_DISABLE, ///< TSP debug table cmd: disable 178 } TSP_DEBUG_CMD; 179 180 typedef enum 181 { 182 TSP_CLR_SRC_PIDFLT_0 = 0x1, ///< TSP debug table clear source: pidflt 0 183 TSP_CLR_SRC_PIDFLT_FILE = 0x2, ///< TSP debug table clear source: pidflt file 184 } TSP_DEBUG_CLR_SRC; 185 186 //---------------------------------- 187 /// DMX debug table information structure 188 //---------------------------------- 189 typedef struct 190 { 191 TSP_DEBUG_CMD TspCmd; 192 TSP_DEBUG_SRC TspSrc; 193 TSP_DEBUG_FIFO TspFifo; 194 } TSP_DisconPktCnt_Info, TSP_DropPktCnt_Info; 195 196 typedef struct 197 { 198 TSP_DEBUG_CMD TspCmd; 199 TSP_DEBUG_TSIF TspTsif; 200 } TSP_LockPktCnt_info; 201 202 typedef struct 203 { 204 TSP_DEBUG_CMD TspCmd; 205 TSP_DEBUG_FIFO TspFifo; 206 TSP_DEBUG_FIFO_SRC TspFifoSrc; 207 } TSP_AVPktCnt_info; 208 209 //-------------------------------------------------------------------------------------------------- 210 // Macro of bit operations 211 //-------------------------------------------------------------------------------------------------- 212 #define HAS_FLAG(flag, bit) ((flag) & (bit)) 213 #define SET_FLAG(flag, bit) ((flag)|= (bit)) 214 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 215 #define SET_FLAG1(flag, bit) ((flag)| (bit)) 216 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 217 218 // define NULL function 219 #define HAL_TSP_SecFlt_SelSecBuf(u32EngId, u32SecFltId, u32BufId, bEnable) 220 #define HAL_TSP_SecFlt_SetEcmIdx(u32EngId, u32SecFltId, u32EcmIdx) 221 #define HAL_TSP_SecFlt_ResetEmmIdx(u32EngId, u32SecFltId) 222 #define HAL_TSP_SelAudOut(u32EngId) 223 224 //AV FIFO Enum 225 #define TSP_FIFO_AU 0UL 226 #define TSP_FIFO_AUB 1UL 227 #define TSP_FIFO_V3D 2UL 228 #define TSP_FIFO_VD 3UL 229 #define TSP_FIFO_AUC 4UL 230 #define TSP_FIFO_AUD 5UL 231 232 //TSP IF Source Enum 233 #define TSP_SRC_FROM_TSIF0_LIVE 0x00000001UL 234 #define TSP_SRC_FROM_TSIF0_FILE 0x00000002UL 235 #define TSP_SRC_FROM_TSIF1 0x00000003UL 236 #define TSP_SRC_FROM_TSIF2 0x00000004UL 237 #define TSP_SRC_FROM_MMFI0 0x00000006UL 238 #define TSP_SRC_FROM_MMFI1 0x00000007UL 239 240 //TSP Packet Demux Enum 241 #define TSP_PKTDMX_NONE 0x00000000UL 242 #define TSP_PKTDMX0_LIVE 0x00000002UL 243 #define TSP_PKTDMX0_FILE 0x00000004UL 244 #define TSP_PKTDMX1 0x00000008UL 245 #define TSP_PKTDMX2 0x00000010UL 246 247 248 //////////////////////////////////////////////// 249 // HAL API 250 //////////////////////////////////////////////// 251 252 //enum of Capcbility item 253 #define HAL_TSP_CAP_PID_FILTER_NUM 0x00000000UL 254 #define HAL_TSP_CAP_SEC_FILTER_NUM 0x00000001UL 255 #define HAL_TSP_CAP_SEC_BUF_NUM 0x00000002UL 256 #define HAL_TSP_CAP_PVR_ENG_NUM 0x00000003UL 257 #define HAL_TSP_CAP_PVR_FILTER_NUM 0x00000004UL 258 #define HAL_TSP_CAP_PVR1_FILTER_NUM 0x00000005UL 259 #define HAL_TSP_CAP_MMFI0_FILTER_NUM 0x00000006UL 260 #define HAL_TSP_CAP_MMFI1_FILTER_NUM 0x00000007UL 261 #define HAL_TSP_CAP_TSIF_NUM 0x00000008UL 262 #define HAL_TSP_CAP_DEMOD_NUM 0x00000009UL 263 #define HAL_TSP_CAP_TS_PAD_NUM 0x0000000aUL 264 #define HAL_TSP_CAP_VQ_NUM 0x0000000bUL 265 #define HAL_TSP_CAP_CA_FLT_NUM 0x0000000cUL 266 #define HAL_TSP_CAP_CA_KEY_NUM 0x0000000dUL 267 #define HAL_TSP_CAP_FW_ALIGN 0x0000000eUL 268 #define HAL_TSP_CAP_VQ_ALIGN 0x0000000fUL 269 #define HAL_TSP_CAP_VQ_PITCH 0x00000010UL 270 #define HAL_TSP_CAP_SEC_BUF_ALIGN 0x00000011UL 271 #define HAL_TSP_CAP_PVR_ALIGN 0x00000012UL 272 #define HAL_TSP_CAP_PVRCA_PATH_NUM 0x00000013UL 273 #define HAL_TSP_CAP_SHAREKEY_FLT_RANGE 0x00000014UL 274 #define HAL_TSP_CAP_CA0_FLT_RANGE 0x00000015UL 275 #define HAL_TSP_CAP_CA1_FLT_RANGE 0x00000016UL 276 #define HAL_TSP_CAP_CA2_FLT_RANGE 0x00000017UL 277 #define HAL_TSP_CAP_SHAREKEY_FLT1_RANGE 0x00000018UL 278 #define HAL_TSP_CAP_SHAREKEY_FLT2_RANGE 0x00000019UL 279 #define HAL_TSP_CAP_HW_TYPE 0x0000001aUL 280 #define HAL_TSP_CAP_VFIFO_NUM 0x0000001cUL 281 #define HAL_TSP_CAP_AFIFO_NUM 0x0000001dUL 282 #define HAL_TSP_CAP_HWPCR_SUPPORT 0x0000001eUL 283 #define HAL_TSP_CAP_PCRFLT_START_IDX 0x0000001fUL 284 #define HAL_TSP_CAP_HWWP_SET_NUM 0x00000020UL 285 #define HAL_TSP_CAP_DSCMB_ENG_NUM 0x00000021UL 286 #define HAL_TSP_CAP_MERGESTR_NUM 0x00000022UL 287 #define HAL_TSP_CAP_MAX_SEC_FLT_DEPTH 0x00000023UL 288 #define HAL_TSP_CAP_FW_BUF_SIZE 0x00000024UL 289 #define HAL_TSP_CAP_FW_BUF_RANGE 0x00000025UL 290 #define HAL_TSP_CAP_VQ_BUF_RANGE 0x00000026UL 291 #define HAL_TSP_CAP_SEC_BUF_RANGE 0x00000027UL 292 #define HAL_TSP_CAP_FIQ_NUM 0x00000028UL 293 294 // Output pad mode 295 #define HAL_TSP_OUTPAD_DMD 0x00000000UL 296 #define HAL_TSP_OUTPAD_S2P 0x10000000UL 297 #define HAL_TSP_OUTPAD_TSO 0x20000000UL 298 #define HAL_TSP_OUTPAD_S2P1 0x40000000UL 299 #define HAL_TSP_OUTPAD_TSO1 0x80000000UL 300 301 //STC update Control Parameters define 302 #define HAL_TSP_STC_UPDATE_FW 0x00UL 303 #define HAL_TSP_STC_UPDATE_HK 0x01UL 304 #define HAL_TSP_STC_UPDATE_UPDATEONCE 0x02UL 305 306 //S2P Clock Option 307 #define HAL_S2P_CLK_OPT_NONE 0x00000000UL 308 #define HAL_S2P_CLK_OPT_INVERT 0x00000001UL 309 #define HAL_S2P_CLK_OPT_NON_INVERT 0x00000002UL 310 311 //[LEGACY] //[OBSOLETE] 312 extern MS_BOOL _bIsHK; 313 //[LEGACY] //[OBSOLETE] 314 315 MS_BOOL HAL_TSP_GetCap(MS_U32 u32Cap, void* pData); 316 MS_BOOL HAL_TSP_Alive(void); 317 void HAL_TSP_HW_Lock_Init(void); 318 void HAL_TSP_HW_Lock_Release(void); 319 void HAL_TSP_SetPKTSize(MS_U32 u32PKTSize); 320 void HAL_TSP_SetOwner(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_BOOL bOwner); 321 MS_BOOL HAL_TSP_TTX_IsAccess(MS_U32 u32Try); 322 void HAL_TSP_TTX_UnlockAccess(void); 323 324 void HAL_ResetAll(void); 325 void HAL_TSP_PowerCtrl(MS_BOOL bOn); 326 void HAL_TSP_SaveFltState(void); 327 void HAL_TSP_RestoreFltState(void); 328 void HAL_TSP_Enable_ValidSync_Dectect(void); 329 void HAL_Reset_WB(void); 330 MS_BOOL HAL_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY* pphyStartAddr, MS_PHY* pphyEndAddr); 331 void HAL_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr); 332 333 void HAL_TSP_ORAcess_Optimize(MS_BOOL bEnable); 334 void HAL_TSP_Reset(MS_U32 u32EngId); 335 void HAL_TSP_SetBank(MS_VIRT virtBankAddr, MS_VIRT virtPMBankAddr); 336 void HAL_TSP_WbDmaEnable(MS_BOOL bEnable); 337 void HAL_TSP_HwPatch(void); 338 void HAL_TSP_CPU_SetBase(MS_PHY phyAddr, MS_U32 u32Size); 339 void HAL_TSP_SetCtrlMode(MS_U32 u32EngId, MS_U32 u32Mode, MS_U32 u32TsIfId); 340 MS_U32 HAL_TSP_GetCtrlMode(MS_U32 u32EngId); 341 342 void HAL_TSP_Ind_Enable(void); 343 MS_U32 HAL_TSP_Scmb_Status(MS_U32 u32TSSrc, MS_U32 u32GroupId, MS_U32 u32PidFltId); 344 345 void HAL_TSP_RemoveDupAVPkt(MS_BOOL bEnable); 346 void HAL_TSP_RemoveDupAVFifoPkt(MS_U32 u32StreamId, MS_BOOL bEnable); 347 void HAL_TSP_TEI_RemoveErrorPkt(MS_U32 u32PktType, MS_BOOL bEnable); 348 MS_BOOL HAL_TSP_DupPktCnt_Clear(void); 349 MS_BOOL HAL_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable); 350 351 void HAL_TSP_Int_ClearSw(void); 352 void HAL_TSP_Int_ClearHw(MS_U32 u32Mask); 353 void HAL_TSP_Int_ClearHw2(MS_U32 u32Mask); 354 void HAL_TSP_Int_Enable(MS_U32 u32Mask); 355 void HAL_TSP_Int_Disable(MS_U32 u32Mask); 356 void HAL_TSP_Int2_Enable(MS_U32 u32Mask); 357 void HAL_TSP_Int2_Disable(MS_U32 u32Mask); 358 MS_U32 HAL_TSP_HW_INT_STATUS(void); 359 MS_U32 HAL_TSP_HW_INT2_STATUS(void); 360 MS_U32 HAL_TSP_SW_INT_STATUS(void); 361 362 MS_BOOL HAL_TSP_TsOutPadCfg(MS_U32 u32OutPad, MS_U32 u32OutPadMode, MS_U32 u32InPad, MS_BOOL bInParallel); 363 void HAL_TSP_SelPad(MS_U32 u32EngId, MS_U32 u32Flow, MS_U32 u32Pad, MS_BOOL bParl); 364 void HAL_TSP_SelPad_ClkInv(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bClkInv); 365 void HAL_TSP_SelPad_ExtSync(MS_U32 u32EngId, MS_BOOL bExtSync, MS_U32 u32Flow); 366 void HAL_TSP_SelPad_Parl(MS_U32 u32EngId, MS_BOOL bParl, MS_U32 u32Flow); 367 MS_BOOL HAL_TSP_BlockTSOIn_En(MS_U32 u32EngId, MS_U32 u32TSIf, MS_BOOL bBlockMode); 368 MS_BOOL HAL_TSP_TsOuOutClockPhase(MS_U16 u16OutPad, MS_U16 u16Val, MS_BOOL bEnable, MS_U32 u32S2pOpt); 369 void HAL_TSP_TSOut_En(MS_BOOL bEnable); 370 MS_BOOL HAL_TSP_GetTSIF_Status(MS_U8 u8TsIfId, MS_U16* pu16Pad, MS_U16* pu16Clk, MS_BOOL* pbExtSync, MS_BOOL* pbParl); 371 void HAL_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, MS_U32 u32Flow, MS_BOOL bInvert); 372 void HAL_TSP_Flush_AV_FIFO(MS_U32 u32StreamId, MS_BOOL bFlush); 373 MS_U32 HAL_TSP_Get_AVFifoLevel(MS_U32 u32StreamId); 374 void HAL_TSP_AVFIFO_Src_Select(MS_U32 u32Fifo, MS_U32 u32Src); 375 void HAL_TSP_AVFIFO_Block_Disable(MS_U32 u32Fifo, MS_BOOL bDisable); 376 MS_BOOL HAL_TSP_TSIF_Enable(MS_U8 u8_tsif, MS_BOOL bEnable); 377 void HAL_TSP_SelMatchPidSrc(MS_U32 u32Src); 378 MS_BOOL HAL_TSP_PidFlt_Src_Select(MS_U32 u32Src); 379 380 381 void HAL_TSP_CmdQ_SetSTC(MS_U32 u32EngId, MS_U32 u32STC); 382 void HAL_TSP_CmdQ_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32); 383 MS_U32 HAL_TSP_CmdQ_GetSTC(MS_U32 u32EngId); 384 MS_U32 HAL_TSP_CmdQ_GetSTC_32(MS_U32 u32EngId); 385 MS_U32 HAL_TSP_CmdQ_CmdCount(void); 386 MS_BOOL HAL_TSP_CmdQ_Reset(void); 387 void HAL_TSP_CmdQ_TsDma_SetAddr(MS_PHY phyStreamAddr); 388 MS_BOOL HAL_TSP_CmdQ_TsDma_SetSize(MS_U32 u32StreamSize); 389 void HAL_TSP_CmdQ_TsDma_Start(MS_U32 u32TsDmaCtrl); 390 MS_U32 HAL_TSP_CmdQ_TsDma_GetState(void); 391 MS_U32 HAL_TSP_CmdQ_EmptyCount(void); 392 void HAL_TSP_CmdQ_TsDma_Reset(void); 393 MS_BOOL HAL_TSP_CmdQ_IsEmpty(void); 394 void HAL_TSP_TsDma_SetDelay(MS_U32 u32Delay); 395 void HAL_TSP_TsDma_Pause(void); 396 void HAL_TSP_TsDma_Resume(void); 397 MS_U8 HAL_TSP_Get_CmdQFifoLevel(void); 398 399 void HAL_TSP_FileIn_192BlockScheme_En(MS_BOOL bEnable); 400 void HAL_TSP_filein_enable(MS_BOOL b_enable); 401 void HAL_TSP_FileIn_Set(MS_BOOL bset); 402 void HAL_TSP_ResetTimeStamp(void); 403 MS_U32 HAL_TSP_GetPlayBackTimeStamp(void); 404 void HAL_TSP_SetPlayBackTimeStamp(MS_U32 u32Stamp); 405 void HAL_TSP_SetPlayBackTimeStampClk(MS_U8 u8Id, MS_U32 u32ClkSrc); 406 MS_U32 HAL_TSP_GetFileInTimeStamp(void); 407 MS_BOOL HAL_TSP_GetFilinReadAddr(MS_PHY* pphyReadAddr); 408 void HAL_TSP_SetDMABurstLen(MS_U32 u32Len); 409 410 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); //T12 new 411 void HAL_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC, MS_U32 u32STC_32); 412 void HAL_TSP_Stc_ctrl(MS_U32 u32EngId, MS_U32 u32Sync); 413 MS_U32 HAL_TSP_GetSTCSynth(MS_U32 u32EngId); 414 //void HAL_TSP_SetSTC_32(MS_U32 u32EngId, MS_U32 u32STC_32); 415 void HAL_TSP_STC_Update_Disable(MS_U32 u32EngId, MS_BOOL bDisable); 416 MS_U32 HAL_TSP_GetSTC(MS_U32 u32EngId); 417 MS_U32 HAL_TSP_GetSTC_32(MS_U32 u32EngId); 418 MS_BOOL HAL_TSP_SelectSTCEng(MS_U32 u32FltSrc, MS_U32 u32Eng); 419 MS_BOOL HAL_TSP_GetPcr(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr); 420 MS_BOOL HAL_TSP_Check_FIFO_Overflow(MS_U32 u32StreamId); 421 void HAL_TSP_HWPcr_SetSrcId(MS_U32 u32EngId, MS_U32 u32SrcId); 422 void HAL_TSP_HWPcr_SelSrc(MS_U32 u32EngId, MS_U32 u32Src); 423 void HAL_TSP_HWPcr_Reset(MS_U32 u32EngId, MS_BOOL bReset); 424 void HAL_TSP_HWPcr_Int_Enable(MS_U32 u32EngId, MS_BOOL bEnable); 425 void HAL_TSP_HWPcr_Read(MS_U32 u32EngId, MS_U32 *pu32Pcr, MS_U32 *pu32Pcr_32); 426 427 //MS_U32 HAL_TSP_PidFltId(MS_U32 u32PidType); 428 void HAL_TSP_PidFlt_SetPid(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32PID); 429 void HAL_TSP_PidFlt_SelFltOutput(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32FltOutput); 430 void HAL_TSP_PidFlt_SelSecFlt(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32SecFltId); 431 MS_U32 HAL_TSP_PidFlt_GetSecFlt(MS_U32 u32EngId, MS_U32 u32PidFltId); 432 MS_U32 HAL_TSP_PidFlt_GetPid(MS_U32 u32EngId, MS_U32 u32PidFltId); 433 MS_U32 HAL_TSP_PidFlt_GetFltOutput(MS_U32 u32EngId, MS_U32 u32PidFltId); 434 void HAL_TSP_PidFlt_SelFltSource(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32FltSource); 435 void HAL_TSP_PidFlt_SetFltSrcStreamID(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32SrcStrId); 436 437 void HAL_TSP_PidFlt_SetHWPcrPid(MS_U32 u32EngId, MS_U32 u32PID); 438 MS_U32 HAL_TSP_PidFlt_GetHWPcrPid(MS_U32 u32EngId); 439 void HAL_TSP_PidFlt_HWPcrFlt_Enable(MS_U32 u32EngId, MS_BOOL bEnable); 440 441 void HAL_TSP_SecBuf_ResetBuffer(MS_U32 u32EngId, MS_U32 u32SecBufId); 442 void HAL_TSP_SecFlt_ResetState(MS_U32 u32EngId, MS_U32 u32SecFltId); 443 void HAL_TSP_SecFlt_SetType(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32FltType); 444 void HAL_TSP_SecFlt_SetRmnCount(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32RmnCount); 445 void HAL_TSP_SecFlt_ClrCtrl(MS_U32 u32EngId, MS_U32 u32SecFltId); 446 void HAL_TSP_SecFlt_SetMask(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8Mask); 447 void HAL_TSP_SecFlt_SetNMask(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8NMask); 448 void HAL_TSP_SecFlt_SetMatch(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8Match); 449 void HAL_TSP_SecFlt_SetReqCount(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32ReqCount); 450 MS_U32 HAL_TSP_SecFlt_GetMode(MS_U32 u32EngId, MS_U32 u32SecFltId); 451 void HAL_TSP_SecFlt_PcrReset(MS_U32 u32EngId, MS_U32 u32SecFltId); 452 void HAL_TSP_SecFlt_VerReset(MS_U32 u32SecFltId); 453 void HAL_TSP_SecFlt_SetDataAddr(MS_PHY phyDataAddr); 454 455 MS_PHY HAL_TSP_SecBuf_GetBufRead(MS_U32 u32EngId, MS_U32 u32SecBufId); 456 MS_PHY HAL_TSP_SecBuf_GetBufWrite(MS_U32 u32EngId, MS_U32 u32SecBufId); 457 void HAL_TSP_SecBuf_SetBuffer(MS_U32 u32EngId, MS_U32 u32SecBufId, MS_PHY phyStartAddr, MS_U32 u32BufSize); 458 void HAL_TSP_SecBuf_SetBufRead(MS_U32 u32EngId, MS_U32 u32SecBufId, MS_PHY phyReadAddr); 459 MS_PHY HAL_TSP_SecBuf_GetBufStart(MS_U32 u32EngId, MS_U32 u32SecBufId); 460 MS_PHY HAL_TSP_SecBuf_GetBufEnd(MS_U32 u32EngId, MS_U32 u32SecBufId); 461 MS_PHY HAL_TSP_SecBuf_GetBufCur(MS_U32 u32EngId, MS_U32 u32SecBufId); 462 void HAL_TSP_SecFlt_SetMode(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32SecFltMode); 463 MS_U32 HAL_TSP_SecFlt_GetCRC32(MS_U32 u32EngId, MS_U32 u32SecFltId); 464 MS_U32 HAL_TSP_SecFlt_GetState(MS_U32 u32EngId, MS_U32 u32SecFltId); 465 void HAL_TSP_SecBuf_SetBufRead_tmp(MS_U32 u32EngId, MS_U32 u32SecBufId, MS_PHY phyReadAddr); 466 MS_PHY HAL_TSP_SecBuf_GetBufWrite_tmp(MS_U32 u32EngId, MS_U32 u32SecBufId); 467 468 void HAL_TSP_PVR_SetBuffer(MS_U8 u8PVRId, MS_PHY phyBufStart0, MS_PHY phyBufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1); 469 void HAL_TSP_PVR_Enable(MS_U8 u8PVRId, MS_BOOL bEnable); 470 void HAL_TSP_PVR_Reset(MS_U8 u8PVRId); 471 void HAL_TSP_PVR_All(MS_U8 u8PVRId, MS_BOOL bPvrAll, MS_BOOL bWithNull, MS_BOOL bOldMode); 472 MS_PHY HAL_TSP_PVR_GetBufWrite(MS_U8 u8PVRId); 473 void HAL_TSP_PVR_WaitFlush(MS_U8 u8PVRId); 474 void HAL_TSP_PVR_BypassHeader_En(MS_U8 u8PVRId, MS_BOOL bBypassHD); 475 void HAL_TSP_PVR_Src_Select(MS_U8 u8PVRId, MS_U32 u32Src); 476 MS_U32 HAL_TSP_PVR_StartingEngs_Get(MS_U32 u32PktDmxSrc); 477 MS_BOOL HAL_TSP_PVR_IsEnabled(MS_U32 u32EngId); 478 MS_BOOL HAL_TSP_PVR_Alignment_Enable(MS_U8 u8PVRId, MS_BOOL bEnable); 479 MS_BOOL HAL_TSP_PVR_ForceSync_Enable(MS_U8 u8PVRId, MS_BOOL bEnable); 480 void HAL_TSP_PVR_PacketMode(MS_U8 u8PVRId, MS_BOOL bSet); 481 MS_BOOL HAL_TSP_PVR_Fifo_Block_Disable(MS_U8 u8PVRId, MS_BOOL bDisable); 482 MS_U32 HAL_TSP_GetPVRTimeStamp(MS_U8 u8PVRId); 483 void HAL_TSP_SetPVRTimeStamp(MS_U8 u8PVRId, MS_U32 u32Stamp); 484 void HAL_TSP_SetPVRTimeStampClk(MS_U8 u8PVRId, MS_U32 u32ClkSrc); 485 486 MS_BOOL HAL_TSP_Read_DropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt); 487 void HAL_TSP_TSIF0_Enable(MS_BOOL bEnable); 488 void HAL_TSP_TSIF1_Enable(MS_BOOL bEnable); 489 void HAL_TSP_TSIFFI_SrcSelect(MS_BOOL bFileMode); 490 491 MS_U32 HAL_REG32_IndR(REG32 *reg); 492 void HAL_REG32_IndW(REG32 *reg, MS_U32 value); 493 494 // void HAL_TSP_SetFwMsg(MS_U32 u32Mode); 495 // MS_U32 HAL_TSP_GetFwMsg(void); 496 void HAL_TSP_ISR_SAVE_ALL(void); 497 void HAL_TSP_ISR_RESTORE_ALL(void); 498 void HAL_TSP_PS_Path_Disable(void); 499 void HAL_TSP_PS_Path_Enable(MS_U32 u32TsDmaCtrl); 500 void HAL_TSP_CSA_Set_ScrmPath(MS_U8 u8EngId, MS_U32 u32ScrmPath); 501 MS_U32 HAL_TSP_CSA_Get_ScrmPath(MS_U8 u8EngId); 502 MS_BOOL HAL_TSP_CSA_Set_CACtrl(MS_U8 u8EngId, MS_U8 u8SrcTSIF, MS_U32 u32Dst); 503 MS_BOOL HAL_TSP_CSA_Get_CACtrl(MS_U8 u8EngId, MS_U8* pu8SrcTSIF, MS_U32* pu32Dst); 504 505 MS_U32 HAL_TSP_Get_FW_VER(void); 506 MS_BOOL HAL_TSP_Check_FW_VER(void); 507 MS_BOOL HAL_TSP_SetFwDbgMem(MS_PHY phyAddr, MS_U32 u32Size); 508 MS_BOOL HAL_TSP_SetFwDbgWord(MS_U32 u32Word); 509 MS_U32 HAL_TSP_GetDBGPortInfo(MS_U32 u32dbgsel); 510 MS_U8 HAL_TSP_Get_PesScmb_Sts(MS_U8 u8FltId); 511 MS_U8 HAL_TSP_Get_TsScmb_Sts(MS_U8 u8FltId); 512 513 //------- VQ Funcions ----------------------------------------------------------- 514 void HAL_TSP_SetVQBuffer(MS_U8 u8VQId, MS_PHY phyBaseAddr, MS_U32 u32BufLen); 515 void HAL_TSP_VQueue_Enable(MS_BOOL bEnable); 516 void HAL_TSP_VQueue_Reset(MS_U8 u8VQId); 517 void HAL_TSP_VQueue_OverflowInt_En(MS_U8 u8VQId, MS_BOOL bEnable); 518 void HAL_TSP_VQueue_Clr_OverflowInt(MS_U8 u8VQId); 519 void HAL_TSP_Set_Req_VQ_RX_Threshold(MS_U8 u8req_len); 520 MS_U32 HAL_TSP_Get_VQStatus(void); 521 void HAL_TSP_VQBlock_Disable(MS_U8 u8VQId, MS_BOOL bDisable); 522 //----------------------------------------------------------------------------- 523 524 //------------------ MOBF Functions --------------- 525 //--- decrypt address must be the same as encrypt address ------ 526 void HAL_TSP_MOBF_Select(MS_U8 u8Model, MS_U8 u8MobfIndex0, MS_U8 u8MobfIndex1); 527 //--------------------------------------------------------- 528 529 // ------------------------------------------------------------- 530 // Common api for mode setting 531 // u32Cmd[31]: 0 -> public cmd, 1 -> private cmd 532 // ------------------------------------------------------------- 533 // HAL_CMD_ONEWAY : Oneway record enable, 1-> Rec scrmable stream disable, 2 -> PVR oneway, 4 -> LoadFW oneway 534 // ------------------------------------------------------------- 535 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 536 #define HAL_CMD_ONEWAY 0x80000001UL //u32Config0: 1-> Rec SCM stream disable , 2->OnewayPVRPort, 4->OnewayFW; u32Config1,pData: Don't care 537 #define HAL_CMD_PVR_PES_MODE 0x00000030UL //u32Config0: PVR EngineID, u32Config1=1, *pData = 1 is enable, pData = 0 is disable 538 539 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Opt); 540 541 // ------------------------------------------------------------- 542 // Debug table 543 // ------------------------------------------------------------- 544 MS_U32 HAL_TSP_Get_DisContiCnt(TSP_DisconPktCnt_Info* TspDisconPktCntInfo); 545 MS_U32 HAL_TSP_Get_DropPktCnt(TSP_DropPktCnt_Info* TspDropCntInfo); 546 MS_U32 HAL_TSP_Get_LockPktCnt(TSP_LockPktCnt_info* TspLockCntInfo); 547 MS_U32 HAL_TSP_GetAVPktCnt(TSP_AVPktCnt_info* TspAVCntInfo); 548 549 MS_U32 HAL_TSP_Get_SecTEI_PktCount(MS_U32 u32PktSrc); 550 MS_BOOL HAL_TSP_Reset_SecTEI_PktCount(MS_U32 u32PktSrc); 551 MS_U32 HAL_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltId); 552 MS_BOOL HAL_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltId); 553 554 // ------------------------------------------------------------- 555 // Merge Stream 556 // ------------------------------------------------------------- 557 MS_BOOL HAL_TSP_Set_Sync_Byte(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SyncByte, MS_BOOL bSet); 558 MS_BOOL HAL_TSP_Set_Src_Id(MS_U8 u8Path, MS_U8 u8Id, MS_U8 *pu8SrcId, MS_BOOL bSet); 559 560 // ATS Calibration API 561 MS_BOOL HAL_TSP_Set_ATS_AdjPeriod(MS_U16 u16Value); 562 MS_BOOL HAL_TSP_Set_ATS_AdjEnable(MS_BOOL bEnable); 563 MS_BOOL HAL_TSP_Set_ATS_AdjOffset(MS_BOOL bIncreased, MS_U16 u16Offset); 564 MS_BOOL HAL_TSP_DropScmbPkt(MS_U32 u32StreamId,MS_BOOL bEnable); 565 566 567 568 #endif // #ifndef __HAL_TSP_H__ 569