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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSO.h 98 // Description: TS I/O Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _TSO_REG_H_ 103 #define _TSO_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define TSO_ENGINE_NUM (1UL) 137 #define TSO_PIDFLT_NUM (128UL) 138 #define TSO_REP_PIDFLT_NUM (16UL) 139 #define TSO_TSIF_NUM (3UL) 140 #define TSO_FILE_IF_NUM (2UL) 141 #define TSO_SVQ_UNIT_SIZE (208UL) 142 143 #define TSO_PIDFLT_NUM_ALL TSO_PIDFLT_NUM 144 145 #define TSO_PID_NULL 0x1FFFUL 146 147 #define TSO_MIU_BUS 4UL 148 149 //------------------------------------------------------------------------------------------------- 150 // Harware Capability 151 //------------------------------------------------------------------------------------------------- 152 153 #define TSO_IN_MUX_TS0 0x0UL 154 #define TSO_IN_MUX_TS1 0x1UL 155 #define TSO_IN_MUX_TS2 0x2UL 156 #define TSO_IN_MUX_TS3 0x3UL 157 #define TSO_IN_MUX_TS4 0x4UL 158 #define TSO_IN_MUX_TS5 0x5UL 159 #define TSO_IN_MUX_TSDEMOD 0x7UL 160 #define TSO_IN_MUX_MEM 0x8UL 161 162 #define TSO_CLKIN_TS0 0x00UL 163 #define TSO_CLKIN_TS1 0x04UL 164 #define TSO_CLKIN_TS2 0x08UL 165 #define TSO_CLKIN_TS3 0x0CUL 166 #define TSO_CLKIN_TS4 0x10UL 167 #define TSO_CLKIN_TS5 0x14UL 168 #define TSO_CLKIN_DMD 0x1CUL 169 170 //--------------- u16ClkOutDivSrcSel ------------- 171 #define TSO_OUT_DIV_DMPLLDIV5 0x0000UL // dmplldiv5 = 844/5 = 172.8MHz 172 #define TSO_OUT_DIV_DMPLLDIV3 0x0001UL // dmplldiv3 = 844/3 = 288MHz 173 174 // Note: 175 // DVB-T dmplldiv5 / 2 (11+1) = 7.2 MHz 176 // DVB-C dmplldiv5 / 2 (11+1) = 7.2 MHz 177 // ATSC dmplldiv5 / 2 (11+1) = 7.2 MHz 178 // ISDB-T dmplldiv_3 / 2 (17+1) = 8 MHz 179 180 //---------------- u16ClkOutSel --------------- 181 #define TSO_OUT_DIV2 0x0000UL // Must also select div src and set div num 182 #define TSO_OUT_62MHz 0x0400UL 183 #define TSO_OUT_54MHz 0x0800UL 184 #define TSO_OUT_PTSO_OUT 0x0C00UL //live-in 185 #define TSO_OUT_PTSO_OUT_DIV8 0x1000UL //live-in 186 #define TSO_OUT_27MHz 0x1400UL 187 #define TSO_OUT_DEMOD_P 0x1C00UL //live-in 188 189 //--------------- u16PreTsoOutSel ------------- 190 #define TSO_PRE_OUT_TS0IN 0x0000UL 191 #define TSO_PRE_OUT_TS1IN 0x0001UL 192 #define TSO_PRE_OUT_TS2IN 0x0002UL 193 #define TSO_PRE_OUT_DEMDOIN 0x0003UL 194 #define TSO_PRE_OUT_TS3IN 0x0004UL 195 #define TSO_PRE_OUT_TS4IN 0x0005UL 196 #define TSO_PRE_OUT_TS5IN 0x0006UL 197 198 //------------------------------------------------------------------------------------------------- 199 // Type and Structure 200 //------------------------------------------------------------------------------------------------- 201 202 #define REG_PIDFLT_BASE (0x00210000UL << 1UL) // Fit the size of REG32 203 204 #define REG_CTRL_BASE_TSO (0x27400UL) // 0x113A 205 #define REG_CTRL_BASE_TSO1 (0x47A00UL) // 0x123D 206 207 208 typedef struct _REG32 209 { 210 volatile MS_U16 L; 211 volatile MS_U16 empty_L; 212 volatile MS_U16 H; 213 volatile MS_U16 empty_H; 214 } REG32; 215 216 typedef struct _REG16 217 { 218 volatile MS_U16 data; 219 volatile MS_U16 _resv; 220 } REG16; 221 222 typedef REG32 REG_PidFlt; 223 224 // PID 225 #define TSO_PIDFLT_PID_MASK 0x00001FFFUL 226 #define TSO_PIDFLT_PID_SHFT 0UL 227 228 // Channel source 229 #define TSO_PIDFLT_IN_SHIFT 13UL 230 #define TSO_PIDFLT_IN_MASK 0x0000E000UL 231 #define TSO_PIDFLT_IN_CH0 0x00002000UL 232 #define TSO_PIDFLT_IN_CH5 0x0000A000UL 233 #define TSO_PIDFLT_IN_CH6 0x0000C000UL 234 235 typedef struct _REG_Pid 236 { // Index(word) CPU(byte) Default 237 REG_PidFlt Flt[TSO_PIDFLT_NUM]; 238 } REG_Pid; 239 240 241 typedef struct _REG_Ctrl_TSO 242 { 243 //---------------------------------------------- 244 // 0xBF802A00 MIPS direct access 245 //---------------------------------------------- 246 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 247 248 REG16 SW_RSTZ; // 0xbf827400 0x00 249 #define TSO_SW_RSTZ_DISABLE 0x0001UL 250 #define TSO_SW_RSTZ_CLK_STAMP 0x0002UL 251 #define TSO_SW_RSTZ_CMDQ1 0x0100UL 252 #define TSO_SW_RSTZ_WB1 0x0200UL 253 #define TSO_SW_RSTZ_WB_DMA1 0x0400UL 254 #define TSO_SW_RSTZ_TS_FIN1 0x0800UL 255 #define TSO_SW_RSTZ_CMDQ 0x1000UL 256 #define TSO_SW_RSTZ_WB 0x2000UL 257 #define TSO_SW_RSTZ_WB_DMA 0x4000UL 258 #define TSO_SW_RSTZ_TS_FIN 0x8000UL 259 #define TSO_SW_RSTZ_ALL 0x00FEUL 260 261 REG16 SW_RSTZ1; // 0xbf827404 0x01 262 #define TSO_SW_RSTZ1_CH_IF1 0x0001UL 263 #define TSO_SW_RSTZ1_CH_IF5 0x0010UL 264 #define TSO_SW_RSTZ1_CH_IF6 0x0020UL 265 #define TSO_SW_RSTZ1_ALL 0x0031UL 266 267 REG32 _xbf827408_740c; // 0xbf827408~0xbf82740c 0x02~03 268 269 REG16 TSO_CH0_IF1_CFG0; // 0xbf827410 0x04 270 #define TSO_PKT_SIZE_CHK_LIVE_MASK 0x00FFUL 271 #define TSO_PIDFLT_PKT_SIZE_MASK 0xFF00UL 272 #define TSO_PIDFLT_PKT_SIZE_SHIFT 8UL 273 274 REG16 TSO_CH0_IF1_CFG1; // 0xbf827414 0x05 //sunc byte 275 REG16 TSO_CH0_IF1_CFG2; // 0xbf827418 0x06 276 #define TSO_CHCFG_P_SEL 0x0001UL 277 #define TSO_CHCFG_EXT_SYNC_SEL 0x0002UL 278 #define TSO_CHCFG_TS_SIN_C0 0x0004UL 279 #define TSO_CHCFG_TS_SIN_C1 0x0008UL 280 #define TSO_CHCFG_PIDFLT_REC_ALL 0x0010UL // bypass all packets 281 #define TSO_CHCFG_PIDFLT_REC_NULL 0x0020UL // bypass NULL packets 282 #define TSO_CHCFG_PIDFLT_OVF_INT_EN 0x0040UL 283 #define TSO_CHCFG_PIDFLT_OVF_CLR 0x0080UL 284 #define TSO_CHCFG_FORCE_SYNC_BYTE 0x0100UL 285 #define TSO_CHCFG_SKIP_TEI_PKT 0x0200UL 286 #define TSO_CHCFG_DIS_LOCKED_PKT_CNT 0x0400UL 287 #define TSO_CHCFG_CLR_LOCKED_PKT_CNT 0x0800UL 288 #define TSO_CHCFG_TRC_CLK_LD_DIS 0x1000UL 289 #define TSO_CHCFG_TRC_CLK_CLR 0x2000UL 290 REG16 TSO_CH0_IF1_CFG3; // 0xbf82741c 0x07 291 292 REG16 _xbf827470_747c[12]; // 0xbf827420~0xbf82744c 0x08~13 293 294 REG16 TSO_CH0_IF5_CFG0; // 0xbf827450 0x14 295 REG16 TSO_CH0_IF5_CFG1; // 0xbf827454 0x15 296 REG16 TSO_CH0_IF5_CFG2; // 0xbf827458 0x16 297 REG16 TSO_CH0_IF5_CFG3; // 0xbf82745c 0x17 298 299 REG16 TSO_CH0_IF6_CFG0; // 0xbf827460 0x18 300 REG16 TSO_CH0_IF6_CFG1; // 0xbf827464 0x19 301 REG16 TSO_CH0_IF6_CFG2; // 0xbf827468 0x1a 302 REG16 TSO_CH0_IF6_CFG3; // 0xbf82746c 0x1b 303 304 REG16 TSO_CFG0; // 0xbf827470 0x1c 305 #define TSO_CFG0_S2P0_SHIFT 0UL 306 #define TSO_CFG0_S2P1_SHIFT 1UL 307 #define TSO_CFG0_S2P_CFG_MASK 0x001FUL 308 #define TSO_CFG0_S2P_EN 0x0001UL 309 #define TSO_CFG0_S2P_TS_SIN_C0 0x0002UL 310 #define TSO_CFG0_S2P_TS_SIN_C1 0x0004UL 311 #define TSO_CFG0_S2P_TS_3WIRE_MOD 0x0008UL 312 #define TSO_CFG0_S2P_BYPASS 0x0010UL 313 314 REG16 TSO_CFG1; // 0xbf827474 0x1d 315 #define TSO_CFG1_TSO_OUT_EN 0x0001UL 316 #define TSO_CFG1_TSO_TSIF1_EN 0x0002UL 317 #define TSO_CFG1_TSO_TSIF5_EN 0x0020UL 318 #define TSO_CFG1_TSO_TSIF6_EN 0x0040UL 319 #define TSO_CFG1_CLK_TRC_SEL_MASK 0x0E00UL 320 #define TSO_CFG1_PKT_LOCK_CLR 0x2000UL 321 #define TSO_CFG1_NULL_EN 0x4000UL 322 #define TSO_CFG1_PKT_PARAM_LD 0x8000UL 323 324 REG16 TSO_CFG2; // 0xbf827478 0x1e 325 #define TSO_CFG2_VALID_BYTECNT_MASK 0x00FFUL 326 #define TSO_CFG2_INVALID_BYTECNT_MASK 0xFF00UL 327 #define TSO_CFG2_VALID_BYTECNT_SHIFT 0UL 328 #define TSO_CFG2_INVALID_BYTECNT_SHIFT 8UL 329 330 REG16 TSO_CFG3; // 0xbf82747c 0x1f //opif_pkt_size 331 332 REG32 REP_PidFlt[16]; // 0xbf827480~0xbf8274F8 0x20~0x3e 333 #define REP_PIDFLT_ORG_PID_MASK 0x00001FFFUL 334 #define REP_PIDFLT_SRC_MASK 0x0000E000UL 335 #define REP_PIDFLT_SRC_SHIFT 13UL 336 #define REP_PIDFLT_SRC_CH1 0x00002000UL 337 #define REP_PIDFLT_SRC_CH5 0x0000A000UL 338 #define REP_PIDFLT_SRC_CH6 0x0000C000UL 339 #define REP_PIDFLT_NEW_PID_MASK 0x01FFF000UL 340 #define REP_PIDFLT_NEW_PID_SHIFT 16UL 341 #define REP_PIDFLT_REPLACE_EN 0x80000000UL 342 343 REG16 TSO_CLR_BYTE_CNT; // 0xbf827500 0x40 344 #define TSO_CLR_BYTE_CNT_1 0x0000UL 345 #define TSO_CLR_BYTE_CNT_5 0x0004UL 346 #define TSO_CLR_BYTE_CNT_6 0x0005UL 347 348 REG32 TSO_SYSTIMESTAMP; // 0xbf827504~0xbf827508 0x41~42 349 350 REG16 TSO_CFG4; // 0xbf82750c 0x43 351 #define TSO_CFG4_LOCK_RET_SYS_TIMESTAMP 0x0001UL 352 #define TSO_CFG4_ENABLE_SYS_TIMESTAMP 0x0002UL 353 #define TSO_CFG4_SET_SYS_TIMESTAMP 0x0004UL 354 #define TSO_CFG4_SET_TIMESTAMP_BASE_MASK 0x0008UL 355 #define TSO_CFG4_SET_TIMESTAMP_90K 0x0000UL 356 #define TSO_CFG4_SET_TIMESTAMP_27M 0x0008UL 357 #define TSO_CFG4_PIDTABLE_SRAM_SD_EN 0x0010UL 358 #define TSO_CFG4_NULL_PKT_ID_MASK 0xF000UL 359 360 REG16 TSO_CFG5; // 0xbf82750c 0x44 361 #define TSO_CFG5_WIRE_MODE_EN_1 0x0001UL 362 #define TSO_CFG5_WIRE_MODE_EN_5 0x0010UL 363 #define TSO_CFG5_WIRE_MODE_EN_6 0x0020UL 364 #define TSO_CFG5_DIS_MIU_RQ 0x0400UL 365 366 REG32 TSO_INDR_ADDR; // 0xbf82750c~0xbf827510 0x45~0x46 367 REG32 TSO_INDR_WDATA; // 0xbf827514~0xbf827518 0x47~0x48 368 REG16 TSO_INDR_RDATA; // 0xbf82751c 0x49 369 REG16 TSO_INDR_CTRL ; // 0xbf827520 0x4a 370 #define TSO_INDIR_W_ENABLE 0x0001UL 371 #define TSO_INDIR_R_ENABLE 0x0002UL 372 373 REG16 TSO_STATUS; // 0xbf827524 0x4b 374 375 REG16 TSO_FI_TIMER[2]; // 0xbf827528~0xbf82752c 0x4c~0x4d 376 377 REG16 TSO_STATUS1; // 0xbf827530 0x4e 378 #define TSO_PIDFLT_OVF_EVER_TSIF0 0x0001UL 379 #define TSO_PIDFLT_OVF_EVER_TSIF5 0x0010UL 380 #define TSO_PIDFLT_OVF_EVER_TSIF6 0x0020UL 381 382 REG16 _xbf827534_7568[12]; // 0xbf827534~0xbf827568 0x4f~0x5a 383 384 REG16 TSO_TRACE_HIGH; // 0xbf82756c 0x5b 385 REG16 TSO_TRACE_LOW; // 0xbf827570 0x5c 386 REG16 TSO_TRACE_1t; // 0xbf827574 0x5d 387 388 REG16 TSO_BLOCK_SIZE_DB; // 0xbf827578 0x5e 389 REG16 TSO_BLOCK_OPT_DB; // 0xbf82757c 0x5f 390 391 REG32 TSO_Filein_raddr; // 0xbf827580~0xbf827584 0x60-0x61 392 REG32 TSO_Filein_rNum; // 0xbf827588~0xbf82758c 0x62-0x63 393 REG16 TSO_Filein_Ctrl; // 0xbf827590 0x64 394 #define TSO_FILEIN_CTRL_MASK 0x0003UL 395 #define TSO_FILEIN_RSTART 0x0001UL 396 #define TSO_FILEIN_ABORT 0x0002UL 397 #define TSO_FILEIN_MOBF_IDX_MASK 0x1F00UL 398 #define TSO_FILEIN_MOBF_IDX_SHIFT 8UL 399 #define TSO_FILEIN_RIU_TSO_NS 0x2000UL 400 401 REG32 TSO_Filein_raddr1; // 0xbf827594~0xbf827598 0x65-0x66 402 REG32 TSO_Filein_rNum1; // 0xbf82759c~0xbf8275a0 0x67-0x68 403 REG16 TSO_Filein_Ctrl1; // 0xbf8275a4 0x69 404 405 REG16 TSO_PKT_CNT_SEL; // 0xbf8275a8 0x6a 406 #define TSO_PKT_CNT_SEL_MASK 0x000FUL 407 #define TSO_PKT_CNT_LOCKED_CNT_MASK 0x00F0UL 408 #define TSO_PKT_CNT_DBG_MASK 0xFF00UL 409 410 REG16 TSO_PKT_CHKSIZE_FI; // 0xbf8275ac 0x6b 411 #define TSO_PKT_CHKSIZE_FI_MASK 0x00FFUL 412 #define TSO_PKT_CHKSIZE_FI1_MASK 0xFF00UL 413 414 REG32 TSO_LPCR2[2]; // 0xbf8275b0~ 0xbf8275bc 0x6c~0x6f 415 REG32 TSO_TIMESTAMP[2]; // 0xbf8275c0~ 0xbf8275cc 0x70~0x73 416 REG32 TSO_TSO2MI_RADDR[2]; // 0xbf8275d0~ 0xbf8275dc 0x74~0x77 417 418 REG16 TSO_CMDQ_STATUS; // 0xbf8275e0 0x78 419 #define TSO_CMDQ_SIZE 8UL 420 #define TSO_CMDQ_STS_WCNT_MASK 0x000FUL 421 #define TSO_CMDQ_STS_WLEVEL_MASK 0x0030UL 422 #define TSO_CMDQ_STS_FIFO_FULL 0x0040UL 423 #define TSO_CMDQ_STS_FIFO_EMPTY 0x0080UL 424 #define TSO_CMDQ_STS1_SHIFT 8UL 425 426 REG16 TSO_FILE_CFG[2]; // 0xbf8275e4~0xbf8275e8 0x79~0x7a 427 #define TSO_FICFG_TSO2MI_RPRI 0x0001UL 428 #define TSO_FICFG_MEM_TSDATA_ENDIAN 0x0002UL 429 #define TSO_FICFG_MEM_TS_W_ORDER 0x0004UL 430 #define TSO_FICFG_LPCR2_WLD 0x0008UL 431 #define TSO_FICFG_LPCR2_LD 0x0010UL 432 #define TSO_FICFG_DIS_MIU_RQ 0x0020UL 433 #define TSO_FICFG_RADDR_READ 0x0040UL 434 #define TSO_FICFG_TS_DATAPORT_SEL 0x0080UL 435 #define TSO_FICFG_TSO_FILEIN 0x0100UL 436 #define TSO_FICFG_TIMER_ENABLE 0x0200UL 437 #define TSO_FICFG_PKT192_BLK_DISABLE 0x0400UL 438 #define TSO_FICFG_PKT192_ENABLE 0x0800UL 439 #define TSO_FICFG_FILE_SEGMENT 0x1000UL 440 #define TSO_FICFG_CLK_TIMESTAMP_SEL_MASK 0x2000UL 441 #define TSO_FICFG_CLK_TIMESTAMP_27M 0x2000UL 442 #define TSO_FICFG_CLK_TIMESTAMP_90K 0x0000UL 443 444 REG16 TSO_Interrupt; // 0xbf8275ec 0x7b 445 #define TSO_INT_ENABLE_MASK 0x00FFUL 446 #define TSO_INT_STATUS_MASK 0xFF00UL 447 #define TSO_INT_DMA_DONE 0x0001UL 448 #define TSO_INT_DMA_DONE1 0x0002UL 449 #define TSO_INT_TRCCLK_UPDATE 0x0004UL 450 451 REG16 TSO_Interrupt1; // 0xbf8275f0 0x7c 452 #define TSO_INT1_ENABLE_MASK 0x00FFUL 453 #define TSO_INT1_STATUS_MASK 0xFF00UL 454 #define TSO_INT1_PIDFLT1_OVF 0x0001UL 455 #define TSO_INT1_PIDFLT5_OVF 0x0010UL 456 #define TSO_INT1_PIDFLT6_OVF 0x0020UL 457 458 REG32 TSO_DBG; // 0xbf8275f4~0xbf8275f8 0x7d~0x7e 459 REG16 TSO_DBG_SEL; // 0xbf8275fc 0x7f 460 461 } REG_Ctrl_TSO; 462 463 typedef struct _REG_Ctrl_TSO1 464 { 465 //---------------------------------------------- 466 // 0xBF802A00 MIPS direct access 467 //---------------------------------------------- 468 // Index(word) CPU(byte) MIPS(0x13A00/2+index)*4 469 470 REG16 TSO_PRE_HEADER1_CFG0; // 0xbf847A00 0x00 471 #define TSO_PRE_HD1_CFG0_LOCAL_STRID_MASK 0x00FFUL 472 473 REG16 TSO_PRE_HEADER1_CFG1; // 0xbf847A04 0x01 474 REG16 TSO_PRE_HEADER1_CFG2; // 0xbf847A08 0x02 475 REG16 TSO_PRE_HEADER1_CFG3; // 0xbf847A0c 0x03 476 477 REG16 _xbf827a10_7a3c[12]; // 0xbf847A10~0xbf847A3c 0x04~0x0f 478 479 REG16 TSO_PRE_HEADER5_CFG0; // 0xbf847A40 0x10 480 REG16 TSO_PRE_HEADER5_CFG1; // 0xbf847A44 0x11 481 REG16 TSO_PRE_HEADER5_CFG2; // 0xbf847A48 0x12 482 REG16 TSO_PRE_HEADER5_CFG3; // 0xbf847A4c 0x13 483 484 REG16 TSO_PRE_HEADER6_CFG0; // 0xbf847A40 0x14 485 REG16 TSO_PRE_HEADER6_CFG1; // 0xbf847A44 0x15 486 REG16 TSO_PRE_HEADER6_CFG2; // 0xbf847A48 0x16 487 REG16 TSO_PRE_HEADER6_CFG3; // 0xbf847A4c 0x17 488 489 REG32 TSO_SVQ1_BASE; // 0xbf847A50~0xbf847A54 0x18~0x19 490 REG16 TSO_SVQ1_SIZE; // 0xbf847A58 0x1a //unit:200byte/pkt 491 REG16 TSO_SVQ1_TX_CFG; // 0xbf847A5c 0x1b 492 #define TSO_SVQ_TX_CFG_WR_THRESHOLD_MASK 0x000FUL 493 #define TSO_SVQ_TX_CFG_PRI_THRESHOLD_MASK 0x00F0UL 494 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_MASK 0x0F00UL 495 #define TSO_SVQ_TX_CFG_FORCE_FIRE_CNT_SHIFT 8UL 496 #define TSO_SVQ_TX_CFG_TX_RESET 0x1000UL 497 #define TSO_SVQ_TX_CFG_OVF_INT_EN 0x2000UL 498 #define TSO_SVQ_TX_CFG_OVF_CLR 0x4000UL 499 #define TSO_SVQ_TX_CFG_SVQ_EN 0x8000UL 500 501 REG16 _xbf827a60_7a9c[12]; // 0xbf847A60~0xbf847A9c 0x1c~0x27 502 503 REG32 TSO_SVQ5_BASE; // 0xbf847Aa0~0xbf847Aa4 0x28~0x29 504 REG16 TSO_SVQ5_SIZE; // 0xbf847Aa8 0x2a //unit:200byte/pkt 505 REG16 TSO_SVQ5_TX_CFG; // 0xbf847Aac 0x2b 506 507 REG32 TSO_SVQ6_BASE; // 0xbf847Ab0~0xbf847Ab4 0x2c~0x2d 508 REG16 TSO_SVQ6_SIZE; // 0xbf847Ab8 0x2e //unit:200byte/pkt 509 REG16 TSO_SVQ6_TX_CFG; // 0xbf847Abc 0x2f 510 511 REG16 TSO_SVQ_RX_CFG; // 0xbf847Ac0 0x30 512 #define TSO_SVQ_RX_CFG_MODE_MASK 0x0003UL 513 #define TSO_SVQ_RX_CFG_MODE_OPENCBL 0x0000UL 514 #define TSO_SVQ_RX_CFG_MODE_CIPL 0x0001UL 515 #define TSO_SVQ_RX_CFG_MODE_192PKT 0x0002UL 516 #define TSO_SVQ_RX_CFG_RD_THRESHOLD_MASK 0x001CUL 517 #define TSO_SVQ_RX_CFG_ARBMODE_MASK 0x0060UL 518 #define TSO_SVQ_RX_CFG_ARBMODE_RUNROBIN 0x0000UL 519 #define TSO_SVQ_RX_CFG_ARBMODE_FIXPRI 0x0020UL 520 #define TSO_SVQ_RX_CFG_ARBMODE_DYMPRI 0x0040UL 521 #define TSO_SVQ_RX_CFG_DRAM_SD_ENABLE 0x0080UL 522 #define TSO_SVQ_RX_CFG_SVQ_FORCE_RESET 0x0100UL 523 #define TSO_SVQ_RX_CFG_SVQ_MIU_NS 0x0200UL 524 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_MASK 0x7C00UL 525 #define TSO_SVQ_RX_CFG_SVQ_MOBF_IDX_SHIFT 10UL 526 #define TSO_SVQ_RX_CFG_SVQ_DYN_PRI 0x8000UL 527 528 REG16 TSO_SVQ_RX_PRI[3]; // 0xbf847Ac4~0xbf847Acc 0x31~0x33 529 #define TSO_SVQ_RX_NUM 6UL 530 #define TSO_SVQ_RX_PRI_MASK 0xFFUL 531 #define TSO_SVQ_RX_PRI_SHIFT 8UL 532 533 REG32 TSO_SVQ_STATUS; // 0xbf847Ad0~0xbf847Ad4 0x34~0x35 534 #define TSO_SVQ_STS_MASK 0x000FUL 535 #define TSO_SVQ1_STS_SHIFT 0UL 536 #define TSO_SVQ5_STS_SHIFT 16UL 537 #define TSO_SVQ6_STS_SHIFT 20UL 538 #define TSO_SVQ_STS_EVER_FULL 0x0001UL 539 #define TSO_SVQ_STS_EVER_OVF 0x0002UL 540 #define TSO_SVQ_STS_EMPTY 0x0004UL 541 #define TSO_SVQ_STS_BUSY 0x0008UL 542 543 REG32 TSO_SVQ_STATUS2; // 0xbf847Ad8~0xbf847Adc 0x36~0x37 544 #define TSO_SVQ_STS2_MASK 0x000FUL 545 #define TSO_SVQ1_STS2_SHIFT 0UL 546 #define TSO_SVQ5_STS2_SHIFT 16UL 547 #define TSO_SVQ6_STS2_SHIFT 20UL 548 #define TSO_SVQ_STS2_TXFIFO_WLEVEL_MASK 0x000CUL 549 #define TSO_SVQ_STS2_TXFIFO_FULL 0x0002UL 550 #define TSO_SVQ_STS2_TXFIFO_EMPTY 0x0001UL 551 552 REG32 TSO_DELTA; // 0xbf847Ae0~0xbf847Ae4 0x38~0x39 553 554 REG16 TSO_DELTA_CFG; // 0xbf847Ae8 0x3a 555 #define TSO_DELTA_CFG_SEL_CH_MASK 0x0007UL 556 #define TSO_DELTA_CFG_DELTA_CLR 0x0008UL 557 #define TSO_DELTA_CFG_MAX_ID_MASK 0x0700UL 558 #define TSO_DELTA_CFG_MAX_ID_SHIFT 8UL 559 560 } REG_Ctrl_TSO1; 561 562 563 #endif // _TSO_REG_H_ 564 565