1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halPVR.h 20 // @brief PVR HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_PVR_H__ 24 #define __HAL_PVR_H__ 25 26 //-------------------------------------------------------------------------------------------------- 27 // Macro and Define 28 //-------------------------------------------------------------------------------------------------- 29 #define HAL_TSP_RET_NULL 0xFFFFFFFF 30 31 // PVR define 32 #define PVR_NUM 4 33 #define PVR_PIDFLT_DEF 0x1fff 34 35 // PVR buffer define 36 #define PVR_NON_OVERWRITE (MS_U64)0xDEADBEEFDEADBEEFLL 37 // If the PVR buffer in non-OverWrite state, the first 8 bytes of the PVR buffer must be the PVR_NON_OVERWRITE value 38 39 //VQ define 40 #define VQ_NUM 4 41 #define VQ_PACKET_UNIT_LEN 208 42 43 #define TSP_TSIF0 0x00 44 #define TSP_TSIF1 0x01 45 #define TSP_TSIF2 0x02 46 #define TSP_TSIF3 0x03 47 #define TSP_TSIF4 0x04 // not support 48 #define TSP_TSIF5 0x05 // not support 49 #define TSP_TSIF6 0x06 // not support 50 51 //FQ define 52 #define TSP_FQ_NUM 4 53 54 55 //u32Cmd of MApi_DMX_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config, MS_U32 u32DataNum, void *pData); 56 #define HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK 0x00000001 //[u32Config] 1:disable cc check on fw, 0: enable cc check on fw; [u32DataNum,*pData] do not use 57 58 //######################################################################### 59 //#### Software Capability Macro Start 60 //######################################################################### 61 62 #define TSP_CA_RESERVED_FLT_NUM 1 63 #define TSP_RECFLT_NUM 1 64 #define TSP_PIDFLT_REC_NUM TSP_PIDFLT_NUM // 0~191 (0 for CA) 65 // 195 for Err 66 // 194 for REC 67 // 193 for PCR1 68 // 192 for PCR0 69 70 #if HW_PCRFLT_ENABLE 71 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + STC_ENG_NUM + TSP_RECFLT_NUM) 72 #else 73 #define TSP_PIDFLT_NUM_ALL (TSP_PIDFLT_NUM + TSP_RECFLT_NUM) 74 #endif 75 76 //######################################################################### 77 //#### Software Capability Macro End 78 //######################################################################### 79 80 // CA FLT ID (CA HW limitation, the PID Filter "0" must be reserved for CA to connect PID SLOT TABLE.) 81 #define TSP_CAFLT_START_ID 0 82 #define TSP_CAFLT_END_ID (TSP_CAFLT_START_ID + TSP_CA_RESERVED_FLT_NUM) 83 84 // section FLT ID 85 #define TSP_SECFLT_START_ID TSP_CAFLT_END_ID 86 #define TSP_SECBUF_START_ID TSP_CAFLT_END_ID 87 #define TSP_SECFLT_END_ID (TSP_SECFLT_START_ID + TSP_SECFLT_NUM - TSP_CA_RESERVED_FLT_NUM) 88 #define TSP_SECBUF_END_ID (TSP_SECBUF_START_ID + TSP_SECBUF_NUM - TSP_CA_RESERVED_FLT_NUM) 89 90 // PID 91 #define TSP_PIDFLT_START_ID TSP_CAFLT_END_ID 92 #define TSP_PIDFLT_END_ID (TSP_PIDFLT_START_ID + TSP_PIDFLT_NUM - TSP_CA_RESERVED_FLT_NUM) 93 94 // PCR 95 #define TSP_PCRFLT_START_ID TSP_PIDFLT_END_ID 96 #define HAL_TSP_PCRFLT_GET_ID(NUM) (TSP_PCRFLT_START_ID + (NUM)) 97 #define TSP_PCRFLT_END_ID (TSP_PCRFLT_START_ID + TSP_PCRFLT_NUM) 98 99 // REC 100 #define TSP_RECFLT_IDX TSP_PCRFLT_END_ID 101 102 //-------------------------------------------------------------------------------------------------- 103 // Driver Compiler Option 104 //-------------------------------------------------------------------------------------------------- 105 106 107 //-------------------------------------------------------------------------------------------------- 108 // PVR Hardware Abstraction Layer 109 //-------------------------------------------------------------------------------------------------- 110 111 // HW characteristic 112 113 typedef enum _PVRENG_SEQ 114 { 115 E_TSP_PVR_PVRENG_START = 0, 116 E_TSP_PVR_PVRENG_0 = E_TSP_PVR_PVRENG_START, 117 E_TSP_PVR_PVRENG_1, 118 E_TSP_PVR_PVRENG_2, 119 E_TSP_PVR_PVRENG_3, 120 E_TSP_PVR_PVRENG_END, 121 E_TSP_PVR_ENG_INVALID, 122 } PVRENG_SEQ; 123 124 typedef enum _FILEENG_SEQ 125 { 126 E_FILEENG_TSIF0 = TSP_TSIF0, 127 E_FILEENG_TSIF1 = TSP_TSIF1, 128 E_FILEENG_TSIF2 = TSP_TSIF2, 129 E_FILEENG_TSIF3 = TSP_TSIF3, 130 E_FILEENG_INVALID, 131 132 } FILEENG_SEQ; 133 134 #if 1 // Destination type 135 typedef enum _TSP_DST_SEQ 136 { 137 E_TSP_DST_FIFO_VIDEO, 138 E_TSP_DST_FIFO_VIDEO3D, 139 E_TSP_DST_FIFO_VIDEO3, //Not support 140 E_TSP_DST_FIFO_VIDEO4, //Not support 141 E_TSP_DST_FIFO_VIDEO5, //Not support 142 E_TSP_DST_FIFO_VIDEO6, //Not support 143 E_TSP_DST_FIFO_VIDEO7, //Not support 144 E_TSP_DST_FIFO_VIDEO8, //Not support 145 146 E_TSP_DST_FIFO_AUDIO, 147 E_TSP_DST_FIFO_AUDIO2, 148 E_TSP_DST_FIFO_AUDIO3, 149 E_TSP_DST_FIFO_AUDIO4, 150 E_TSP_DST_FIFO_AUDIO5, //Not support 151 E_TSP_DST_FIFO_AUDIO6, //Not support 152 153 E_TSP_DST_INVALID, 154 } TSP_DST_SEQ; 155 #else 156 #define TSP_FltType MS_U32 157 /// TS stream fifo type (Exclusive usage) 158 #define E_TSP_FLT_FIFO_MASK 0x000000FF 159 #define E_TSP_FLT_FIFO_VIDEO 0x00000001 160 #define E_TSP_FLT_FIFO_AUDIO 0x00000002 161 #define E_TSP_FLT_FIFO_AUDIO2 0x00000004 162 #define E_TSP_FLT_FIFO_VIDEO3D 0x00000008 163 #endif 164 165 typedef enum _TSP_SRC_SEQ{ 166 E_TSP_SRC_PKTDMX0, 167 E_TSP_SRC_PKTDMX1, 168 E_TSP_SRC_PKTDMX2, 169 E_TSP_SRC_PKTDMX3, 170 E_TSP_SRC_PKTDMX4, //not used 171 E_TSP_SRC_PKTDMX5, //not used 172 E_TSP_SRC_MMFI0, 173 E_TSP_SRC_MMFI1, 174 175 E_TSP_SRC_INVALID, 176 } TSP_SRC_SEQ; 177 178 typedef enum _TSIF_CFG 179 { 180 // @NOTE should be Exclusive usage 181 E_TSP_TSIF_CFG_DIS = 0x0000, // 1: enable ts interface 0 and vice versa oppsite with en 182 E_TSP_TSIF_CFG_EN = 0x0001, 183 E_TSP_TSIF_CFG_PARA = 0x0002, 184 E_TSP_TSIF_CFG_SERL = 0x0000, // oppsite with Parallel 185 E_TSP_TSIF_CFG_EXTSYNC = 0x0004, 186 E_TSP_TSIF_CFG_BITSWAP = 0x0008, 187 E_TSP_TSIF_CFG_3WIRE = 0x0010 188 } TSP_TSIF_CFG; 189 190 // for stream input source 191 typedef enum _HAL_TS_PAD 192 { 193 E_TSP_TS_PAD_EXT0, 194 E_TSP_TS_PAD_EXT1, 195 E_TSP_TS_PAD_EXT2, 196 E_TSP_TS_PAD_EXT3, // 4/3 wired serial mode 197 E_TSP_TS_PAD_EXT4, // 4/3 wired serial mode 198 E_TSP_TS_PAD_EXT5, // 4/3 wired serial mode 199 E_TSP_TS_PAD_EXT6, // 3 wired serial mode 200 E_TSP_TS_PAD_EXT7, // not support 201 E_TSP_TS_PAD_INTER0, 202 E_TSP_TS_PAD_INTER1, // not support 203 E_TSP_TS_PAD_TSOUT0, 204 E_TSP_TS_PAD_TSOUT1, // not support 205 E_TSP_TS_PAD_INVALID, 206 } TSP_TS_PAD; 207 208 // for ts pad mode 209 typedef enum _HAL_TS_PAD_MUX_MODE 210 { 211 E_TSP_TS_PAD_MUX_PARALLEL, // in 212 E_TSP_TS_PAD_MUX_3WIRED_SERIAL, // in 213 E_TSP_TS_PAD_MUX_4WIRED_SERIAL, // in 214 E_TSP_TS_PAD_MUX_TSO, // out 215 E_TSP_TS_PAD_MUX_S2P, // out 216 E_TSP_TS_PAD_MUX_S2P1, // out 217 E_TSP_TS_PAD_MUX_DEMOD, // out 218 219 E_TSP_TS_PAD_MUX_INVALID 220 } TSP_TS_PAD_MUX_MODE; 221 222 223 // for pkt converter mode 224 typedef enum _HAL_TS_PKT_CONVERTER_MODE 225 { 226 E_TSP_PKT_CONVERTER_188Mode = 0, 227 E_TSP_PKT_CONVERTER_CIMode = 1, 228 E_TSP_PKT_CONVERTER_OpenCableMode = 2, 229 E_TSP_PKT_CONVERTER_ATSMode = 3, 230 E_TSP_PKT_CONVERTER_MxLMode = 4, 231 E_TSP_PKT_CONVERTER_Invalid, 232 } TSP_TS_PKT_CONVERTER_MODE; 233 234 typedef enum _HAL_TS_MXL_PKT_MODE 235 { 236 E_TSP_TS_MXL_PKT_192 = 4, 237 E_TSP_TS_MXL_PKT_196 = 8, 238 E_TSP_TS_MXL_PKT_200 = 12, 239 E_TSP_TS_MXL_PKT_INVALID, 240 } TSP_TS_MXL_PKT_MODE; 241 242 243 typedef enum _HAL_DMX_FLOW_DST 244 { 245 E_TSP_DMX_FLOW_PLAYBACK, 246 E_TSP_DMX_FLOW_PLAYBACK1, 247 E_TSP_DMX_FLOW_PLAYBACK2, 248 E_TSP_DMX_FLOW_PLAYBACK3, 249 }_HAL_DMX_FLOW_DST; 250 251 252 typedef enum _HAL_TSP_CLK_TYPE 253 { 254 E_TSP_HAL_TSP_CLK, 255 E_TSP_HAL_STC_CLK, 256 E_TSP_HAL_INVALID 257 } EN_TSP_HAL_CLK_TYPE; 258 259 260 typedef struct _HAL_TSP_CLK_STATUS 261 { 262 MS_BOOL bEnable; 263 MS_BOOL bInvert; 264 MS_U8 u8ClkSrc; 265 } ST_TSP_HAL_CLK_STATUS; 266 267 268 typedef enum _PCR_SRC 269 { 270 /* register setting for kaiser pcr 271 0: tsif0 272 1: tsif1 273 2: tsif2 274 3: tsif3 275 4: tsif4 276 5: tsif5 277 6: un-used 278 7: un-used 279 8: pkt merge 0 280 9: pkt merge 1 281 a: MM file in 1 282 b: MM file in 2 283 */ 284 E_TSP_PCR_SRC_TSIF0 = 0, 285 E_TSP_PCR_SRC_TSIF1, 286 E_TSP_PCR_SRC_TSIF2, 287 E_TSP_PCR_SRC_TSIF3, 288 E_TSP_PCR_SRC_TSIF4, 289 E_TSP_PCR_SRC_TSIF5, 290 E_TSP_PCR_SRC_PKT_MERGE0 = 8, 291 E_TSP_PCR_SRC_PKT_MERGE1, 292 E_TSP_PCR_SRC_MMFI0, 293 E_TSP_PCR_SRC_MMFI1, 294 E_TSP_PCR_SRC_INVALID, 295 } TSP_PCR_SRC; 296 297 typedef enum _CLR_SRC 298 { 299 E_TSP_CLR_SRC_TSIF0, 300 E_TSP_CLR_SRC_TSIF1, 301 E_TSP_CLR_SRC_TSIF2, //not support 302 E_TSP_CLR_SRC_TSIF3, //not support 303 E_TSP_CLR_SRC_MMFI0, 304 E_TSP_CLR_SRC_MMFI1, 305 E_TSP_CLR_SRC_INVALID, 306 } TSP_CLR_SRC; 307 308 309 typedef enum _HAL_TSP_TSIF // for HW TSIF 310 { 311 E_TSP_HAL_TSIF_0 , 312 E_TSP_HAL_TSIF_1 , 313 E_TSP_HAL_TSIF_2 , 314 E_TSP_HAL_TSIF_3 , 315 E_TSP_HAL_TSIF_4 , // not support 316 E_TSP_HAL_TSIF_5 , // not support 317 E_TSP_HAL_TSIF_6 , // not support 318 319 // @NOTE There are no real TSIFs for TSIF_PVRx , just use those for PVR backward competiable. 320 E_TSP_HAL_TSIF_PVR0 , 321 E_TSP_HAL_TSIF_PVR1 , 322 E_TSP_HAL_TSIF_PVR2 , 323 E_TSP_HAL_TSIF_PVR3 , 324 E_TSP_HAL_TSIF_INVALID , 325 } TSP_HAL_TSIF; 326 327 328 typedef enum _TSP_HAL_FileState 329 { 330 /// Command Queue is Idle 331 E_TSP_HAL_FILE_STATE_IDLE = 0000000000, 332 /// Command Queue is Busy 333 E_TSP_HAL_FILE_STATE_BUSY = 0x00000001, 334 /// Command Queue is Paused. 335 E_TSP_HAL_FILE_STATE_PAUSE = 0x00000002, 336 337 E_TSP_HAL_FILE_STATE_INVALID, 338 }TSP_HAL_FileState; 339 340 typedef enum 341 { 342 E_TSP_HAL_CAP_TYPE_PIDFLT_NUM = 0, 343 E_TSP_HAL_CAP_TYPE_SECFLT_NUM = 1, 344 E_TSP_HAL_CAP_TYPE_SECBUF_NUM = 2, 345 346 E_TSP_HAL_CAP_TYPE_RECENG_NUM = 3, 347 E_TSP_HAL_CAP_TYPE_RECFLT_NUM = 4, 348 E_TSP_HAL_CAP_TYPE_RECFLT1_NUM = 5, 349 350 E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM = 6, 351 E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM = 7, 352 353 E_TSP_HAL_CAP_TYPE_TSIF_NUM = 8, 354 E_TSP_HAL_CAP_TYPE_DEMOD_NUM = 9, 355 E_TSP_HAL_CAP_TYPE_TSPAD_NUM = 10, 356 E_TSP_HAL_CAP_TYPE_VQ_NUM = 11, 357 358 E_TSP_HAL_CAP_TYPE_CAFLT_NUM = 12, 359 E_TSP_HAL_CAP_TYPE_CAKEY_NUM = 13, 360 361 E_TSP_HAL_CAP_TYPE_FW_ALIGN = 14, 362 E_TSP_HAL_CAP_TYPE_VQ_ALIGN = 15, 363 E_TSP_HAL_CAP_TYPE_VQ_PITCH = 16, 364 E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN = 17, 365 E_TSP_HAL_CAP_TYPE_PVR_ALIGN = 18, 366 367 E_TSP_HAL_CAP_TYPE_PVRCA_PATH_NUM = 19, 368 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT_RANGE = 20, 369 E_TSP_HAL_CAP_TYPE_PVRCA0_FLT_RANGE = 21, 370 E_TSP_HAL_CAP_TYPE_PVRCA1_FLT_RANGE = 22, 371 E_TSP_HAL_CAP_TYPE_PVRCA2_FLT_RANGE = 23, 372 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT1_RANGE = 24, 373 E_TSP_HAL_CAP_TYPE_SHAREKEY_FLT2_RANGE = 25, 374 375 E_TSP_HAL_CAP_TYPE_HW_TYPE = 26, 376 377 //27 is reserved, and can not be used 378 379 E_TSP_HAL_CAP_TYPE_VFIFO_NUM = 28, 380 E_TSP_HAL_CAP_TYPE_AFIFO_NUM = 29, 381 E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT = 30, 382 E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX = 31, 383 E_TSP_HAL_CAP_TYPE_RECFLT_IDX = 32, 384 385 E_TSP_HAL_CAP_TYPE_DSCMB_ENG_NUM = 33, 386 E_TSP_HAL_CAP_TYPE_MAX_MERGESTR_NUM = 34, 387 E_TSP_HAL_CAP_MAX_SEC_FLT_DEPTH = 35, 388 E_TSP_HAL_CAP_FW_BUF_SIZE = 36, 389 E_TSP_HAL_CAP_FW_BUF_RANGE = 37, 390 E_TSP_HAL_CAP_VQ_BUF_RANGE = 38, 391 E_TSP_HAL_CAP_SEC_BUF_RANGE = 39, 392 E_TSP_HAL_CAP_FIQ_NUM = 40, 393 E_TSP_HAL_CAP_TYPE_NULL, 394 } TSP_HAL_CAP_TYPE; 395 396 // @F_TODO remove unused enum member 397 typedef enum 398 { 399 E_TSP_HAL_CAP_VAL_PIDFLT_NUM = (TSP_PCRFLT_END_ID - TSP_PIDFLT_START_ID), 400 E_TSP_HAL_CAP_VAL_SECFLT_NUM = (TSP_SECFLT_END_ID - TSP_SECFLT_START_ID), 401 E_TSP_HAL_CAP_VAL_SECBUF_NUM = (TSP_SECBUF_END_ID - TSP_SECBUF_START_ID), 402 403 E_TSP_HAL_CAP_VAL_RECENG_NUM = 4, 404 E_TSP_HAL_CAP_VAL_RECFLT_NUM = TSP_PIDFLT_REC_NUM, 405 E_TSP_HAL_CAP_VAL_RECFLT_IDX = TSP_RECFLT_IDX, 406 E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX = TSP_PCRFLT_START_ID, 407 E_TSP_HAL_CAP_VAL_RECFLT1_NUM = 0xDEADBEEF, // 0xDEADBEEF for not support 408 409 E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM = 4, //MMFI0 filters 410 E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM = 4, //MMFI1 filters 411 412 E_TSP_HAL_CAP_VAL_TSIF_NUM = 4, 413 E_TSP_HAL_CAP_VAL_DEMOD_NUM = 2, //internal demod 414 E_TSP_HAL_CAP_VAL_TSPAD_NUM = 3, 415 E_TSP_HAL_CAP_VAL_VQ_NUM = 4, 416 417 E_TSP_HAL_CAP_VAL_CAFLT_NUM = (TSP_PIDFLT_END_ID - TSP_PIDFLT_START_ID), //@NOTE: flt number for descrypt purpose 418 E_TSP_HAL_CAP_VAL_CAKEY_NUM = 0xDEADBEEF, 419 420 E_TSP_HAL_CAP_VAL_FW_ALIGN = 0x100, 421 E_TSP_HAL_CAP_VAL_VQ_ALIGN = 16, // 16 byte align?? 422 E_TSP_HAL_CAP_VAL_VQ_PITCH = 208, // 208 byte per VQ unit 423 E_TSP_HAL_CAP_VAL_SECBUF_ALIGN = 16, // 16 byte align 424 E_TSP_HAL_CAP_VAL_PVR_ALIGN = 16, 425 426 E_TSP_HAL_CAP_VAL_PVRCA_PATH_NUM = 0xDEADBEEF, 427 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT_RANGE = 0xDEADBEEF, 428 E_TSP_HAL_CAP_VAL_PVRCA0_FLT_RANGE = 0xDEADBEEF, 429 E_TSP_HAL_CAP_VAL_PVRCA1_FLT_RANGE = 0xDEADBEEF, 430 E_TSP_HAL_CAP_VAL_PVRCA2_FLT_RANGE = 0xDEADBEEF, 431 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT1_RANGE = 0xDEADBEEF, 432 E_TSP_HAL_CAP_VAL_SHAREKEY_FLT2_RANGE = 0xDEADBEEF, 433 434 E_TSP_HAL_CAP_VAL_HW_TYPE = 0x80002003, 435 436 E_TSP_HAL_CAP_VAL_VFIFO_NUM = 2, 437 E_TSP_HAL_CAP_VAL_AFIFO_NUM = 4, 438 E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT = 1, 439 E_TSP_HAL_CAP_VAL_FIQ_NUM = TSP_TSIF_NUM, 440 441 E_TSP_HAL_CAP_VAL_FW_BUF_SIZE = 0x4000, 442 443 E_TSP_HAL_CAP_VAL_NULL = 0xDEADBEEF, 444 } TSP_HAL_CAP_VAL; 445 446 /// TSP TEI Remove Error Packet Infomation 447 typedef enum 448 { 449 E_TSP_HAL_TEI_REMOVE_AUDIO_PKT, ///< TEI Remoce Audio Packet 450 E_TSP_HAL_TEI_REMOVE_VIDEO_PKT ///< TEI Remoce Video Packet 451 452 }TSP_HAL_TEI_RmPktType; 453 454 /// TSP Packet Converter Input Mode 455 typedef enum 456 { 457 E_TSP_HAL_PKT_MODE_NORMAL, ///< Normal Mode (bypass) 458 E_TSP_HAL_PKT_MODE_CI, ///< CI+ 1.4 (188 bytes) 459 E_TSP_HAL_PKT_MODE_OPEN_CABLE, ///< Open Cable (200 bytes) 460 E_TSP_HAL_PKT_MODE_ATS, ///< ATS mode (192 bytes) (188+TimeStamp) 461 E_TSP_HAL_PKT_MODE_MXL_192, ///< MXL mode (192 bytes) 462 E_TSP_HAL_PKT_MODE_MXL_196, ///< MXL mode (196 bytes) 463 E_TSP_HAL_PKT_MODE_MXL_200 ///< MXL mode (200 bytes) 464 465 }TSP_HAL_PKT_MODE; 466 467 // TSP TimeStamp Clk Select 468 typedef enum 469 { 470 E_TSP_HAL_TIMESTAMP_CLK_90K = 0, 471 E_TSP_HAL_TIMESTAMP_CLK_27M = 1, 472 E_TSP_HAL_TIMESTAMP_CLK_INVALID = 2 473 474 } TSP_HAL_TimeStamp_Clk; 475 476 //---------------------------------- 477 /// DMX debug table information structure 478 //---------------------------------- 479 480 typedef enum 481 { 482 E_TSP_HAL_FLOW_LIVE0, 483 E_TSP_HAL_FLOW_LIVE1, 484 E_TSP_HAL_FLOW_LIVE2, 485 E_TSP_HAL_FLOW_LIVE3, 486 E_TSP_HAL_FLOW_LIVE4, // not support 487 E_TSP_HAL_FLOW_LIVE5, // not support 488 E_TSP_HAL_FLOW_LIVE6, // not support 489 490 E_TSP_HAL_FLOW_FILE0, 491 E_TSP_HAL_FLOW_FILE1, 492 E_TSP_HAL_FLOW_FILE2, 493 E_TSP_HAL_FLOW_FILE3, 494 E_TSP_HAL_FLOW_FILE4, // not support 495 E_TSP_HAL_FLOW_FILE5, // not support 496 E_TSP_HAL_FLOW_FILE6, // not support 497 498 E_TSP_HAL_FLOW_MMFI0, 499 E_TSP_HAL_FLOW_MMFI1, 500 501 E_TSP_HAL_FLOW_INVALID, 502 503 } TSP_HAL_FLOW; 504 505 typedef enum 506 { 507 E_TSP_HAL_MIU_SEL_MMFI = 0, 508 E_TSP_HAL_MIU_SEL_FQ = 1, 509 510 E_TSP_HAL_MIU_SEL_INVALID, 511 512 } TSP_HAL_MIU_SEL_TYPE; 513 514 //-------------------------------------------------------------------------------------------------- 515 // PVR HAL API 516 //-------------------------------------------------------------------------------------------------- 517 // Static Register Mapping for external access 518 #define REG_PIDFLT_BASE0 (0x00240000UL) 519 #define REG_PIDFLT_BASE1 (0x00241000UL) 520 #define REG_SECFLT_BASE (0x00221000UL) 521 #define REG_SECBUF_BASE (0x00221024UL) 522 #define REG_CTRL_BASE (0x00210200UL) 523 524 #define _REGPid0 ((REG_Pid*) (REG_PIDFLT_BASE0)) 525 #define _REGPid1 ((REG_Pid*) (REG_PIDFLT_BASE1)) 526 #define _REGSec ((REG_Sec*) (REG_SECFLT_BASE)) 527 #define _REGBuf ((REG_Buf*) (REG_SECBUF_BASE)) 528 //#define _REGSynth ((REG_Synth*)(REG_SYNTH_BASE )) 529 530 #define PPIDFLT0(_fltid) (&(_REGPid0->Flt[_fltid])) 531 #define PPIDFLT1(_fltid) (&(_REGPid1->Flt[_fltid])) 532 #define PSECFLT(_fltid) (&(((REG_Sec*)(REG_SECFLT_BASE+(_fltid>>5)*0x1000))->Flt[_fltid&(0x1F)])) 533 #define PSECBUF(_bufid) (&(((REG_Buf*)(REG_SECBUF_BASE+(_bufid>>5)*0x1000))->Buf[_bufid&(0x1F)])) 534 535 //#define TSIF2PKTDMX(_tsif) (((_tsif)<2)?(_tsif):((_tsif > 3)?(_tsif+2):(_tsif+1))) 536 537 //#define PKTDMX2TSIF(_pktdmx) ((_pktdmx)>2)?(((_pktdmx)==2)?(_pktdmx-1):(_pktdmx)):(((_pktdmx)==5)?(_pktdmx-2):(_pktdmx-1)) 538 539 540 541 //******************** PIDFLT DEFINE START ********************// 542 // PID 543 #define TSP_PIDFLT_PID_MASK 0x00001FFF 544 #define TSP_PIDFLT_PID_SHFT 0 545 546 // Continuous counter 547 #define TSP_PIDFLT_CC_MASK 0xFF000000 548 #define TSP_PIDFLT_CC_SHFT 24 549 550 // PIDFLT SRC 551 typedef enum _TSP_PIDFLT_SRC 552 { 553 E_TSP_PIDFLT_LIVE0, 554 E_TSP_PIDFLT_LIVE1, 555 E_TSP_PIDFLT_LIVE2, 556 E_TSP_PIDFLT_LIVE3, 557 E_TSP_PIDFLT_LIVE4, // not support 558 E_TSP_PIDFLT_LIVE5, // not support 559 E_TSP_PIDFLT_LIVE6, // not support 560 E_TSP_PIDFLT_FILE0, 561 E_TSP_PIDFLT_FILE1, 562 E_TSP_PIDFLT_FILE2, 563 E_TSP_PIDFLT_FILE3, 564 E_TSP_PIDFLT_FILE4, // not support 565 E_TSP_PIDFLT_FILE5, // not support 566 E_TSP_PIDFLT_FILE6, // not support 567 E_TSP_PIDFLT_INVALID, 568 } TSP_PIDFLT_SRC; 569 570 #define TSP_PIDFLT_IN_MASK 0x0000E000 571 #define TSP_PIDFLT_TSIF_SHFT 13 572 #define TSP_PIDFLT_TSIF0 0x00 573 #define TSP_PIDFLT_TSIF1 0x01 574 #define TSP_PIDFLT_TSIF2 0x02 575 #define TSP_PIDFLT_TSIF3 0x03 576 #define TSP_PIDFLT_TSIF_MAX 0x04 577 578 // Section filter Id (0~63) 579 #define TSP_PIDFLT_SECFLT_MASK 0x000000FF // [21:16] secflt id 580 #define TSP_PIDFLT_SECFLT_SHFT 0 581 582 // PIDFLT DST 583 typedef enum _TSP_PIDFLT_DST 584 { 585 E_TSP_PIDFLT_DST_VIDEO, 586 E_TSP_PIDFLT_DST_AUDIO, 587 E_TSP_PIDFLT_DST_PVR, 588 589 E_TSP_PIDFLT_DST_INVALID, 590 } TSP_PIDFLT_DST; 591 592 // AF/Sec/Video/V3D/Audio/AudioB/AudioC/AudioD/PVR1/PVR2/PVR3/PVR4 593 #define TSP_PIDFLT_SECFLT_NULL 0x000000FF // software usage clean selected section filter 594 #define TSP_PIDFLT_OUT_MASK 0x001FBF00 595 #define TSP_PIDFLT_OUT_SHFT 8 596 #define TSP_PIDFLT_OUT_NONE 0x00000000 597 #define TSP_PIDFLT_OUT_SECAF 0x00000100 598 #define TSP_PIDFLT_OUT_SECFLT 0x00000200 599 #define TSP_PIDFLT_OUT_VFIFO 0x00000400 600 #define TSP_PIDFLT_OUT_VFIFO3D 0x00000800 601 #define TSP_PIDFLT_OUT_AFIFO 0x00001000 602 #define TSP_PIDFLT_OUT_AFIFO2 0x00002000 603 #define TSP_PIDFLT_OUT_VFIFO3 0x00000000 //Not Support 604 #define TSP_PIDFLT_OUT_AFIFO3 0x00080000 605 #define TSP_PIDFLT_OUT_AFIFO4 0x00100000 606 #define TSP_PIDFLT_OUT_VFIFO4 0x00000000 //Not Support 607 608 // SRC ID 609 #define TSP_PIDFLT_SRCID_MASK 0xF0000000 610 #define TSP_PIDFLT_SRCID_SHIFT 28 611 612 //enable LUT 613 #define TSP_PIDFLT_OUT_LUT 0x00000000 //Not support 614 615 #define TSP_PIDFLT_PVRFLT_MASK 0x00078000 616 #define TSP_PIDFLT_PVRFLT_SHFT 15 617 #define TSP_PIDFLT_OUT_PVR1 0x00008000 618 #define TSP_PIDFLT_OUT_PVR2 0x00010000 619 #define TSP_PIDFLT_OUT_PVR3 0x00020000 620 #define TSP_PIDFLT_OUT_PVR4 0x00040000 621 622 623 #define TSP_PIDFLT_PKTPUSH_PASS_MASK 0x00200000 624 #define TSP_PIDFLT_PKTPUSH_PASS_SHFT 21 625 #define TSP_PID_FLT_PKTPUSH_PASS 0x00200000 626 627 #define TSP_PIDFLT_TSOFLT_MASK 0x00400000 628 #define TSP_PIDFLT_TSOFLT_SHFT 22 629 #define TSP_PID_FLT_OUT_TSO0 0x00400000 630 631 //******************** PIDFLT DEFINE END ********************// 632 void TSP32_IdrW(TSP32 *preg, MS_U32 value); 633 MS_U32 TSP32_IdrR(TSP32 *preg); 634 635 //=========================TSIF================================ 636 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad); 637 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable); 638 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn); 639 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable); 640 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 641 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable); 642 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable); 643 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable); 644 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable); 645 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable); 646 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv); 647 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis); 648 MS_BOOL HAL_TSP_GET_TSIF_FileEnStatus(MS_U32 u32FileEn); 649 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable); 650 651 //=========================TSP================================ 652 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn); 653 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable); 654 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn); 655 void HAL_TSP_SetBank(MS_VIRT u32BankAddr); 656 void HAL_TSP_Reset(MS_BOOL bEn); 657 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn); 658 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus); 659 void HAL_TSP_Power(MS_BOOL bEn); 660 void HAL_TSP_CPU(MS_BOOL bEn); 661 void HAL_TSP_ResetCPU(MS_BOOL bReset); 662 void HAL_TSP_HwPatch(void); 663 void HAL_TSP_RestoreFltState(void); 664 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize); 665 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn); 666 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc); 667 void HAL_TSP_PktBuf_Reset(MS_U32 pktBufId, MS_BOOL bEn); 668 void HAL_TSP_SaveFltState(void); 669 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo); 670 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData); 671 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable); 672 void HAL_TSP_Bank1137_Write(MS_U32 u32Offset,MS_U16 u16Value); 673 674 //=========================TSO================================ 675 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet); 676 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad); 677 678 //=========================Filein================================ 679 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize); 680 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr); 681 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size); 682 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng); 683 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn); 684 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 685 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng); 686 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng); 687 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng); 688 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable); 689 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng); 690 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn); 691 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet); 692 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp); 693 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk); 694 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng); 695 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng); 696 697 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng); 698 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng); 699 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng); 700 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr); 701 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable); 702 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng); 703 /* 704 // Only used by [HW test code] 705 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng); 706 */ 707 708 //=========================PCR FLT================================ 709 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid); 710 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId); 711 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable); 712 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src); 713 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc);//[Jason] 714 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr); 715 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId); 716 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId); 717 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId); 718 719 //=========================STC================================ 720 void HAL_TSP_STC_Init(void); 721 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync); 722 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync); 723 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable); 724 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL); 725 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL); 726 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL); 727 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL); 728 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable); 729 730 //=========================FIFO================================ 731 void HAL_TSP_FIFO_SetSrc (TSP_DST_SEQ eFltType, MS_U32 pktDmxId); 732 void HAL_TSP_FIFO_GetSrc (TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId); 733 void HAL_TSP_FIFO_Bypass (TSP_DST_SEQ eFltType, MS_BOOL bEn); 734 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType); 735 void HAL_TSP_FIFO_ClearAll (void); 736 MS_U32 HAL_TSP_FIFO_PidHit (TSP_DST_SEQ eFltType); 737 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 738 MS_U32 HAL_TSP_FIFO_Level (TSP_DST_SEQ eFltType); 739 MS_BOOL HAL_TSP_FIFO_Overflow (TSP_DST_SEQ eFltType); 740 MS_BOOL HAL_TSP_FIFO_Empty (TSP_DST_SEQ eFltType); 741 void HAL_TSP_FIFO_BlockDis (TSP_DST_SEQ eFltType, MS_BOOL bDisable); 742 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType); 743 void HAL_TSP_FIFO_Reset (TSP_DST_SEQ eFltType, MS_BOOL bReset); 744 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip); 745 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn); 746 void HAL_TSP_PS_SRC(MS_U32 tsIf); 747 //void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable); // for PS mode A/V fifo pull back 748 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bEnable);// for PS mode A/V fifo pull back 749 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType); // read A/V fifo data 750 MS_U16 HAL_TSP_FIFO_ReadPkt(void); // 751 void HAL_TSP_FIFO_Connect(MS_BOOL bEn); // 752 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn); 753 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn); 754 755 //=========================VQ================================ 756 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 757 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen); 758 void HAL_TSP_VQ_Enable(MS_BOOL bEn); 759 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn); 760 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn); 761 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn); 762 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis); 763 764 //=========================Pid Flt================================ 765 //void HAL_TSP_PidFlt_SetFltOut(MS_U32 pPidFlt, MS_U32 u32FltOu); 766 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32PID); 767 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn); 768 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut); 769 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId); 770 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn); 771 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable); 772 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn); 773 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt); 774 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt); 775 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID); 776 777 //=========================SecFlt================================ 778 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode); 779 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType); 780 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt); 781 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt); 782 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt); 783 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt); 784 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask); 785 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask); 786 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match); 787 void HAL_TSP_SecFlt_SetReqCount(REG_SecFlt *pSecFlt, MS_U32 u32ReqCount); 788 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode); 789 MS_U32 HAL_TSP_SecFlt_GetCRC32(REG_SecFlt *pSecFlt); 790 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt); 791 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId); 792 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId); 793 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet); 794 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt); 795 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet); // @TODO not implement yet 796 797 //=========================Sec Buf================================ 798 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize); 799 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr); 800 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf); 801 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf); 802 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf); 803 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf); 804 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf); 805 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf); 806 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId); 807 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf); 808 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart); 809 810 //=========================PVR================================ 811 void HAL_PVR_SetBank(MS_U32 u32BankAddr); 812 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId); 813 void HAL_PVR_Exit(MS_U32 u32PVREng); 814 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable); 815 /* 816 void HAL_PVR_SetTSIF(MS_U32 u32PVREng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP); 817 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis); 818 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn); 819 */ 820 void HAL_PVR_FlushData(MS_U32 u32PVREng); 821 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip); 822 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable); 823 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode); 824 void HAL_PVR_Start(MS_U32 u32PVREng); 825 void HAL_PVR_Stop(MS_U32 u32PVREng); 826 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause); 827 void HAL_PVR_RecPid(MS_U32 u32PVREng, MS_BOOL bSet); 828 void HAL_PVR_RecNull(MS_BOOL bSet); 829 void HAL_PVR_SetPidflt(MS_U32 u32PVREng, MS_U16 u16Fltid, MS_U16 u16Pid); 830 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1); 831 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng, MS_U32 u32StartAddr0, MS_U32 u32StartAddr1); 832 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng, MS_U32 u32MidAddr0, MS_U32 u32MidAddr1); 833 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng, MS_U32 u32EndAddr0, MS_U32 u32EndAddr1); 834 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng); 835 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng, MS_BOOL bSet); 836 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng, MS_U32 u32Stamp); 837 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng); 838 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32PVREng, MS_BOOL bEnable); 839 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream); 840 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable); 841 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime); 842 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc); 843 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable); 844 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn); 845 /* 846 void HAL_TSP_PVR_SPSConfig(MS_U8 u8Eng, MS_BOOL CTR_mode); 847 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode); 848 */ 849 850 //=========================FQ================================ 851 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc); 852 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng); 853 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull); 854 855 //=========================HCMD================================ 856 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type); 857 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value); 858 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr); 859 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value); 860 MS_BOOL HAL_TSP_HCMD_Alive(void); 861 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis); 862 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable); 863 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1); 864 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1); 865 866 //=========================INT================================ 867 void HAL_TSP_INT_Enable(MS_U32 u16Mask); 868 void HAL_TSP_INT_Disable(MS_U32 u16Mask); 869 void HAL_TSP_INT_ClrHW(MS_U32 u16Mask); 870 MS_U32 HAL_TSP_INT_GetHW(void); 871 void HAL_TSP_INT_ClrSW(void); 872 MS_U32 HAL_TSP_INT_GetSW(void); 873 874 //=========================Mapping================================ 875 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 876 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc); 877 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc); 878 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng); 879 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF u32TSIF, MS_BOOL bFileIn); 880 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng); 881 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void); 882 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng); 883 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif); 884 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow); 885 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId); 886 887 //========================DSCMB Functions=================================== 888 extern MS_BOOL HAL_DSCMB_GetBank(MS_U32 *u32Bank); 889 extern MS_BOOL HAL_DSCMB_PidIdx_SetTsId(MS_U32 u32fltid , MS_U32 u32TsId ); 890 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts); 891 892 //========================MOBF Functions===================================== 893 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key); 894 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key); 895 896 //========================Protection range=================================== 897 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn); 898 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL); 899 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn); 900 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL); 901 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable); 902 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng, MS_PHY u32AddrH, MS_PHY u32AddrL); 903 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable); 904 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 905 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable); 906 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL); 907 908 //========================Debug table============================= 909 void HAL_TSP_FltNullPkt_En(MS_BOOL bEn); 910 911 // @TODO Renaming Load and Get 912 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf); 913 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 914 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock); 915 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif); 916 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc); 917 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId); 918 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn); 919 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType); 920 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType); 921 922 // @TODO Implement Drop and Dis Hal 923 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId); 924 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn); 925 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload); 926 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop); 927 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType); 928 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType); 929 930 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf); 931 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 932 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void); 933 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif); 934 935 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf); 936 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn); 937 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void); 938 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif); 939 940 //========================MergeStream Functions============================= 941 void HAL_TSP_PktConverter_Init(void); 942 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode); 943 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet); 944 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet); 945 /* 946 void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen); 947 */ 948 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable); 949 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable); 950 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId); 951 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId); 952 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path); 953 954 955 #endif // #ifndef __HAL_PVR_H__ 956