1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halPVR.c
20 // @brief PVR HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #include "MsCommon.h"
24 #include "halCHIP.h"
25 #include "regTSP.h"
26 #include "halTSP.h"
27 #include "drvSYS.h"
28 #include "ULog.h"
29 #include "MsOS.h"
30
31
32 #ifdef CONFIG_MSTAR_CLKM
33 #include "drvCLKM.h"
34 #endif
35
36 #include "drvMMIO.h"
37
38 #define KANOU02 (MDrv_SYS_GetChipRev() >= 0x1) // This feature/behavior is supported after Kano U02
39 #define KANOU03 (MDrv_SYS_GetChipRev() >= 0x2) // This feature/behavior is supported after Kano U03
40
41 #define TSP_MIU_SEL_BITS_LEN 2
42
43 //--------------------------------------------------------------------------------------------------
44 // Driver Compiler Option
45 //--------------------------------------------------------------------------------------------------
46
47
48 //--------------------------------------------------------------------------------------------------
49 // TSP Hardware Abstraction Layer
50 //--------------------------------------------------------------------------------------------------
51 MS_VIRT _u32RegBase = 0;
52
53 static REG_Ctrl* _RegCtrl = NULL;
54 static REG_Ctrl2* _RegCtrl2 = NULL;
55 static REG_Ctrl3* _RegCtrl3 = NULL;
56 static REG_Ctrl4* _RegCtrl4 = NULL;
57 static REG_Ctrl5* _RegCtrl5 = NULL;
58 static REG_Ctrl6* _RegCtrl6 = NULL;
59 static REG_Ctrl7* _RegCtrl7 = NULL;
60 static REG_Ctrl8* _RegCtrl8 = NULL;
61
62
63
64 // @F_TODO These parameters need to be combined with global variables in Utopia 2.0
65 static MS_U32 _u32PidFltReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
66 static MS_U32 _u32PidDstReg[(TSP_PIDFLT_NUM * sizeof(REG_PidFlt))];
67 static MS_U32 _u32SecReg[(TSP_SECFLT_NUM * ((sizeof(REG_SecFlt) - sizeof(((REG_SecFlt*)0)->_x50))/sizeof(TSP32)))];
68
69 //-------------------------------------------------------------------------------------------------
70 // Local Structures
71 //-------------------------------------------------------------------------------------------------
72
73 typedef struct // structure for PVR Buffer
74 {
75 MS_BOOL bOverWrite; // True : means the PVR buffer has been written already
76 // False : means the PVR buffer has not been written yet
77 MS_U32 u32Start; // PVR buffer physical start address
78 MS_U32 u32End; // PVR buffer physical end address
79 MS_BOOL bPA2KSEG1_Mapping; // True : means PA2KSEG1 mapping success
80
81 }PVR_Buf;
82
83 static PVR_Buf _stPvrBuf[PVR_NUM];
84
85 //-------------------------------------------------------------------------------------------------
86 // Local Functions
87 //-------------------------------------------------------------------------------------------------
88 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value);
89
_delay(MS_U32 usec)90 static void _delay(MS_U32 usec)
91 {
92 MsOS_DelayTaskUs_Poll(usec);
93 }
94
REG32_R(REG32 * reg)95 static MS_U32 REG32_R(REG32 *reg)
96 {
97 MS_U32 value = 0;
98 value = (reg)->low;
99 value |= (reg)->high << 16;
100 return value;
101 }
102
103
REG16_R(REG16 * reg)104 static MS_U16 REG16_R(REG16 *reg)
105 {
106 MS_U16 value = 0;
107 value = (reg)->data;
108 return value;
109 }
110
111 static MS_BOOL _u32RegDump = 0;
112 static void _REG32_DUMP(REG32 * reg, MS_U32 value );
113 static void _REG16_DUMP(REG16 * reg, MS_U16 value);
114
115 #if 0
116 #define REG32_W(reg, value); { (reg)->low = ((value) & 0x0000FFFF); \
117 (reg)->high = ((value) >> 16);\
118 if(_u32RegDump)\
119 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n", (((MS_U32)(&(reg)->low) - _u32RegBase)>>(1+8)), ((((MS_U32)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1,(value) & 0x0000FFFF);\
120 printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)(&(reg)->high) - _u32RegBase)>>(1+8)),((((MS_U32)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1, (value) >> 16);}}
121
122 #define REG16_W(reg, value); {(reg)->data = ((value) & 0x0000FFFF);\
123 if(_u32RegDump)\
124 {printf("wriu bank:0x%04X addr:0x%02X value:0x%04X\n\n", (((MS_U32)reg) - _u32RegBase)>>(1+8), ((((MS_U32)reg - _u32RegBase)>>1)&0xFF)>>1, (value) & 0x0000FFFF);}}
125 #endif
126 #define REG32_W(reg, value) { (reg)->low = ((value) & 0x0000FFFF); \
127 (reg)->high = ((value) >> 16);\
128 if(_u32RegDump){_REG32_DUMP(reg, value);}}
129
130 #define REG16_W(reg, value) {(reg)->data = ((value) & 0x0000FFFF);\
131 if(_u32RegDump){_REG16_DUMP(reg, value);}}
132
133
134 #define _AND_(flag, bit) ((flag) & (bit) )
135
136 #define _SET_(flag, bit) ((flag) | (bit) )
137 #define _CLR_(flag, bit) ((flag) & (~(bit)))
138
139 #define REG16_SET(reg, value) REG16_W(reg, _SET_(REG16_R(reg), value))
140 #define REG32_SET(reg, value) REG32_W(reg, _SET_(REG32_R(reg), value))
141 #define REG16_CLR(reg, value) REG16_W(reg, _CLR_(REG16_R(reg), value))
142 #define REG32_CLR(reg, value) REG32_W(reg, _CLR_(REG32_R(reg), value))
143
144 #define REG16_MSK_W(reg, mask, value) REG16_W((reg), _CLR_(REG16_R(reg), (mask)) | _AND_((value), (mask)))
145 #define REG32_MSK_W(reg, mask, value) REG32_W((reg), _CLR_(REG32_R(reg), (mask)) | _AND_((value), (mask)))
146
147 #define MIU_BUS (4)
148
149
150 //-------------------------------------------------------------------------------------------------
151 // Debug Message
152 //-------------------------------------------------------------------------------------------------
153 typedef enum
154 {
155 E_HAL_TSP_DBG_LEVEL_NONE, // no debug message shown
156 E_HAL_TSP_DBG_LEVEL_ERR, // only shows error message that can't be recover
157 E_HAL_TSP_DBG_LEVEL_WARN, // error case can be recover, like retry
158 E_HAL_TSP_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc.
159 E_HAL_TSP_DBG_LEVEL_INFO, // information for internal parameter
160 E_HAL_TSP_DBG_LEVEL_FUNC, // Function trace and input parameter trace
161 E_HAL_TSP_DBG_LEVEL_TRACE, // debug trace
162 } EN_HAL_TSP_DBGMSG_LEVEL;
163
164 typedef enum
165 {
166 E_HAL_TSP_DBG_MODEL_NONE, // @temporarily , need to refine
167 E_HAL_TSP_DBG_MODEL_ALL,
168 } EN_HAL_TSP_DBGMSG_MODEL;
169
170 #define HAL_TSP_DBGMSG(_level,_model,_f) do {if(_u32TSPDbgLevel >= (_level)&&((_u32TSPDbgModel&_model)!=0)) (_f);} while(0)
171 static MS_U32 _u32TSPDbgLevel = E_HAL_TSP_DBG_LEVEL_ERR;
172 static MS_U32 _u32TSPDbgModel = E_HAL_TSP_DBG_MODEL_ALL;
173
174
175 //--------------------------------------------------------------------------------------------------
176 // Implementation
177 //--------------------------------------------------------------------------------------------------
TSP32_IdrW(TSP32 * preg,MS_U32 value)178 void TSP32_IdrW(TSP32 *preg, MS_U32 value)
179 {
180 MS_U32 tempDump = _u32RegDump;
181 if(_u32RegDump)
182 {
183 //test_chip_top.write_ind32('h00221004, 32'hffffffff); //indirect .... (address,data)
184 _u32RegDump = 0;
185 printf("test_chip_top.write_ind32(\'h%08lx, 32\'h%08lx);\n", (long unsigned int)preg, (long unsigned int)value);
186 }
187 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
188 REG32_W(&_RegCtrl->Idr_Write, value);
189 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_WRITE);
190 _u32RegDump = tempDump;
191 }
192
TSP32_IdrR(TSP32 * preg)193 MS_U32 TSP32_IdrR(TSP32 *preg)
194 {
195 MS_U32 tempDump = _u32RegDump;
196 if(_u32RegDump)
197 {
198 _u32RegDump = 0;
199 }
200 REG32_W(&_RegCtrl->Idr_Addr, (MS_VIRT)preg);
201 REG16_W(&_RegCtrl->Idr_Ctrl, TSP_IDR_START | TSP_IDR_READ);
202 _u32RegDump = tempDump;
203 return REG32_R(&_RegCtrl->Idr_Read);
204 }
205
HAL_TSP_SetBank(MS_VIRT u32BankAddr)206 void HAL_TSP_SetBank(MS_VIRT u32BankAddr)
207 {
208 _u32RegBase = u32BankAddr;
209 _RegCtrl = (REG_Ctrl*)(u32BankAddr + 0x2A00UL); //TSP0 0x1015, TSP1 0x1016
210 _RegCtrl2 = (REG_Ctrl2*)(u32BankAddr + 0xE0400UL); //TSP3 0x1702,
211 _RegCtrl3 = (REG_Ctrl3*)(u32BankAddr + 0xE0600UL); //TSP4 0x1703
212 _RegCtrl4 = (REG_Ctrl4*)(u32BankAddr + 0xC2000UL); //TSP6 0x1610
213 _RegCtrl5 = (REG_Ctrl5*)(u32BankAddr + 0xC2200UL); //TSP7 0x1611
214 _RegCtrl6 = (REG_Ctrl6*)(u32BankAddr + 0xC4E00UL); //TSP8 0x1627
215 _RegCtrl7 = (REG_Ctrl7*)(u32BankAddr + 0xE1800UL); //TSP9 0x170C
216 _RegCtrl8 = (REG_Ctrl8*)(u32BankAddr + 0xE1A00UL); //TSP10 0x170D
217 }
218
HAL_TSP_RegDump(MS_BOOL bEnable)219 void HAL_TSP_RegDump(MS_BOOL bEnable)
220 {
221 _u32RegDump = bEnable;
222 }
223 #if 1
_REG32_DUMP(REG32 * reg,MS_U32 value)224 static void _REG32_DUMP(REG32* reg, MS_U32 value )
225 {
226 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7?h06 ....reg ,16?h400a ......
227 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7?h06 ....reg ,16?h400a ......
228 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
229 MS_U32 bank = ((MS_VIRT)(&(reg)->low) - _u32RegBase)>>(1+8);
230 MS_U32 addr_low = ((((MS_VIRT)(&(reg)->low) - _u32RegBase)>>1)&0xFF)>>1;
231 MS_U32 addr_high = ((((MS_VIRT)(&(reg)->high) - _u32RegBase)>>1)&0xFF)>>1;
232 MS_U32 val_low = (value) & 0x0000FFFF;
233 MS_U32 val_high = ((value) & 0xFFFF0000 )>>16;
234
235 if(bank == 0x15)
236 {
237 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
238 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
239 }
240 else if(bank == 0x16)
241 {
242 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
243 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
244 }
245 else if(bank == 0x38)
246 {
247 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_low, (long unsigned int)val_low);
248 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr_high, (long unsigned int)val_high);
249 }
250 }
_REG16_DUMP(REG16 * reg,MS_U16 value)251 static void _REG16_DUMP(REG16* reg, MS_U16 value )
252 {
253 //`RIU_W(`TSP_REG_BASE + 7'h06, 2'b11, 16'h400a); //..bank 15 ,7?h06 ....reg ,16?h400a ......
254 //`RIU_W(`TSP_REG_BASE1 + 7'h72, 2'b11, 16'hc000); // ..bank 16 ,7?h06 ....reg ,16?h400a ......
255 //`RIU_W((24'h103800>>1) + 7'h56 , 2'b11, 16'h0000); //....bank 038
256 MS_U32 bank = ((MS_VIRT)(&(reg)) - _u32RegBase)>>(1+8);
257 MS_U32 addr = ((((MS_VIRT)(&(reg)) - _u32RegBase)>>1)&0xFF)>>1;
258 MS_U32 val = (value) & 0x0000FFFF;
259
260 if(bank == 0x15)
261 {
262 printf("`RIU_W(TSP_REG_BASE + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
263 }
264 else if(bank == 0x16)
265 {
266 printf("`RIU_W(TSP_REG_BASE1 + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
267 }
268 else if(bank == 0x38)
269 {
270 printf("`RIU_W((24\'h103800>>1) + 7\'h%02lx, 2\'b11, 16\'h%04lx);\n", (long unsigned int)addr, (long unsigned int)val);
271 }
272 }
273 #endif
274
275 // [HW Issue]
276 // The K3 series PVR write pointer's return value is different from K1 series chip.
277 // For example, if PVR MIU alignment is 16 bytes. Write 32 bytes to PVR buffer from PVR start address 0.
278 // The 32 bytes data would be allocated to PVR buffer(address 0~31).
279 // And then we get the write pointer. The K3 series write pointer will return the value 16(W).
280 // The last MIU alignment address of the written data.
281 // The K1 series write pointer will return the value 32(W').
282 // The next MIU alignment address for the next writting.
283 // PVR write pointer value has 1 MIU alignment difference between K3 and K1 series.
284 // To SW, the K1 series write pointer's return value is more meaningful than K3 series.
285 // Now we use _Adjust_PVR_WritePtr function to make K3 series write pointer's return value consistent with K1 series.
286 // --------------------------------->
287 // S W W' E
288 // ######################
289 // +----------+----------+----------+
290 // 0 16 32
291 // ----------------------------------
292
_Adjust_PVR_WritePtr(MS_U32 u32Eng,MS_U32 u32WritePtr)293 static MS_U32 _Adjust_PVR_WritePtr(MS_U32 u32Eng, MS_U32 u32WritePtr)
294 {
295 if(_stPvrBuf[u32Eng].bPA2KSEG1_Mapping != TRUE)
296 {
297 return u32WritePtr;
298 }
299
300 if (_stPvrBuf[u32Eng].u32Start == 0)
301 {
302 return u32WritePtr;
303 }
304
305 if (!((E_TSP_PVR_PVRENG_START <= u32Eng) && (E_TSP_PVR_PVRENG_END > u32Eng))) // PVR Eng number check
306 {
307 return u32WritePtr;
308 }
309
310 if( _stPvrBuf[u32Eng].bOverWrite ) // If PVR buffer in OverWrite state
311 {
312 u32WritePtr = u32WritePtr + (1 << MIU_BUS);
313 }
314 else // If PVR buffer in non-OverWrite state
315 {
316 MsOS_ReadMemory();
317
318 if(*((MS_U64*)(MsOS_PA2KSEG1(_stPvrBuf[u32Eng].u32Start)))!= PVR_NON_OVERWRITE)
319 {
320 _stPvrBuf[u32Eng].bOverWrite = TRUE; // Set PVR buffer to OverWrite state
321 u32WritePtr = u32WritePtr + (1 << MIU_BUS);
322 }
323 }
324
325 if( u32WritePtr >= _stPvrBuf[u32Eng].u32End )
326 {
327 //reset write address
328 u32WritePtr = _stPvrBuf[u32Eng].u32Start;
329 }
330
331 return u32WritePtr;
332 }
333
HAL_TSP_HwPatch(void)334 void HAL_TSP_HwPatch(void)
335 {
336 //For sram
337 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_HW_STANDBY_MODE);
338 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
339
340 // @F_TODO check these setting with Stephen
341 // TSP_HW_CFG4_WSTAT_CH_EN <--this is bit disable HW sync section buf id with section filter id
342 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_BYTE_ADDR_DMA|TSP_HW_CFG4_ALT_TS_SIZE|TSP_HW_CFG4_WSTAT_CH_EN);
343
344 // Bad initial value of TSP_CTRL1
345 // Suppose Standby mode for TSP should NOT be enabled.
346 // Enabling TSP standby mode cause TSP section registers (SRAM in AEON) malfunction.
347 // Disable it by SW at this stage.
348 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_STANDBY);
349
350 //enable PVR record to bypass header
351 REG16_SET(&_RegCtrl->reg15b4, TSP_PVR_PID_BYPASS|TSP_PVR_PID_BYPASS2);
352 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PID_BYPASS3_REC);
353 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PID_BYPASS4_REC);
354
355 // load lpcr1 for all pvr engines, HW default value may be wrong
356 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
357 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
358 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
359 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
360
361 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
362
363 //Disable TSP_RM_OVF_GLITCH to fix that section A would occur overflow when section B occured overflow at first.
364 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ2PINGPONG_EN | TSP_RM_PKT_DEMUX_PIPE /*| TSP_PVR1_ALIGN_EN*/);
365
366 //Disable all live pathes block mechanism
367 REG16_SET(&_RegCtrl->reg160C, TSP_DOUBLE_BUF_DESC/*| TSP_VQTX0_BLOCK_DIS|TSP_VQTX2_BLOCK_DIS|TSP_VQTX3_BLOCK_DIS*/);
368 REG16_SET(&_RegCtrl->reg160E, TSP_RM_DMA_GLITCH);
369
370 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PUSI_3BYTE_MODE); //Enable audio 3 byte mode
371
372 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
373
374 //record null packets for record-all case
375 REG16_SET(&_RegCtrl->PVRConfig, TSP_MATCH_PID_LD | TSP_REC_NULL);
376 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BLK_AD_SCMBTIS_TSP);
377
378 //Disable pvr1 & pvr2 block mechanism
379 //DisableAV FIFO block mechanism for live path
380 //REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN|TSP_PVR1_BLOCK_DIS|TSP_PVR2_BLOCK_DIS|TSP_V_BLOCK_DIS|TSP_A_BLOCK_DIS|TSP_AD_BLOCK_DIS); // by angie
381
382 //fix load fw secure issue (dma_start = 1 , polling dma_done , dma_start = 0)
383 REG16_SET(&_RegCtrl3->CFG3_16, CFG3_16_FIXED_DMA_RSTART_OTP_ONEWAY_LOAD_FW);
384
385 //Internal Sync Patch
386 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_DATA_CHK_2T);
387
388 //fix filter null pkt
389 if(KANOU03)
390 {
391 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_FIX_FILTER_NULL_PKT);
392 }
393
394 //Fixed filein_192+timer_en+byte_time=0 Error
395 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_FIX_192_TIMER_0_EN);
396
397 //Fixed filein_192 timestamp & LPCR ring back first issue
398 #if 0 //@NOTE: temporailiy disable
399 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_TIMESTAMP_RING_BACK_EN | FIXED_LPCR_RING_BACK_EN);
400 #endif
401 //serial mode config
402 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_SYNC_RISING_DETECT | TSP_VALID_FALLING_DETECT);
403
404 if(KANOU02)
405 {
406 REG16_SET(&_RegCtrl6->CFG6_2A, FIXED_VQ_MIU_REG_FLUSH);
407 }
408 }
409
410 // ------------ initial config ------------
411 // Sync Byte: 0x47 , 0x48 .... , 0x4e
412 // Source id : 0 , 1 , ... , 7
413 // User can use "HAL_TSP_PktConverter_SetSyncByte()" to change Sync Byte configuration
414 // , and use "HAL_TSP_PktConverter_SetSrcId()" to change Source id configuration
HAL_TSP_PktConverter_Init(void)415 void HAL_TSP_PktConverter_Init(void)
416 {
417 MS_U8 u8Path, u8Idx;
418 MS_U8 u8SyncByte, u8SrcId;
419
420 for(u8Path = 0; u8Path < TSP_TSIF_NUM; ++u8Path)
421 {
422 HAL_TSP_PktConverter_ForceSync(u8Path,TRUE);//default: FALSE
423 HAL_TSP_PktConverter_SrcIdFlt(u8Path,TRUE); //default: FALSE
424
425 u8SyncByte = 0x47;
426 u8SrcId = 0;
427
428 for(u8Idx = 0; u8Idx < TSP_MERGESTREAM_NUM; ++u8Idx,++u8SyncByte,++u8SrcId)
429 {
430 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Idx, &u8SyncByte, TRUE);
431 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Idx, &u8SrcId, TRUE);
432 }
433 }
434 }
435
436
HAL_TSP_Reset(MS_BOOL bEn)437 void HAL_TSP_Reset(MS_BOOL bEn)
438 {
439 //MS_U16 reg;
440
441 if (bEn)
442 {
443 #if 0
444
445 // WB DMA source won't be reset by SW_RST bit so we use HWPATCH to make it's source to default
446 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
447 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
448
449 #endif
450 // reset CMDQ for tsif 0~3
451 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
452 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
453 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
454 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
455 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
456 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
457 }
458 else
459 {
460 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_SW_RST);
461
462 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_WB_DMA_RESET);
463 // set CMDQ for tsif 0~3
464 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
465 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
466 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
467 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
468 }
469 }
470
471
HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)472 void HAL_TSP_Path_Reset(MS_U32 tsIf,MS_BOOL bEn)
473 {
474 switch(tsIf)
475 {
476 case 0: if(bEn)
477 {
478 REG16_SET(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
479 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
480 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
481 }
482 else
483 {
484 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF0 | CFG_12_REG_REST_PDBF0);
485 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT0);
486 REG16_CLR(&_RegCtrl->reg160C,TSP_TIMESTAMP_RESET);
487 }
488 break;
489 case 1: if(bEn)
490 {
491 REG16_SET(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
492 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
493 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
494 }
495 else
496 {
497 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF1 | CFG_12_REG_REST_PDBF1);
498 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT1);
499 REG16_CLR(&_RegCtrl2->CFG_00,CFG_00_RST_TS_FIN1);
500 }
501 break;
502 case 2: if(bEn)
503 {
504 REG16_SET(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
505 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
506 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
507 }
508 else
509 {
510 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF2 | CFG_12_REG_REST_PDBF2);
511 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT2);
512 REG16_CLR(&_RegCtrl2->CFG_05,CFG_05_RST_TS_FIN2);
513 }
514 break;
515 case 3: if(bEn)
516 {
517 REG16_SET(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3);
518 REG16_SET(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3);
519 REG16_SET(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3);
520 }
521 else
522 {
523 REG16_CLR(&_RegCtrl2->CFG_12,CFG_12_REG_REST_RBF3 | CFG_12_REG_REST_PDBF3);
524 REG16_CLR(&_RegCtrl2->CFG_10,CFG_10_RESET_PDFLT3);
525 REG16_CLR(&_RegCtrl2->CFG_0A,CFG_0A_RST_TS_FIN3);
526 }
527 break;
528 default: break;
529 }
530 }
531
HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType,MS_U8 u8Index,ST_TSP_HAL_CLK_STATUS * pstClkStatus)532 MS_BOOL HAL_TSP_GetClockSetting(EN_TSP_HAL_CLK_TYPE eClkType, MS_U8 u8Index, ST_TSP_HAL_CLK_STATUS *pstClkStatus)
533 {
534 switch(eClkType)
535 {
536 case E_TSP_HAL_TSP_CLK:
537 pstClkStatus->bEnable = !(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_DISABLE);
538 pstClkStatus->bInvert = !!(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_INVERT);
539 pstClkStatus->u8ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & REG_CLKGEN0_TSP_CLK_MASK) >> REG_CLKGEN0_TSP_SRC_SHIFT;
540 break;
541 default:
542 return FALSE;
543 }
544
545 return TRUE;
546 }
547
HAL_TSP_Power(MS_BOOL bEn)548 void HAL_TSP_Power(MS_BOOL bEn)
549 {
550 if(bEn)
551 {
552 #ifdef CONFIG_MSTAR_CLKM
553
554 MS_S32 s32Handle;
555
556 // Enable TSP Clk
557 s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
558 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSP_FAST");
559 // Enable STC1,2 Clk
560 // STC0
561 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc0");
562 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STC0_BUF");
563 // STC1
564 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc1");
565 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STC0_BUF");
566 // Stamp
567 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
568 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_STAMP_NORMAL");
569 // Parser
570 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
571 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_PARSER_NORMAL");
572 // Enable TSIF => Disable TSIF
573 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
574 //TS0
575 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
576 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
577 //TS1
578 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
579 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
580 //TS2
581 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
582 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
583 //TS3
584 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
585 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TS0_PAD0");
586
587 //TSO0
588 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
589 Drv_Clkm_Set_Clk_Source(s32Handle,"CLK_TSOIN0_PAD0");
590
591 #else
592
593 // Enable TSP Clk
594 TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) & ~REG_CLKGEN0_TSP_CLK_MASK)
595 | (REG_CLKGEN0_TSP_SRC_192MHZ << REG_CLKGEN0_TSP_SRC_SHIFT);
596 // Enable STC1,2 Clk
597 // STC0
598 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) & ~REG_CLKGEN0_STC0_MASK)
599 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC0_SHIFT));
600 // STC1
601 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) & ~REG_CLKGEN0_STC1_MASK)
602 | (REG_CLKGEN0_STC_SRC_SYNTH << (REG_CLKGEN0_STC_SRC_SHIFT+REG_CLKGEN0_STC1_SHIFT));
603
604 // Stamp
605 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) & ~REG_CLKGEN0_STAMP_MASK);
606
607 // Parser
608 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) & ~REG_CLKGEN0_PARSER_MASK);
609
610 // Enable TSIF => Disable TSIF
611 // FixME Enable flowset would enable TSx clk so we don't enable TSx clk
612 //TS0
613 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK);
614
615 //TS1
616 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS1_SHIFT));
617
618 //TS2
619 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS2_SHIFT));
620
621 //TS3
622 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK << REG_CLKGEN0_TS3_SHIFT));
623
624 //TSO0
625 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK);
626
627 #endif
628
629 // TSP Boot clk sel
630 TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) = (TSP_TOP_REG(REG_TOP_TSP_BOOT_CLK_SEL) & ~REG_TOP_TSP_BOOT_CLK_SEL_MASK) | REG_TOP_TSP_BOOT_CLK_SEL_TSP;
631
632 // TSP SRAM sel
633 TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) = TSP_MMFI_REG(REG_MMFI_TSP_SEL_SRAM) | REG_MMFI_TSP_SEL_SRAM_EN;
634
635 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_PREVENT_SRAM_COLLISION);
636
637 // Disable MCM
638 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP
639 }
640 else
641 {
642 // Enable MCM
643 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_TSP2MI_REQ_MCM_DISABLE);//TSP
644
645 #ifdef CONFIG_MSTAR_CLKM
646
647 MS_S32 s32Handle;
648
649 // Disable TSP Clk
650 // [2016.10.14] Because AESDMA share clk with TSP. We can't disable TSP clk.
651 // s32Handle = Drv_Clkm_Get_Handle("g_clk_tsp");
652 // Drv_Clkm_Clk_Gate_Disable(s32Handle);
653
654 // Disable STC Clk
655 //STC0
656 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc0");
657 Drv_Clkm_Clk_Gate_Disable(s32Handle);
658 //STC0
659 s32Handle = Drv_Clkm_Get_Handle("g_clk_stc1");
660 Drv_Clkm_Clk_Gate_Disable(s32Handle);
661 // Stamp
662 s32Handle = Drv_Clkm_Get_Handle("g_clk_stamp");
663 Drv_Clkm_Clk_Gate_Disable(s32Handle);
664 // Parser
665 s32Handle = Drv_Clkm_Get_Handle("g_clk_parser");
666 Drv_Clkm_Clk_Gate_Disable(s32Handle);
667 //TS0
668 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
669 Drv_Clkm_Clk_Gate_Disable(s32Handle);
670 //TS1
671 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
672 Drv_Clkm_Clk_Gate_Disable(s32Handle);
673 //TS2
674 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
675 Drv_Clkm_Clk_Gate_Disable(s32Handle);
676 //TS3
677 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
678 Drv_Clkm_Clk_Gate_Disable(s32Handle);
679
680 //TSO0
681 s32Handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
682 Drv_Clkm_Clk_Gate_Disable(s32Handle);
683
684 #else
685 // Disable TSP Clk
686 // [2016.10.11] Because AESDMA share clk with TSP. We can't disable TSP clk.
687 // TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSP_CLK),(REG_CLKGEN0_TSP_DISABLE << REG_CLKGEN0_TSP_SHIFT));
688
689 // Disable STC Clk
690 //STC0
691 TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC0_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC0_SHIFT));
692 //STC1
693 TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STC1_CLK),(REG_CLKGEN0_STC_DISABLE << REG_CLKGEN0_STC1_SHIFT));
694
695 // Stamp
696 TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_STAMP_CLK),(REG_CLKGEN0_STAMP_DISABLE << REG_CLKGEN0_STAMP_SHIFT));
697
698 // Parser
699 TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_PARSER_CLK),(REG_CLKGEN0_PARSER_DISABLE << REG_CLKGEN0_PARSER_SHIFT));
700
701 // Disable TSIF clk
702 //TS0
703 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS0_SHIFT));
704 //TS1
705 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS1_SHIFT));
706 //TS2
707 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS2_SHIFT));
708 //TS3
709 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TS3_SHIFT));
710
711 //TSO0
712 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = _SET_(TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK),(REG_CLKGEN0_TS_DISABLE << REG_CLKGEN0_TSO0_SHIFT));
713
714 #endif
715
716 }
717 }
718
HAL_TSP_CPU(MS_BOOL bEn)719 void HAL_TSP_CPU(MS_BOOL bEn)
720 {
721 if (bEn)
722 {
723 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
724 }
725 else
726 {
727 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
728 }
729 }
HAL_TSP_ResetCPU(MS_BOOL bReset)730 void HAL_TSP_ResetCPU(MS_BOOL bReset)
731 {
732 // @NOTE TRUE for stop cpu clock
733 if (bReset)
734 {
735 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
736 }
737 else
738 {
739 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_CPU_EN);
740 }
741 }
742
743
HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr,MS_U32 u32FwSize)744 MS_BOOL HAL_TSP_LoadFW(MS_U32 u32FwPhyAddr, MS_U32 u32FwSize)
745 {
746
747 #define _TSP_QMEM_I_MASK 0xffffc000 //code: 0x2000, data: 0x1000, total: 0x3000
748 #define _TSP_QMEM_I_ADDR_HIT 0x00000000
749 #define _TSP_QMEM_I_ADDR_MISS 0xffffffff
750 #define _TSP_QMEM_D_MASK 0xffffc000
751 #define _TSP_QMEM_D_ADDR_HIT 0x00000000
752 #define _TSP_QMEM_D_ADDR_MISS 0xffffffff
753 #define _TSP_QMEM_SIZE 0x1000 // 16K bytes, 32bit aligment //0x4000 this is 4 byte address
754
755 REG32_W(&_RegCtrl->Cpu_Base, 0); // 16 bytes address unit
756
757 MS_U32 u32DnldCtrl = 0;
758 MS_U32 u32DnldCtrl1 = 0;
759
760 // Check MIU select
761 MS_U8 u8MiuSel = 0;
762 MS_PHY phyMiuOffsetFWBuf = 0;
763 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFWBuf, u32FwPhyAddr);
764 REG16_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG16_R(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM) & (~REG_MIU_SEL_FILEIN0_MASK)) | ((u8MiuSel << REG_MIU_SEL_FILEIN0_SHIFT) & REG_MIU_SEL_FILEIN0_MASK));
765
766 u32DnldCtrl = (phyMiuOffsetFWBuf >> MIU_BUS) >> TSP_DNLD_ADDR_ALI_SHIFT;
767 u32DnldCtrl1 = u32DnldCtrl >> 16;
768
769 REG16_W(&_RegCtrl->Dnld_Ctrl_Addr, (MS_U16)(u32DnldCtrl & TSP_DNLD_ADDR_MASK)); // oneway register
770 REG16_MSK_W(&_RegCtrl->Dnld_AddrH, TSP_DMA_RADDR_MSB_MASK, (MS_U16)u32DnldCtrl1);
771 REG16_W(&_RegCtrl->Dnld_Ctrl_Size, _TSP_QMEM_SIZE);
772 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
773 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START);
774
775 //@TODO temprarily comment because of Secure Protect
776 #if 1
777 while (!(REG16_R(&_RegCtrl->TSP_Ctrl) & TSP_CTRL_DNLD_DONE))
778 {
779 }
780 #endif
781
782
783 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_DNLD_START| TSP_CTRL_DNLD_DONE);
784
785 REG32_W(&_RegCtrl->Qmem_Imask, _TSP_QMEM_I_MASK);
786 REG32_W(&_RegCtrl->Qmem_Ibase, _TSP_QMEM_I_ADDR_HIT);
787 REG32_W(&_RegCtrl->Qmem_Dmask, _TSP_QMEM_D_MASK);
788 REG32_W(&_RegCtrl->Qmem_Dbase, _TSP_QMEM_D_ADDR_HIT);
789
790 #undef _TSP_QMEM_I_MASK
791 #undef _TSP_QMEM_I_ADDR_HIT
792 #undef _TSP_QMEM_I_ADDR_MISS
793 #undef _TSP_QMEM_D_MASK
794 #undef _TSP_QMEM_D_ADDR_HIT
795 #undef _TSP_QMEM_D_ADDR_MISS
796 #undef _TSP_QMEM_SIZE
797
798 return TRUE;
799 }
800
HAL_TSP_RestoreFltState(void)801 void HAL_TSP_RestoreFltState(void)
802 {
803 MS_U32 u32Size;
804 TSP32 * pRegEnd;
805 TSP32 * pReg;
806 int i, j;
807
808 for (i = 0; i < TSP_PIDFLT_NUM; i++)
809 {
810 TSP32_IdrW(&(_REGPid0->Flt[i]), _u32PidFltReg[i]);
811 TSP32_IdrW(&(_REGPid1->Flt[i]), _u32PidDstReg[i]);
812 }
813
814 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
815
816 for (i = 0; i < TSP_SECFLT_NUM; i++)
817 {
818 pReg = (TSP32*)&(_REGSec->Flt[i]);
819 pRegEnd = pReg + u32Size;
820 j = 0;
821 for ( ; pReg < pRegEnd; pReg++)
822 {
823 TSP32_IdrW(pReg, _u32SecReg[i*u32Size+j]);
824 j++;
825 }
826 }
827
828 }
829
HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)830 void HAL_TSP_PktBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
831 {
832 if(bEn)
833 {
834 switch(pktDmxId)
835 {
836 case 0:
837 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
838 break;
839 case 1:
840 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
841 break;
842 case 2:
843 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
844 break;
845 case 3:
846 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3);
847 break;
848 default:
849 break;
850 }
851 }
852 else
853 {
854 switch(pktDmxId)
855 {
856 case 0:
857 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF0);
858 break;
859 case 1:
860 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF1);
861 break;
862 case 2:
863 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF2);
864 break;
865 case 3:
866 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_PDBF3);
867 break;
868 default:
869 break;
870 }
871 }
872 }
873
HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId,MS_BOOL bEn)874 void HAL_TSP_RecvBuf_Reset(MS_U32 pktDmxId, MS_BOOL bEn)
875 {
876 if(bEn)
877 {
878 switch(pktDmxId)
879 {
880 case 0:
881 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
882 break;
883 case 1:
884 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
885 break;
886 case 2:
887 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
888 break;
889 case 3:
890 REG16_SET(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3);
891 break;
892 default:
893 break;
894 }
895 }
896 else
897 {
898 switch(pktDmxId)
899 {
900 case 0:
901 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF0);
902 break;
903 case 1:
904 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF1);
905 break;
906 case 2:
907 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF2);
908 break;
909 case 3:
910 REG16_CLR(&_RegCtrl2->CFG_12, CFG_12_REG_REST_RBF3);
911 break;
912 default:
913 break;
914 }
915 }
916 }
917
HAL_TSP_SetTSIF(MS_U16 u16TSIF,TSP_TSIF_CFG u16Cfg,MS_BOOL bFileIn)918 MS_BOOL HAL_TSP_SetTSIF(MS_U16 u16TSIF, TSP_TSIF_CFG u16Cfg, MS_BOOL bFileIn)
919 {
920 if(bFileIn)
921 {
922 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, TRUE); // this returns true only we don't check the return value
923 HAL_TSP_TSIF_LiveEn(u16TSIF, FALSE); // this returns true only we don't check the return value
924 }
925 else
926 {
927 HAL_TSP_TSIF_FileEn((FILEENG_SEQ)u16TSIF, FALSE);
928 HAL_TSP_TSIF_LiveEn(u16TSIF, TRUE);
929 }
930
931 if(bFileIn != TRUE)
932 {
933 HAL_TSP_TSIF_BitSwap(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_BITSWAP)?TRUE:FALSE));
934 HAL_TSP_TSIF_ExtSync(u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_EXTSYNC)?TRUE:FALSE));
935 HAL_TSP_TSIF_Parl (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_PARA )?TRUE:FALSE));
936 HAL_TSP_TSIF_3Wire (u16TSIF, ((u16Cfg&E_TSP_TSIF_CFG_3WIRE )?TRUE:FALSE));
937 }
938
939 return TRUE;
940 }
941
HAL_TSP_TSIF_LiveEn(MS_U32 tsIf,MS_BOOL bEnable)942 MS_BOOL HAL_TSP_TSIF_LiveEn(MS_U32 tsIf, MS_BOOL bEnable)
943 {
944 if(bEnable)
945 {
946 switch(tsIf)
947 {
948 case 0:
949 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
950 break;
951 case 1:
952 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
953 break;
954 case 2:
955 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
956 break;
957 case 3:
958 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN);
959 break;
960 default:
961 return FALSE;
962 }
963 }
964 else
965 {
966 switch(tsIf)
967 {
968 case 0:
969 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF0_ENABLE);
970 break;
971 case 1:
972 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TSIF1_ENABLE);
973 break;
974 case 2:
975 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_IF2_EN);
976 break;
977 case 3:
978 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_IF3_EN);
979 break;
980 default:
981 return FALSE;
982 }
983 }
984
985 return TRUE;
986 }
987
HAL_TSP_TSIF_SelPad(MS_U32 tsIf,TSP_TS_PAD eTSPad)988 MS_BOOL HAL_TSP_TSIF_SelPad(MS_U32 tsIf, TSP_TS_PAD eTSPad) // @FIXME modify this parameter to enum plz
989 {
990 MS_U32 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
991 MS_U32 pad_src = REG_TOP_TS_SRC_EXT0;
992 #ifdef CONFIG_MSTAR_CLKM
993 MS_S32 handle;
994 MS_U8 u8NameIdx = 0;
995 char* u8ClkSrcNames[] =
996 {
997 "CLK_TS0_PAD0",
998 "CLK_TS0_PAD1",
999 "CLK_TS0_PAD2",
1000 "CLK_TS0_PAD3",
1001 "CLK_TS0_PAD4",
1002 "CLK_TS0_PAD5",
1003 "CLK_TS0_PAD6",
1004 "CLK_TS0_PADTSO"
1005 };
1006 #endif
1007
1008 //@NOTE
1009 //EX3~6 are serial mode and ts2_padmax_mode must be 2 or 3.
1010
1011
1012 switch (eTSPad)
1013 {
1014 default:
1015 case E_TSP_TS_PAD_EXT0:
1016 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
1017 pad_src = REG_TOP_TS_SRC_EXT0;
1018 break;
1019 case E_TSP_TS_PAD_EXT1:
1020 clk_src = REG_CLKGEN0_TS_SRC_EXT1;
1021 pad_src = REG_TOP_TS_SRC_EXT1;
1022 break;
1023 case E_TSP_TS_PAD_EXT2:
1024 clk_src = REG_CLKGEN0_TS_SRC_EXT2;
1025 pad_src = REG_TOP_TS_SRC_EXT2;
1026 break;
1027 case E_TSP_TS_PAD_EXT3:
1028 clk_src = REG_CLKGEN0_TS_SRC_EXT3;
1029 pad_src = REG_TOP_TS_SRC_EXT3;
1030 break;
1031 case E_TSP_TS_PAD_EXT4:
1032 clk_src = REG_CLKGEN0_TS_SRC_EXT4;
1033 pad_src = REG_TOP_TS_SRC_EXT4;
1034 break;
1035 case E_TSP_TS_PAD_EXT5:
1036 clk_src = REG_CLKGEN0_TS_SRC_EXT5;
1037 pad_src = REG_TOP_TS_SRC_EXT5;
1038 break;
1039 case E_TSP_TS_PAD_EXT6:
1040 clk_src = REG_CLKGEN0_TS_SRC_EXT6;
1041 pad_src = REG_TOP_TS_SRC_EXT6;
1042 break;
1043 case E_TSP_TS_PAD_TSOUT0:
1044 clk_src = REG_CLKGEN0_TS_SRC_TSO0;
1045 pad_src = REG_TOP_TS_SRC_TSO0;
1046 break;
1047 case E_TSP_TS_PAD_INTER0:
1048 clk_src = REG_CLKGEN0_TS_SRC_EXT0;
1049 pad_src = REG_TOP_TS_SRC_EXT0;
1050 printf("[%s][%d]Warning KANO not support Internal Demod\n",__FUNCTION__,__LINE__);
1051 break;
1052 }
1053
1054 #ifdef CONFIG_MSTAR_CLKM
1055 switch(clk_src)
1056 {
1057 case REG_CLKGEN0_TS_SRC_EXT0:
1058 u8NameIdx = 0;
1059 break;
1060 case REG_CLKGEN0_TS_SRC_EXT1:
1061 u8NameIdx = 1;
1062 break;
1063 case REG_CLKGEN0_TS_SRC_EXT2:
1064 u8NameIdx = 2;
1065 break;
1066 case REG_CLKGEN0_TS_SRC_EXT3:
1067 u8NameIdx = 3;
1068 break;
1069 case REG_CLKGEN0_TS_SRC_EXT4:
1070 u8NameIdx = 4;
1071 break;
1072 case REG_CLKGEN0_TS_SRC_EXT5:
1073 u8NameIdx = 5;
1074 break;
1075 case REG_CLKGEN0_TS_SRC_EXT6:
1076 u8NameIdx = 6;
1077 break;
1078 case REG_CLKGEN0_TS_SRC_TSO0:
1079 u8NameIdx = 7;
1080 break;
1081 default:
1082 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1083 u8NameIdx = 0;
1084 break;
1085 }
1086 #endif
1087
1088 //@FIXME use enum instead of constant
1089 switch (tsIf)
1090 {
1091 case 0:
1092 TSP_TOP_REG(REG_TOP_TS0_MUX) = (TSP_TOP_REG(REG_TOP_TS0_MUX) & ~REG_TOP_TS_SRC_MASK) | (pad_src<<REG_TOP_TS0_SHIFT);
1093
1094 #ifdef CONFIG_MSTAR_CLKM
1095 handle = Drv_Clkm_Get_Handle("g_clk_ts");
1096 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1097 #else
1098 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & ~REG_CLKGEN0_TS_MASK) | (clk_src<<(REG_CLKGEN0_TS0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1099 #endif
1100 break;
1101 case 1:
1102 TSP_TOP_REG(REG_TOP_TS1_MUX) = (TSP_TOP_REG(REG_TOP_TS1_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS1_SHIFT))
1103 | (pad_src<<REG_TOP_TS1_SHIFT);
1104 #ifdef CONFIG_MSTAR_CLKM
1105 handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1106 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1107 #else
1108 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT))
1109 | (clk_src<<(REG_CLKGEN0_TS1_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1110 #endif
1111 break;
1112 case 2:
1113 TSP_TOP_REG(REG_TOP_TS2_MUX) = (TSP_TOP_REG(REG_TOP_TS2_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS2_SHIFT))
1114 | (pad_src<<REG_TOP_TS2_SHIFT);
1115 #ifdef CONFIG_MSTAR_CLKM
1116 handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1117 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1118 #else
1119 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT))
1120 | (clk_src<<(REG_CLKGEN0_TS2_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1121 #endif
1122 break;
1123 case 3:
1124 TSP_TOP_REG(REG_TOP_TS3_MUX) = (TSP_TOP_REG(REG_TOP_TS3_MUX) & ~(REG_TOP_TS_SRC_MASK<<REG_TOP_TS3_SHIFT))
1125 | (pad_src<<REG_TOP_TS3_SHIFT);
1126 #ifdef CONFIG_MSTAR_CLKM
1127 handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1128 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1129 #else
1130 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & ~(REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT))
1131 | (clk_src<<(REG_CLKGEN0_TS3_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1132 #endif
1133 break;
1134
1135 default:
1136 return FALSE;
1137 }
1138 return TRUE;
1139 }
1140
_HAL_TSO_SetPad1OutMux(MS_BOOL bSet)1141 static void _HAL_TSO_SetPad1OutMux(MS_BOOL bSet)
1142 {
1143 if(bSet)
1144 {
1145 TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) = TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) & ~(REG_TOP_TS1MODE_MASK << REG_TOP_TS1MODE_SHIFT);
1146 }
1147 else
1148 {
1149 TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) = ((TSP_TOP_REG(REG_TOP_TS_PADMUX_MODE) & ~(REG_TOP_TS1MODE_MASK << REG_TOP_TS1MODE_SHIFT))
1150 | (REG_TOP_TS1MODE_INPUT << REG_TOP_TS1MODE_SHIFT));
1151 }
1152 }
1153
HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)1154 void HAL_TSO_SetTSOOutMUX(MS_BOOL bSet)
1155 {
1156 _HAL_TSO_SetPad1OutMux(bSet);
1157 }
1158
HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad,TSP_TS_PAD_MUX_MODE eOutPadMode,TSP_TS_PAD eInPad,TSP_TS_PAD_MUX_MODE eInPadMode,MS_BOOL bEnable)1159 MS_BOOL HAL_TSP_TsOutPadCfg(TSP_TS_PAD eOutPad, TSP_TS_PAD_MUX_MODE eOutPadMode, TSP_TS_PAD eInPad, TSP_TS_PAD_MUX_MODE eInPadMode, MS_BOOL bEnable)
1160 {
1161 MS_U16 u16Temp = 0;
1162
1163 switch(eOutPad) // output pad
1164 {
1165 case E_TSP_TS_PAD_EXT1: // TS_pad #1
1166 if(eInPad == E_TSP_TS_PAD_EXT1) // output pad == input pad ?
1167 {
1168 return FALSE;
1169 }
1170
1171 _HAL_TSO_SetPad1OutMux(bEnable); // set pad mode (input or output)
1172
1173 switch(eOutPadMode) // set pad output mode
1174 {
1175 case E_TSP_TS_PAD_MUX_TSO:
1176 // input from TSO
1177 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT))
1178 | (REG_TOP_TS_OUT_MODE_TSO << REG_TOP_TS_OUT_MODE_SHIFT);
1179 break;
1180 case E_TSP_TS_PAD_MUX_S2P:
1181 // input from S2P
1182 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT))
1183 | (REG_TOP_TS_OUT_MODE_S2P << REG_TOP_TS_OUT_MODE_SHIFT);
1184
1185 u16Temp = REG_TSO_TSP_S2P_EN | REG_TSO_TSP_S2P_TS_SIN_C0 | REG_TSO_TSP_S2P_TS_SIN_C1; // S2P enable bit , serial bit count setting
1186 if(eInPadMode == E_TSP_TS_PAD_MUX_PARALLEL)
1187 {
1188 u16Temp |= REG_TSO_TSP_BYPASS_S2P; // bypass S2P: if input is parallel , set it
1189 }
1190 else if(eInPadMode == E_TSP_TS_PAD_MUX_3WIRED_SERIAL)
1191 {
1192 u16Temp |= REG_TSO_TSP_S2P_3WIRE; // input pad is 3-wire serial
1193 }
1194
1195 // S2P config
1196 TSP_TSO_REG(REG_TSO_TSP_CONFIG0) = (TSP_TSO_REG(REG_TSO_TSP_CONFIG0) & ~REG_TSO_TSP_S2P_MASK) | u16Temp;
1197 // select S2P input pad
1198 TSP_TOP_REG(REG_TOP_TSO4_5_MUX) = (TSP_TOP_REG(REG_TOP_TSO4_5_MUX) & ~REG_TOP_TSO4_MASK)
1199 | (eInPad << REG_TOP_TSO4_SHIFT);
1200 // select S2P input clk source
1201 #ifdef CONFIG_MSTAR_CLKM
1202 {
1203 MS_S32 handle;
1204 MS_U8 u8NameIdx = 0;
1205 char* u8ClkSrcNames[] =
1206 {
1207 "CLK_S2P0_PAD0",
1208 "CLK_S2P0_PAD1",
1209 "CLK_S2P0_PAD2",
1210 "CLK_S2P0_PAD3",
1211 "CLK_S2P0_PAD4",
1212 "CLK_S2P0_PAD5",
1213 "CLK_S2P0_PAD6"
1214 };
1215
1216 switch(eInPad)
1217 {
1218 case E_TSP_TS_PAD_EXT0:
1219 u8NameIdx = 0;
1220 break;
1221 case E_TSP_TS_PAD_EXT1:
1222 u8NameIdx = 1;
1223 break;
1224 case E_TSP_TS_PAD_EXT2:
1225 u8NameIdx = 2;
1226 break;
1227 case E_TSP_TS_PAD_EXT3:
1228 u8NameIdx = 3;
1229 break;
1230 case E_TSP_TS_PAD_EXT4:
1231 u8NameIdx = 4;
1232 break;
1233 case E_TSP_TS_PAD_EXT5:
1234 u8NameIdx = 5;
1235 break;
1236 case E_TSP_TS_PAD_EXT6:
1237 u8NameIdx = 6;
1238 break;
1239 default:
1240 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1241 u8NameIdx = 0;
1242 break;
1243 }
1244
1245 handle = Drv_Clkm_Get_Handle("g_clk_s2p_in");
1246 Drv_Clkm_Set_Clk_Source(handle, u8ClkSrcNames[u8NameIdx]);
1247 }
1248 #else
1249 TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) = (TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) & ~(REG_CLKGEN0_S2P_IN_CLK_MASK << REG_CLKGEN0_S2P_IN_CLK_SHIFT))
1250 | ((eInPad & REG_CLKGEN0_S2P_IN_CLK_SRC_MASK) << (REG_CLKGEN0_S2P_IN_CLK_SHIFT + REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT));
1251 #endif
1252 break;
1253 case E_TSP_TS_PAD_MUX_S2P1:
1254 // input from S2P1
1255 TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) = (TSP_TOP_REG(REG_TOP_TS_OUTPUT_MODE) & ~(REG_TOP_TS_OUT_MODE_MASK << REG_TOP_TS_OUT_MODE_SHIFT))
1256 | (REG_TOP_TS_OUT_MODE_S2P1 << REG_TOP_TS_OUT_MODE_SHIFT);
1257
1258 u16Temp = REG_TSO_TSP_S2P1_EN | REG_TSO_TSP_S2P1_TS_SIN_C0 | REG_TSO_TSP_S2P1_TS_SIN_C1;// S2P1 enable bit , serial bit count setting
1259 if(eInPadMode == E_TSP_TS_PAD_MUX_PARALLEL)
1260 {
1261 u16Temp |= REG_TSO_TSP_BYPASS_S2P1; // bypass S2P1: if input is parallel , set it
1262 }
1263 else if(eInPadMode == E_TSP_TS_PAD_MUX_3WIRED_SERIAL)
1264 {
1265 u16Temp |= REG_TSO_TSP_S2P1_3WIRE; // input pad is 3-wire serial
1266 }
1267 // S2P1 config
1268 TSP_TSO_REG(REG_TSO_TSP_CONFIG0) = (TSP_TSO_REG(REG_TSO_TSP_CONFIG0) & ~REG_TSO_TSP_S2P1_MASK) | u16Temp;
1269 // select S2P1 input pad
1270 TSP_TOP_REG(REG_TOP_TSO4_5_MUX) = (TSP_TOP_REG(REG_TOP_TSO4_5_MUX) & ~REG_TOP_TSO5_MASK)
1271 | (eInPad << REG_TOP_TSO5_SHIFT);
1272 #ifdef CONFIG_MSTAR_CLKM
1273 {
1274 MS_S32 handle;
1275 MS_U8 u8NameIdx = 0;
1276 char* u8ClkSrcNames[] =
1277 {
1278 "CLK_S2P1_PAD0",
1279 "CLK_S2P1_PAD1",
1280 "CLK_S2P1_PAD2",
1281 "CLK_S2P1_PAD3",
1282 "CLK_S2P1_PAD4",
1283 "CLK_S2P1_PAD5",
1284 "CLK_S2P1_PAD6"
1285 };
1286
1287 switch(eInPad)
1288 {
1289 case E_TSP_TS_PAD_EXT0:
1290 u8NameIdx = 0;
1291 break;
1292 case E_TSP_TS_PAD_EXT1:
1293 u8NameIdx = 1;
1294 break;
1295 case E_TSP_TS_PAD_EXT2:
1296 u8NameIdx = 2;
1297 break;
1298 case E_TSP_TS_PAD_EXT3:
1299 u8NameIdx = 3;
1300 break;
1301 case E_TSP_TS_PAD_EXT4:
1302 u8NameIdx = 4;
1303 break;
1304 case E_TSP_TS_PAD_EXT5:
1305 u8NameIdx = 5;
1306 break;
1307 case E_TSP_TS_PAD_EXT6:
1308 u8NameIdx = 6;
1309 break;
1310 default:
1311 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1312 u8NameIdx = 0;
1313 break;
1314 }
1315
1316 handle = Drv_Clkm_Get_Handle("g_clk_s2p1_in");
1317 Drv_Clkm_Set_Clk_Source(handle, u8ClkSrcNames[u8NameIdx]);
1318 }
1319 #else
1320 // select S2P1 input clk source
1321 TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) = (TSP_CLKGEN0_REG(REG_CLKGEN0_S2P_IN_CLK_SRC) & ~(REG_CLKGEN0_S2P_IN_CLK_MASK << REG_CLKGEN0_S2P1_IN_CLK_SHIFT))
1322 | ((eInPad & REG_CLKGEN0_S2P_IN_CLK_SRC_MASK) << (REG_CLKGEN0_S2P1_IN_CLK_SHIFT + REG_CLKGEN0_S2P_IN_CLK_SRC_SHIFT));
1323 #endif
1324
1325 break;
1326 default:
1327 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%d] Warining wrong output PAD Mode:%u\n",__FUNCTION__,__LINE__, eOutPadMode));
1328 return FALSE;
1329 }
1330 break;
1331 default:
1332 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1333 return FALSE;
1334 }
1335
1336 return TRUE;
1337 }
1338
_TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad,MS_U32 * pu32PADSrc,MS_U32 * pu32CLKSrc)1339 static MS_BOOL _TSP_Hal_TSPAD2RelatedReg_Mapping(TSP_TS_PAD eTSPad, MS_U32* pu32PADSrc, MS_U32* pu32CLKSrc)
1340 {
1341 switch (eTSPad)
1342 {
1343 case E_TSP_TS_PAD_EXT0:
1344 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
1345 *pu32PADSrc = REG_TOP_TS_SRC_EXT0;
1346 break;
1347 case E_TSP_TS_PAD_EXT1:
1348 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_EXT1;
1349 *pu32PADSrc = REG_TOP_TS_SRC_EXT1;
1350 break;
1351 case E_TSP_TS_PAD_INTER0:
1352 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_DMD0;
1353 *pu32PADSrc = REG_TOP_TS_SRC_DMD0;
1354 break;
1355 case E_TSP_TS_PAD_TSOUT0:
1356 *pu32CLKSrc = REG_CLKGEN0_TS_SRC_TSO0;
1357 *pu32PADSrc = REG_TOP_TS_SRC_TSO0;
1358 break;
1359
1360 default:
1361 return FALSE;
1362 }
1363
1364 return TRUE;
1365 }
1366
HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng,TSP_TS_PAD eTSPad)1367 MS_BOOL HAL_TSP_TSO_TSIF_SelPad(MS_U32 u32TSOEng, TSP_TS_PAD eTSPad)
1368 {
1369 MS_U32 u32CLKSrc = REG_CLKGEN0_TS_SRC_EXT0;
1370 MS_U32 u32PADSrc = REG_TOP_TS_SRC_EXT0;
1371 _TSP_Hal_TSPAD2RelatedReg_Mapping(eTSPad, &u32PADSrc, &u32CLKSrc);
1372
1373 switch(u32TSOEng)
1374 {
1375 case 0:
1376 TSP_TOP_REG(REG_TOP_TSO0_MUX) = (TSP_TOP_REG(REG_TOP_TSO0_MUX) & ~REG_TOP_TS_SRC_MASK) | u32PADSrc;
1377 #ifdef CONFIG_MSTAR_CLKM
1378 {
1379 MS_S32 handle;
1380 MS_U8 u8NameIdx = 0;
1381 char* u8ClkSrcNames[] =
1382 {
1383 "CLK_TSOIN0_PAD0",
1384 "CLK_TSOIN0_PAD1",
1385 "CLK_TSOIN0_PAD2",
1386 "CLK_TSOIN0_PAD3",
1387 "CLK_TSOIN0_PAD4",
1388 "CLK_TSOIN0_PAD5",
1389 "CLK_TSOIN0_PAD6"
1390 };
1391
1392 switch(u32CLKSrc)
1393 {
1394 case REG_CLKGEN0_TS_SRC_EXT0:
1395 u8NameIdx = 0;
1396 break;
1397 case REG_CLKGEN0_TS_SRC_EXT1:
1398 u8NameIdx = 1;
1399 break;
1400 case REG_CLKGEN0_TS_SRC_EXT2:
1401 u8NameIdx = 2;
1402 break;
1403 case REG_CLKGEN0_TS_SRC_EXT3:
1404 u8NameIdx = 3;
1405 break;
1406 case REG_CLKGEN0_TS_SRC_EXT4:
1407 u8NameIdx = 4;
1408 break;
1409 case REG_CLKGEN0_TS_SRC_EXT5:
1410 u8NameIdx = 5;
1411 break;
1412 default:
1413 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1414 u8NameIdx = 0;
1415 break;
1416 }
1417
1418 handle = Drv_Clkm_Get_Handle("g_clk_tso_in");
1419 Drv_Clkm_Set_Clk_Source(handle,u8ClkSrcNames[u8NameIdx]);
1420 }
1421 #else
1422 TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) = (TSP_CLKGEN0_REG(REG_CLKGEN0_TSO0_CLK) & ~REG_CLKGEN0_TS_MASK)
1423 | (u32CLKSrc << (REG_CLKGEN0_TSO0_SHIFT+REG_CLKGEN0_TS_SRC_SHIFT));
1424 #endif
1425 return TRUE;
1426
1427 default:
1428 return FALSE;
1429 }
1430 }
1431
1432
HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf,MS_BOOL bClkInv)1433 MS_BOOL HAL_TSP_TSIF_SelPad_ClkInv(MS_U32 tsIf , MS_BOOL bClkInv)
1434 {
1435 if (bClkInv)
1436 {
1437 switch (tsIf)
1438 {
1439 case 0:
1440 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
1441 break;
1442 case 1:
1443 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
1444 break;
1445 case 2:
1446 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
1447 break;
1448 case 3:
1449 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
1450 break;
1451 default:
1452 return FALSE;
1453 }
1454 }
1455 else
1456 {
1457 switch (tsIf)
1458 {
1459 case 0:
1460 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS0_SHIFT));
1461 break;
1462 case 1:
1463 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS1_SHIFT));
1464 break;
1465 case 2:
1466 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS2_SHIFT));
1467 break;
1468 case 3:
1469 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_INVERT)<<(REG_CLKGEN0_TS3_SHIFT));
1470 break;
1471 default:
1472 return FALSE;
1473 }
1474 }
1475 return TRUE;
1476 }
1477
HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf,MS_BOOL bClkDis)1478 MS_BOOL HAL_TSP_TSIF_SelPad_ClkDis(MS_U32 tsIf , MS_BOOL bClkDis)
1479 {
1480 if (bClkDis)
1481 {
1482 #ifdef CONFIG_MSTAR_CLKM
1483 MS_S32 s32Handle;
1484
1485 switch (tsIf)
1486 {
1487 case 0:
1488 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
1489 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1490 break;
1491 case 1:
1492 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1493 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1494 break;
1495 case 2:
1496 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1497 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1498 break;
1499 case 3:
1500 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1501 Drv_Clkm_Clk_Gate_Disable(s32Handle);
1502 break;
1503 default:
1504 return FALSE;
1505 }
1506 #else
1507 switch (tsIf)
1508 {
1509 case 0:
1510 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1511 break;
1512 case 1:
1513 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1514 break;
1515 case 2:
1516 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1517 break;
1518 case 3:
1519 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) |= ((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1520 break;
1521 default:
1522 return FALSE;
1523 }
1524 #endif
1525 }
1526 else
1527 {
1528 #ifdef CONFIG_MSTAR_CLKM
1529 MS_S32 s32Handle;
1530 MS_U16 u16ClkSrc;
1531 MS_U8 u8NameIdx = 0;
1532 char* u8ClkSrcNames[] =
1533 {
1534 "CLK_TS0_PAD0",
1535 "CLK_TS0_PAD1",
1536 "CLK_TS0_PAD2",
1537 "CLK_TS0_PAD3",
1538 "CLK_TS0_PAD4",
1539 "CLK_TS0_PAD5",
1540 "CLK_TS0_PAD6",
1541 "CLK_TS0_PADTSO"
1542 };
1543
1544 switch (tsIf)
1545 {
1546 case 0:
1547 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts");
1548 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) & REG_CLKGEN0_TS_MASK) >> (REG_CLKGEN0_TS0_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1549 break;
1550 case 1:
1551 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts1");
1552 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS1_SHIFT)) >> (REG_CLKGEN0_TS1_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1553 break;
1554 case 2:
1555 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts2");
1556 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS2_SHIFT)) >> (REG_CLKGEN0_TS2_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1557 break;
1558 case 3:
1559 s32Handle = Drv_Clkm_Get_Handle("g_clk_ts3");
1560 u16ClkSrc = (TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) & (REG_CLKGEN0_TS_MASK<<REG_CLKGEN0_TS3_SHIFT)) >> (REG_CLKGEN0_TS3_SHIFT + REG_CLKGEN0_TS_SRC_SHIFT);
1561 break;
1562 default:
1563 return FALSE;
1564 }
1565
1566 switch(u16ClkSrc)
1567 {
1568 case REG_CLKGEN0_TS_SRC_EXT0:
1569 u8NameIdx = 0;
1570 break;
1571 case REG_CLKGEN0_TS_SRC_EXT1:
1572 u8NameIdx = 1;
1573 break;
1574 case REG_CLKGEN0_TS_SRC_EXT2:
1575 u8NameIdx = 2;
1576 break;
1577 case REG_CLKGEN0_TS_SRC_EXT3:
1578 u8NameIdx = 3;
1579 break;
1580 case REG_CLKGEN0_TS_SRC_EXT4:
1581 u8NameIdx = 4;
1582 break;
1583 case REG_CLKGEN0_TS_SRC_EXT5:
1584 u8NameIdx = 5;
1585 break;
1586 case REG_CLKGEN0_TS_SRC_EXT6:
1587 u8NameIdx = 6;
1588 break;
1589 case REG_CLKGEN0_TS_SRC_TSO0:
1590 u8NameIdx = 7;
1591 break;
1592 default:
1593 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] Pad not support !!\n",__FUNCTION__,__LINE__));
1594 u8NameIdx = 0;
1595 break;
1596 }
1597
1598 Drv_Clkm_Set_Clk_Source(s32Handle, u8ClkSrcNames[u8NameIdx]);
1599 #else
1600 switch (tsIf)
1601 {
1602 case 0:
1603 TSP_CLKGEN0_REG(REG_CLKGEN0_TS0_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS0_SHIFT));
1604 break;
1605 case 1:
1606 TSP_CLKGEN0_REG(REG_CLKGEN0_TS1_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS1_SHIFT));
1607 break;
1608 case 2:
1609 TSP_CLKGEN0_REG(REG_CLKGEN0_TS2_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS2_SHIFT));
1610 break;
1611 case 3:
1612 TSP_CLKGEN0_REG(REG_CLKGEN0_TS3_CLK) &= ~((REG_CLKGEN0_TS_DISABLE)<<(REG_CLKGEN0_TS3_SHIFT));
1613 break;
1614 default:
1615 return FALSE;
1616 }
1617 #endif
1618 }
1619 return TRUE;
1620 }
1621
1622 // @NOTE tsif0 and tsif2 can do filein and livein simulatenously,so tsif0 tsif2's output are both live TS Data
HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1623 MS_BOOL HAL_TSP_TSIF_FileEn(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1624 {
1625 if(bEnable)
1626 {
1627 switch(eFileEng)
1628 {
1629 case E_FILEENG_TSIF0:
1630 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE); // for wishbone DMA (load firmware or playback)
1631 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL); //Tsif0 output is live TS
1632 REG16_SET(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN); //filein enable
1633 break;
1634 case E_FILEENG_TSIF1:
1635 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1); // for wishbone DMA (load firmware or playback) we don't use this fileEng for FW
1636 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
1637 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
1638 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN); //filein enable
1639 break;
1640 case E_FILEENG_TSIF2:
1641 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
1642 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
1643 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
1644 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
1645 break;
1646 case E_FILEENG_TSIF3:
1647 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3);
1648 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3);
1649 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3);
1650 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3);
1651 break;
1652 default:
1653 return FALSE;
1654 }
1655 }
1656 else
1657 {
1658 switch(eFileEng)
1659 {
1660 case E_FILEENG_TSIF0:
1661 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_PVR_CMD_QUEUE_ENABLE);
1662 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_DATA_PORT_SEL);
1663 REG16_CLR(&_RegCtrl->TSP_Ctrl, TSP_CTRL_TSFILE_EN);
1664 break;
1665 case E_FILEENG_TSIF1:
1666 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TSP_FILE_SEGMENT1);
1667 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_SEGMENT_TSIF1);
1668 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TS_DATA_PORT_SEL1);
1669 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_TSP_FILE_IN_TSIF1_EN);
1670 break;
1671 case E_FILEENG_TSIF2:
1672 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_FILE_SEGMENT2);
1673 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILE_SEGMENT_TSIF2);
1674 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_TSP_FILEIN_TSIF2);
1675 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TS_DATA_PORT_SEL2);
1676 break;
1677 case E_FILEENG_TSIF3:
1678 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TSP_FILE_SEGMENT3);
1679 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_SEGMENT_TSIF3);
1680 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA_PORT_SEL3);
1681 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_TSP_FILE_IN_TSIF3);
1682 break;
1683 default:
1684 return FALSE;
1685 }
1686 }
1687
1688 return TRUE;
1689 }
1690
HAL_TSP_TSIF_BitSwap(MS_U32 tsIf,MS_BOOL bEnable)1691 void HAL_TSP_TSIF_BitSwap(MS_U32 tsIf, MS_BOOL bEnable)
1692 {
1693 if(bEnable)
1694 {
1695 switch(tsIf)
1696 {
1697 case 0:
1698 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1699 break;
1700 case 1:
1701 REG16_SET(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1702 break;
1703 case 2:
1704 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1705 break;
1706 case 3:
1707 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP);
1708 break;
1709 default:
1710 return;
1711 }
1712 }
1713 else
1714 {
1715 switch(tsIf)
1716 {
1717 case 0:
1718 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA0_SWAP);
1719 break;
1720 case 1:
1721 REG16_CLR(&_RegCtrl->Hw_PVRCfg, TSP_HW_CFG4_TS_DATA1_SWAP);
1722 break;
1723 case 2:
1724 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TS_DATA2_SWAP);
1725 break;
1726 case 3:
1727 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TS_DATA3_SWAP);
1728 break;
1729 default:
1730 return;
1731 }
1732 }
1733 }
1734
HAL_TSP_TSIF_ExtSync(MS_U32 tsIf,MS_BOOL bEnable)1735 void HAL_TSP_TSIF_ExtSync(MS_U32 tsIf, MS_BOOL bEnable)
1736 {
1737 if(bEnable)
1738 {
1739 printf("External Sync\n");
1740
1741 switch(tsIf)
1742 {
1743 case 0:
1744 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1745 break;
1746 case 1:
1747 REG16_SET(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1748 break;
1749 case 2:
1750 REG32_SET(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1751 break;
1752 case 3:
1753 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3);
1754 break;
1755 default:
1756 return;
1757 }
1758 }
1759 else
1760 {
1761 printf("Internal Sync\n");
1762
1763 switch(tsIf)
1764 {
1765 case 0:
1766 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_EXTSYNC);
1767 break;
1768 case 1:
1769 REG16_CLR(&_RegCtrl->Hw_Config2, TSP_HW_CFG2_TSIF1_EXTSYNC);
1770 break;
1771 case 2:
1772 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_EXT_SYNC_SEL2);
1773 break;
1774 case 3:
1775 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_EXT_SYNC_SEL3);
1776 break;
1777 default:
1778 return;
1779 }
1780 }
1781 }
1782
1783 //void HAL_TSP_TSIF_Full_Block(MS_U32 tsIf, MS_BOOL bEnable)
HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng,MS_BOOL bEnable)1784 void HAL_TSP_Filein_Bypass(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
1785 {
1786 if(bEnable)
1787 {
1788 switch(eFileEng)
1789 {
1790 case 0:
1791 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1792 break;
1793 case 1:
1794 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1795 break;
1796 case 2:
1797 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1798 break;
1799 case 3:
1800 REG16_SET(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP3);
1801 break;
1802 default:
1803 return;
1804 }
1805
1806 REG16_MSK_W(&_RegCtrl3->CFG3_10,CFG3_10_PS_MODE_SRC_MASK,(eFileEng << CFG3_10_PS_MODE_SRC_SHIFT));
1807 }
1808 else
1809 {
1810 switch(eFileEng)
1811 {
1812 case 0:
1813 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP);
1814 break;
1815 case 1:
1816 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP1);
1817 break;
1818 case 2:
1819 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP2);
1820 break;
1821 case 3:
1822 REG16_CLR(&(_RegCtrl->TSP_Ctrl2), TSP_AV_DIRECT_STOP3);
1823 break;
1824 default:
1825 return;
1826 }
1827
1828 }
1829 }
1830
HAL_TSP_TSIF_Parl(MS_U32 tsIf,MS_BOOL bEnable)1831 void HAL_TSP_TSIF_Parl(MS_U32 tsIf, MS_BOOL bEnable)
1832 {
1833 if(bEnable)
1834 {
1835 switch(tsIf)
1836 {
1837 case 0:
1838 REG16_SET(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1839 break;
1840 case 1:
1841 REG16_SET(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1842 break;
1843 case 2:
1844 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1845 break;
1846 case 3:
1847 REG16_SET(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3);
1848 break;
1849 default:
1850 return;
1851 }
1852 }
1853 else
1854 {
1855 switch(tsIf)
1856 {
1857 case 0:
1858 REG16_CLR(&(_RegCtrl->Hw_Config0), TSP_HW_CFG0_TSIF0_PARL);
1859 break;
1860 case 1:
1861 REG16_CLR(&(_RegCtrl->Hw_Config2), TSP_HW_CFG2_TSIF1_PARL);
1862 break;
1863 case 2:
1864 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_P_SEL2);
1865 break;
1866 case 3:
1867 REG16_CLR(&(_RegCtrl2->CFG_0B), CFG_0B_P_SEL3);
1868 break;
1869 default:
1870 return;
1871 }
1872 }
1873 }
1874
HAL_TSP_PAD_3Wire(MS_U32 u32Pad,MS_BOOL bEnable)1875 void HAL_TSP_PAD_3Wire(MS_U32 u32Pad, MS_BOOL bEnable)
1876 {
1877 #if 0 //@NOTE: Kano do NOT need to set
1878 if(bEnable)
1879 {
1880 switch(u32Pad)
1881 {
1882 case 0:
1883 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS0_3WIRE_EN;
1884 break;
1885 case 1:
1886 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS1_3WIRE_EN;
1887 break;
1888 case 2:
1889 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE)| REG_TOP_TSP_TS2_3WIRE_EN;
1890 break;
1891 case 3:
1892 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) | REG_TOP_TSP_TS3_3WIRE_EN;
1893 break;
1894
1895 default:
1896 return;
1897 }
1898 }
1899 else
1900 {
1901 switch(u32Pad)
1902 {
1903 case 0:
1904 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS0_3WIRE_EN;
1905 break;
1906 case 1:
1907 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS1_3WIRE_EN;
1908 break;
1909 case 2:
1910 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS2_3WIRE_EN;
1911 break;
1912 case 3:
1913 TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) = TSP_TOP_REG(REG_TOP_TSP_3WIRE_MODE) & ~REG_TOP_TSP_TS3_3WIRE_EN;
1914 break;
1915 default:
1916 return;
1917 }
1918 }
1919 #endif
1920 }
1921
HAL_TSP_TSIF_3Wire(MS_U32 tsIf,MS_BOOL bEnable)1922 void HAL_TSP_TSIF_3Wire(MS_U32 tsIf, MS_BOOL bEnable)
1923 {
1924 if(bEnable)
1925 {
1926 switch(tsIf)
1927 {
1928 case 0:
1929 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1930 break;
1931 case 1:
1932 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1933 break;
1934 case 2:
1935 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1936 break;
1937 case 3:
1938 REG16_SET(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS3);
1939 break;
1940 default:
1941 return;
1942 }
1943 }
1944 else
1945 {
1946 switch(tsIf)
1947 {
1948 case 0:
1949 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS0);
1950 break;
1951 case 1:
1952 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS1);
1953 break;
1954 case 2:
1955 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS2);
1956 break;
1957 case 3:
1958 REG16_CLR(&(_RegCtrl3->CFG3_37), HW4_CFG37_3WIRE_SERIAL_MODE_TS3);
1959 break;
1960 default:
1961 return;
1962 }
1963 }
1964
1965 }
1966
HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId,MS_BOOL bEn)1967 void HAL_TSP_PktDmx_CCDrop(MS_U32 pktDmxId, MS_BOOL bEn)
1968 {
1969 if(bEn)
1970 {
1971 REG16_SET(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
1972 }
1973 else
1974 {
1975 REG16_CLR(&_RegCtrl3->CFG3_0C, ((1 << pktDmxId) << CFG3_0C_PKTDMX_CC_DROP_SHIFT) & CFG3_0C_PKTDMX_CC_DROP_MSAK);
1976 }
1977 }
1978
HAL_TSP_ReDirect_File(MS_U32 reDir,MS_U32 tsIf,MS_BOOL bEn)1979 void HAL_TSP_ReDirect_File(MS_U32 reDir, MS_U32 tsIf, MS_BOOL bEn)
1980 {
1981 //@NOTE Not support in KANO(K7)
1982 #if 0
1983 MS_U16 u16Src = 0;
1984
1985 if((reDir > 0) || (tsIf > 1))
1986 return;
1987
1988 if(bEn)
1989 {
1990 u16Src = (MS_U16)(tsIf + 1) << CFG_01_PDFLT2_FILE_SRC_SHIFT;
1991 }
1992
1993 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PDFLT2_FILE_SRC, u16Src);
1994 #endif
1995 }
1996
HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)1997 void HAL_TSP_TRACE_MARK_En(MS_U32 u32Tsif,TSP_DST_SEQ eFltType,MS_BOOL bEn)
1998 {
1999 if(bEn)
2000 {
2001 switch(u32Tsif)
2002 {
2003 case 0:
2004 switch (eFltType)
2005 {
2006 case E_TSP_DST_FIFO_VIDEO:
2007 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
2008 break;
2009 case E_TSP_DST_FIFO_VIDEO3D:
2010 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
2011 break;
2012 case E_TSP_DST_FIFO_AUDIO:
2013 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
2014 break;
2015 case E_TSP_DST_FIFO_AUDIO2:
2016 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
2017 break;
2018 default:
2019 break;
2020 }
2021 break;
2022 case 1:
2023 switch (eFltType)
2024 {
2025 case E_TSP_DST_FIFO_VIDEO:
2026 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
2027 break;
2028 case E_TSP_DST_FIFO_VIDEO3D:
2029 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
2030 break;
2031 case E_TSP_DST_FIFO_AUDIO:
2032 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
2033 break;
2034 case E_TSP_DST_FIFO_AUDIO2:
2035 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
2036 break;
2037 default:
2038 break;
2039 }
2040 break;
2041 case 2:
2042 switch (eFltType)
2043 {
2044 case E_TSP_DST_FIFO_VIDEO:
2045 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
2046 break;
2047 case E_TSP_DST_FIFO_VIDEO3D:
2048 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
2049 break;
2050 case E_TSP_DST_FIFO_AUDIO:
2051 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
2052 break;
2053 case E_TSP_DST_FIFO_AUDIO2:
2054 REG16_SET(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
2055 break;
2056 default:
2057 break;
2058 }
2059 break;
2060 case 3:
2061 switch (eFltType)
2062 {
2063 case E_TSP_DST_FIFO_VIDEO:
2064 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V_EN);
2065 break;
2066 case E_TSP_DST_FIFO_VIDEO3D:
2067 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN);
2068 break;
2069 case E_TSP_DST_FIFO_AUDIO:
2070 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_A_EN);
2071 break;
2072 case E_TSP_DST_FIFO_AUDIO2:
2073 REG16_SET(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN);
2074 break;
2075 default:
2076 break;
2077 }
2078 break;
2079 default:
2080 break;
2081 }
2082 }
2083 else
2084 {
2085 switch(u32Tsif)
2086 {
2087 case 0:
2088 switch (eFltType)
2089 {
2090 case E_TSP_DST_FIFO_VIDEO:
2091 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V_EN);
2092 break;
2093 case E_TSP_DST_FIFO_VIDEO3D:
2094 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_V3D_EN);
2095 break;
2096 case E_TSP_DST_FIFO_AUDIO:
2097 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_A_EN);
2098 break;
2099 case E_TSP_DST_FIFO_AUDIO2:
2100 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX0_TRACE_MARK_AB_EN);
2101 break;
2102 default:
2103 break;
2104 }
2105 break;
2106 case 1:
2107 switch (eFltType)
2108 {
2109 case E_TSP_DST_FIFO_VIDEO:
2110 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V_EN);
2111 break;
2112 case E_TSP_DST_FIFO_VIDEO3D:
2113 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_V3D_EN);
2114 break;
2115 case E_TSP_DST_FIFO_AUDIO:
2116 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_A_EN);
2117 break;
2118 case E_TSP_DST_FIFO_AUDIO2:
2119 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX1_TRACE_MARK_AB_EN);
2120 break;
2121 default:
2122 break;
2123 }
2124 break;
2125 case 2:
2126 switch (eFltType)
2127 {
2128 case E_TSP_DST_FIFO_VIDEO:
2129 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V_EN);
2130 break;
2131 case E_TSP_DST_FIFO_VIDEO3D:
2132 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_V3D_EN);
2133 break;
2134 case E_TSP_DST_FIFO_AUDIO:
2135 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_A_EN);
2136 break;
2137 case E_TSP_DST_FIFO_AUDIO2:
2138 REG16_CLR(&_RegCtrl3->CFG3_2A, CFG3_2A_PKTDMX2_TRACE_MARK_AB_EN);
2139 break;
2140 default:
2141 break;
2142 }
2143 break;
2144 case 3:
2145 switch (eFltType)
2146 {
2147 case E_TSP_DST_FIFO_VIDEO:
2148 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V_EN);
2149 break;
2150 case E_TSP_DST_FIFO_VIDEO3D:
2151 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_V3D_EN);
2152 break;
2153 case E_TSP_DST_FIFO_AUDIO:
2154 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_A_EN);
2155 break;
2156 case E_TSP_DST_FIFO_AUDIO2:
2157 REG16_CLR(&_RegCtrl3->CFG3_2B, CFG3_2B_PKTDMX3_TRACE_MARK_AB_EN);
2158 break;
2159 default:
2160 break;
2161 }
2162 break;
2163 default:
2164 break;
2165 }
2166 }
2167 }
2168
HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)2169 void HAL_TSP_BD_AUD_En(MS_U32 u32BD,MS_BOOL bEn)
2170 {
2171
2172 if(bEn == TRUE)
2173 {
2174 switch(u32BD)
2175 {
2176 case 0:
2177 REG16_SET(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
2178 break;
2179 case 1:
2180 REG16_SET(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
2181 break;
2182 default:
2183 printf("Not support !!\n");
2184 break;
2185 }
2186 }
2187 else
2188 {
2189 switch(u32BD)
2190 {
2191 case 0:
2192 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD_AUD_EN);
2193 break;
2194 case 1:
2195 REG16_CLR(&_RegCtrl->reg15b4, TSP_BD2_AUD_EN);
2196 break;
2197 default:
2198 printf("Not support !!\n");
2199 break;
2200
2201 }
2202 }
2203
2204 }
2205
HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng,MS_U32 u32PktSize)2206 void HAL_TSP_Filein_PktSize(FILEENG_SEQ eFileEng, MS_U32 u32PktSize)
2207 {
2208 MS_U32 u32PktLen = u32PktSize;
2209
2210 if(u32PktSize == 130)
2211 {
2212 u32PktLen = 188;
2213 }
2214 else if(u32PktSize == 134)
2215 {
2216 u32PktLen = 192;
2217 }
2218
2219 if(u32PktSize == 130 || u32PktSize == 134) //RVU
2220 {
2221 MS_U16 u16value = 0;
2222
2223 if(u32PktSize == 134)
2224 {
2225 switch(eFileEng)
2226 {
2227 case E_FILEENG_TSIF0:
2228 u16value = HW4_CFG36_PKT130_TIMESTAMP_EN0;
2229 break;
2230 case E_FILEENG_TSIF1:
2231 u16value = HW4_CFG36_PKT130_TIMESTAMP_EN1;
2232 break;
2233 case E_FILEENG_TSIF2:
2234 u16value = CFG4_54_RVU_TIMESTAMP_EN2;
2235 break;
2236 case E_FILEENG_TSIF3:
2237 u16value = CFG4_54_RVU_TIMESTAMP_EN3;
2238 break;
2239 default:
2240 printf("Not support !!\n");
2241 break;
2242 }
2243 }
2244
2245 switch(eFileEng)
2246 {
2247 case E_FILEENG_TSIF0:
2248 u16value |= HW4_CFG36_PKT130_PSI_EN0 | HW4_CFG36_PKT130_EN0;
2249 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
2250 break;
2251 case E_FILEENG_TSIF1:
2252 u16value |= HW4_CFG36_PKT130_PSI_EN1 | HW4_CFG36_PKT130_EN1;
2253 REG16_SET(&_RegCtrl3->CFG3_36, u16value);
2254 break;
2255 //@TODO not implement
2256
2257 case E_FILEENG_TSIF2:
2258 u16value |= CFG4_54_RVU_PSI_EN2 | CFG4_54_RVU_EN2;
2259 REG16_SET(&_RegCtrl4->CFG4_54, u16value);
2260 break;
2261 case E_FILEENG_TSIF3:
2262 u16value |= CFG4_54_RVU_PSI_EN3 | CFG4_54_RVU_EN3;
2263 REG16_SET(&_RegCtrl4->CFG4_54, u16value);
2264 break;
2265 default:
2266 return;
2267 }
2268
2269 }
2270
2271 switch(eFileEng)
2272 {
2273 case E_FILEENG_TSIF0:
2274 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_ALT_TS_SIZE);
2275 REG16_W(&_RegCtrl->PktChkSizeFilein, (REG16_R(&_RegCtrl->PktChkSizeFilein) & ~TSP_PKT_SIZE_MASK) | (TSP_PKT_SIZE_MASK & (u32PktLen-1)));
2276 break;
2277 case E_FILEENG_TSIF1:
2278 REG16_W(&_RegCtrl2->CFG_02, (REG16_R(&_RegCtrl2->CFG_02) & ~CFG_02_PKT_CHK_SIZE_FIN1) | (CFG_02_PKT_CHK_SIZE_FIN1 & (u32PktLen-1)));
2279 break;
2280 case E_FILEENG_TSIF2:
2281 REG16_W(&_RegCtrl2->CFG_07, (REG16_R(&_RegCtrl2->CFG_07) & ~CFG_07_PKT_CHK_SIZE_FILEIN2) | (CFG_07_PKT_CHK_SIZE_FILEIN2 & (u32PktLen-1)));
2282 break;
2283 case E_FILEENG_TSIF3:
2284 REG16_W(&_RegCtrl2->CFG_0C, (REG16_R(&_RegCtrl2->CFG_0C) & ~CFG_0C_PKT_CHK_SIZE_FILEIN3) | (CFG_0C_PKT_CHK_SIZE_FILEIN3 & (u32PktLen-1)));
2285 break;
2286 default:
2287 break;
2288 }
2289 }
2290
HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng,MS_U32 addr)2291 void HAL_TSP_Filein_Addr(FILEENG_SEQ eFileEng, MS_U32 addr)
2292 {
2293 switch(eFileEng)
2294 {
2295 case E_FILEENG_TSIF0:
2296 REG32_W(&_RegCtrl->TsDma_Addr, addr);
2297 break;
2298 case E_FILEENG_TSIF1:
2299 REG32_W(&_RegCtrl2->CFG_30_31, addr);
2300 break;
2301 case E_FILEENG_TSIF2:
2302 REG32_W(&_RegCtrl2->CFG_35_36, addr);
2303 break;
2304 case E_FILEENG_TSIF3:
2305 REG32_W(&_RegCtrl2->CFG_3A_3B, addr);
2306 break;
2307 default:
2308 break;
2309 }
2310 }
2311
HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng,MS_U32 size)2312 void HAL_TSP_Filein_Size(FILEENG_SEQ eFileEng, MS_U32 size)
2313 {
2314 switch(eFileEng)
2315 {
2316 case E_FILEENG_TSIF0:
2317 REG32_W(&_RegCtrl->TsDma_Size, size);
2318 break;
2319 case E_FILEENG_TSIF1:
2320 REG32_W(&_RegCtrl2->CFG_32_33, size);
2321 break;
2322 case E_FILEENG_TSIF2:
2323 REG32_W(&_RegCtrl2->CFG_37_38, size);
2324 break;
2325 case E_FILEENG_TSIF3:
2326 REG32_W(&_RegCtrl2->CFG_3C_3D, size);
2327 break;
2328 default:
2329 break;
2330 }
2331 }
2332
HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)2333 void HAL_TSP_Filein_Start(FILEENG_SEQ eFileEng)
2334 {
2335 switch(eFileEng)
2336 {
2337 case E_FILEENG_TSIF0:
2338 REG16_SET(&_RegCtrl->TsDma_Ctrl, TSP_TSDMA_CTRL_START);
2339 break;
2340 case E_FILEENG_TSIF1:
2341 REG16_SET(&_RegCtrl2->CFG_34, CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START);
2342 break;
2343 case E_FILEENG_TSIF2:
2344 REG16_SET(&_RegCtrl2->CFG_39, CFG_39_FILEIN_CTRL_TSIF2_START);
2345 break;
2346 case E_FILEENG_TSIF3:
2347 REG16_SET(&_RegCtrl2->CFG_3E, CFG_3E_FILEIN_CTRL_TSIF3_START);
2348 break;
2349 default:
2350 break;
2351 }
2352 }
2353
HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)2354 MS_BOOL HAL_TSP_File_Pause(FILEENG_SEQ eFileEng)
2355 {
2356 switch (eFileEng)
2357 {
2358 case E_FILEENG_TSIF0:
2359 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
2360 return TRUE;
2361 case E_FILEENG_TSIF1:
2362 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
2363 return TRUE;
2364 case E_FILEENG_TSIF2:
2365 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
2366 return TRUE;
2367 case E_FILEENG_TSIF3:
2368 REG16_SET(&_RegCtrl3->CFG3_21, CFG3_21_TSIF3_FILE_PAUSE);
2369 return TRUE;
2370 default:
2371 return FALSE;
2372 }
2373 }
2374
HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)2375 MS_BOOL HAL_TSP_File_Resume(FILEENG_SEQ eFileEng)
2376 {
2377 switch (eFileEng)
2378 {
2379 case E_FILEENG_TSIF0:
2380 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_FILEIN_PAUSE);
2381 return TRUE;
2382 case E_FILEENG_TSIF1:
2383 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF1_FILE_PAUSE);
2384 return TRUE;
2385 case E_FILEENG_TSIF2:
2386 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF2_FILE_PAUSE);
2387 return TRUE;
2388 case E_FILEENG_TSIF3:
2389 REG16_CLR(&_RegCtrl3->CFG3_21, CFG3_21_TSIF3_FILE_PAUSE);
2390 return TRUE;
2391 default:
2392 return FALSE;
2393 }
2394 }
2395
HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)2396 void HAL_TSP_Filein_Init_Trust_Start(FILEENG_SEQ eFileEng)
2397 {
2398 switch(eFileEng)
2399 {
2400 case E_FILEENG_TSIF0:
2401 REG16_SET(&_RegCtrl->TsDma_Ctrl, (TSP_TSDMA_INIT_TRUST | TSP_TSDMA_CTRL_START));
2402 break;
2403 case E_FILEENG_TSIF1:
2404 REG16_SET(&_RegCtrl2->CFG_34, (CFG_34_REG_TSP_FILEIN_INIT_TRUST_TSIF1 | CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_START));
2405 break;
2406 case E_FILEENG_TSIF2:
2407 REG16_SET(&_RegCtrl2->CFG_39, (CFG_39_FILEIN_INIT_TRUST_TSIF2 | CFG_39_FILEIN_CTRL_TSIF2_START));
2408 break;
2409 case E_FILEENG_TSIF3:
2410 REG16_SET(&_RegCtrl2->CFG_3E, (CFG_3E_FILEIN_INIT_TRUST_TSIF3 | CFG_3E_FILEIN_CTRL_TSIF3_START));
2411 break;
2412 default:
2413 break;
2414 }
2415 }
2416
HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng,MS_BOOL bEn)2417 void HAL_TSP_Filein_Abort(FILEENG_SEQ eFileEng, MS_BOOL bEn)
2418 {
2419 if(bEn)
2420 {
2421 switch(eFileEng)
2422 {
2423 case E_FILEENG_TSIF0:
2424 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
2425 break;
2426 case E_FILEENG_TSIF1:
2427 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
2428 break;
2429 case E_FILEENG_TSIF2:
2430 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
2431 break;
2432 case E_FILEENG_TSIF3:
2433 REG16_SET(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3);
2434 break;
2435 default:
2436 break;
2437 }
2438 }
2439 else
2440 {
2441 switch(eFileEng)
2442 {
2443 case E_FILEENG_TSIF0:
2444 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF0);
2445 break;
2446 case E_FILEENG_TSIF1:
2447 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF1);
2448 break;
2449 case E_FILEENG_TSIF2:
2450 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF2);
2451 break;
2452 case E_FILEENG_TSIF3:
2453 REG16_CLR(&_RegCtrl2->CFG_04, CFG_04_TSP_FILEIN_ABORT_ECO_TSIF3);
2454 break;
2455 default:
2456 break;
2457 }
2458 }
2459 }
2460
HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)2461 void HAL_TSP_Filein_CmdQRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
2462 {
2463 if(bEnable)
2464 {
2465 switch(eFileEng)
2466 {
2467 case E_FILEENG_TSIF0:
2468 REG16_SET(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
2469 break;
2470 case E_FILEENG_TSIF1:
2471 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
2472 break;
2473 case E_FILEENG_TSIF2:
2474 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
2475 break;
2476 case E_FILEENG_TSIF3:
2477 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
2478 break;
2479 default:
2480 break;
2481 }
2482 }
2483 else
2484 {
2485 switch(eFileEng)
2486 {
2487 case E_FILEENG_TSIF0:
2488 REG16_CLR(&_RegCtrl->TSP_Ctrl1, TSP_CTRL1_CMDQ_RESET);
2489 break;
2490 case E_FILEENG_TSIF1:
2491 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_RST_CMDQ_FILEIN_TSIF1);
2492 break;
2493 case E_FILEENG_TSIF2:
2494 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_RST_CMDQ_FILEIN_TSIF2);
2495 break;
2496 case E_FILEENG_TSIF3:
2497 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_RST_CMDQ_FILEIN_TSIF3);
2498 break;
2499 default:
2500 break;
2501 }
2502 }
2503 }
2504
HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)2505 MS_U32 HAL_TSP_Filein_CmdQSlot(FILEENG_SEQ eFileEng)
2506 {
2507 switch(eFileEng)
2508 {
2509 case E_FILEENG_TSIF0:
2510 return (TSP_CMDQ_SIZE - ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT));
2511 case E_FILEENG_TSIF1:
2512 return (CFG_3F_REG_TSIF1_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT));
2513 case E_FILEENG_TSIF2:
2514 return (CFG_40_REG_TSIF2_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT));
2515 case E_FILEENG_TSIF3:
2516 return (CFG_41_REG_TSIF3_CMD_QUEUE_SIZE - (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT));
2517
2518 default:
2519 return 0;
2520 }
2521 }
2522
HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)2523 MS_U32 HAL_TSP_Filein_CmdQCnt(FILEENG_SEQ eFileEng)
2524 {
2525 switch(eFileEng)
2526 {
2527 case E_FILEENG_TSIF0:
2528 return ((REG16_R(&_RegCtrl->TsDma_mdQ) & TSP_CMDQ_CNT_MASK) >> TSP_CMDQ_CNT_SHFT);
2529 case E_FILEENG_TSIF1:
2530 return (REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_CNT);
2531 case E_FILEENG_TSIF2:
2532 return (REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_CNT);
2533 case E_FILEENG_TSIF3:
2534 return (REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_CNT);
2535 default:
2536 return 0;
2537 }
2538 }
2539
HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)2540 MS_U32 HAL_TSP_Filein_CmdQLv(FILEENG_SEQ eFileEng)
2541 {
2542 switch(eFileEng)
2543 {
2544 case E_FILEENG_TSIF0:
2545 return ((REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_CMDQ_WR_LEVEL_MASK) >> TSP_CMDQ_WR_LEVEL_SHFT);
2546 case E_FILEENG_TSIF1:
2547 return ((REG16_R(&_RegCtrl2->CFG_3F) & CFG_3F_REG_TSIF1_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2548 case E_FILEENG_TSIF2:
2549 return ((REG16_R(&_RegCtrl2->CFG_40) & CFG_40_REG_TSIF2_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2550 case E_FILEENG_TSIF3:
2551 return ((REG16_R(&_RegCtrl2->CFG_41) & CFG_41_REG_TSIF3_CMD_QUEUE_WR_LEVEL) >> CFG_3F_REG_TSIF1_CMD_QUEUE_LEVEL_SHIFT);
2552 default:
2553 return 0;
2554 }
2555 }
2556
HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng,MS_U32 delay,MS_BOOL bEnable)2557 void HAL_TSP_Filein_ByteDelay(FILEENG_SEQ eFileEng, MS_U32 delay, MS_BOOL bEnable)
2558 {
2559 if(bEnable)
2560 {
2561 switch(eFileEng)
2562 {
2563 case E_FILEENG_TSIF0:
2564 REG32_W(&_RegCtrl->TsFileIn_Timer, delay & TSP_FILE_TIMER_MASK);
2565 REG16_SET(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
2566 break;
2567 case E_FILEENG_TSIF1:
2568 REG16_W(&_RegCtrl2->CFG_03, delay & CFG_03_TSP_FILE_TIMER1);
2569 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
2570 break;
2571 case E_FILEENG_TSIF2:
2572 REG16_W(&_RegCtrl2->CFG_08, delay & CFG_08_TSP_FILE_TIMER2);
2573 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
2574 break;
2575 case E_FILEENG_TSIF3:
2576 REG16_W(&_RegCtrl2->CFG_0D, delay & CFG_0D_TSP_FILE_TIMER3);
2577 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3);
2578 break;
2579 default:
2580 break;
2581 }
2582 }
2583 else
2584 {
2585 switch(eFileEng)
2586 {
2587 case E_FILEENG_TSIF0:
2588 REG16_CLR(&_RegCtrl->reg15b4, TSP_FILEIN_BYTETIMER_ENABLE);
2589 REG32_W(&_RegCtrl->TsFileIn_Timer, 0x0000);
2590 break;
2591 case E_FILEENG_TSIF1:
2592 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_TIMER_EN1);
2593 REG16_W(&_RegCtrl2->CFG_03, 0x0000);
2594 break;
2595 case E_FILEENG_TSIF2:
2596 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_TIMER_EN2);
2597 REG16_W(&_RegCtrl2->CFG_08, 0x0000);
2598 break;
2599 case E_FILEENG_TSIF3:
2600 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_TIMER_EN3);
2601 REG16_W(&_RegCtrl2->CFG_0D, 0x0000);
2602 break;
2603 default:
2604 break;
2605 }
2606 }
2607 }
2608
HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)2609 MS_U32 HAL_TSP_Filein_Status(FILEENG_SEQ eFileEng)
2610 {
2611 switch(eFileEng)
2612 {
2613 case E_FILEENG_TSIF0:
2614 return !(REG16_R(&_RegCtrl->TsDma_Ctrl) & TSP_TSDMA_FILEIN_DONE);
2615 case E_FILEENG_TSIF1:
2616 return !(REG16_R(&_RegCtrl2->CFG_34) & CFG_34_REG_TSP_FILEIN_CTRL_TSIF1_DONE);
2617 case E_FILEENG_TSIF2:
2618 return !(REG16_R(&_RegCtrl2->CFG_39) & CFG_39_FILEIN_CTRL_TSIF2_DONE);
2619 case E_FILEENG_TSIF3:
2620 return !(REG16_R(&_RegCtrl2->CFG_3E) & CFG_3E_FILEIN_CTRL_TSIF3_DONE);
2621 default:
2622 return 0;
2623 }
2624 }
2625
2626 // Only used by [HW test code]
2627 /*
2628 MS_BOOL HAL_TSP_Filein_Done_Status(FILEENG_SEQ eFileEng)
2629 {
2630 return !HAL_TSP_Filein_Status(eFileEng);
2631 }
2632 */
2633
2634 //To do : only tsif0 has pause functionality in Kaiser
HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)2635 TSP_HAL_FileState HAL_TSP_Filein_GetState(FILEENG_SEQ eFileEng)
2636 {
2637 TSP_HAL_FileState state = E_TSP_HAL_FILE_STATE_INVALID;
2638 MS_U32 u32Status = HAL_TSP_Filein_Status(eFileEng);
2639
2640 // @FIXME in kaiser u01 only tsif0 file eng has pause function
2641 switch (eFileEng)
2642 {
2643 case E_FILEENG_TSIF0:
2644 if (REG16_R(&_RegCtrl->TSP_Ctrl1) & TSP_CTRL1_FILEIN_PAUSE )
2645 {
2646 state = E_TSP_HAL_FILE_STATE_PAUSE;
2647 }
2648 else if (u32Status)
2649 {
2650 state = E_TSP_HAL_FILE_STATE_BUSY;
2651 }
2652 else
2653 {
2654 state = E_TSP_HAL_FILE_STATE_IDLE;
2655 }
2656 break;
2657 case E_FILEENG_TSIF1:
2658 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF1_FILE_PAUSE)
2659 {
2660 state = E_TSP_HAL_FILE_STATE_PAUSE;
2661 }
2662 else if (u32Status)
2663 {
2664 state = E_TSP_HAL_FILE_STATE_BUSY;
2665 }
2666 else
2667 {
2668 state = E_TSP_HAL_FILE_STATE_IDLE;
2669 }
2670 break;
2671 case E_FILEENG_TSIF2:
2672 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF2_FILE_PAUSE)
2673 {
2674 state = E_TSP_HAL_FILE_STATE_PAUSE;
2675 }
2676 else if (u32Status)
2677 {
2678 state = E_TSP_HAL_FILE_STATE_BUSY;
2679 }
2680 else
2681 {
2682 state = E_TSP_HAL_FILE_STATE_IDLE;
2683 }
2684 break;
2685 case E_FILEENG_TSIF3:
2686 if (REG16_R(&_RegCtrl3->CFG3_21) & CFG3_21_TSIF3_FILE_PAUSE)
2687 {
2688 state = E_TSP_HAL_FILE_STATE_PAUSE;
2689 }
2690 else if (u32Status)
2691 {
2692 state = E_TSP_HAL_FILE_STATE_BUSY;
2693 }
2694 else
2695 {
2696 state = E_TSP_HAL_FILE_STATE_IDLE;
2697 }
2698 break;
2699 default:
2700 state = E_TSP_HAL_FILE_STATE_INVALID;
2701 break;
2702 }
2703 return state;
2704 }
2705
HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)2706 void HAL_TSP_Filein_PacketMode(FILEENG_SEQ eFileEng,MS_BOOL bSet)
2707 {
2708 if(bSet)
2709 {
2710 switch(eFileEng)
2711 {
2712 case E_FILEENG_TSIF0:
2713 REG16_SET(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
2714 break;
2715 case E_FILEENG_TSIF1:
2716 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
2717 break;
2718 case E_FILEENG_TSIF2:
2719 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
2720 break;
2721 case E_FILEENG_TSIF3:
2722 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3);
2723 break;
2724 default:
2725 break;
2726 }
2727 }
2728 else
2729 {
2730 switch(eFileEng)
2731 {
2732 case E_FILEENG_TSIF0:
2733 REG16_CLR(&_RegCtrl->reg160C, TSP_FILEIN192_EN);
2734 break;
2735 case E_FILEENG_TSIF1:
2736 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_EN1);
2737 break;
2738 case E_FILEENG_TSIF2:
2739 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_EN2);
2740 break;
2741 case E_FILEENG_TSIF3:
2742 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_EN3);
2743 break;
2744 default:
2745 break;
2746 }
2747 }
2748
2749 }
2750
HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng,MS_BOOL bEn)2751 void HAL_TSP_Filein_BlockTimeStamp(FILEENG_SEQ eFileEng, MS_BOOL bEn)
2752 {
2753 if(bEn)
2754 {
2755 switch(eFileEng)
2756 {
2757 case E_FILEENG_TSIF0:
2758 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
2759 break;
2760 case E_FILEENG_TSIF1:
2761 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
2762 break;
2763 case E_FILEENG_TSIF2:
2764 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
2765 break;
2766 case E_FILEENG_TSIF3:
2767 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3);
2768 default:
2769 break;
2770 }
2771 }
2772 else
2773 {
2774 switch(eFileEng)
2775 {
2776 case E_FILEENG_TSIF0:
2777 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_PKT192_BLK_DIS_FIN);
2778 break;
2779 case E_FILEENG_TSIF1:
2780 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_PKT192_BLK_DISABLE1);
2781 break;
2782 case E_FILEENG_TSIF2:
2783 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_TSP_PKT192_BLK_DISABLE2);
2784 break;
2785 case E_FILEENG_TSIF3:
2786 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_PKT192_BLK_DISABLE3);
2787 break;
2788 default:
2789 break;
2790 }
2791 }
2792 }
2793
_HAL_TSP_FILEIN_ResetPktTimeStamp(FILEENG_SEQ eFileEng,MS_U32 u32InitTimeStamp)2794 static void _HAL_TSP_FILEIN_ResetPktTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32InitTimeStamp)
2795 {
2796 switch(eFileEng)
2797 {
2798 case E_FILEENG_TSIF0:
2799 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
2800 REG32_W(&_RegCtrl6->CFG6_50_51, u32InitTimeStamp);
2801 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_0);
2802 break;
2803 case E_FILEENG_TSIF1:
2804 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
2805 REG32_W(&_RegCtrl6->CFG6_52_53, u32InitTimeStamp);
2806 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_1);
2807 break;
2808 case E_FILEENG_TSIF2:
2809 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
2810 REG32_W(&_RegCtrl6->CFG6_54_55, u32InitTimeStamp);
2811 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_2);
2812 break;
2813 case E_FILEENG_TSIF3:
2814 REG16_SET(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_3);
2815 REG32_W(&_RegCtrl6->CFG6_56_57, u32InitTimeStamp);
2816 REG16_CLR(&_RegCtrl3->CFG3_17, CFG3_17_INIT_TIMESTAMP_TSIF_3);
2817 break;
2818 default:
2819 break;
2820 }
2821 }
2822
HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng,MS_U32 u32Stamp)2823 void HAL_TSP_Filein_SetTimeStamp(FILEENG_SEQ eFileEng, MS_U32 u32Stamp)
2824 {
2825 switch(eFileEng)
2826 {
2827 case E_FILEENG_TSIF0:
2828 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
2829 REG32_W(&_RegCtrl->LPcr2, u32Stamp);
2830 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_WLD);
2831 break;
2832 case E_FILEENG_TSIF1:
2833 REG16_SET(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
2834 REG32_W(&_RegCtrl2->CFG_50_51, u32Stamp);
2835 REG16_CLR(&_RegCtrl2->CFG_01, CFG_01_LPCR2_WLD1);
2836 break;
2837 case E_FILEENG_TSIF2:
2838 REG16_SET(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
2839 REG32_W(&_RegCtrl2->CFG_52_53, u32Stamp);
2840 REG16_CLR(&_RegCtrl2->CFG_06, CFG_06_LPCR2_WLD2);
2841 break;
2842 case E_FILEENG_TSIF3:
2843 REG16_SET(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3);
2844 REG32_W(&_RegCtrl2->CFG_54_55, u32Stamp);
2845 REG16_CLR(&_RegCtrl2->CFG_0B, CFG_0B_LPCR2_WLD3);
2846 break;
2847 default:
2848 break;
2849 }
2850
2851 _HAL_TSP_FILEIN_ResetPktTimeStamp(eFileEng, 0);
2852 }
2853
HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng,TSP_HAL_TimeStamp_Clk eTimeStampClk)2854 void HAL_TSP_Filein_SetTimeStampClk(FILEENG_SEQ eFileEng, TSP_HAL_TimeStamp_Clk eTimeStampClk)
2855 {
2856 switch(eFileEng)
2857 {
2858 case E_FILEENG_TSIF0:
2859 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2860 {
2861 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
2862 }
2863 else
2864 {
2865 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF0_C27M);
2866 }
2867 break;
2868 case E_FILEENG_TSIF1:
2869 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2870 {
2871 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
2872 }
2873 else
2874 {
2875 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF1_C27M);
2876 }
2877 break;
2878 case E_FILEENG_TSIF2:
2879 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2880 {
2881 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
2882 }
2883 else
2884 {
2885 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF2_C27M);
2886 }
2887 break;
2888 case E_FILEENG_TSIF3:
2889 if(eTimeStampClk==E_TSP_HAL_TIMESTAMP_CLK_27M)
2890 {
2891 REG16_SET(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF3_C27M);
2892 }
2893 else
2894 {
2895 REG16_CLR(&_RegCtrl3->CFG3_0F, CFG3_0F_TSIF3_C27M);
2896 }
2897 break;
2898 default:
2899 break;
2900 }
2901 }
2902
HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)2903 MS_U32 HAL_TSP_Filein_GetTimeStamp(FILEENG_SEQ eFileEng)
2904 {
2905 MS_U32 u32Stamp = 0;
2906 switch(eFileEng)
2907 {
2908 case E_FILEENG_TSIF0:
2909 REG16_CLR(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
2910 u32Stamp = REG32_R(&_RegCtrl->LPcr2);
2911 REG16_SET(&_RegCtrl->reg160C, TSP_LPCR2_RLD);
2912 break;
2913 case E_FILEENG_TSIF1:
2914 REG16_CLR(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
2915 u32Stamp = REG32_R(&_RegCtrl2->CFG_50_51);
2916 REG16_SET(&_RegCtrl2->CFG_00, CFG_00_LPCR2_LOAD_TSIF1);
2917 break;
2918 case E_FILEENG_TSIF2:
2919 REG16_CLR(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
2920 u32Stamp = REG32_R(&_RegCtrl2->CFG_52_53);
2921 REG16_SET(&_RegCtrl2->CFG_05, CFG_05_LPCR2_LOAD_TSIF2);
2922 break;
2923 case E_FILEENG_TSIF3:
2924 REG16_CLR(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3);
2925 u32Stamp = REG32_R(&_RegCtrl2->CFG_54_55);
2926 REG16_SET(&_RegCtrl2->CFG_0A, CFG_0A_LPCR2_LOAD_TSIF3);
2927 break;
2928 default:
2929 u32Stamp = 0;
2930 break;
2931 }
2932 return u32Stamp;
2933 }
2934
HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)2935 MS_U32 HAL_TSP_Filein_PktTimeStamp(FILEENG_SEQ eFileEng)
2936 {
2937 switch(eFileEng)
2938 {
2939 case E_FILEENG_TSIF0:
2940 return REG32_R(&_RegCtrl->TimeStamp_FileIn);
2941 case E_FILEENG_TSIF1:
2942 return REG32_R(&_RegCtrl2->CFG_42_43);
2943 case E_FILEENG_TSIF2:
2944 return REG32_R(&_RegCtrl2->CFG_44_45);
2945 case E_FILEENG_TSIF3:
2946 return REG32_R(&_RegCtrl2->CFG_46_47);
2947 default:
2948 break;
2949 }
2950 return 0;
2951 }
2952
HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng,MS_PHY * pu32Addr)2953 void HAL_TSP_Filein_GetCurAddr(FILEENG_SEQ eFileEng, MS_PHY *pu32Addr)
2954 {
2955 switch(eFileEng)
2956 {
2957 case E_FILEENG_TSIF0:
2958 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl->TsFileIn_RPtr) & TSP_FILE_RPTR_MASK);
2959 break;
2960 case E_FILEENG_TSIF1:
2961 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6A_6B) & CFG_6A_6B_TSP2MI_RADDR_S_TSIF1);
2962 break;
2963 case E_FILEENG_TSIF2:
2964 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6C_6D) & CFG_6C_6D_TSP2MI_RADDR_S_TSIF2);
2965 break;
2966 case E_FILEENG_TSIF3:
2967 *pu32Addr = (MS_PHY)(REG32_R(&_RegCtrl2->CFG_6E_6F) & CFG_6E_6F_TSP2MI_RADDR_S_TSIF3);
2968 break;
2969 default:
2970 break;
2971 }
2972
2973 }
2974
HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng,MS_BOOL bEnable)2975 void HAL_TSP_Filein_WbFsmRst(FILEENG_SEQ eFileEng, MS_BOOL bEnable)
2976 {
2977 if(bEnable)
2978 {
2979 switch(eFileEng)
2980 {
2981 case E_FILEENG_TSIF0:
2982 REG16_SET(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_RESET);
2983 break;
2984 case E_FILEENG_TSIF1:
2985 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
2986 break;
2987 case E_FILEENG_TSIF2:
2988 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
2989 break;
2990 case E_FILEENG_TSIF3:
2991 REG16_SET(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3);
2992 break;
2993 default:
2994 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
2995 break;
2996 }
2997 }
2998 else
2999 {
3000 switch(eFileEng)
3001 {
3002 case E_FILEENG_TSIF0:
3003 REG16_CLR(&_RegCtrl3->CFG3_53, CFG3_53_WB_FSM_RESET);
3004 break;
3005 case E_FILEENG_TSIF1:
3006 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF1);
3007 break;
3008 case E_FILEENG_TSIF2:
3009 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF2);
3010 break;
3011 case E_FILEENG_TSIF3:
3012 REG16_CLR(&_RegCtrl6->CFG6_2B, TSP_RESET_WB_DMA_FSM_TSIF3);
3013 break;
3014 default:
3015 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupported File Eng: %uld !\n",__FILE__,__FUNCTION__,__LINE__,(MS_U32)eFileEng));
3016 break;
3017 }
3018 }
3019 }
3020
3021
HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng,MS_BOOL bEnable,MS_U32 u32Key)3022 void HAL_TSP_Filein_MOBF_Enable(FILEENG_SEQ eFileEng, MS_BOOL bEnable, MS_U32 u32Key)
3023 {
3024 if(bEnable)
3025 {
3026 switch(eFileEng)
3027 {
3028 case E_FILEENG_TSIF0:
3029 REG16_W(&_RegCtrl->Mobf_Filein_Idx, (u32Key & TSP_MOBF_FILEIN_MASK));
3030 break;
3031 case E_FILEENG_TSIF1:
3032 REG16_W(&_RegCtrl2->CFG_75, (u32Key & CFG_75_FI_MOBF_INDEC_TSIF1_MASK));
3033 break;
3034 case E_FILEENG_TSIF2:
3035 REG16_W(&_RegCtrl2->CFG_76, (u32Key & CFG_76_FI_MOBF_INDEC_TSIF2_MASK));
3036 break;
3037 case E_FILEENG_TSIF3:
3038 REG16_W(&_RegCtrl2->CFG_77, (u32Key & CFG_77_FI_MOBF_INDEC_TSIF3_MASK));
3039 break;
3040 default:
3041 break;
3042 }
3043 }
3044 else
3045 {
3046 switch(eFileEng)
3047 {
3048 case E_FILEENG_TSIF0:
3049 REG16_W(&_RegCtrl->Mobf_Filein_Idx, 0);
3050 break;
3051 case E_FILEENG_TSIF1:
3052 REG16_W(&_RegCtrl2->CFG_75, 0);
3053 break;
3054 case E_FILEENG_TSIF2:
3055 REG16_W(&_RegCtrl2->CFG_76, 0);
3056 break;
3057 case E_FILEENG_TSIF3:
3058 REG16_W(&_RegCtrl2->CFG_77, 0);
3059 break;
3060 default:
3061 break;
3062 }
3063 }
3064 }
3065
HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)3066 MS_U32 HAL_TSP_FltSrc2PktDmx_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
3067 {
3068 switch (ePidFltSrc)
3069 {
3070 case E_TSP_PIDFLT_LIVE0:
3071 return TSP_PIDFLT_TSIF0;
3072 case E_TSP_PIDFLT_LIVE1:
3073 return TSP_PIDFLT_TSIF2;
3074 case E_TSP_PIDFLT_LIVE2:
3075 return TSP_PIDFLT_TSIF3;
3076 case E_TSP_PIDFLT_LIVE3:
3077 return TSP_PIDFLT_TSIF1;
3078 case E_TSP_PIDFLT_FILE0:
3079 return TSP_PIDFLT_TSIF1;
3080 case E_TSP_PIDFLT_FILE1:
3081 return TSP_PIDFLT_TSIF3;
3082 case E_TSP_PIDFLT_FILE2:
3083 return TSP_PIDFLT_TSIF0;
3084 case E_TSP_PIDFLT_FILE3:
3085 return TSP_PIDFLT_TSIF2;
3086 default:
3087 printf("[TSP_ERR][%s][%d] Wrong filter source!!!\n",__FUNCTION__, __LINE__);
3088 break;
3089 }
3090
3091 return 0;
3092 }
3093
HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId,MS_U32 u32FltIn)3094 void HAL_TSP_PidFlt_SetFltIn(MS_U32 fltId, MS_U32 u32FltIn)
3095 {
3096 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
3097 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_IN_MASK) | ((u32FltIn << TSP_PIDFLT_TSIF_SHFT) & TSP_PIDFLT_IN_MASK));
3098 }
3099
HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId,MS_U32 u32FltOut)3100 void HAL_TSP_PidFlt_SetFltOut(MS_U32 fltId, MS_U32 u32FltOut)
3101 {
3102 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3103 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_OUT_MASK)) | (u32FltOut & TSP_PIDFLT_OUT_MASK)));
3104 }
3105
HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId,MS_U32 u32SrcID)3106 void HAL_TSP_PidFlt_SetSrcID(MS_U32 fltId, MS_U32 u32SrcID)
3107 {
3108 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3109 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcID << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
3110 }
3111
HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId,MS_U32 u32SecFltId)3112 void HAL_TSP_PidFlt_SetSecFlt(MS_U32 fltId, MS_U32 u32SecFltId)
3113 {
3114 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3115 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_SECFLT_MASK) | ((u32SecFltId << TSP_PIDFLT_SECFLT_SHFT) & TSP_PIDFLT_SECFLT_MASK));
3116 }
3117
HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId,MS_U32 u32PVREng,MS_BOOL bEn)3118 void HAL_TSP_PidFlt_SetPvrFlt(MS_U32 fltId, MS_U32 u32PVREng, MS_BOOL bEn)
3119 {
3120 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3121 if(bEn)
3122 {
3123 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK) | (((1 << u32PVREng) << TSP_PIDFLT_PVRFLT_SHFT) & TSP_PIDFLT_PVRFLT_MASK));
3124 }
3125 else
3126 {
3127 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PVRFLT_MASK));
3128 }
3129 }
3130
HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId,MS_U8 u8Enable)3131 void HAL_TSP_PidFlt_SetFltRushPass(MS_U32 fltId, MS_U8 u8Enable)
3132 {
3133 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
3134 if(u8Enable)
3135 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) | (TSP_PID_FLT_PKTPUSH_PASS));
3136 else
3137 TSP32_IdrW( pPidFlt, TSP32_IdrR(pPidFlt) & ~(TSP_PID_FLT_PKTPUSH_PASS));
3138 }
3139
HAL_TSP_PidFlt_SetPid(MS_U32 fltId,MS_U32 u32Pid)3140 void HAL_TSP_PidFlt_SetPid(MS_U32 fltId, MS_U32 u32Pid)
3141 {
3142 REG_PidFlt *pPidFlt = PPIDFLT0(fltId);
3143 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_PID_MASK) | ((u32Pid << TSP_PIDFLT_PID_SHFT) & TSP_PIDFLT_PID_MASK));
3144 }
3145
3146 //-------------------------------------------------------------------------------------------------
3147 // For section filter part
3148 //-------------------------------------------------------------------------------------------------
3149
HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)3150 void HAL_TSP_SecFlt_BurstLen(MS_U32 burstMode)
3151 {
3152 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SEC_DMA_BURST_EN);
3153 REG16_MSK_W(&_RegCtrl->Hw_Config4, TSP_HW_DMA_MODE_MASK, (burstMode << TSP_HW_DMA_MODE_SHIFT));
3154 }
3155
HAL_TSP_SecFlt_SetType(REG_SecFlt * pSecFlt,MS_U32 u32FltType)3156 void HAL_TSP_SecFlt_SetType(REG_SecFlt *pSecFlt, MS_U32 u32FltType)
3157 {
3158 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_USER_MASK) | (u32FltType << TSP_SECFLT_USER_SHFT));
3159 }
3160
3161
HAL_TSP_SecFlt_SetMode(REG_SecFlt * pSecFlt,MS_U32 u32SecFltMode)3162 void HAL_TSP_SecFlt_SetMode(REG_SecFlt *pSecFlt, MS_U32 u32SecFltMode)
3163 {
3164 TSP32_IdrW(&pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_MASK) | ((u32SecFltMode << TSP_SECFLT_MODE_SHFT) & TSP_SECFLT_MODE_MASK));
3165 }
3166
3167
3168 // match mask --> 0 will compare
HAL_TSP_SecFlt_SetMask(REG_SecFlt * pSecFlt,MS_U8 * pu8Mask)3169 void HAL_TSP_SecFlt_SetMask(REG_SecFlt *pSecFlt, MS_U8 *pu8Mask)
3170 {
3171 MS_U32 i,j;
3172 MS_U32 u32Temp;
3173
3174 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3175 {
3176 j = (i<< 2);
3177 u32Temp = (pu8Mask[j]) | (pu8Mask[j+ 1] << 8 ) | (pu8Mask[j+ 2] << 16 )| (pu8Mask[j+ 3] << 24);
3178 TSP32_IdrW((TSP32 *)&pSecFlt->Mask[i], u32Temp);
3179 }
3180 }
3181
3182
3183 // not match mask --> 1 will compare
HAL_TSP_SecFlt_SetNMask(REG_SecFlt * pSecFlt,MS_U8 * pu8NMask)3184 void HAL_TSP_SecFlt_SetNMask(REG_SecFlt *pSecFlt, MS_U8 *pu8NMask)
3185 {
3186 MS_U32 i,j;
3187 MS_U32 u32Temp;
3188
3189 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3190 {
3191 j = (i<< 2);
3192 u32Temp = (pu8NMask[j]) | (pu8NMask[j+ 1] << 8 ) | (pu8NMask[j+ 2] << 16 )| (pu8NMask[j+ 3] << 24);
3193 TSP32_IdrW((TSP32 *)&pSecFlt->NMask[i], u32Temp);
3194 }
3195 }
3196
3197
HAL_TSP_SecFlt_SetMatch(REG_SecFlt * pSecFlt,MS_U8 * pu8Match)3198 void HAL_TSP_SecFlt_SetMatch(REG_SecFlt *pSecFlt, MS_U8 *pu8Match)
3199 {
3200 MS_U32 i,j;
3201 MS_U32 u32Temp;
3202
3203 for (i = 0; i < (TSP_FILTER_DEPTH/sizeof(MS_U32)); i++)
3204 {
3205 j = (i<< 2);
3206 u32Temp = (pu8Match[j]) | (pu8Match[j+ 1] << 8 ) | (pu8Match[j+ 2] << 16 )| (pu8Match[j+ 3] << 24);
3207 TSP32_IdrW((TSP32 *)&pSecFlt->Match[i], u32Temp);
3208 }
3209 }
3210
3211
3212 //[LIMIT] Is impossible to identify the pidfilter is assigned a secfilter/buffer or not
HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt * pSecFlt,MS_U16 u16BufId)3213 void HAL_TSP_SecFlt_SelSecBuf(REG_SecFlt *pSecFlt, MS_U16 u16BufId)
3214 {
3215 TSP32_IdrW( &pSecFlt->Ctrl, (TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_SECBUF_MASK)
3216 | ((u16BufId << TSP_SECFLT_SECBUF_SHFT) & TSP_SECFLT_SECBUF_MASK) );
3217 }
3218
3219
HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt * pSecFlt)3220 MS_U16 HAL_TSP_SecFlt_GetSecBuf(REG_SecFlt *pSecFlt)
3221 {
3222 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_SECBUF_MASK) >> TSP_SECFLT_SECBUF_SHFT);
3223 }
3224
HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt * pPidFlt)3225 MS_U32 HAL_TSP_PidFlt_GetFltOutput(REG_PidFlt *pPidFlt)
3226 {
3227 return (TSP32_IdrR(pPidFlt) & TSP_PIDFLT_OUT_MASK);
3228 }
3229
HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)3230 void HAL_TSP_SecFlt_DropEnable(MS_BOOL bSet)
3231 {
3232 // don't have to implement no reference
3233 }
3234
3235
3236 // @FIXME: Is it secflt or secbuf?
HAL_TSP_SecFlt_ResetState(REG_SecFlt * pSecFlt)3237 void HAL_TSP_SecFlt_ResetState(REG_SecFlt* pSecFlt)
3238 {
3239 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~(TSP_SECFLT_STATE_MASK));
3240 }
3241
3242
HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt * pSecFlt)3243 void HAL_TSP_SecFlt_ClrCtrl(REG_SecFlt *pSecFlt)
3244 {
3245 TSP32_IdrW(&pSecFlt->Ctrl, 0);
3246 }
3247
HAL_TSP_SecFlt_GetState(REG_SecFlt * pSecFlt)3248 MS_U32 HAL_TSP_SecFlt_GetState(REG_SecFlt *pSecFlt)
3249 {
3250 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_STATE_MASK) >> TSP_SECFLT_STATE_SHFT);
3251 }
3252
3253
HAL_TSP_SecFlt_GetMode(REG_SecFlt * pSecFlt)3254 MS_U32 HAL_TSP_SecFlt_GetMode(REG_SecFlt *pSecFlt)
3255 {
3256 return ((TSP32_IdrR(&pSecFlt->Ctrl) & TSP_SECFLT_MODE_MASK) >> TSP_SECFLT_MODE_SHFT);
3257 }
3258
3259
HAL_TSP_SecFlt_PcrReset(REG_SecFlt * pSecFlt)3260 void HAL_TSP_SecFlt_PcrReset(REG_SecFlt *pSecFlt)
3261 {
3262 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_PCRRST);
3263 }
3264
3265
HAL_TSP_SecFlt_TryAlloc(REG_SecFlt * pSecFlt,MS_U16 u16TSPId)3266 MS_BOOL HAL_TSP_SecFlt_TryAlloc(REG_SecFlt* pSecFlt, MS_U16 u16TSPId)
3267 {
3268 MS_U32 reg;
3269
3270 //_TSP_HW_Lock();
3271
3272 // rmn counter doesn't need 32bit (check 13818) so we use some of it to store owner and alloc info
3273 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & (TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
3274 if (reg & TSP_SECFLT_ALLOC_MASK)
3275 {
3276 //_TSP_HW_Unlock();
3277 return FALSE;
3278 }
3279 reg |= TSP_SECFLT_ALLOC_MASK | ((u16TSPId<<TSP_SECFLT_OWNER_SHFT) & TSP_SECFLT_OWNER_MASK);
3280 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
3281
3282 //_TSP_HW_Unlock();
3283 return TRUE;
3284 }
3285
3286
HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt * pSecFlt,MS_BOOL bSet)3287 void HAL_TSP_SecFlt_SetAutoCRCChk(REG_SecFlt *pSecFlt, MS_BOOL bSet)
3288 {
3289 if(bSet)
3290 {
3291 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) | TSP_SECFLT_MODE_AUTO_CRCCHK);
3292 }
3293 else
3294 {
3295 TSP32_IdrW(&pSecFlt->Ctrl, TSP32_IdrR(&pSecFlt->Ctrl) & ~TSP_SECFLT_MODE_AUTO_CRCCHK);
3296 }
3297 }
3298
3299
HAL_TSP_SecFlt_Free(REG_SecFlt * pSecFlt)3300 void HAL_TSP_SecFlt_Free(REG_SecFlt* pSecFlt)
3301 {
3302 MS_U32 reg;
3303
3304 reg = TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECFLT_OWNER_MASK | TSP_SECFLT_ALLOC_MASK);
3305 TSP32_IdrW(&pSecFlt->RmnCnt, reg);
3306 }
3307
HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt * pSecFlt)3308 void HAL_TSP_SecFlt_ResetRmnCnt(REG_SecFlt* pSecFlt)
3309 {
3310 TSP32_IdrW(&pSecFlt->RmnCnt, TSP32_IdrR(&pSecFlt->RmnCnt) & ~(TSP_SECBUF_RMNCNT_MASK));
3311 }
3312
3313 //-------------------------------------------------------------------------------------------------
3314 // For section buffer part
3315 //-------------------------------------------------------------------------------------------------
HAL_TSP_SecBuf_SetBuf(REG_SecBuf * pSecBuf,MS_U32 u32StartAddr,MS_U32 u32BufSize)3316 void HAL_TSP_SecBuf_SetBuf(REG_SecBuf *pSecBuf, MS_U32 u32StartAddr, MS_U32 u32BufSize)
3317 {
3318 // Check MIU select
3319 MS_U8 u8MiuSel;
3320 MS_PHY phyMiuOffsetSecBuf;
3321 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetSecBuf, u32StartAddr);
3322 REG16_W(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW, (REG16_R(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW) & (~REG_MIU_SEL_SECTION_MASK)) | ((u8MiuSel << REG_MIU_SEL_SECTION_SHIFT) & REG_MIU_SEL_SECTION_MASK));
3323
3324 MS_U32 owner;
3325 // To avoid SW read hidden HW byte enable information.
3326 owner = TSP32_IdrR(&pSecBuf->Start); // @FIXME local variable but not used?
3327
3328 TSP32_IdrW(&pSecBuf->Start, phyMiuOffsetSecBuf);
3329 TSP32_IdrW(&pSecBuf->End, phyMiuOffsetSecBuf + u32BufSize);
3330 }
3331
3332
HAL_TSP_SecBuf_SetRead(REG_SecBuf * pSecBuf,MS_U32 u32ReadAddr)3333 void HAL_TSP_SecBuf_SetRead(REG_SecBuf *pSecBuf, MS_U32 u32ReadAddr)
3334 {
3335 TSP32_IdrW(&pSecBuf->Read, u32ReadAddr);
3336 }
3337
3338
HAL_TSP_SecBuf_GetStart(REG_SecBuf * pSecBuf)3339 MS_U32 HAL_TSP_SecBuf_GetStart(REG_SecBuf *pSecBuf)
3340 {
3341 return TSP32_IdrR(&pSecBuf->Start);
3342 }
3343
3344
HAL_TSP_SecBuf_GetEnd(REG_SecBuf * pSecBuf)3345 MS_U32 HAL_TSP_SecBuf_GetEnd(REG_SecBuf *pSecBuf)
3346 {
3347 return TSP32_IdrR(&pSecBuf->End);
3348 }
3349
3350
HAL_TSP_SecBuf_GetBufCur(REG_SecBuf * pSecBuf)3351 MS_U32 HAL_TSP_SecBuf_GetBufCur(REG_SecBuf *pSecBuf)
3352 {
3353 //BufCur is control by firmware
3354 //we use Cur pointer to receive the newest data
3355 //and use write pointer to guarantee that the data between
3356 //read and write pointer is correct, so that user won't get
3357 //unverified data.
3358 return TSP32_IdrR(&pSecBuf->Cur);
3359 }
3360
3361
HAL_TSP_SecBuf_Reset(REG_SecBuf * pSecBuf)3362 void HAL_TSP_SecBuf_Reset(REG_SecBuf *pSecBuf)
3363 {
3364 MS_U32 start;
3365
3366 start = TSP32_IdrR(&pSecBuf->Start);
3367
3368 TSP32_IdrW(&pSecBuf->Cur, start);
3369 TSP32_IdrW(&pSecBuf->Read, start);
3370 TSP32_IdrW(&pSecBuf->Write, start);
3371
3372 start = ( (MS_VIRT)pSecBuf - (MS_VIRT)REG_SECBUF_BASE ) / sizeof(REG_SecBuf) ;
3373 HAL_TSP_HCMD_BufRst(start); // @FIXME seems we don't need to do this
3374 }
3375
3376
HAL_TSP_SecBuf_GetRead(REG_SecBuf * pSecBuf)3377 MS_U32 HAL_TSP_SecBuf_GetRead(REG_SecBuf *pSecBuf)
3378 {
3379 return TSP32_IdrR((TSP32*)&pSecBuf->Read);
3380 }
3381
3382
HAL_TSP_SecBuf_GetWrite(REG_SecBuf * pSecBuf)3383 MS_U32 HAL_TSP_SecBuf_GetWrite(REG_SecBuf *pSecBuf)
3384 {
3385 return TSP32_IdrR((TSP32*)&pSecBuf->Write);
3386 }
3387
3388
HAL_TSP_SecBuf_TryAlloc(REG_SecBuf * pSecBuf,MS_U16 u16TSPId)3389 MS_BOOL HAL_TSP_SecBuf_TryAlloc(REG_SecBuf *pSecBuf, MS_U16 u16TSPId)
3390 {
3391 // @TODO make sure the owner and alloc info is necessary or not.
3392 MS_U32 reg;
3393
3394 //_TSP_HW_Lock();
3395
3396 reg = TSP32_IdrR(&pSecBuf->Start) & (TSP_SECBUF_OWNER_MASK | TSP_SECBUF_ALLOC_MASK);
3397 //if (reg & TSP_SECBUF_ALLOC_MASK)
3398 //{
3399 // //_TSP_HW_Unlock();
3400 // return FALSE;
3401 //}
3402 reg |= TSP_SECBUF_ALLOC_MASK | ((u16TSPId<<TSP_SECBUF_OWNER_SHFT) & TSP_SECBUF_OWNER_MASK);
3403 //TSP32_IdrW(&pSecBuf->Start, reg);
3404
3405 //_TSP_HW_Unlock();
3406 return TRUE;
3407 }
3408
3409
HAL_TSP_SecBuf_Free(REG_SecBuf * pSecBuf)3410 void HAL_TSP_SecBuf_Free(REG_SecBuf *pSecBuf)
3411 {
3412 // @TODO ref to HAL_TSP_SecBuf_TryAlloc
3413 TSP32_IdrW(&pSecBuf->Start, 0x0);
3414 }
3415
HAL_TSP_PidFlt_GetPid(REG_PidFlt * pPidFlt)3416 MS_U32 HAL_TSP_PidFlt_GetPid(REG_PidFlt* pPidFlt)
3417 {
3418 return ((TSP32_IdrR(pPidFlt) & TSP_PIDFLT_PID_MASK) >> TSP_PIDFLT_PID_SHFT);
3419 }
3420
HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId,MS_BOOL bEnable)3421 void HAL_TSP_PcrFlt_Enable(MS_U32 pcrFltId, MS_BOOL bEnable)
3422 {
3423 switch(pcrFltId)
3424 {
3425 case 0:
3426 if(bEnable)
3427 {
3428 REG16_SET(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
3429 }
3430 else
3431 {
3432 REG16_CLR(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_EN);
3433 }
3434 break;
3435 case 1:
3436 if(bEnable)
3437 {
3438 REG16_SET(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
3439 }
3440 else
3441 {
3442 REG16_CLR(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_EN);
3443 }
3444 break;
3445 default:
3446 break;
3447 }
3448 }
3449
HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId,MS_U32 u32Pid)3450 void HAL_TSP_PcrFlt_SetPid(MS_U32 pcrFltId, MS_U32 u32Pid)
3451 {
3452 switch(pcrFltId)
3453 {
3454 case 0:
3455 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR0, TSP_PIDFLT_PCR0_PID_MASK, u32Pid);
3456 break;
3457 case 1:
3458 REG16_MSK_W(&_RegCtrl->PIDFLT_PCR1, TSP_PIDFLT_PCR1_PID_MASK, u32Pid);
3459 break;
3460 default:
3461 break;
3462 }
3463
3464 }
3465
HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)3466 MS_U32 HAL_TSP_PcrFlt_GetPid(MS_U32 pcrFltId)
3467 {
3468 switch(pcrFltId)
3469 {
3470 case 0:
3471 return (REG16_R(&_RegCtrl->PIDFLT_PCR0) & TSP_PIDFLT_PCR0_PID_MASK);
3472 case 1:
3473 return (REG16_R(&_RegCtrl->PIDFLT_PCR1) & TSP_PIDFLT_PCR1_PID_MASK);
3474 default:
3475 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
3476 return PVR_PIDFLT_DEF;
3477 }
3478 }
3479
HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId,TSP_PCR_SRC src)3480 void HAL_TSP_PcrFlt_SetSrc(MS_U32 pcrFltId, TSP_PCR_SRC src)
3481 {
3482 switch(pcrFltId)
3483 {
3484 case 0:
3485 //src 0
3486 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR0_SRC_MASK, src << CFG_01_PCR0_SRC_SHIFT);
3487 break;
3488 case 1:
3489 //src 1
3490 REG16_MSK_W(&_RegCtrl2->CFG_01, CFG_01_PCR1_SRC_MASK, src << CFG_01_PCR1_SRC_SHIFT);
3491 break;
3492 default:
3493 break;
3494 }
3495 }
3496
HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId,TSP_PCR_SRC * pPcrSrc)3497 void HAL_TSP_PcrFlt_GetSrc(MS_U32 pcrFltId, TSP_PCR_SRC *pPcrSrc)
3498 {
3499 switch(pcrFltId)
3500 {
3501 case 0:
3502 //src 0
3503 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR0_SRC_MASK) >> CFG_01_PCR0_SRC_SHIFT;
3504 break;
3505 case 1:
3506 //src 1
3507 *pPcrSrc = (REG16_R(&_RegCtrl2->CFG_01) & CFG_01_PCR1_SRC_MASK) >> CFG_01_PCR1_SRC_SHIFT;
3508 break;
3509 default:
3510 break;
3511 }
3512 }
3513
3514
HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)3515 TSP_PCR_SRC HAL_TSP_FltSrc2PCRSrc_Mapping(TSP_PIDFLT_SRC ePidFltSrc)
3516 {
3517 TSP_PCR_SRC ePcrSrc = E_TSP_PCR_SRC_INVALID;
3518 switch(ePidFltSrc)
3519 {
3520 case E_TSP_PIDFLT_LIVE0:
3521 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
3522 break;
3523 case E_TSP_PIDFLT_LIVE1:
3524 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
3525 break;
3526 case E_TSP_PIDFLT_LIVE2:
3527 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
3528 break;
3529 case E_TSP_PIDFLT_LIVE3:
3530 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
3531 break;
3532 case E_TSP_PIDFLT_FILE0:
3533 ePcrSrc = E_TSP_PCR_SRC_TSIF1;
3534 break;
3535 case E_TSP_PIDFLT_FILE1:
3536 ePcrSrc = E_TSP_PCR_SRC_TSIF3;
3537 break;
3538 case E_TSP_PIDFLT_FILE2:
3539 ePcrSrc = E_TSP_PCR_SRC_TSIF0;
3540 break;
3541 case E_TSP_PIDFLT_FILE3:
3542 ePcrSrc = E_TSP_PCR_SRC_TSIF2;
3543 break;
3544 default:
3545 printf("[TSP_ERR][%s][%d] Wrong Flt Src type!!!\n",__FUNCTION__,__LINE__);
3546 break;
3547 }
3548 return ePcrSrc;
3549
3550 }
3551
3552
HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId,MS_U32 * pu32Pcr_H,MS_U32 * pu32Pcr)3553 void HAL_TSP_PcrFlt_GetPcr(MS_U32 pcrFltId, MS_U32 *pu32Pcr_H, MS_U32 *pu32Pcr)
3554 {
3555 switch(pcrFltId)
3556 {
3557 case 0:
3558 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
3559 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR0_L);
3560 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR0_H) & 0x1;
3561 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_READ);
3562 break;
3563 case 1:
3564 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
3565 *pu32Pcr = REG32_R(&_RegCtrl->HWPCR1_L);
3566 *pu32Pcr_H = REG32_R(&_RegCtrl->HWPCR1_H) & 0x1;
3567 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_READ);
3568 break;
3569 default:
3570 break;
3571 }
3572 }
3573
HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)3574 void HAL_TSP_PcrFlt_Reset(MS_U32 pcrFltId)
3575 {
3576 switch(pcrFltId)
3577 {
3578 case 0:
3579 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
3580 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR0_RESET);
3581 break;
3582 case 1:
3583 REG16_CLR(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
3584 REG16_SET(&_RegCtrl->PCR_Cfg, TSP_PCR1_RESET);
3585 break;
3586 default:
3587 break;
3588 }
3589 }
3590
3591
HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)3592 void HAL_TSP_PcrFlt_ClearInt(MS_U32 pcrFltId)
3593 {
3594 switch(pcrFltId)
3595 {
3596 case 0:
3597 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L,TSP_HWINT2_PCR0_UPDATE_END);
3598 REG16_W(&_RegCtrl->SwInt_Stat1_L,
3599 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) |
3600 (~TSP_HWINT2_PCR0_UPDATE_END & TSP_HWINT2_STATUS_MASK));
3601 break;
3602 case 1:
3603 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L,TSP_HWINT2_PCR1_UPDATE_END);
3604 REG16_W(&_RegCtrl->SwInt_Stat1_L,
3605 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) |
3606 (~TSP_HWINT2_PCR1_UPDATE_END & TSP_HWINT2_STATUS_MASK));
3607 break;
3608 default:
3609 break;
3610 }
3611 }
3612
HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)3613 MS_U32 HAL_TSP_PcrFlt_GetIntMask(MS_U32 pcrFltId)
3614 {
3615 switch(pcrFltId)
3616 {
3617 case 0:
3618 return (TSP_HWINT2_PCR0_UPDATE_END_EN << 8);
3619 case 1:
3620 return (TSP_HWINT2_PCR1_UPDATE_END_EN << 8);
3621 default:
3622 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[TSP ERROR][%s][%d] PCR flt id not support !!\n",__FUNCTION__,__LINE__));
3623 return 0;
3624 }
3625 }
3626
HAL_TSP_STC_Init(void)3627 void HAL_TSP_STC_Init(void)
3628 {
3629 /////////////Set STC control by HK////////////////
3630 // select synth from chip top : bit 1 -> 0 -> controlled by HK
3631 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
3632 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
3633
3634 // set HK STC synth CW
3635 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
3636 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = 0x0000;
3637 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = 0x2800;
3638 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = 0x0000;
3639 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = 0x2800;
3640
3641 // set STC synth
3642 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3643 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
3644 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3645 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3646 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
3647 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3648
3649 #if 0 // we don't use TSP CPU to control STC anymmore, so we don't have to do the following
3650 /////////////Set STC control by TSP////////////////
3651 // select synth from TSP : bit 1 -> 1 -> controlled by TSP
3652 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_SEL;
3653 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_SEL;
3654
3655 // set TSP STC synth CW
3656 //if CLK_MPLL_SYN is 432MHz, set 0x28000000;if CLK_MPLL_SYN is 216MHz, set 0x14000000
3657 TSP32_IdrW((TSP32 *)(0x0021024c<<1), 0x28000000);
3658 TSP32_IdrW((TSP32 *)(0x00210280<<1), 0x28000000); //STC1
3659
3660 // t2 , t3 had no 0x0021025c, it was add after t4, eanble synthesizer
3661 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x01);
3662 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x01);
3663 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))|0x02); //STC1
3664 TSP32_IdrW((TSP32 *)(0x0021025c<<1), TSP32_IdrR((TSP32 *)(0x0021025c<<1))& ~0x02);
3665 #endif
3666 }
3667
HAL_TSP_GetSTCSynth(MS_U32 Eng,MS_U32 * u32Sync)3668 void HAL_TSP_GetSTCSynth(MS_U32 Eng, MS_U32* u32Sync)
3669 {
3670 switch (Eng)
3671 {
3672 case 0:
3673 // get HK STC synth CW
3674 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L);
3675 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) << 16 ;
3676 break;
3677 case 1:
3678 // get HK STC synth CW
3679 *u32Sync = TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L);
3680 *u32Sync |= TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) << 16 ;
3681 break;
3682 }
3683 }
3684
HAL_TSP_SetSTCSynth(MS_U32 Eng,MS_U32 u32Sync)3685 void HAL_TSP_SetSTCSynth(MS_U32 Eng, MS_U32 u32Sync)
3686 {
3687 switch (Eng)
3688 {
3689 case 0:
3690 //set STC controller : HK or TSP CPU
3691 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC_CW_SEL;
3692
3693 // set HK STC synth CW
3694 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_L) = u32Sync & 0xFFFF;
3695 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC_CW_H) = u32Sync >> 16;
3696
3697 // set STC synth : toggle update bit
3698 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3699 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC_CW_EN;
3700 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC_CW_EN);
3701 break;
3702 case 1:
3703 //set STC controller : HK or TSP CPU
3704 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~REG_CLKGEN0_STC1_CW_SEL;
3705
3706 // set HK STC synth CW
3707 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_L) = u32Sync & 0xFFFF;
3708 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_STC1_CW_H) = u32Sync >> 16;
3709
3710 // set STC synth : toggle update bit
3711 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3712 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) |= REG_CLKGEN0_STC1_CW_EN;
3713 TSP_CLKGEN0_REG(REG_CLKGEN0_DC0_SYTNTH) &= ~(REG_CLKGEN0_STC1_CW_EN);
3714 break;
3715 }
3716 }
3717
HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)3718 void HAL_TSP_STC64_Mode_En(MS_BOOL bEnable)
3719 {
3720 if (bEnable)
3721 {
3722 REG16_SET(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
3723 }
3724 else
3725 {
3726 REG16_CLR(&_RegCtrl->TSP_Cfg5, TSP_SYSTIME_MODE);
3727 }
3728 }
3729
HAL_TSP_STC64_Set(MS_U32 Eng,MS_U32 stcH,MS_U32 stcL)3730 void HAL_TSP_STC64_Set(MS_U32 Eng, MS_U32 stcH, MS_U32 stcL)
3731 {
3732 switch (Eng)
3733 {
3734 case 0:
3735 REG32_W(&_RegCtrl->Pcr_L, stcL);
3736 REG32_W(&_RegCtrl->Pcr_H, stcH);
3737 break;
3738 case 1:
3739 REG32_W(&_RegCtrl->PCR64_2_L, stcL);
3740 REG32_W(&_RegCtrl->PCR64_2_H, stcH);
3741 break;
3742 }
3743 }
3744
HAL_TSP_STC64_Get(MS_U32 Eng,MS_U32 * pStcH,MS_U32 * pStcL)3745 void HAL_TSP_STC64_Get(MS_U32 Eng, MS_U32* pStcH, MS_U32* pStcL)
3746 {
3747 switch (Eng)
3748 {
3749 case 0:
3750 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3751 *pStcH = REG32_R(&_RegCtrl->Pcr_H);
3752 *pStcL = REG32_R(&_RegCtrl->Pcr_L);
3753 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3754 break;
3755 case 1:
3756 REG16_CLR(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
3757 *pStcH = REG32_R(&_RegCtrl->PCR64_2_H);
3758 *pStcL = REG32_R(&_RegCtrl->PCR64_2_L);
3759 REG16_SET(&_RegCtrl->reg15b8, TSP_64bit_PCR2_ld);
3760 break;
3761 }
3762 }
3763
HAL_TSP_STC33_CmdQSet(MS_U32 stcH,MS_U32 stcL)3764 void HAL_TSP_STC33_CmdQSet(MS_U32 stcH, MS_U32 stcL)
3765 {
3766 // @TODO ask designer for the difference between 64bit STC and 33 Bit STC
3767 // and it's hw limit (like: cmdQ delay)
3768 REG16_W(&_RegCtrl->Pcr_H_CmdQ, stcH & TSP_REG_PCR_CMDQ_H);
3769 REG32_W(&_RegCtrl->Pcr_L_CmdQ, stcL);
3770 }
3771
HAL_TSP_STC33_CmdQGet(MS_U32 * pStcH,MS_U32 * pStcL)3772 void HAL_TSP_STC33_CmdQGet(MS_U32* pStcH, MS_U32* pStcL)
3773 {
3774 REG16_CLR(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3775 *pStcH = REG16_R(&_RegCtrl->Pcr_H_CmdQ) & TSP_REG_PCR_CMDQ_H;
3776 *pStcL = REG32_R(&_RegCtrl->Pcr_L_CmdQ);
3777 REG16_SET(&_RegCtrl->reg15b8, TSP_cnt_33b_ld);
3778 }
3779
HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType,MS_U32 pktDmxId)3780 void HAL_TSP_FIFO_SetSrc(TSP_DST_SEQ eFltType, MS_U32 pktDmxId)
3781 {
3782 switch (eFltType)
3783 {
3784 case E_TSP_DST_FIFO_VIDEO :
3785 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID_SRC_SHIFT);
3786 break;
3787 case E_TSP_DST_FIFO_VIDEO3D :
3788 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_VID3D_SRC_MASK, ((MS_U16)pktDmxId) << TSP_VID3D_SRC_SHIFT);
3789 break;
3790 case E_TSP_DST_FIFO_AUDIO :
3791 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUD_SRC_SHIFT);
3792 break;
3793 case E_TSP_DST_FIFO_AUDIO2 :
3794 REG16_MSK_W(&_RegCtrl->FIFO_Src, TSP_AUDB_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDB_SRC_SHIFT);
3795 break;
3796 case E_TSP_DST_FIFO_AUDIO3 :
3797 REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDC_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDC_SRC_SHIFT);
3798 break;
3799 case E_TSP_DST_FIFO_AUDIO4 :
3800 REG16_MSK_W(&_RegCtrl->PCR_Cfg, TSP_AUDD_SRC_MASK, ((MS_U16)pktDmxId) << TSP_AUDD_SRC_SHIFT);
3801 break;
3802 default:
3803 break;
3804 }
3805 }
3806
HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType,TSP_SRC_SEQ * pktDmxId)3807 void HAL_TSP_FIFO_GetSrc(TSP_DST_SEQ eFltType, TSP_SRC_SEQ *pktDmxId)
3808 {
3809 switch (eFltType)
3810 {
3811 case E_TSP_DST_FIFO_VIDEO :
3812 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID_SRC_MASK) >> TSP_VID_SRC_SHIFT;
3813 break;
3814 case E_TSP_DST_FIFO_VIDEO3D:
3815 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_VID3D_SRC_MASK) >> TSP_VID3D_SRC_SHIFT;
3816 break;
3817 case E_TSP_DST_FIFO_AUDIO :
3818 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUD_SRC_MASK) >> TSP_AUD_SRC_SHIFT;
3819 break;
3820 case E_TSP_DST_FIFO_AUDIO2 :
3821 *pktDmxId = ((REG16_R(&_RegCtrl->FIFO_Src)) & TSP_AUDB_SRC_MASK) >> TSP_AUDB_SRC_SHIFT;
3822 break;
3823 case E_TSP_DST_FIFO_AUDIO3 :
3824 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDC_SRC_MASK) >> TSP_AUDC_SRC_SHIFT;
3825 break;
3826 case E_TSP_DST_FIFO_AUDIO4 :
3827 *pktDmxId = ((REG16_R(&_RegCtrl->PCR_Cfg)) & TSP_AUDD_SRC_MASK) >> TSP_AUDD_SRC_SHIFT;
3828 break;
3829 default:
3830 break;
3831 }
3832 }
3833
HAL_TSP_FIFO_ClearAll()3834 void HAL_TSP_FIFO_ClearAll()
3835 {
3836 // clear ALL FIFO !!!
3837 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
3838 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
3839 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
3840 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
3841 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
3842 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
3843
3844 }
3845
3846
HAL_TSP_FIFO_Connect(MS_BOOL bEn)3847 void HAL_TSP_FIFO_Connect(MS_BOOL bEn)
3848 {
3849 if(bEn == TRUE)
3850 {
3851 REG16_SET(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
3852 }
3853 else
3854 {
3855 REG16_CLR(&_RegCtrl->reg15b4,TSP_AVFIFO_RD_EN);
3856 }
3857
3858 }
3859
3860
HAL_TSP_FIFO_ReadPkt(void)3861 MS_U16 HAL_TSP_FIFO_ReadPkt(void)
3862 {
3863 return (REG16_R(&_RegCtrl->PKT_CNT) & TSP_PKT_CNT_MASK);
3864 }
3865
3866
3867
3868
HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)3869 void HAL_TSP_FIFO_ReadSrc(TSP_DST_SEQ eFltType)
3870 {
3871 switch (eFltType)
3872 {
3873 case E_TSP_DST_FIFO_VIDEO:
3874 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
3875 break;
3876 case E_TSP_DST_FIFO_AUDIO:
3877 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_A) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
3878 break;
3879 case E_TSP_DST_FIFO_AUDIO2:
3880 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AB) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
3881 break;
3882 case E_TSP_DST_FIFO_VIDEO3D:
3883 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_V3D) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
3884 break;
3885 case E_TSP_DST_FIFO_AUDIO3:
3886 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AC) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
3887 break;
3888 case E_TSP_DST_FIFO_AUDIO4:
3889 REG16_MSK_W(&_RegCtrl3->CFG3_2C, CFG3_2C_AVFIFO_READ_SEL_MASK, ((MS_U16)CFG3_2C_AVFIFO_READ_SEL_AD) << CFG3_2C_AVFIFO_READ_SEL_SHIFT);
3890 break;
3891 default:
3892 break;
3893 }
3894 }
3895
3896
3897
3898
3899 //@NOTE for TS mode
3900 //@TODO need to rename (TS enable or PKTDMX_BYPASS)
HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)3901 void HAL_TSP_Flt_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
3902 {
3903 if(bEn)
3904 {
3905 switch (eFltType)
3906 {
3907 case E_TSP_DST_FIFO_VIDEO:
3908 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
3909 break;
3910 case E_TSP_DST_FIFO_AUDIO:
3911 REG16_SET(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
3912 break;
3913 case E_TSP_DST_FIFO_AUDIO2:
3914 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
3915 break;
3916 case E_TSP_DST_FIFO_VIDEO3D:
3917 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
3918 break;
3919 case E_TSP_DST_FIFO_AUDIO3:
3920 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_C_BYPASS);
3921 break;
3922 case E_TSP_DST_FIFO_AUDIO4:
3923 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_D_BYPASS);
3924 break;
3925 default:
3926 break;
3927 }
3928 }
3929 else
3930 {
3931 switch (eFltType)
3932 {
3933 case E_TSP_DST_FIFO_VIDEO:
3934 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_VPID_BYPASS);
3935 break;
3936 case E_TSP_DST_FIFO_AUDIO:
3937 REG16_CLR(&_RegCtrl->Hw_Config0, TSP_HW_CFG0_TSIF0_APID_BYPASS);
3938 break;
3939 case E_TSP_DST_FIFO_AUDIO2:
3940 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_B_BYPASS);
3941 break;
3942 case E_TSP_DST_FIFO_VIDEO3D:
3943 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_VPID_3D_BYPASS);
3944 break;
3945 case E_TSP_DST_FIFO_AUDIO3:
3946 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_C_BYPASS);
3947 break;
3948 case E_TSP_DST_FIFO_AUDIO4:
3949 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_APID_D_BYPASS);
3950 break;
3951 default:
3952 break;
3953
3954 }
3955 }
3956 }
3957
3958
HAL_TSP_PS_SRC(MS_U32 tsIf)3959 void HAL_TSP_PS_SRC(MS_U32 tsIf)
3960 {
3961 REG16_MSK_W(&_RegCtrl3->CFG3_10, CFG3_10_PS_MODE_SRC_MASK,(((MS_U16)tsIf)<< CFG3_10_PS_MODE_SRC_SHIFT));
3962 }
3963
3964
3965
3966 //PS MODE
3967 //NEED TO rename
HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType,MS_BOOL bEn)3968 void HAL_TSP_FIFO_Bypass(TSP_DST_SEQ eFltType, MS_BOOL bEn) // @NOTE this function only for Tsif0 fileEng other fileEng has no by pass capability
3969 {
3970 if(bEn)
3971 {
3972 switch (eFltType)
3973 {
3974 case E_TSP_DST_FIFO_VIDEO:
3975 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
3976 break;
3977 case E_TSP_DST_FIFO_VIDEO3D:
3978 REG16_SET(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
3979 break;
3980 case E_TSP_DST_FIFO_AUDIO:
3981 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
3982 break;
3983 case E_TSP_DST_FIFO_AUDIO2:
3984 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
3985 break;
3986 case E_TSP_DST_FIFO_AUDIO3:
3987 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
3988 break;
3989 case E_TSP_DST_FIFO_AUDIO4:
3990 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
3991 break;
3992 default:
3993 break;
3994 }
3995 }
3996 else
3997 {
3998 switch (eFltType)
3999 {
4000 case E_TSP_DST_FIFO_VIDEO :
4001 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_VID_EN);
4002 break;
4003 case E_TSP_DST_FIFO_VIDEO3D:
4004 REG16_CLR(&_RegCtrl->TSP_Ctrl2, TSP_PS_VID_3D_EN);
4005 break;
4006 case E_TSP_DST_FIFO_AUDIO :
4007 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUD_EN);
4008 break;
4009 case E_TSP_DST_FIFO_AUDIO2 :
4010 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDB_EN);
4011 break;
4012 case E_TSP_DST_FIFO_AUDIO3 :
4013 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDC_EN);
4014 break;
4015 case E_TSP_DST_FIFO_AUDIO4 :
4016 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_PS_AUDD_EN);
4017 break;
4018 default:
4019 break;
4020 }
4021 }
4022 }
4023
HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng,TSP_DST_SEQ eFltType)4024 void HAL_TSP_FIFO_Bypass_Src(FILEENG_SEQ eFileEng, TSP_DST_SEQ eFltType)
4025 {
4026 // (K6 HW CL) Kano doesn't support
4027 // PS mode source sel need to be independent
4028 }
4029
HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)4030 MS_U32 HAL_TSP_FIFO_PidHit(TSP_DST_SEQ eFltType)
4031 {
4032 switch (eFltType)
4033 {
4034 case E_TSP_DST_FIFO_VIDEO :
4035 return REG16_R(&_RegCtrl->Vd_Pid_Hit) & TSP_VPID_MASK;
4036 case E_TSP_DST_FIFO_VIDEO3D :
4037 return REG16_R(&_RegCtrl2->CFG_70) & CFG_70_MATCHECED_VPID_3D_MASK;
4038 case E_TSP_DST_FIFO_AUDIO :
4039 return REG16_R(&_RegCtrl->Aud_Pid_Hit) & TSP_APID_MASK;
4040 case E_TSP_DST_FIFO_AUDIO2 :
4041 return REG16_R(&_RegCtrl2->CFG_71) & CFG_71_MATCHECED_APID_B_MASK;
4042 case E_TSP_DST_FIFO_AUDIO3 :
4043 return REG16_R(&_RegCtrl2->CFG_74) & CFG_74_MATCHECED_APID_C_MASK;
4044 case E_TSP_DST_FIFO_AUDIO4 :
4045 return REG16_R(&_RegCtrl2->CFG_7C) & CFG_7C_MATCHECED_APID_D_MASK;
4046 default:
4047 return PVR_PIDFLT_DEF;
4048 }
4049 }
4050
HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType,MS_BOOL bReset)4051 void HAL_TSP_FIFO_Reset(TSP_DST_SEQ eFltType, MS_BOOL bReset)
4052 {
4053 if (bReset)
4054 {
4055 switch (eFltType)
4056 {
4057 case E_TSP_DST_FIFO_VIDEO :
4058 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
4059 break;
4060 case E_TSP_DST_FIFO_VIDEO3D:
4061 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
4062 break;
4063
4064 case E_TSP_DST_FIFO_AUDIO :
4065 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
4066 break;
4067 case E_TSP_DST_FIFO_AUDIO2 :
4068 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
4069 break;
4070 case E_TSP_DST_FIFO_AUDIO3 :
4071 REG16_SET(&_RegCtrl->reg160E, TSP_RESET_AFIFO3);
4072 break;
4073 case E_TSP_DST_FIFO_AUDIO4 :
4074 REG16_SET(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4);
4075 break;
4076 default :
4077 break;
4078 }
4079 }
4080 else
4081 {
4082 switch (eFltType)
4083 {
4084 case E_TSP_DST_FIFO_VIDEO :
4085 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO);
4086 break;
4087 case E_TSP_DST_FIFO_VIDEO3D:
4088 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_VFIFO3D);
4089 break;
4090
4091 case E_TSP_DST_FIFO_AUDIO :
4092 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO);
4093 break;
4094 case E_TSP_DST_FIFO_AUDIO2 :
4095 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO2);
4096 break;
4097 case E_TSP_DST_FIFO_AUDIO3 :
4098 REG16_CLR(&_RegCtrl->reg160E, TSP_RESET_AFIFO3);
4099 break;
4100 case E_TSP_DST_FIFO_AUDIO4 :
4101 REG16_CLR(&_RegCtrl->PktChkSizeFilein, TSP_RESET_AFIFO4);
4102 break;
4103 default :
4104 break;
4105 }
4106 }
4107
4108 _delay(1);
4109 }
4110
HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)4111 void HAL_TSP_FIFO_Skip_Scrmb(TSP_DST_SEQ eFltType,MS_BOOL bSkip)
4112 {
4113 if(bSkip)
4114 {
4115 switch(eFltType)
4116 {
4117 case E_TSP_DST_FIFO_VIDEO:
4118 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
4119 break;
4120 case E_TSP_DST_FIFO_VIDEO3D:
4121 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
4122 break;
4123 case E_TSP_DST_FIFO_AUDIO:
4124 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
4125 break;
4126 case E_TSP_DST_FIFO_AUDIO2:
4127 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
4128 break;
4129 case E_TSP_DST_FIFO_AUDIO3:
4130 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AC_EN);
4131 break;
4132 case E_TSP_DST_FIFO_AUDIO4:
4133 REG16_SET(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AD_EN);
4134 break;
4135 default:
4136 break;
4137 }
4138 }
4139 else
4140 {
4141 switch(eFltType)
4142 {
4143 case E_TSP_DST_FIFO_VIDEO:
4144 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V_EN);
4145 break;
4146 case E_TSP_DST_FIFO_VIDEO3D:
4147 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_V3D_EN);
4148 break;
4149 case E_TSP_DST_FIFO_AUDIO:
4150 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_A_EN);
4151 break;
4152 case E_TSP_DST_FIFO_AUDIO2:
4153 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AB_EN);
4154 break;
4155 case E_TSP_DST_FIFO_AUDIO3:
4156 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AC_EN);
4157 break;
4158 case E_TSP_DST_FIFO_AUDIO4:
4159 REG16_CLR(&_RegCtrl3->CFG3_34, CFG3_34_MASK_SRC_AD_EN);
4160 break;
4161 default:
4162 break;
4163 }
4164
4165 }
4166 }
4167
4168
HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType,MS_BOOL bDisable)4169 void HAL_TSP_FIFO_BlockDis(TSP_DST_SEQ eFltType, MS_BOOL bDisable)
4170 {
4171 if(bDisable)
4172 {
4173 switch(eFltType)
4174 {
4175 case E_TSP_DST_FIFO_VIDEO:
4176 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
4177 break;
4178 case E_TSP_DST_FIFO_VIDEO3D:
4179 REG32_SET(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
4180 break;
4181 case E_TSP_DST_FIFO_AUDIO :
4182 REG32_SET(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
4183 break;
4184 case E_TSP_DST_FIFO_AUDIO2 :
4185 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
4186 break;
4187 case E_TSP_DST_FIFO_AUDIO3 :
4188 REG32_SET(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS);
4189 break;
4190 case E_TSP_DST_FIFO_AUDIO4 :
4191 REG32_SET(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS);
4192 break;
4193 default:
4194 break;
4195 }
4196 }
4197 else
4198 {
4199 switch(eFltType)
4200 {
4201 case E_TSP_DST_FIFO_VIDEO:
4202 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V_BLOCK_DIS);
4203 break;
4204 case E_TSP_DST_FIFO_VIDEO3D:
4205 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_V3d_BLOCK_DIS);
4206 break;
4207 case E_TSP_DST_FIFO_AUDIO :
4208 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_A_BLOCK_DIS);
4209 break;
4210 case E_TSP_DST_FIFO_AUDIO2 :
4211 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AD_BLOCK_DIS);
4212 break;
4213 case E_TSP_DST_FIFO_AUDIO3 :
4214 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_AC_BLOCK_DIS);
4215 break;
4216 case E_TSP_DST_FIFO_AUDIO4 :
4217 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_ADD_BLOCK_DIS);
4218 break;
4219 default:
4220 break;
4221 }
4222 }
4223 }
4224
HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)4225 MS_BOOL HAL_TSP_FIFO_IsReset(TSP_DST_SEQ eFltType)
4226 {
4227 MS_U32 u32Matched = 0;
4228 switch (eFltType)
4229 {
4230 case E_TSP_DST_FIFO_VIDEO :
4231 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO;
4232 break;
4233 case E_TSP_DST_FIFO_VIDEO3D:
4234 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_VFIFO3D;
4235 break;
4236 case E_TSP_DST_FIFO_AUDIO :
4237 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO;
4238 break;
4239 case E_TSP_DST_FIFO_AUDIO2 :
4240 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO2;
4241 break;
4242 case E_TSP_DST_FIFO_AUDIO3 :
4243 u32Matched = REG16_R(&_RegCtrl->reg160E) & TSP_RESET_AFIFO3;
4244 break;
4245 case E_TSP_DST_FIFO_AUDIO4 :
4246 u32Matched = REG16_R(&_RegCtrl->PktChkSizeFilein) & TSP_RESET_AFIFO4;
4247 break;
4248 default :
4249 return FALSE;
4250 }
4251 return (u32Matched) ? TRUE: FALSE;
4252 }
4253
HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)4254 MS_U32 HAL_TSP_FIFO_GetStatus(TSP_DST_SEQ eFltType)
4255 {
4256 #define E_TSP_FIFO_STATUS_ISRESET 0x80000000
4257 #define E_TSP_FIFO_STATUS_EMPTY 0x00000001
4258 #define E_TSP_FIFO_STATUS_OVERFLOW 0x00000002
4259 #define E_TSP_FIFO_STATUS_LEVEL 0x0000000C
4260 #define TSP_FIFO_STATUS_LEVEL_SHFT 2 //shift the value get from HAL_TSP_FIFO_Level to the u32Status level position
4261 // @NOTE please follow K2 like series to return this value
4262 // since API layer didn't define for each column
4263 // we only defined that 0x80000000 stands for this fifo reset is High
4264 // 0x00000001 stands for this fifo is empty
4265 // 0x00000002 stands for this fifo is overflow
4266 // 0x0000000C is a mask for this fifo level
4267 // this is exclusive usage
4268 MS_U32 u32Status = 0;
4269 if (HAL_TSP_FIFO_IsReset(eFltType))
4270 {
4271 u32Status |= E_TSP_FIFO_STATUS_ISRESET;
4272 }
4273 if (HAL_TSP_FIFO_Empty(eFltType))
4274 {
4275 u32Status |= E_TSP_FIFO_STATUS_EMPTY;
4276 }
4277 if (HAL_TSP_FIFO_Overflow(eFltType))
4278 {
4279 u32Status |= E_TSP_FIFO_STATUS_OVERFLOW;
4280 }
4281
4282 u32Status |= ((HAL_TSP_FIFO_Level(eFltType)<<TSP_FIFO_STATUS_LEVEL_SHFT)&E_TSP_FIFO_STATUS_LEVEL);
4283
4284 return u32Status;
4285 }
4286
HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)4287 MS_U32 HAL_TSP_FIFO_Level(TSP_DST_SEQ eFltType)
4288 {
4289 switch (eFltType)
4290 {
4291 case E_TSP_DST_FIFO_VIDEO :
4292 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_LEVEL) >> TSP_VFIFO_LEVEL_SHFT;
4293 case E_TSP_DST_FIFO_VIDEO3D :
4294 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_LEVEL) >> TSP_VFIFO3D_LEVEL_SHFT;
4295 case E_TSP_DST_FIFO_AUDIO :
4296 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_LEVEL) >> TSP_AFIFO_LEVEL_SHFT;
4297 case E_TSP_DST_FIFO_AUDIO2 :
4298 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_LEVEL) >> TSP_AFIFOB_LEVEL_SHFT;
4299 case E_TSP_DST_FIFO_AUDIO3 :
4300 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_LEVEL) >> TSP_AFIFOC_LEVEL_SHFT;
4301 case E_TSP_DST_FIFO_AUDIO4:
4302 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_LEVEL) >> TSP_AFIFOD_LEVEL_SHFT;
4303 default :
4304 return 0;
4305 }
4306 }
4307
HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)4308 MS_BOOL HAL_TSP_FIFO_Overflow(TSP_DST_SEQ eFltType)
4309 {
4310 switch (eFltType)
4311 {
4312 case E_TSP_DST_FIFO_VIDEO :
4313 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_FULL) >> TSP_VFIFO_FULL_SHFT;
4314 case E_TSP_DST_FIFO_VIDEO3D :
4315 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_FULL) >> TSP_VFIFO3D_FULL_SHFT;
4316 case E_TSP_DST_FIFO_AUDIO :
4317 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_FULL) >> TSP_AFIFO_FULL_SHFT;
4318 case E_TSP_DST_FIFO_AUDIO2 :
4319 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_FULL) >> TSP_AFIFOB_FULL_SHFT;
4320 case E_TSP_DST_FIFO_AUDIO3 :
4321 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_FULL) >> TSP_AFIFOC_FULL_SHFT;
4322 case E_TSP_DST_FIFO_AUDIO4 :
4323 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_FULL) >> TSP_AFIFOD_FULL_SHFT;
4324 default :
4325 return FALSE;
4326 }
4327 }
4328
HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)4329 MS_BOOL HAL_TSP_FIFO_Empty(TSP_DST_SEQ eFltType)
4330 {
4331 switch (eFltType)
4332 {
4333 case E_TSP_DST_FIFO_VIDEO :
4334 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO_EMPTY) >> TSP_VFIFO_EMPTY_SHFT;
4335 case E_TSP_DST_FIFO_VIDEO3D:
4336 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_VFIFO3D_EMPTY) >> TSP_VFIFO3D_EMPTY_SHFT;
4337 case E_TSP_DST_FIFO_AUDIO :
4338 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFO_EMPTY) >> TSP_AFIFO_EMPTY_SHFT;
4339 case E_TSP_DST_FIFO_AUDIO2 :
4340 return (REG16_R(&_RegCtrl->AVFifoSts) & TSP_AFIFOB_EMPTY) >> TSP_AFIFOB_EMPTY_SHFT;
4341 case E_TSP_DST_FIFO_AUDIO3 :
4342 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOC_EMPTY) >> TSP_AFIFOC_EMPTY_SHFT;
4343 case E_TSP_DST_FIFO_AUDIO4 :
4344 return (REG16_R(&_RegCtrl3->CFG3_33) & TSP_AFIFOD_EMPTY) >> TSP_AFIFOD_EMPTY_SHFT;
4345 default :
4346 return FALSE;
4347 }
4348 }
4349
_HAL_TSP_VQ_TxConfig(MS_U32 vqId)4350 static MS_BOOL _HAL_TSP_VQ_TxConfig(MS_U32 vqId)
4351 {
4352 // reg_vq_wr_threshold = 0x8
4353 // reg_vq_forcefire_cnt_1k= 0xC
4354
4355 switch(vqId)
4356 {
4357 case 0:
4358 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ0_WR_THRESHOLD_SHIFT) & TSP_VQ0_WR_THRESHOLD_MASK));
4359 REG16_W(&_RegCtrl->VQ0_CTRL, (REG16_R(&_RegCtrl->VQ0_CTRL) & (~TSP_VQ0_FORCE_FIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ0_FORCE_FIRE_CNT_1K_SHIFT) & TSP_VQ0_FORCE_FIRE_CNT_1K_MASK));
4360 break;
4361 case 1:
4362 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ1_WR_THRESHOLD_SHIFT) & TSP_VQ1_WR_THRESHOLD_MASK));
4363 REG16_W(&_RegCtrl->VQ1_Config, (REG16_R(&_RegCtrl->VQ1_Config) & (~TSP_VQ1_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ1_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ1_FORCEFIRE_CNT_1K_MASK));
4364 break;
4365 case 2:
4366 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ2_WR_THRESHOLD_SHIFT) & TSP_VQ2_WR_THRESHOLD_MASK));
4367 REG16_W(&_RegCtrl->VQ2_Config, (REG16_R(&_RegCtrl->VQ2_Config) & (~TSP_VQ2_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ2_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ2_FORCEFIRE_CNT_1K_MASK));
4368 break;
4369 case 3:
4370 REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_WR_THRESHOLD_MASK)) | ((0x8 << TSP_VQ3_WR_THRESHOLD_SHIFT) & TSP_VQ3_WR_THRESHOLD_MASK));
4371 REG16_W(&_RegCtrl->VQ3_Config, (REG16_R(&_RegCtrl->VQ3_Config) & (~TSP_VQ3_FORCEFIRE_CNT_1K_MASK)) | ((0xC << TSP_VQ3_FORCEFIRE_CNT_1K_SHIFT) & TSP_VQ3_FORCEFIRE_CNT_1K_MASK));
4372 break;
4373 default:
4374 return FALSE;
4375 }
4376 return TRUE;
4377 }
4378
HAL_TSP_SetVQ(MS_PHYADDR u32BaseAddr,MS_U32 u32BufLen)4379 MS_BOOL HAL_TSP_SetVQ( MS_PHYADDR u32BaseAddr, MS_U32 u32BufLen)
4380 {
4381 MS_U32 vqId = 0;
4382 MS_U32 u32VQ_PktNum = 0;
4383 MS_U32 u32Addr = 0;
4384 MS_U32 u32OneBufSize = 0;
4385
4386 // Check MIU select
4387 MS_U8 u8MiuSel = 0;
4388 _phy_to_miu_offset(u8MiuSel, u32Addr, u32BaseAddr);
4389 REG16_W(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW, (REG16_R(&_RegCtrl6->CFG6_2D_REG_MIU_SEL_FW) & (~REG_MIU_SEL_VQ_MASK)) | ((u8MiuSel << REG_MIU_SEL_VQ_SHIFT) & REG_MIU_SEL_VQ_MASK));
4390
4391 u32OneBufSize = ((u32BufLen >> MIU_BUS) / VQ_NUM) << MIU_BUS; //miu alignment
4392 u32VQ_PktNum = u32OneBufSize / VQ_PACKET_UNIT_LEN;
4393
4394 for(vqId = 0; vqId < VQ_NUM; vqId ++)
4395 {
4396 if(TRUE != _HAL_TSP_VQ_TxConfig(vqId))
4397 {
4398 return FALSE;
4399 }
4400
4401 // in kaiser we needs to set 6 VQ and the base unit is 208 so total vq size should be N*208*6
4402 if (TRUE != HAL_TSP_VQ_Buffer(vqId, u32Addr, u32VQ_PktNum))
4403 {
4404 return FALSE;
4405 }
4406 u32Addr += u32OneBufSize;
4407 }
4408
4409 HAL_TSP_VQ_Enable(TRUE);
4410 return TRUE;
4411
4412 }
4413
HAL_TSP_VQ_Buffer(MS_U32 vqId,MS_PHYADDR u32BaseAddr,MS_U32 u32VQ_PktNum)4414 MS_BOOL HAL_TSP_VQ_Buffer(MS_U32 vqId, MS_PHYADDR u32BaseAddr, MS_U32 u32VQ_PktNum)
4415 {
4416 switch(vqId)
4417 {
4418 case 0:
4419 REG32_W(&_RegCtrl->VQ0_BASE, (u32BaseAddr >> MIU_BUS));
4420 REG16_W(&_RegCtrl->VQ0_SIZE, u32VQ_PktNum);
4421 break;
4422 case 1:
4423 REG32_W(&_RegCtrl->VQ1_Base, (u32BaseAddr >> MIU_BUS));
4424 REG16_W(&_RegCtrl->VQ1_Size, u32VQ_PktNum);
4425 break;
4426 case 2:
4427 REG32_W(&_RegCtrl->VQ2_Base, (u32BaseAddr >> MIU_BUS));
4428 REG16_W(&_RegCtrl->VQ2_Size, u32VQ_PktNum);
4429 break;
4430 case 3:
4431 REG32_W(&_RegCtrl->VQ3_Base, (u32BaseAddr >> MIU_BUS));
4432 REG16_W(&_RegCtrl->VQ3_Size, u32VQ_PktNum);
4433 break;
4434 default:
4435 return FALSE;
4436 }
4437 return TRUE;
4438 }
4439
HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)4440 MS_BOOL HAL_TSP_VQ_Block_Dis(MS_U32 vqId,MS_BOOL bDis)
4441 {
4442 if(bDis == TRUE)
4443 {
4444 switch(vqId)
4445 {
4446 case 0:
4447 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
4448 break;
4449 case 1:
4450 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
4451 break;
4452 case 2:
4453 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
4454 break;
4455 case 3:
4456 REG16_SET(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS);
4457 break;
4458 default:
4459 return FALSE;
4460 }
4461 }
4462 else
4463 {
4464 switch(vqId)
4465 {
4466 case 0:
4467 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX0_BLOCK_DIS);
4468 break;
4469 case 1:
4470 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX1_BLOCK_DIS);
4471 break;
4472 case 2:
4473 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX2_BLOCK_DIS);
4474 break;
4475 case 3:
4476 REG16_CLR(&_RegCtrl->reg160E, TSP_VQTX3_BLOCK_DIS);
4477 break;
4478 default:
4479 return FALSE;
4480 }
4481 }
4482
4483 return TRUE;
4484 }
4485
HAL_TSP_VQ_Enable(MS_BOOL bEn)4486 void HAL_TSP_VQ_Enable(MS_BOOL bEn)
4487 {
4488 if (bEn)
4489 {
4490 REG16_SET(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
4491 }
4492 else
4493 {
4494 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_VQ_EN|TSP_VQ2PINGPONG_EN);
4495 }
4496 }
HAL_TSP_VQ_Reset(MS_U32 vqId,MS_BOOL bEn)4497 void HAL_TSP_VQ_Reset(MS_U32 vqId, MS_BOOL bEn)
4498 {
4499 if(bEn)
4500 {
4501 switch(vqId)
4502 {
4503 case 0:
4504 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
4505 break;
4506 case 1:
4507 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
4508 break;
4509 case 2:
4510 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
4511 break;
4512 case 3:
4513 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET);
4514 break;
4515 default:
4516 break;
4517 }
4518 }
4519 else
4520 {
4521 switch(vqId)
4522 {
4523 case 0:
4524 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_RESET);
4525 break;
4526 case 1:
4527 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_RESET);
4528 break;
4529 case 2:
4530 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_RESET);
4531 break;
4532 case 3:
4533 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_RESET);
4534 break;
4535 default:
4536 break;
4537 }
4538 }
4539 }
4540
HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId,MS_BOOL bEn)4541 void HAL_TSP_VQ_OverflowInt_En(MS_U32 vqId, MS_BOOL bEn)
4542 {
4543 if(bEn)
4544 {
4545 switch(vqId)
4546 {
4547 case 0:
4548 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
4549 break;
4550 case 1:
4551 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
4552 break;
4553 case 2:
4554 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
4555 break;
4556 case 3:
4557 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN);
4558 break;
4559 default:
4560 break;
4561 }
4562 }
4563 else
4564 {
4565 switch(vqId)
4566 {
4567 case 0:
4568 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_OVERFLOW_INT_EN);
4569 break;
4570 case 1:
4571 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_OVF_INT_EN);
4572 break;
4573 case 2:
4574 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_OVF_INT_EN);
4575 break;
4576 case 3:
4577 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_OVF_INT_EN);
4578 break;
4579 default:
4580 break;
4581 }
4582 }
4583 }
4584
HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId,MS_BOOL bEn)4585 void HAL_TSP_VQ_OverflowInt_Clr(MS_U32 vqId, MS_BOOL bEn)
4586 {
4587 if(bEn)
4588 {
4589 switch(vqId)
4590 {
4591 case 0:
4592 REG16_SET(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
4593 break;
4594 case 1:
4595 REG16_SET(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
4596 break;
4597 case 2:
4598 REG16_SET(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
4599 break;
4600 case 3:
4601 REG16_SET(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT);
4602 break;
4603 default:
4604 break;
4605 }
4606 }
4607 else
4608 {
4609 switch(vqId)
4610 {
4611 case 0:
4612 REG16_CLR(&_RegCtrl->VQ0_CTRL, TSP_VQ0_CLR_OVERFLOW_INT);
4613 break;
4614 case 1:
4615 REG16_CLR(&_RegCtrl->VQ1_Config, TSP_VQ1_CLR_OVF_INT);
4616 break;
4617 case 2:
4618 REG16_CLR(&_RegCtrl->VQ2_Config, TSP_VQ2_CLR_OVF_INT);
4619 break;
4620 case 3:
4621 REG16_CLR(&_RegCtrl->VQ3_Config, TSP_VQ3_CLR_OVF_INT);
4622 break;
4623 default:
4624 break;
4625 }
4626 }
4627 }
4628
HAL_PVR_Init(MS_U32 u32PVREng,MS_U32 pktDmxId)4629 void HAL_PVR_Init(MS_U32 u32PVREng, MS_U32 pktDmxId)
4630 {
4631 switch(u32PVREng)
4632 {
4633 case 0:
4634 // PVR 1
4635 REG16_SET(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
4636 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR1_SRC_MASK) | (((MS_U16)pktDmxId) << TSP_PVR1_SRC_SHIFT));
4637 break;
4638 case 1:
4639 // PVR 2
4640 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
4641 REG16_W(&(_RegCtrl->FIFO_Src), (REG16_R(&(_RegCtrl->FIFO_Src)) & ~TSP_PVR2_SRC_MASK_L) | ((((MS_U16)pktDmxId) & 0x01) << TSP_PVR2_SRC_SHIFT_L));
4642 REG16_W(&(_RegCtrl->PCR_Cfg), (REG16_R(&(_RegCtrl->PCR_Cfg)) & ~TSP_PVR2_SRC_MASK_H) | ((((MS_U16)pktDmxId) >> 1) << TSP_PVR2_SRC_SHIFT_H));
4643 break;
4644 case 2:
4645 // PVR 3
4646 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC, pktDmxId << CFG_15_PVR3_SRC_SHIFT);
4647 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN);
4648 break;
4649 case 3:
4650 // PVR 3
4651 REG16_MSK_W(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC, pktDmxId << CFG_15_PVR4_SRC_SHIFT);
4652 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN);
4653 break;
4654 default:
4655 break;
4656 }
4657 }
4658
HAL_PVR_Exit(MS_U32 u32PVREng)4659 void HAL_PVR_Exit(MS_U32 u32PVREng)
4660 {
4661 switch(u32PVREng)
4662 {
4663 case 0:
4664 //reset pvr control registers
4665 REG16_CLR(&(_RegCtrl->reg15b8), TSP_PVR1_PINGPONG);
4666 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR1_SRC_MASK);
4667
4668 //reset write address
4669 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4670 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4671 break;
4672 case 1:
4673 //reset pvr control registers
4674 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_REG_PINGPONG_EN);
4675 REG16_CLR(&(_RegCtrl->FIFO_Src), TSP_PVR2_SRC_MASK_L);
4676 REG16_CLR(&(_RegCtrl->PCR_Cfg), TSP_PVR2_SRC_MASK_H);
4677
4678 //reset write address
4679 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4680 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4681 break;
4682 case 2:
4683 //reset pvr control registers
4684 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR3_SRC);
4685 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_REG_PINGPONG_EN);
4686
4687 //reset write address
4688 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4689 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4690 break;
4691 case 3:
4692 //reset pvr control registers
4693 REG16_CLR(&(_RegCtrl2->CFG_15), CFG_15_PVR4_SRC);
4694 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_REG_PINGPONG_EN);
4695
4696 //reset write address
4697 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4698 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4699 break;
4700 default:
4701 break;
4702 }
4703
4704 //reset PVR buffer to non-OverWrite state
4705 if(_stPvrBuf[u32PVREng].bPA2KSEG1_Mapping== TRUE)
4706 {
4707 _stPvrBuf[u32PVREng].bOverWrite = FALSE;
4708 }
4709 //reset time-stamp
4710 HAL_PVR_SetPVRTimeStamp(u32PVREng,0);
4711
4712 }
4713
HAL_PVR_Start(MS_U32 u32PVREng)4714 void HAL_PVR_Start(MS_U32 u32PVREng)
4715 {
4716 switch(u32PVREng)
4717 {
4718 case 0:
4719 //reset write address
4720 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4721 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_FLUSH);
4722
4723 //enable string to miu
4724 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
4725 break;
4726 case 1:
4727 //reset write address
4728 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4729 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_RST_WADR);
4730
4731 //enable string to miu
4732 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
4733 break;
4734 case 2:
4735 //reset write address
4736 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4737 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_RST_WADR);
4738
4739 //enable string to miu
4740 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN);
4741 break;
4742 case 3:
4743 //reset write address
4744 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4745 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_RST_WADR);
4746
4747 //enable string to miu
4748 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN);
4749 break;
4750 default:
4751 break;
4752 }
4753
4754 if(_stPvrBuf[u32PVREng].bPA2KSEG1_Mapping== TRUE)
4755 {
4756 if((E_TSP_PVR_PVRENG_START <= u32PVREng) && (E_TSP_PVR_PVRENG_END > u32PVREng)) // PVR Eng number check
4757 {
4758 _stPvrBuf[u32PVREng].bOverWrite = FALSE; // Set PVR buffer to non-OverWrite state
4759 }
4760 }
4761 }
4762
HAL_PVR_Stop(MS_U32 u32PVREng)4763 void HAL_PVR_Stop(MS_U32 u32PVREng)
4764 {
4765 switch(u32PVREng)
4766 {
4767 case 0:
4768 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_ENABLE);
4769 break;
4770 case 1:
4771 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_EN);
4772 break;
4773 case 2:
4774 //clear string to miu
4775 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_EN);
4776 break;
4777 case 3:
4778 //clear string to miu
4779 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_EN);
4780 break;
4781 default:
4782 break;
4783 }
4784 }
4785
HAL_PVR_Pause(MS_U32 u32PVREng,MS_BOOL bPause)4786 void HAL_PVR_Pause(MS_U32 u32PVREng , MS_BOOL bPause)
4787 {
4788 if(bPause)
4789 {
4790 switch(u32PVREng)
4791 {
4792 case 0:
4793 REG16_SET(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
4794 break;
4795 case 1:
4796 REG32_SET(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
4797 break;
4798 case 2:
4799 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE);
4800 break;
4801 case 3:
4802 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE);
4803 break;
4804 default:
4805 break;
4806 }
4807 }
4808 else
4809 {
4810 switch(u32PVREng)
4811 {
4812 case 0:
4813 REG16_CLR(&(_RegCtrl->Hw_PVRCfg), TSP_HW_CFG4_PVR_PAUSE);
4814 break;
4815 case 1:
4816 REG32_CLR(&(_RegCtrl->PVR2_Config), TSP_PVR2_STR2MIU_PAUSE);
4817 break;
4818 case 2:
4819 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PVR3_STR2MI_PAUSE);
4820 break;
4821 case 3:
4822 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PVR4_STR2MI_PAUSE);
4823 break;
4824 default:
4825 break;
4826 }
4827 }
4828 }
4829
HAL_PVR_RecPid(MS_U32 u32PVREng,MS_BOOL bSet)4830 void HAL_PVR_RecPid(MS_U32 u32PVREng , MS_BOOL bSet)
4831 {
4832 if(bSet)
4833 {
4834 switch(u32PVREng)
4835 {
4836 case 0:
4837 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
4838 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
4839 break;
4840 case 1:
4841 REG16_SET(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
4842 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
4843 break;
4844 case 2:
4845 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC);
4846 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3);
4847 break;
4848 case 3:
4849 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC);
4850 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4);
4851 break;
4852 default:
4853 break;
4854 }
4855 }
4856 else
4857 {
4858 switch(u32PVREng)
4859 {
4860 case 0:
4861 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS);
4862 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR1_REC_ALL_EN);
4863 break;
4864 case 1:
4865 REG16_CLR(&(_RegCtrl->reg15b4), TSP_PVR_PID_BYPASS2);
4866 REG16_SET(&(_RegCtrl->PVRConfig), TSP_PVR2_REC_ALL_EN);
4867 break;
4868 case 2:
4869 REG16_CLR(&(_RegCtrl2->CFG_16), CFG_16_PID_BYPASS3_REC);
4870 REG16_SET(&(_RegCtrl2->CFG_16), CFG_16_REC_ALL3);
4871 break;
4872 case 3:
4873 REG16_CLR(&(_RegCtrl2->CFG_23), CFG_23_PID_BYPASS4_REC);
4874 REG16_SET(&(_RegCtrl2->CFG_23), CFG_23_REC_ALL4);
4875 break;
4876 default:
4877 break;
4878 }
4879 }
4880 }
4881
HAL_PVR_RecNull(MS_BOOL bSet)4882 void HAL_PVR_RecNull(MS_BOOL bSet)
4883 {
4884 if(bSet == TRUE)
4885 {
4886 REG16_SET(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
4887 }
4888 else
4889 {
4890 REG16_CLR(&(_RegCtrl->PVRConfig), TSP_REC_NULL);
4891 }
4892 }
4893
HAL_PVR_SetBuf(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32BufSize0,MS_U32 u32StartAddr1,MS_U32 u32BufSize1)4894 void HAL_PVR_SetBuf(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32BufSize0, MS_U32 u32StartAddr1, MS_U32 u32BufSize1)
4895 {
4896 // Check MIU select
4897 MS_U8 u8MiuSel;
4898 MS_PHY phyMiuOffsetPvrBuf0, phyMiuOffsetPvrBuf1;
4899 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf0, u32StartAddr0);
4900 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetPvrBuf1, u32StartAddr1);
4901
4902 MS_U32 u32EndAddr0 = phyMiuOffsetPvrBuf0 + u32BufSize0;
4903 MS_U32 u32EndAddr1 = phyMiuOffsetPvrBuf1 + u32BufSize1;
4904 //MS_U32 u32Temp;
4905 switch(u32PVREng)
4906 {
4907 case 0:
4908 // Select MIU
4909 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR1_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR1_SHIFT) & REG_MIU_SEL_PVR1_MASK));
4910
4911 //head1
4912 REG32_W(&_RegCtrl->TsRec_Head, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4913 //end1
4914 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4915 //mid1
4916 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4917
4918 //head2
4919 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (phyMiuOffsetPvrBuf1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
4920 //end2
4921 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
4922 //mid2
4923 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (phyMiuOffsetPvrBuf1>>MIU_BUS) & TSP_HW_PVR1_BUF_MID2_MASK);
4924 break;
4925 case 1:
4926 // Select MIU
4927 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR2_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR2_SHIFT) & REG_MIU_SEL_PVR2_MASK));
4928
4929 //head1
4930 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (phyMiuOffsetPvrBuf0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4931 //end1
4932 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4933 //mid1
4934 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (phyMiuOffsetPvrBuf0 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4935
4936 //head2
4937 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (phyMiuOffsetPvrBuf1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4938 //end2
4939 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4940 //mid2
4941 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (phyMiuOffsetPvrBuf1 >>MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4942 break;
4943 case 2:
4944 // Select MIU
4945 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR3_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR3_SHIFT) & REG_MIU_SEL_PVR3_MASK));
4946
4947 //head1
4948 REG32_W(&(_RegCtrl2->CFG_17_18), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD);
4949 //end1
4950 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0 >> MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL);
4951 //mid1
4952 REG32_W(&(_RegCtrl2->CFG_19_1A), (phyMiuOffsetPvrBuf0 >> MIU_BUS) & CFG_19_1A_PVR3_STR2MI_MID);
4953
4954 //head2
4955 REG32_W(&(_RegCtrl2->CFG_1D_1E), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2);
4956 //end2
4957 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1 >> MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2);
4958 //mid2
4959 REG32_W(&(_RegCtrl2->CFG_1F_20), (phyMiuOffsetPvrBuf1 >> MIU_BUS) & CFG_1F_20_PVR3_STR2MI_MID2);
4960 break;
4961 case 3:
4962 // Select MIU
4963 REG16_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG16_R(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ) & (~REG_MIU_SEL_PVR4_MASK)) | ((u8MiuSel << REG_MIU_SEL_PVR4_SHIFT) & REG_MIU_SEL_PVR4_MASK));
4964
4965 //head1
4966 REG32_W(&(_RegCtrl2->CFG_24_25), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD);
4967 //end1
4968 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL);
4969 //mid1
4970 REG32_W(&(_RegCtrl2->CFG_26_27), (phyMiuOffsetPvrBuf0>>MIU_BUS) & CFG_26_27_PVR4_STR2MI_MID);
4971
4972 //head2
4973 REG32_W(&(_RegCtrl2->CFG_2A_2B), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2);
4974 //end2
4975 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2);
4976 //mid2
4977 REG32_W(&(_RegCtrl2->CFG_2C_2D), (phyMiuOffsetPvrBuf1>>MIU_BUS) & CFG_2C_2D_PVR4_STR2MI_MID2);
4978 break;
4979
4980 default:
4981 break;
4982 }
4983 }
4984
HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng,MS_U32 u32StartAddr0,MS_U32 u32StartAddr1)4985 void HAL_PVR_SetStr2Miu_StartAddr(MS_U32 u32PVREng , MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
4986 {
4987 //MS_U32 u32Temp;
4988 switch(u32PVREng)
4989 {
4990 case 0:
4991 //head1
4992 REG32_W(&_RegCtrl->TsRec_Head, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
4993
4994 //head2
4995 REG32_W(&_RegCtrl->Str2mi_head2pvr1, (u32StartAddr1>> MIU_BUS) & TSP_HW_PVR1_BUF_HEAD2_MASK);
4996 break;
4997 case 1:
4998 //head1
4999 REG32_W(&_RegCtrl->Str2mi_head1_pvr2, (u32StartAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5000
5001 //head2
5002 REG32_W(&_RegCtrl->Str2mi_head2_pvr2, (u32StartAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5003
5004 break;
5005 case 2:
5006 //head1
5007 REG32_W(&(_RegCtrl2->CFG_17_18), (u32StartAddr0>>MIU_BUS) & CFG_17_18_PVR3_STR2MI_HEAD);
5008
5009 //head2
5010 REG32_W(&(_RegCtrl2->CFG_1D_1E), (u32StartAddr1>>MIU_BUS) & CFG_1D_1E_PVR3_STR2MI_HEAD2);
5011 break;
5012 case 3:
5013 //head1
5014 REG32_W(&(_RegCtrl2->CFG_24_25), (u32StartAddr0>>MIU_BUS) & CFG_24_25_PVR4_STR2MI_HEAD);
5015
5016 //head2
5017 REG32_W(&(_RegCtrl2->CFG_2A_2B), (u32StartAddr1>>MIU_BUS) & CFG_2A_2B_PVR4_STR2MI_HEAD2);
5018 break;
5019 default:
5020 break;
5021 }
5022 MS_VIRT virtStart = MsOS_PA2KSEG1(u32StartAddr0);
5023 //PA2KSEG1 mapping detection, 0 : not mapping.
5024 if(0 == virtStart)
5025 {
5026 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_INFO, E_HAL_TSP_DBG_MODEL_ALL, printf("[PA2KSEG1_Mapping][%s][%d] PA2KSEG1_Mapping fail !!\n",__FUNCTION__,__LINE__));
5027 _stPvrBuf[u32PVREng].bPA2KSEG1_Mapping= FALSE;
5028 }
5029 else
5030 {
5031 if((E_TSP_PVR_PVRENG_START <= u32PVREng) && (E_TSP_PVR_PVRENG_END > u32PVREng)) // PVR Eng number check
5032 {
5033 _stPvrBuf[u32PVREng].u32Start = u32StartAddr0;
5034
5035 if( (!_stPvrBuf[u32PVREng].bOverWrite) && (_stPvrBuf[u32PVREng].u32Start!= 0) )
5036 {
5037 *((MS_U64*)(MsOS_PA2KSEG1(_stPvrBuf[u32PVREng].u32Start)))= PVR_NON_OVERWRITE;
5038 }
5039 }
5040 _stPvrBuf[u32PVREng].bPA2KSEG1_Mapping= TRUE;
5041 }
5042 }
5043
HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng,MS_U32 u32MidAddr0,MS_U32 u32MidAddr1)5044 void HAL_PVR_SetStr2Miu_MidAddr(MS_U32 u32PVREng , MS_U32 u32MidAddr0, MS_U32 u32MidAddr1)
5045 {
5046 switch(u32PVREng)
5047 {
5048 case 0:
5049 //mid1
5050 REG32_W(&(_RegCtrl->TsRec_Mid_PVR1_WPTR), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
5051
5052 //mid2
5053 REG32_W(&(_RegCtrl->Str2mi_mid2pvr1), (u32MidAddr1>>4) & TSP_HW_PVR1_BUF_MID2_MASK);
5054 break;
5055 case 1:
5056 //mid1
5057 REG32_W(&(_RegCtrl->Str2mi_mid1_wptr_pvr2), (u32MidAddr0>>4) & TSP_STR2MI2_ADDR_MASK);
5058
5059 //mid2
5060 REG32_W(&(_RegCtrl->Str2mi_mid2_pvr2), (u32MidAddr1>>4) & TSP_STR2MI2_ADDR_MASK);
5061 break;
5062 case 2:
5063 //mid1
5064 REG32_W(&(_RegCtrl2->CFG_19_1A), (u32MidAddr0>>4) & CFG_19_1A_PVR3_STR2MI_MID);
5065
5066 //mid2
5067 REG32_W(&(_RegCtrl2->CFG_1F_20), (u32MidAddr1>>4) & CFG_1F_20_PVR3_STR2MI_MID2);
5068 break;
5069 case 3:
5070 //mid1
5071 REG32_W(&(_RegCtrl2->CFG_26_27), (u32MidAddr0>>4) & CFG_26_27_PVR4_STR2MI_MID);
5072
5073 //mid2
5074 REG32_W(&(_RegCtrl2->CFG_2C_2D), (u32MidAddr1>>4) & CFG_2C_2D_PVR4_STR2MI_MID2);
5075 break;
5076 default:
5077 break;
5078 }
5079 }
5080
HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng,MS_U32 u32EndAddr0,MS_U32 u32EndAddr1)5081 void HAL_PVR_SetStr2Miu_EndAddr(MS_U32 u32PVREng , MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
5082 {
5083 switch(u32PVREng)
5084 {
5085 case 0:
5086 //end1
5087 REG32_W(&(_RegCtrl->TsRec_Tail), (u32EndAddr0 >> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5088
5089 //end2
5090 REG32_W(&(_RegCtrl->Str2mi_tail2pvr1), (u32EndAddr1 >> MIU_BUS) &TSP_HW_PVR1_BUF_TAIL2_MASK);
5091 break;
5092 case 1:
5093 //end1
5094 REG32_W(&_RegCtrl->Str2mi_tail1_pvr2, (u32EndAddr0>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5095
5096 //end2
5097 REG32_W(&_RegCtrl->Str2mi_tail2_pvr2, (u32EndAddr1>> MIU_BUS) & TSP_STR2MI2_ADDR_MASK);
5098 break;
5099 case 2:
5100 //end1
5101 REG32_W(&(_RegCtrl2->CFG_1B_1C), (u32EndAddr0>>MIU_BUS) & CFG_1B_1C_PVR3_STR2MI_TAIL);
5102
5103 //end2
5104 REG32_W(&(_RegCtrl2->CFG_21_22), (u32EndAddr1>>MIU_BUS) & CFG_21_22_PVR3_STR2MI_TAIL2);
5105 break;
5106 case 3:
5107 //end1
5108 REG32_W(&(_RegCtrl2->CFG_28_29), (u32EndAddr0>>MIU_BUS) & CFG_28_29_PVR4_STR2MI_TAIL);
5109
5110 //end2
5111 REG32_W(&(_RegCtrl2->CFG_2E_2F), (u32EndAddr1>>MIU_BUS) & CFG_2E_2F_PVR4_STR2MI_TAIL2);
5112 break;
5113 default:
5114 break;
5115 }
5116 if(_stPvrBuf[u32PVREng].bPA2KSEG1_Mapping == TRUE)
5117 {
5118 if((E_TSP_PVR_PVRENG_START <= u32PVREng) && (E_TSP_PVR_PVRENG_END > u32PVREng)) // PVR Eng number check
5119 {
5120 _stPvrBuf[u32PVREng].u32End = u32EndAddr1;
5121 }
5122 }
5123 }
5124
HAL_PVR_GetWritePtr(MS_U32 u32PVREng)5125 MS_U32 HAL_PVR_GetWritePtr(MS_U32 u32PVREng)
5126 {
5127 MS_U32 WritePtr;
5128 switch(u32PVREng)
5129 {
5130 case 0:
5131 WritePtr = REG32_R(&_RegCtrl->TsRec_Mid_PVR1_WPTR) << MIU_BUS;
5132 break;
5133 case 1:
5134 WritePtr = REG32_R(&_RegCtrl->Str2mi_mid1_wptr_pvr2) << MIU_BUS;
5135 break;
5136 case 2:
5137 WritePtr = REG32_R(&(_RegCtrl2->CFG_66_67)) << MIU_BUS;
5138 break;
5139 case 3:
5140 WritePtr = REG32_R(&(_RegCtrl2->CFG_68_69)) << MIU_BUS;
5141 break;
5142 default:
5143 WritePtr = 0;
5144 break;
5145 }
5146 return _Adjust_PVR_WritePtr(u32PVREng, WritePtr);
5147 }
5148
5149
HAL_PVR_GetEngSrc(MS_U32 u32EngDst,TSP_SRC_SEQ * eSrc)5150 void HAL_PVR_GetEngSrc(MS_U32 u32EngDst, TSP_SRC_SEQ *eSrc)
5151 {
5152 MS_U16 u16Value = 0;
5153
5154 switch(u32EngDst)
5155 {
5156 case 0:
5157 // PVR 1
5158 *eSrc = ((REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR1_SRC_MASK) >> TSP_PVR1_SRC_SHIFT);
5159 break;
5160 case 1:
5161 // PVR 2
5162 u16Value = (REG16_R(&(_RegCtrl->FIFO_Src)) & TSP_PVR2_SRC_MASK_L) >> TSP_PVR2_SRC_SHIFT_L;
5163 u16Value |= ((REG16_R(&(_RegCtrl->PCR_Cfg)) & TSP_PVR2_SRC_MASK_H) << 1);
5164 *eSrc = (TSP_SRC_SEQ)u16Value;
5165 break;
5166 case 2:
5167 // PVR 3
5168 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR3_SRC) >> CFG_15_PVR3_SRC_SHIFT);
5169 break;
5170 case 3:
5171 // PVR 4
5172 *eSrc = ((REG16_R(&(_RegCtrl2->CFG_15 )) & CFG_15_PVR4_SRC) >> CFG_15_PVR4_SRC_SHIFT);
5173 break;
5174 default:
5175 break;
5176 }
5177 }
5178
5179
5180 // kaiser Only!!!
HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)5181 FILEENG_SEQ HAL_TSP_FilePath2Tsif_Mapping(MS_U32 u32FileEng)
5182 {
5183 switch (u32FileEng)
5184 {
5185 case 0: //File in Eng 0
5186 return E_FILEENG_TSIF1;
5187 case 1: //File in Eng 1
5188 return E_FILEENG_TSIF3;
5189 case 2: //File in Eng 2
5190 return E_FILEENG_TSIF0;
5191 case 3: //File in Eng 3
5192 return E_FILEENG_TSIF2;
5193 default:
5194 return E_FILEENG_INVALID;
5195 }
5196 }
5197
5198 // @NOTE for backward competible when calling flowset pvr
5199 // kaiser Only!!!
HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)5200 TSP_SRC_SEQ HAL_TSP_Eng2PktDmx_Mapping(MS_U32 u32Eng)
5201 {
5202 switch(u32Eng)
5203 {
5204 case 0:
5205 return E_TSP_SRC_PKTDMX2;
5206 case 1:
5207 return E_TSP_SRC_PKTDMX3;
5208 case 2:
5209 return E_TSP_SRC_PKTDMX2;
5210 case 3:
5211 return E_TSP_SRC_PKTDMX3;
5212 default:
5213 return E_TSP_SRC_INVALID;
5214 }
5215 }
5216
5217 // kaiser Only!!!
HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF,MS_BOOL bFileIn)5218 MS_U32 HAL_TSP_TsifMapping(TSP_HAL_TSIF eTSIF, MS_BOOL bFileIn)
5219 {
5220 MS_U32 u32PhyTSIF = 0;
5221 switch (eTSIF)
5222 {
5223 case E_TSP_HAL_TSIF_0:
5224 if(bFileIn)
5225 u32PhyTSIF = TSP_TSIF1; // @NOTE tsif1 is used for playback0 file-in
5226 else
5227 u32PhyTSIF = TSP_TSIF0;
5228 break;
5229 case E_TSP_HAL_TSIF_1:
5230 if(bFileIn)
5231 u32PhyTSIF = TSP_TSIF3; // @NOTE tsif3 is used for playback0 file-in
5232 else
5233 u32PhyTSIF = TSP_TSIF2;
5234 break;
5235 case E_TSP_HAL_TSIF_2:
5236 if(bFileIn)
5237 u32PhyTSIF = TSP_TSIF0;
5238 else
5239 u32PhyTSIF = TSP_TSIF3;
5240 break;
5241 case E_TSP_HAL_TSIF_3:
5242 if(bFileIn)
5243 u32PhyTSIF = TSP_TSIF2;
5244 else
5245 u32PhyTSIF = TSP_TSIF1;
5246 break;
5247 case E_TSP_HAL_TSIF_PVR0:
5248 u32PhyTSIF = TSP_TSIF2;
5249 break;
5250 case E_TSP_HAL_TSIF_PVR1:
5251 u32PhyTSIF = TSP_TSIF3;
5252 break;
5253 case E_TSP_HAL_TSIF_PVR2:
5254 u32PhyTSIF = TSP_TSIF2;
5255 break;
5256 case E_TSP_HAL_TSIF_PVR3:
5257 u32PhyTSIF = TSP_TSIF3;
5258 break;
5259 default:
5260 printf("[PVR ERROR][%s][%d] mapping TSIF error\n",__FUNCTION__,__LINE__);
5261 break;
5262 }
5263
5264 return u32PhyTSIF;
5265 }
5266
5267
5268 // kaiser Only!!!
HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)5269 TSP_PIDFLT_SRC HAL_TSP_PktDmx2FltSrc_Mapping(TSP_SRC_SEQ eSrc)
5270 {
5271 // @NOTE we map hw pkt dmx setting to api layer flow at this function
5272
5273 TSP_PIDFLT_SRC ePidFltSrc = E_TSP_PIDFLT_INVALID;
5274
5275 switch (eSrc)
5276 {
5277 case E_TSP_SRC_PKTDMX0:
5278 ePidFltSrc = E_TSP_PIDFLT_LIVE0;
5279 break;
5280 case E_TSP_SRC_PKTDMX1:
5281 ePidFltSrc = E_TSP_PIDFLT_FILE0;
5282 break;
5283 case E_TSP_SRC_PKTDMX2:
5284 ePidFltSrc = E_TSP_PIDFLT_LIVE1;
5285 break;
5286 case E_TSP_SRC_PKTDMX3:
5287 ePidFltSrc = E_TSP_PIDFLT_FILE1;
5288 break;
5289 default:
5290 // @TODO add assert
5291 printf ("[TSP_ERR][%s][%d] Wrong Engine Source!!\n", __FUNCTION__,__LINE__);
5292 break;
5293 }
5294
5295 return ePidFltSrc;
5296 }
5297
HAL_TSP_GetDefaultFileinEng(void)5298 FILEENG_SEQ HAL_TSP_GetDefaultFileinEng(void)
5299 {
5300 return E_FILEENG_TSIF1;
5301 }
5302
HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType,MS_U32 u32Eng)5303 MS_U32 HAL_TSP_PidFltDstMapping(TSP_PIDFLT_DST eDstType, MS_U32 u32Eng)
5304 {
5305 if(eDstType == E_TSP_PIDFLT_DST_VIDEO)
5306 {
5307 switch(u32Eng)
5308 {
5309 case 0:
5310 return TSP_PIDFLT_OUT_VFIFO;
5311 case 1:
5312 return TSP_PIDFLT_OUT_VFIFO3D;
5313 default:
5314 printf("[TSP ERROR][%s][%d] mapping Vfifo eng error\n", __FUNCTION__, __LINE__);
5315 return 0;
5316 }
5317 }
5318 else if(eDstType == E_TSP_PIDFLT_DST_AUDIO)
5319 {
5320 switch(u32Eng)
5321 {
5322 case 0:
5323 return TSP_PIDFLT_OUT_AFIFO;
5324 case 1:
5325 return TSP_PIDFLT_OUT_AFIFO2;
5326 case 2:
5327 return TSP_PIDFLT_OUT_AFIFO3;
5328 case 3:
5329 return TSP_PIDFLT_OUT_AFIFO4;
5330 default:
5331 printf("[TSP ERROR][%s][%d] mapping Afifo eng error\n", __FUNCTION__, __LINE__);
5332 return 0;
5333 }
5334 }
5335 if(eDstType == E_TSP_PIDFLT_DST_PVR)
5336 {
5337 switch(u32Eng)
5338 {
5339 case 0:
5340 return TSP_PIDFLT_OUT_PVR1;
5341 case 1:
5342 return TSP_PIDFLT_OUT_PVR2;
5343 case 2:
5344 return TSP_PIDFLT_OUT_PVR3;
5345 case 3:
5346 return TSP_PIDFLT_OUT_PVR4;
5347 default:
5348 printf("[TSP ERROR][%s][%d] mapping PVR eng error\n",__FUNCTION__,__LINE__);
5349 return 0;
5350 }
5351 }
5352 else
5353 {
5354 printf("[TSP ERROR][%s][%d] pid filter destination type error\n", __FUNCTION__, __LINE__);
5355 return 0;
5356 }
5357 }
5358
HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)5359 MS_U32 HAL_TSP_Tsif2Fq_Mapping(MS_U32 u32Tsif)
5360 {
5361 MS_U32 u32Fq = 0;
5362
5363 switch (u32Tsif)
5364 {
5365 case 0:
5366 u32Fq = 0;
5367 break;
5368 case 1:
5369 u32Fq = 2;
5370 break;
5371 case 2:
5372 u32Fq = 3;
5373 break;
5374 case 3:
5375 u32Fq = 1;
5376 break;
5377 default:
5378 printf("[PVR ERROR][%s][%d] mapping TSIF:%u error\n",__FUNCTION__,__LINE__,(unsigned int)u32Tsif);
5379 break;
5380 }
5381
5382 return u32Fq;
5383 }
5384
HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)5385 TSP_TS_PAD HAL_TSP_3WirePadMapping(MS_U8 u8Pad3WireId)
5386 {
5387 switch(u8Pad3WireId)
5388 {
5389 case 0:
5390 return E_TSP_TS_PAD_EXT3;
5391 case 1:
5392 return E_TSP_TS_PAD_EXT4;
5393 case 2:
5394 return E_TSP_TS_PAD_EXT5;
5395 case 3:
5396 return E_TSP_TS_PAD_EXT6;
5397 default:
5398 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[PVR ERROR][%s][%d] mapping 3WirePad:%u error\n",__FUNCTION__,__LINE__,u8Pad3WireId));
5399 return E_TSP_TS_PAD_INVALID;
5400 }
5401 }
5402
HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng,MS_BOOL bSet)5403 void HAL_PVR_SetStrPacketMode(MS_U32 u32PVREng , MS_BOOL bSet)
5404 {
5405 if(bSet)
5406 {
5407 switch(u32PVREng)
5408 {
5409 case 0:
5410 REG16_SET(&_RegCtrl->reg160C, TSP_RECORD192_EN);
5411 break;
5412 case 1:
5413 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
5414 break;
5415 case 2:
5416 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN);
5417 break;
5418 case 3:
5419 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN);
5420 break;
5421 default:
5422 break;
5423 }
5424 }
5425 else
5426 {
5427 switch(u32PVREng)
5428 {
5429 case 0:
5430 REG16_CLR(&_RegCtrl->reg160C, TSP_RECORD192_EN);
5431 break;
5432 case 1:
5433 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PKT192_EN);
5434 break;
5435 case 2:
5436 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_PKT192_EN);
5437 break;
5438 case 3:
5439 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_PKT192_EN);
5440 break;
5441 default:
5442 break;
5443 }
5444 }
5445 }
5446
HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)5447 MS_U32 HAL_PVR_GetPVRTimeStamp(MS_U32 u32PVREng)
5448 {
5449 MS_U32 u32lpcr = 0;
5450 switch(u32PVREng)
5451 {
5452 case 0:
5453 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
5454
5455 u32lpcr = REG32_R(&_RegCtrl->PVR1_LPcr1);
5456
5457 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_RLD);
5458
5459 return u32lpcr;
5460 case 1:
5461 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
5462
5463 u32lpcr = REG32_R(&_RegCtrl->PVR2_LPCR1);
5464
5465 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_RLD);
5466 return u32lpcr;
5467 case 2:
5468 REG16_CLR((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
5469
5470 u32lpcr = REG32_R((&_RegCtrl2->CFG_62_63));
5471
5472 REG16_SET((&_RegCtrl2->CFG_16), CFG_16_PVR3_LPCR1_RLD);
5473 return u32lpcr;
5474 case 3:
5475 REG16_CLR((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
5476
5477 u32lpcr = REG32_R((&_RegCtrl2->CFG_64_65));
5478
5479 REG16_SET((&_RegCtrl2->CFG_23), CFG_23_PVR4_LPCR1_RLD);
5480 return u32lpcr;
5481 default:
5482 break;
5483 }
5484 return 0;
5485 }
5486
HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng,MS_U32 u32Stamp)5487 void HAL_PVR_SetPVRTimeStamp(MS_U32 u32PVREng , MS_U32 u32Stamp)
5488 {
5489 switch(u32PVREng)
5490 {
5491 case 0:
5492 REG16_SET(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
5493
5494 REG32_W(&_RegCtrl->PVR1_LPcr1, u32Stamp);
5495
5496 REG16_CLR(&_RegCtrl->reg160C, TSP_PVR1_LPCR1_WLD);
5497 break;
5498 case 1:
5499 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
5500
5501 REG32_W(&_RegCtrl->PVR2_LPCR1, u32Stamp);
5502
5503 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_LPCR1_WLD);
5504 break;
5505 case 2:
5506 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD);
5507
5508 REG32_W((&_RegCtrl2->CFG_62_63), u32Stamp);
5509
5510 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_LPCR1_WLD);
5511 break;
5512 case 3:
5513 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD);
5514
5515 REG32_W((&_RegCtrl2->CFG_64_65), u32Stamp);
5516
5517 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_LPCR1_WLD);
5518 break;
5519 default:
5520 break;
5521 }
5522 }
5523
HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng,MS_U32 u32Stamp)5524 void HAL_PVR_SetPVRTimeStamp_Stream(MS_U32 u32PVREng , MS_U32 u32Stamp)
5525 {
5526 switch(u32PVREng)
5527 {
5528 case 0:
5529 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
5530
5531 REG32_W(&_RegCtrl2->CFG_56_57, u32Stamp);
5532
5533 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD0);
5534 break;
5535 case 1:
5536 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
5537
5538 REG32_W(&_RegCtrl2->CFG_58_59, u32Stamp);
5539
5540 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD1);
5541 break;
5542 case 2:
5543 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2);
5544
5545 REG32_W(&_RegCtrl2->CFG_5A_5B, u32Stamp);
5546
5547 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD2);
5548 break;
5549 case 3:
5550 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3);
5551
5552 REG32_W(&_RegCtrl2->CFG_5C_5D, u32Stamp);
5553
5554 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_WLD3);
5555 break;
5556 default:
5557 break;
5558 }
5559 }
5560
HAL_PVR_Alignment_Enable(MS_U32 u32PVREng,MS_BOOL bEnable)5561 void HAL_PVR_Alignment_Enable(MS_U32 u32PVREng, MS_BOOL bEnable)
5562 {
5563 if(bEnable)
5564 {
5565 switch(u32PVREng)
5566 {
5567 case 0:
5568 REG16_SET(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
5569 break;
5570 case 1:
5571 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
5572 break;
5573 case 2:
5574 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN);
5575 break;
5576 case 3:
5577 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN);
5578 break;
5579 default:
5580 break;
5581 }
5582 }
5583 else
5584 {
5585 switch(u32PVREng)
5586 {
5587 case 0:
5588 REG16_CLR(&_RegCtrl->HW2_Config3, TSP_PVR1_ALIGN_EN);
5589 break;
5590 case 1:
5591 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_PVR_ALIGN_EN);
5592 break;
5593 case 2:
5594 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_PVR_ALIGN_EN);
5595 break;
5596 case 3:
5597 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_PVR_ALIGN_EN);
5598 break;
5599 default:
5600 break;
5601 }
5602 }
5603 }
5604
HAL_PVR_FlushData(MS_U32 u32PVREng)5605 void HAL_PVR_FlushData(MS_U32 u32PVREng)
5606 {
5607 switch(u32PVREng)
5608 {
5609 case 0:
5610 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
5611 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR_DATA);
5612 break;
5613 case 1:
5614 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
5615 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR1_DATA);
5616 break;
5617 case 2:
5618 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR2_DATA);
5619 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR2_DATA);
5620 break;
5621 case 3:
5622 REG16_SET(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR3_DATA);
5623 REG16_CLR(&_RegCtrl3->CFG3_39,HW4_CFG39_FLUSH_PVR3_DATA);
5624 break;
5625 default:
5626 break;
5627 }
5628 }
5629
HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)5630 void HAL_PVR_Skip_Scrmb(MS_U32 u32PVREng,MS_BOOL bSkip)
5631 {
5632 if(bSkip)
5633 {
5634 switch(u32PVREng)
5635 {
5636 case 0:
5637 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
5638 break;
5639 case 1:
5640 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
5641 break;
5642 case 2:
5643 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN);
5644 break;
5645 case 3:
5646 REG16_SET(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR4_EN);
5647 break;
5648 default:
5649 break;
5650 }
5651 }
5652 else
5653 {
5654 switch(u32PVREng)
5655 {
5656 case 0:
5657 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR1_EN);
5658 break;
5659 case 1:
5660 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR2_EN);
5661 break;
5662 case 2:
5663 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR3_EN);
5664 break;
5665 case 3:
5666 REG16_CLR(&_RegCtrl3->CFG3_37, HW4_CFG37_MASK_SCR_PVR4_EN);
5667 break;
5668 default:
5669 break;
5670 }
5671 }
5672 }
5673
5674
HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)5675 void HAL_PVR_Block_Dis(MS_U32 u32PVREng,MS_BOOL bDisable)
5676 {
5677 if(bDisable)
5678 {
5679 switch(u32PVREng)
5680 {
5681 case 0:
5682 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
5683 break;
5684 case 1:
5685 REG32_SET(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
5686 break;
5687 case 2:
5688 REG16_SET(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS);
5689 break;
5690 case 3:
5691 REG16_SET(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS);
5692 break;
5693 default:
5694 break;
5695 }
5696 }
5697 else
5698 {
5699 switch(u32PVREng)
5700 {
5701 case 0:
5702 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR1_BLOCK_DIS);
5703 break;
5704 case 1:
5705 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_PVR2_BLOCK_DIS);
5706 break;
5707 case 2:
5708 REG16_CLR(&_RegCtrl2->CFG_16, CFG_16_PVR3_BLOCK_DIS);
5709 break;
5710 case 3:
5711 REG16_CLR(&_RegCtrl2->CFG_23, CFG_23_PVR4_BLOCK_DIS);
5712 break;
5713 default:
5714 break;
5715 }
5716
5717 }
5718 }
5719
HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)5720 void HAL_PVR_BurstLen(MS_U32 u32PVREng,MS_U16 u16BurstMode)
5721 {
5722 switch(u32PVREng)
5723 {
5724 case 0:
5725 REG16_MSK_W(&_RegCtrl->reg15b8, TSP_BURST_LEN_MASK, (u16BurstMode << TSP_BURST_LEN_SHIFT));
5726 break;
5727 case 1:
5728 REG32_MSK_W(&_RegCtrl->PVR2_Config, TSP_PVR2_BURST_LEN_MASK, (u16BurstMode << TSP_PVR2_BURST_LEN_SHIFT));
5729 break;
5730 case 2:
5731 REG16_MSK_W(&_RegCtrl2->CFG_16, CFG_16_PVR3_BURST_LEN_MASK, (u16BurstMode << CFG_16_PVR3_BURST_LEN_SHIFT));
5732 break;
5733 case 3:
5734 REG16_MSK_W(&_RegCtrl2->CFG_23, CFG_23_PVR4_BURST_LEN_MASK, (u16BurstMode << CFG_23_PVR4_BURST_LEN_SHIFT));
5735 break;
5736 default:
5737 break;
5738 }
5739 }
5740
HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng,MS_BOOL bLocal_Stream)5741 void HAL_PVR_TimeStamp_Sel(MS_U32 u32PVREng, MS_BOOL bLocal_Stream)
5742 {
5743 if (u32PVREng>=TSP_PVRENG_NUM)
5744 {
5745 return;
5746 }
5747
5748 if (bLocal_Stream) //Stream
5749 {
5750 REG16_SET((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
5751 }
5752 else //local
5753 {
5754 REG16_CLR((&_RegCtrl2->CFG_12), CFG_12_TIMESTAMP_SEL_PVR1 << (u32PVREng));
5755 }
5756 }
5757
HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)5758 void HAL_PVR_PauseTime_En(MS_U32 u32PVREng,MS_BOOL bEnable)
5759 {
5760 if(bEnable)
5761 {
5762 switch(u32PVREng)
5763 {
5764 case 0:
5765 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
5766 break;
5767 case 1:
5768 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
5769 break;
5770 case 2:
5771 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3);
5772 break;
5773 case 3:
5774 REG16_CLR(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4);
5775 break;
5776 default:
5777 break;
5778 }
5779 }
5780 else
5781 {
5782 switch(u32PVREng)
5783 {
5784 case 0:
5785 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL1);
5786 break;
5787 case 1:
5788 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL2);
5789 break;
5790 case 2:
5791 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL3);
5792 break;
5793 case 3:
5794 REG16_SET(&_RegCtrl3->CFG3_35, HW4_CFG35_BYPASS_TIMESTAMP_SEL4);
5795 break;
5796 default:
5797 break;
5798 }
5799 }
5800 }
5801
HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)5802 void HAL_PVR_SetPauseTime(MS_U32 u32PVREng,MS_U32 u32PauseTime)
5803 {
5804 switch(u32PVREng)
5805 {
5806 case 0:
5807 REG32_W(&_RegCtrl3->CFG3_44_45, u32PauseTime);
5808 break;
5809 case 1:
5810 REG32_W(&_RegCtrl3->CFG3_46_47, u32PauseTime);
5811 break;
5812 case 2:
5813 REG32_W(&_RegCtrl3->CFG3_48_49, u32PauseTime);
5814 break;
5815 case 3:
5816 REG32_W(&_RegCtrl3->CFG3_4A_4B, u32PauseTime);
5817 break;
5818 default:
5819 break;
5820 }
5821 }
5822
HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId,MS_BOOL bEnable)5823 void HAL_PVR_TimeStamp_Stream_En(MS_U32 u32pktDmxId, MS_BOOL bEnable)
5824 {
5825 if (bEnable)
5826 {
5827 REG16_SET((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
5828 }
5829 else
5830 {
5831 REG16_CLR((&_RegCtrl2->CFG_13), CFG_13_LPCR_EN0 << (u32pktDmxId*2));
5832 }
5833 }
5834
HAL_PVR_MOBF_Enable(MS_U32 u32PVREng,MS_BOOL bEnable,MS_U32 u32Key)5835 void HAL_PVR_MOBF_Enable(MS_U32 u32PVREng, MS_BOOL bEnable, MS_U32 u32Key)
5836 {
5837 switch(u32PVREng)
5838 {
5839 case 0:
5840 REG16_W(&_RegCtrl->MOBF_PVR1_Index[0], (u32Key & TSP_MOBF_PVR1_INDEX_MASK));
5841 break;
5842 case 1:
5843 REG16_W(&_RegCtrl->MOBF_PVR2_Index[0], (u32Key & TSP_MOBF_PVR2_INDEX_MASK));
5844 break;
5845 case 2:
5846 REG16_W(&_RegCtrl2->CFG_78_7B[0], (u32Key & CFG_78_PVR3_INDEX));
5847 break;
5848 case 3:
5849 REG16_W(&_RegCtrl2->CFG_78_7B[2], (u32Key & CFG_78_PVR3_INDEX));
5850 break;
5851 default:
5852 break;
5853 }
5854 }
5855
5856 /*
5857 void HAL_PVR_SetTSIF(MS_U32 u32PVREng , MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP)
5858 {
5859 if (bPara)
5860 {
5861 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
5862 }
5863 else
5864 {
5865 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_PARA_SEL);
5866 }
5867
5868 if (bExtSync)
5869 {
5870 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
5871 }
5872 else
5873 {
5874 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_EXT_SYNC);
5875 }
5876
5877 if (bDataSWP)
5878 {
5879 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
5880 }
5881 else
5882 {
5883 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
5884 }
5885 }
5886
5887 void HAL_PVR_RecAtSync_Dis(MS_U32 u32PVREng, MS_BOOL bDis)
5888 {
5889 if(bDis)
5890 {
5891 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
5892 }
5893 else
5894 {
5895 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl1), PVR_REC_AT_SYNC_DIS);
5896 }
5897 }
5898
5899 void HAL_PVR_SetDataSwap(MS_U32 u32PVREng, MS_BOOL bEn)
5900 {
5901 if(bEn)
5902 {
5903 REG16_SET(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
5904 }
5905 else
5906 {
5907 REG16_CLR(&(_PVRReg[u32PVREng]->PVR_Ctrl0), PVR_TSIF_DATA_SWP);
5908 }
5909 }
5910 */
5911
HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)5912 MS_U32 HAL_TSP_HCMD_GetInfo(MS_U32 u32Type)
5913 {
5914 MS_U32 u32Data;
5915
5916 //reserved
5917 switch (u32Type)
5918 {
5919
5920 case INFO_FW_VERSION:
5921 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
5922 break;
5923 case INFO_FW_DATE:
5924 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_DATE);
5925 break;
5926 default:
5927 REG32_W(&_RegCtrl->MCU_Data0, INFO_FW_VERSION);
5928 break;
5929
5930 }
5931
5932 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_INFO);
5933
5934 _delay(10); // supposed TSP is able to respond in 10us
5935 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
5936 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
5937
5938 return u32Data;
5939 }
5940
HAL_TSP_HCMD_BufRst(MS_U32 u32Value)5941 MS_BOOL HAL_TSP_HCMD_BufRst(MS_U32 u32Value)
5942 {
5943 // MS_U32 u32Data;
5944
5945 REG32_W(&_RegCtrl->MCU_Data0 , u32Value);
5946 REG32_W(&_RegCtrl->MCU_Cmd , TSP_MCU_CMD_BUFRST);
5947 _delay(10); // supposed TSP is able to respond in 10us
5948
5949 return TRUE;
5950 }
5951
HAL_TSP_HCMD_Read(MS_U32 u32Addr)5952 MS_U32 HAL_TSP_HCMD_Read(MS_U32 u32Addr)
5953 {
5954 MS_U32 u32Data;
5955
5956 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
5957 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_READ);
5958
5959 _delay(10); // supposed TSP is able to respond in 10us
5960 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
5961 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
5962
5963 return u32Data;
5964 }
5965
5966
HAL_TSP_HCMD_Write(MS_U32 u32Addr,MS_U32 u32Value)5967 MS_BOOL HAL_TSP_HCMD_Write(MS_U32 u32Addr, MS_U32 u32Value)
5968 {
5969 MS_U32 u32Data;
5970
5971 REG32_W(&_RegCtrl->MCU_Data0, u32Addr);
5972 REG32_W(&_RegCtrl->MCU_Data1, u32Value);
5973 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_WRITE);
5974
5975 _delay(10); // supposed TSP is able to respond in 10us
5976 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
5977 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
5978
5979 return TRUE;
5980 }
5981
5982
HAL_TSP_HCMD_Alive(void)5983 MS_BOOL HAL_TSP_HCMD_Alive(void)
5984 {
5985 MS_U32 u32Data;
5986
5987 REG32_W(&_RegCtrl->MCU_Data1, 0);
5988 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_ALIVE); //@TODO check FW HCMD
5989 _delay(10); // supposed TSP is able to respond in 10us
5990 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
5991 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
5992
5993 return (u32Data == TSP_MCU_DATA_ALIVE)? TRUE : FALSE;
5994 }
5995
HAL_TSP_HCMD_SET(MS_U32 mcu_cmd,MS_U32 mcu_data0,MS_U32 mcu_data1)5996 void HAL_TSP_HCMD_SET(MS_U32 mcu_cmd, MS_U32 mcu_data0, MS_U32 mcu_data1)
5997 {
5998 REG32_W(&_RegCtrl->MCU_Data0, mcu_data0);
5999 REG32_W(&_RegCtrl->MCU_Data1, mcu_data1);
6000 REG32_W(&_RegCtrl->MCU_Cmd, mcu_cmd);
6001 }
6002
HAL_TSP_HCMD_GET(MS_U32 * pmcu_cmd,MS_U32 * pmcu_data0,MS_U32 * pmcu_data1)6003 void HAL_TSP_HCMD_GET(MS_U32* pmcu_cmd, MS_U32* pmcu_data0, MS_U32* pmcu_data1)
6004 {
6005 *pmcu_cmd = REG32_R(&_RegCtrl->MCU_Cmd);
6006 *pmcu_data0 = REG32_R(&_RegCtrl->MCU_Data0);
6007 *pmcu_data1 = REG32_R(&_RegCtrl->MCU_Data1);
6008 }
6009
HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId,MS_BOOL bDis)6010 void HAL_TSP_HCMD_SecRdyInt_Disable(MS_U32 FltId ,MS_BOOL bDis)
6011 {
6012 MS_U32 u32Data = bDis ;
6013
6014 REG32_W(&_RegCtrl->MCU_Data0, FltId);
6015 REG32_W(&_RegCtrl->MCU_Data1,u32Data);
6016 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SECRDYINT_DISABLE); // @TODO add HCMD list here
6017 _delay(10); // supposed TSP is able to respond in 10us
6018 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6019
6020 return ;
6021 }
6022
HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)6023 MS_U32 HAL_TSP_HCMD_Dbg(MS_U32 u32Enable)
6024 {
6025 MS_U32 u32Data;
6026
6027 REG32_W(&_RegCtrl->MCU_Data0, u32Enable);
6028 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_DBG);
6029
6030 _delay(10); // supposed TSP is able to respond in 10us
6031 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6032 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6033
6034 return REG32_R(&_RegCtrl->MCU_Data1);
6035 }
6036
HAL_TSP_GetDBGStatus(MS_U16 u16Sel)6037 MS_U32 HAL_TSP_GetDBGStatus(MS_U16 u16Sel)
6038 {
6039 REG16_W(&_RegCtrl->DBG_SEL, 0);
6040 REG16_SET(&_RegCtrl->DBG_SEL, ((u16Sel << TSP_DBG_SEL_SHIFT) & TSP_DBG_SEL_MASK));
6041
6042 return REG32_R(&_RegCtrl->TSP_Debug);
6043 }
6044
HAL_TSP_INT_Enable(MS_U32 u32Mask)6045 void HAL_TSP_INT_Enable(MS_U32 u32Mask)
6046 {
6047 // Low byte for bank 0x15 7e bit[0:7]
6048 /*
6049 7: audio/video packet error
6050 6: DMA read done
6051 5: HK_INT_FORCE. // it's trigure bit is at bank 15 44 bit[15]
6052 4: TSP_FILE_RP meets TSP_FILE_TAIL.
6053 3: TSP_FILE_RP meets TSP_FILE_MID.
6054 2: HK_INT_FORCE. // it's trigure bit is at bank 15 39 bit[15]
6055 1: STR2MI_WADR meets STR2MI_MID.
6056 0: STR2MI_WADR meets STR2MI_TAIL."
6057 */
6058 REG16_SET(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask);
6059
6060 // High byte for bank 0x16 6c bit[0:7]
6061 /*
6062 [7] : PVR2 meet_tail or PVR2_meet_mid
6063 [6] : vq0, vq1, vq2, vq3 overflow interrupt
6064 [5] : all DMA write address not in the protect zone interrupt
6065 [4] : PVR_cb meet the mid or PVR_cb meet the tail
6066 [3] : pcr filter 0 update finish
6067 [2] : pcr filter 1 update finish
6068 [1] : OTV HW interrupt
6069 [0] : reserved
6070 */
6071 REG16_SET(&_RegCtrl->SwInt_Stat1_L, (TSP_HWINT2_EN_MASK & (u32Mask >> 8)) | TSP_HWINT2_STATUS_MASK);
6072 }
6073
HAL_TSP_INT_Disable(MS_U32 u32Mask)6074 void HAL_TSP_INT_Disable(MS_U32 u32Mask)
6075 {
6076 REG16_CLR(&_RegCtrl->HwInt_Stat, TSP_INT_EN_MASK & u32Mask);
6077
6078 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L, TSP_HWINT2_EN_MASK & (u32Mask >> 8));
6079 REG16_W(&_RegCtrl->SwInt_Stat1_L,
6080 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & ~(TSP_HWINT2_EN_MASK & (u32Mask >> 8))) |
6081 TSP_HWINT2_STATUS_MASK);
6082 }
6083
HAL_TSP_INT_ClrHW(MS_U32 u32Mask)6084 void HAL_TSP_INT_ClrHW(MS_U32 u32Mask)
6085 {
6086 REG16_CLR(&_RegCtrl->HwInt_Stat, (u32Mask & 0x00FF) << 8);
6087
6088 //REG16_CLR(&_RegCtrl->SwInt_Stat1_L, u32Mask & 0xFF00);
6089 REG16_W(&_RegCtrl->SwInt_Stat1_L,
6090 (REG16_R(&_RegCtrl->SwInt_Stat1_L) & (~TSP_HWINT2_STATUS_MASK)) |
6091 (((~(u32Mask >> 8))<< TSP_HWINT2_STATUS_SHIFT) & TSP_HWINT2_STATUS_MASK) );
6092 }
6093
HAL_TSP_INT_GetHW(void)6094 MS_U32 HAL_TSP_INT_GetHW(void)
6095 {
6096 MS_U32 status=0;
6097
6098 status |= ((MS_U32)(((REG16_R(&_RegCtrl->SwInt_Stat1_L) & TSP_HWINT2_STATUS_MASK) >> TSP_HWINT2_STATUS_SHIFT) << 8));
6099
6100 status |= ((MS_U32)((REG16_R(&_RegCtrl->HwInt_Stat) & TSP_HWINT_STATUS_MASK) >> TSP_HWINT_STATUS_SHIFT));
6101
6102 return (status & 0x00FFFFFF);
6103 }
6104
HAL_TSP_INT_ClrSW(void)6105 void HAL_TSP_INT_ClrSW(void)
6106 {
6107 REG32_W(&_RegCtrl->SwInt_Stat, 0);
6108 }
6109
6110
HAL_TSP_INT_GetSW(void)6111 MS_U32 HAL_TSP_INT_GetSW(void)
6112 {
6113 return REG32_R(&_RegCtrl->SwInt_Stat);
6114 }
6115
HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx,MS_U32 inputSrc)6116 void HAL_TSP_Set_RcvBuf_Src(MS_U32 bufIdx, MS_U32 inputSrc)
6117 {
6118 switch (bufIdx)
6119 {
6120 case 0:
6121 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF0_SRC, inputSrc<<(bufIdx * 2));
6122 break;
6123 case 1:
6124 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF1_SRC, inputSrc<<(bufIdx * 2));
6125 break;
6126 case 2:
6127 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF2_SRC, inputSrc<<(bufIdx * 2));
6128 break;
6129 case 3:
6130 REG16_MSK_W(&_RegCtrl2->CFG_11, CFG_11_RECEIVE_BUF3_SRC, inputSrc<<(bufIdx * 2));
6131 break;
6132 default:
6133 break;
6134 }
6135 }
6136
HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)6137 void HAL_TSP_SPD_Bypass_En(MS_BOOL bByPassEn)
6138 {
6139 if (bByPassEn)
6140 {
6141 REG16_SET(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
6142 }
6143 else
6144 {
6145 REG16_CLR(&_RegCtrl3->CFG3_52, CFG3_52_SPD_TSIF0_BYPASS | CFG3_52_SPD_TSIF1_BYPASS | CFG3_52_SPD_TSIF2_BYPASS | CFG3_52_SPD_TSIF3_BYPASS);
6146 }
6147 }
6148
6149 //@TODO
6150 #if 1
HAL_TSP_FileIn_SPDConfig(MS_U32 tsif,MS_BOOL CTR_mode)6151 void HAL_TSP_FileIn_SPDConfig(MS_U32 tsif, MS_BOOL CTR_mode)
6152 {
6153 if(CTR_mode == TRUE)
6154 {
6155 printf("SPD CTR mode = %p\n",&(_RegCtrl7[tsif].CFG7_05));
6156 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_CTR_MODE_SPD_FILEIN); //set CTR mode enable
6157 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[0]), 0x0000); //set counter IV
6158 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[1]), 0x0000);
6159 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[2]), 0x0000);
6160 REG16_W(&(_RegCtrl7[tsif].CFG7_00_03[3]), 0x0000);
6161 REG16_W(&(_RegCtrl7[tsif].CFG7_04), CFG7_04_CTR_IV_SPD_MAX_1K); //set counter IV max vld
6162 REG16_SET(&(_RegCtrl7[tsif].CFG7_05), CFG7_05_LOAD_INIT_CNT_SPD); //load counter IV
6163 }
6164
6165 switch(tsif)
6166 {
6167 case 0: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI0_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6168 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6169 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6170 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6171 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6172 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6173 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6174 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6175 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6176 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY0);
6177 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF0_BYPASS);//bypass SPD
6178 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET); //TSIF SPD reset
6179 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF0_SPD_RESET);
6180 break;
6181 case 1: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI1_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6182 /*
6183 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x2222); //file-in SPD key
6184 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x2222);
6185 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x2222);
6186 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x2222);
6187 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x3333);
6188 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x3333);
6189 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x3333);
6190 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x3333);
6191 */
6192 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6193 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6194 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6195 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6196 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6197 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6198 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6199 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6200 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY1);
6201 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF1_BYPASS);//bypass SPD
6202 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET); //TSIF SPD reset
6203 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF1_SPD_RESET);
6204 break;
6205 case 2: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI2_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6206 /*
6207 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x4444); //file-in SPD key
6208 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x4444);
6209 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x4444);
6210 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x4444);
6211 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x5555);
6212 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x5555);
6213 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x5555);
6214 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x5555);
6215 */
6216 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6217 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6218 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6219 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6220 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6221 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6222 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6223 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6224 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY2);
6225 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF2_BYPASS);//bypass SPD
6226 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET); //TSIF SPD reset
6227 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF2_SPD_RESET);
6228 break;
6229 case 3: REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_FI_KEY_MASK, HW4_CFG43_SRC_AES_FI3_KEY << HW4_CFG43_SRC_AES_FI_KEY_SHIFT);
6230 /*
6231 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x6666); //file-in SPD key
6232 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x6666);
6233 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x6666);
6234 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x6666);
6235 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x7777);
6236 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x7777);
6237 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x7777);
6238 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x7777);
6239 */
6240 REG16_W(&_RegCtrl3->CFG3_68_6F[0], 0x0000); //file-in SPD key
6241 REG16_W(&_RegCtrl3->CFG3_68_6F[1], 0x0000);
6242 REG16_W(&_RegCtrl3->CFG3_68_6F[2], 0x0000);
6243 REG16_W(&_RegCtrl3->CFG3_68_6F[3], 0x0000);
6244 REG16_W(&_RegCtrl3->CFG3_68_6F[4], 0x1111);
6245 REG16_W(&_RegCtrl3->CFG3_68_6F[5], 0x1111);
6246 REG16_W(&_RegCtrl3->CFG3_68_6F[6], 0x1111);
6247 REG16_W(&_RegCtrl3->CFG3_68_6F[7], 0x1111);
6248 REG16_SET(&_RegCtrl3->CFG3_3A,HW4_CFG3A_LOAD_SPD_KEY3);
6249 REG16_CLR(&_RegCtrl3->CFG3_52,CFG3_52_SPD_TSIF3_BYPASS);//bypass SPD
6250 REG16_SET(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF3_SPD_RESET); //TSIF SPD reset
6251 REG16_CLR(&_RegCtrl3->CFG3_1E,CFG3_1E_TSIF3_SPD_RESET);
6252 break;
6253 default:printf("Not Support !!\n");
6254 break;
6255 }
6256 }
6257 #endif
6258
6259 // for TSO
HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId,MS_U32 u32TSOEng,MS_BOOL bEn)6260 void HAL_TSP_PidFlt_SetTSOFlt(MS_U32 fltId, MS_U32 u32TSOEng, MS_BOOL bEn)
6261 {
6262 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
6263 if(bEn)
6264 {
6265 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~TSP_PIDFLT_TSOFLT_MASK) | (((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK));
6266 }
6267 else
6268 {
6269 TSP32_IdrW(pPidFlt, (TSP32_IdrR(pPidFlt) & ~(((1 << u32TSOEng) << TSP_PIDFLT_TSOFLT_SHFT) & TSP_PIDFLT_TSOFLT_MASK)));
6270 }
6271 }
6272
HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap,MS_U32 * pu32CapInfo)6273 MS_BOOL HAL_TSP_GetCaps(TSP_HAL_CAP_TYPE eCap, MS_U32 *pu32CapInfo)
6274 {
6275 switch (eCap)
6276 {
6277 case E_TSP_HAL_CAP_TYPE_PIDFLT_NUM :
6278 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PIDFLT_NUM;
6279 break;
6280
6281 case E_TSP_HAL_CAP_TYPE_SECFLT_NUM :
6282 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECFLT_NUM;
6283 break;
6284
6285 case E_TSP_HAL_CAP_TYPE_SECBUF_NUM :
6286 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_NUM;
6287 break;
6288
6289 case E_TSP_HAL_CAP_TYPE_RECENG_NUM :
6290 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECENG_NUM;
6291 break;
6292
6293 case E_TSP_HAL_CAP_TYPE_RECFLT_NUM :
6294 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_NUM;
6295 break;
6296
6297 case E_TSP_HAL_CAP_TYPE_TSIF_NUM :
6298 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSIF_NUM;
6299 break;
6300
6301 case E_TSP_HAL_CAP_TYPE_DEMOD_NUM :
6302 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_DEMOD_NUM;
6303 break;
6304
6305 case E_TSP_HAL_CAP_TYPE_TSPAD_NUM :
6306 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_TSPAD_NUM;
6307 break;
6308
6309 case E_TSP_HAL_CAP_TYPE_VQ_NUM :
6310 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_NUM;
6311 break;
6312
6313 case E_TSP_HAL_CAP_TYPE_CAFLT_NUM :
6314 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAFLT_NUM;
6315 break;
6316
6317 case E_TSP_HAL_CAP_TYPE_CAKEY_NUM :
6318 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_CAKEY_NUM;
6319 break;
6320
6321 case E_TSP_HAL_CAP_TYPE_SECBUF_ALIGN :
6322 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_SECBUF_ALIGN;
6323 break;
6324
6325 case E_TSP_HAL_CAP_TYPE_PVR_ALIGN:
6326 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PVR_ALIGN;
6327 break;
6328
6329 case E_TSP_HAL_CAP_TYPE_FW_ALIGN :
6330 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_ALIGN;
6331 break;
6332
6333 case E_TSP_HAL_CAP_TYPE_VQ_ALIGN :
6334 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_ALIGN;
6335 break;
6336
6337 case E_TSP_HAL_CAP_TYPE_VQ_PITCH :
6338 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VQ_PITCH;
6339 break;
6340
6341 case E_TSP_HAL_CAP_TYPE_MMFI_AUDIO_FILTER_NUM:
6342 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_AUDIO_FILTER_NUM;
6343 break;
6344
6345 case E_TSP_HAL_CAP_TYPE_MMFI_V3D_FILTER_NUM:
6346 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_MMFI_V3D_FILTER_NUM;
6347 break;
6348
6349 case E_TSP_HAL_CAP_TYPE_HW_TYPE:
6350 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HW_TYPE;
6351 break;
6352
6353 case E_TSP_HAL_CAP_TYPE_RECFLT_IDX :
6354 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_RECFLT_IDX;
6355 break;
6356
6357 case E_TSP_HAL_CAP_TYPE_PCRFLT_START_IDX :
6358 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_PCRFLT_START_IDX;
6359 break;
6360
6361 case E_TSP_HAL_CAP_TYPE_VFIFO_NUM:
6362 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_VFIFO_NUM;
6363 break;
6364
6365 case E_TSP_HAL_CAP_TYPE_AFIFO_NUM:
6366 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_AFIFO_NUM;
6367 break;
6368
6369 case E_TSP_HAL_CAP_TYPE_HWPCR_SUPPORT:
6370 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_HWPCR_SUPPORT;
6371 break;
6372
6373 case E_TSP_HAL_CAP_FIQ_NUM:
6374 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FIQ_NUM;
6375 break;
6376
6377 case E_TSP_HAL_CAP_FW_BUF_SIZE:
6378 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_FW_BUF_SIZE;
6379 break;
6380 case E_TSP_HAL_CAP_FW_BUF_RANGE:
6381 *(pu32CapInfo) = TSP_FW_BUF_LOW_BUD;
6382 *(pu32CapInfo + 1) = TSP_FW_BUF_UP_BUD;
6383 break;
6384 case E_TSP_HAL_CAP_VQ_BUF_RANGE:
6385 *(pu32CapInfo) = TSP_VQ_BUF_LOW_BUD;
6386 *(pu32CapInfo + 1) = TSP_VQ_BUF_UP_BUD;
6387 break;
6388 case E_TSP_HAL_CAP_SEC_BUF_RANGE:
6389 *(pu32CapInfo) = TSP_SEC_BUF_LOW_BUD;
6390 *(pu32CapInfo + 1) = TSP_SEC_BUF_UP_BUD;
6391 break;
6392 default:
6393 *(pu32CapInfo) = E_TSP_HAL_CAP_VAL_NULL;
6394 return FALSE;
6395 }
6396
6397 return TRUE;
6398 }
6399
HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)6400 void HAL_TSP_PktDmx_RmDupAVPkt(MS_BOOL bEnable)
6401 {
6402 if(bEnable)
6403 {
6404 REG16_SET(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
6405 }
6406 else
6407 {
6408 REG16_CLR(&_RegCtrl->reg15b8, TSP_REMOVE_DUP_AV_PKT);
6409 }
6410 }
6411
HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType,MS_BOOL bEnable)6412 void HAL_TSP_TEI_RemoveErrorPkt(TSP_HAL_TEI_RmPktType eHalPktType, MS_BOOL bEnable)
6413 {
6414 if(bEnable)
6415 {
6416 switch (eHalPktType)
6417 {
6418 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
6419 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
6420 break;
6421 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
6422 REG16_SET(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
6423 break;
6424 default:
6425 break;
6426 }
6427 }
6428 else
6429 {
6430 switch (eHalPktType)
6431 {
6432 case E_TSP_HAL_TEI_REMOVE_AUDIO_PKT:
6433 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_APES_ERR_RM_EN);
6434 break;
6435 case E_TSP_HAL_TEI_REMOVE_VIDEO_PKT:
6436 REG16_CLR(&_RegCtrl->Hw_Config4, TSP_HW_CFG4_VPES_ERR_RM_EN);
6437 break;
6438 default:
6439 break;
6440 }
6441 }
6442 }
6443
HAL_TSP_TEI_SKIP(MS_U32 tsIf,MS_BOOL bEnable)6444 void HAL_TSP_TEI_SKIP(MS_U32 tsIf, MS_BOOL bEnable)
6445 {
6446 if(bEnable)
6447 {
6448 switch (tsIf)
6449 {
6450 case 0:
6451 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
6452 break;
6453 case 1:
6454 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
6455 break;
6456 case 2:
6457 REG32_SET(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
6458 break;
6459 case 3:
6460 REG16_SET(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3);
6461 break;
6462 default:
6463 break;
6464 }
6465 }
6466 else
6467 {
6468 switch (tsIf)
6469 {
6470 case 0:
6471 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID0);
6472 break;
6473 case 1:
6474 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID1);
6475 break;
6476 case 2:
6477 REG32_CLR(&_RegCtrl->PVR2_Config, TSP_TEI_SKIP_PKT2);
6478 break;
6479 case 3:
6480 REG16_CLR(&_RegCtrl->reg15b8, TSP_TEI_SKIPE_PKT_PID3);
6481 break;
6482 default:
6483 break;
6484 }
6485 }
6486
6487 }
6488
HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)6489 void HAL_TSP_DisPKTCnt_Clear(TSP_DST_SEQ eFltType)
6490 {
6491 switch (eFltType)
6492 {
6493 case E_TSP_DST_FIFO_VIDEO :
6494 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
6495 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
6496 break;
6497 case E_TSP_DST_FIFO_VIDEO3D:
6498 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
6499 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V3D_CLR);
6500 break;
6501 case E_TSP_DST_FIFO_AUDIO :
6502 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
6503 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
6504 break;
6505 case E_TSP_DST_FIFO_AUDIO2 :
6506 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
6507 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
6508 break;
6509 case E_TSP_DST_FIFO_AUDIO3 :
6510 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
6511 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
6512 break;
6513 case E_TSP_DST_FIFO_AUDIO4 :
6514 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
6515 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
6516 break;
6517 default :
6518 printf("[%s][%s][%d] Clear AVPktNum Error\n",__FILE__,__FUNCTION__,__LINE__);
6519 break;
6520 }
6521 }
6522
_HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)6523 static MS_PHY _HAL_TSP_MIU_OFFSET(MS_PHY Phyaddr)
6524 {
6525 #ifdef HAL_MIU2_BASE
6526 if(Phyaddr >= (MS_PHY)HAL_MIU2_BASE)
6527 return (MS_PHY)HAL_MIU2_BASE;
6528 else
6529 #endif //HAL_MIU2_BUS_BASE
6530 #ifdef HAL_MIU1_BASE
6531 if(Phyaddr >= (MS_PHY)HAL_MIU1_BASE)
6532 return (MS_PHY)HAL_MIU1_BASE;
6533 else
6534 #endif //HAL_MIU1_BUS_BASE
6535 return (MS_PHY)HAL_MIU0_BASE;
6536 }
6537
HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)6538 void HAL_TSP_OR_Address_Protect_En(MS_BOOL bEn)
6539 {
6540 if(bEn == TRUE)
6541 {
6542 REG16_SET(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
6543 }
6544 else
6545 {
6546 REG16_CLR(&_RegCtrl->reg160C,TSP_ORZ_DMAW_PROT_EN);
6547 }
6548 }
6549
HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH,MS_PHY u32AddrL)6550 void HAL_TSP_OR_Address_Protect(MS_PHY u32AddrH, MS_PHY u32AddrL)
6551 {
6552 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
6553
6554 REG32_W(&_RegCtrl->ORZ_DMAW_LBND,(MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_LBND_MASK));
6555 REG32_W(&_RegCtrl->ORZ_DMAW_UBND,(MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_ORZ_DMAW_UBND_MASK));
6556 }
6557
HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)6558 void HAL_TSP_SEC_Address_Protect_En(MS_BOOL bEn)
6559 {
6560
6561 if(bEn == TRUE)
6562 {
6563 REG16_SET(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
6564 }
6565 else
6566 {
6567 REG16_CLR(&_RegCtrl->reg15b4,TSP_SEC_CB_PVR2_DAMW_PROTECT_EN);
6568 }
6569 }
6570
HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID,MS_PHY u32AddrH,MS_PHY u32AddrL)6571 void HAL_TSP_SEC_Address_Protect(MS_U8 u8SecID, MS_PHY u32AddrH, MS_PHY u32AddrL)
6572 {
6573 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
6574 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK);
6575 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_DMAW_BND_MASK);
6576
6577 switch(u8SecID)
6578 {
6579 case 0:
6580 REG32_W(&_RegCtrl->DMAW_LBND0,u32LBnd);
6581 REG32_W(&_RegCtrl->DMAW_UBND0,u32UBnd);
6582 break;
6583 case 1:
6584 REG32_W(&_RegCtrl->DMAW_LBND1,u32LBnd);
6585 REG32_W(&_RegCtrl->DMAW_UBND1,u32UBnd);
6586 break;
6587 default:
6588 break;
6589 }
6590 }
6591
HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)6592 void HAL_TSP_PVR_Address_Protect_En(MS_U32 u32PVREng,MS_BOOL bEnable)
6593 {
6594 if(bEnable)
6595 {
6596 switch(u32PVREng)
6597 {
6598 case 0:
6599 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
6600 break;
6601 case 1:
6602 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
6603 break;
6604 case 2:
6605 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR3_DMAW_PROTECT_EN);
6606 break;
6607 case 3:
6608 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_PVR4_DMAW_PROTECT_EN);
6609 break;
6610 default:
6611 break;
6612 }
6613 }
6614 else
6615 {
6616 switch(u32PVREng)
6617 {
6618 case 0:
6619 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR1_DMAW_PROTECT_EN);
6620 break;
6621 case 1:
6622 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR2_DMAW_PROTECT_EN);
6623 break;
6624 case 2:
6625 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR3_DMAW_PROTECT_EN);
6626 break;
6627 case 3:
6628 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_PVR4_DMAW_PROTECT_EN);
6629 break;
6630 default:
6631 break;
6632 }
6633 }
6634 }
6635
HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32AddrH,MS_PHY u32AddrL)6636 void HAL_TSP_PVR_Address_Protect(MS_U32 u32PVREng,MS_PHY u32AddrH, MS_PHY u32AddrL)
6637 {
6638 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
6639 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK);
6640 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_PVR_MASK);
6641
6642 switch(u32PVREng)
6643 {
6644 case 0:
6645 REG32_W(&_RegCtrl->DMAW_LBND2, u32LBnd);
6646 REG32_W(&_RegCtrl->DMAW_UBND2, u32UBnd);
6647 break;
6648 case 1:
6649 REG32_W(&_RegCtrl->DMAW_LBND3, u32LBnd);
6650 REG32_W(&_RegCtrl->DMAW_UBND3, u32UBnd);
6651 break;
6652 case 2:
6653 REG32_W(&_RegCtrl->DMAW_LBND4, u32LBnd);
6654 REG32_W(&_RegCtrl->DMAW_UBND4, u32UBnd);
6655 break;
6656 case 3:
6657 REG32_W(&_RegCtrl3->CFG3_12_13, u32LBnd);
6658 REG32_W(&_RegCtrl3->CFG3_14_15, u32UBnd);
6659 break;
6660 default:
6661 break;
6662 }
6663 }
6664
HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)6665 void HAL_TSP_FILEIN_Address_Protect_En(FILEENG_SEQ eFileEng,MS_BOOL bEnable)
6666 {
6667 if(bEnable)
6668 {
6669 switch(eFileEng)
6670 {
6671 case E_FILEENG_TSIF0:
6672 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
6673 break;
6674 case E_FILEENG_TSIF1:
6675 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
6676 break;
6677 case E_FILEENG_TSIF2:
6678 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
6679 break;
6680 case E_FILEENG_TSIF3:
6681 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN3_DMAR_PROTECT_EN);
6682 break;
6683 default:
6684 break;
6685 }
6686 }
6687 else
6688 {
6689 switch(eFileEng)
6690 {
6691 case E_FILEENG_TSIF0:
6692 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN0_DMAR_PROTECT_EN);
6693 break;
6694 case E_FILEENG_TSIF1:
6695 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN1_DMAR_PROTECT_EN);
6696 break;
6697 case E_FILEENG_TSIF2:
6698 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN2_DMAR_PROTECT_EN);
6699 break;
6700 case E_FILEENG_TSIF3:
6701 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_FILEIN3_DMAR_PROTECT_EN);
6702 break;
6703 default:
6704 break;
6705 }
6706 }
6707 }
6708
HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH,MS_PHY u32AddrL)6709 void HAL_TSP_FILEIN_Address_Protect(FILEENG_SEQ eFileEng,MS_PHY u32AddrH, MS_PHY u32AddrL)
6710 {
6711 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
6712 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
6713 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_FILEIN_DMAR_BND_MASK);
6714
6715 switch(eFileEng)
6716 {
6717 case E_FILEENG_TSIF0:
6718 REG32_W(&_RegCtrl6->CFG6_30_31, u32LBnd);
6719 REG32_W(&_RegCtrl6->CFG6_32_33, u32UBnd);
6720 break;
6721 case E_FILEENG_TSIF1:
6722 REG32_W(&_RegCtrl6->CFG6_34_35, u32LBnd);
6723 REG32_W(&_RegCtrl6->CFG6_36_37, u32UBnd);
6724 break;
6725 case E_FILEENG_TSIF2:
6726 REG32_W(&_RegCtrl6->CFG6_38_39, u32LBnd);
6727 REG32_W(&_RegCtrl6->CFG6_3A_3B, u32UBnd);
6728 break;
6729 case E_FILEENG_TSIF3:
6730 REG32_W(&_RegCtrl6->CFG6_3C_3D, u32LBnd);
6731 REG32_W(&_RegCtrl6->CFG6_3E_3F, u32UBnd);
6732 break;
6733 default:
6734 break;
6735 }
6736 }
6737
HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)6738 void HAL_TSP_MMFI_Address_Protect_En(MS_U32 u32MMFIEng,MS_BOOL bEnable)
6739 {
6740 if(bEnable)
6741 {
6742 switch(u32MMFIEng)
6743 {
6744 case 0:
6745 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
6746 break;
6747 case 1:
6748 REG16_SET(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
6749 break;
6750 default:
6751 break;
6752 }
6753 }
6754 else
6755 {
6756 switch(u32MMFIEng)
6757 {
6758 case 0:
6759 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI0_DMAR_PROTECT_EN);
6760 break;
6761 case 1:
6762 REG16_CLR(&_RegCtrl3->CFG3_73, CFG3_73_MMFI1_DMAR_PROTECT_EN);
6763 break;
6764 default:
6765 break;
6766 }
6767 }
6768 }
6769
HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH,MS_PHY u32AddrL)6770 void HAL_TSP_MMFI_Address_Protect(MS_U32 u32MMFIEng,MS_PHY u32AddrH, MS_PHY u32AddrL)
6771 {
6772 MS_PHY phyMiuOffset = _HAL_TSP_MIU_OFFSET(u32AddrL);
6773 MS_U32 u32LBnd = (MS_U32)(((u32AddrL - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
6774 MS_U32 u32UBnd = (MS_U32)(((u32AddrH - phyMiuOffset) >> MIU_BUS) & TSP_MMFI_DMAR_BND_MASK);
6775
6776 switch(u32MMFIEng)
6777 {
6778 case 0:
6779 REG32_W(&_RegCtrl6->CFG6_48_49, u32LBnd);
6780 REG32_W(&_RegCtrl6->CFG6_4A_4B, u32UBnd);
6781 break;
6782 case 1:
6783 REG32_W(&_RegCtrl6->CFG6_4C_4D, u32LBnd);
6784 REG32_W(&_RegCtrl6->CFG6_4E_4F, u32UBnd);
6785 break;
6786 default:
6787 break;
6788 }
6789 }
6790
6791
HAL_TSP_SaveFltState(void)6792 void HAL_TSP_SaveFltState(void)
6793 {
6794 MS_U32 u32Size;
6795 TSP32 * pRegEnd;
6796 TSP32 * pReg;
6797 int i, j;
6798
6799 for (i = 0; i < TSP_PIDFLT_NUM; i++)
6800 {
6801 _u32PidFltReg[i] = TSP32_IdrR(&(_REGPid0->Flt[i]));
6802 _u32PidDstReg[i] = TSP32_IdrR(&(_REGPid1->Flt[i]));
6803 }
6804
6805 u32Size = ((MS_VIRT)&(((REG_SecFlt*)0)->_x50))/sizeof(TSP32);
6806 for (i = 0; i < TSP_SECFLT_NUM; i++)
6807 {
6808 pReg = (TSP32*)&(_REGSec->Flt[i]);
6809 pRegEnd = pReg + u32Size;
6810 j = 0;
6811 for ( ; pReg < pRegEnd; pReg++)
6812 {
6813 _u32SecReg[i*u32Size+j] = TSP32_IdrR(pReg);
6814 j++;
6815 }
6816 }
6817 }
6818
HAL_TSP_CMD_Run(MS_U32 u32Cmd,MS_U32 u32Config0,MS_U32 u32Config1,MS_U32 * pData)6819 MS_BOOL HAL_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1, MS_U32* pData)
6820 {
6821 MS_U32 u32Data = 0;
6822 MS_BOOL brtn = FALSE;
6823
6824 //printf("\033[31m [%s] Mode = %lX , Config0 =%lX , Config1 = %lX \033[m\n",__FUNCTION__,u32Cmd,u32Config0,u32Config1); // Eason test
6825
6826 switch (u32Cmd)
6827 {
6828 case HAL_DMX_CMD_RUN_DISABLE_SEC_CC_CHECK:
6829 REG32_W(&_RegCtrl->MCU_Data1, u32Config0);
6830 REG32_W(&_RegCtrl->MCU_Cmd, TSP_MCU_CMD_SEC_CC_CHECK_DISABLE);
6831 _delay(10); // supposed TSP is able to respond in 10us
6832 u32Data = REG32_R(&_RegCtrl->MCU_Data1);
6833 REG32_W(&_RegCtrl->MCU_Cmd, 0); // write null to clear
6834 brtn = (u32Data == TSP_MCU_CMD_SEC_CC_CHECK_DISABLE)? TRUE : FALSE;
6835 break;
6836 default:
6837 break;
6838 }
6839 return brtn;
6840 }
6841
HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng,MS_BOOL bEnable)6842 MS_BOOL HAL_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_BOOL bEnable)
6843 {
6844 printf("[%s] not support!!\n",__FUNCTION__);
6845 return FALSE;
6846 }
6847
HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng,MS_U16 u16CaPvrMode,MS_BOOL bEnable)6848 MS_BOOL HAL_TSP_CAPVR_SPSEnable(MS_U32 u32Eng, MS_U16 u16CaPvrMode, MS_BOOL bEnable)
6849 {
6850 MS_U16 u16value = REG16_R(&_RegCtrl3->CFG3_38);
6851
6852 switch(u32Eng)
6853 {
6854 case 0:
6855 u16value &= ~(HW4_CFG38_CA_PVR1_SEL_MASK|HW4_CFG38_PKT192_SPS_EN1);
6856 break;
6857 case 1:
6858 u16value &= ~(HW4_CFG38_CA_PVR2_SEL_MASK|HW4_CFG38_PKT192_SPS_EN2);
6859 break;
6860 case 2:
6861 u16value &= ~(HW4_CFG38_CA_PVR3_SEL_MASK|HW4_CFG38_PKT192_SPS_EN3);
6862 break;
6863 case 3:
6864 u16value &= ~(HW4_CFG38_CA_PVR4_SEL_MASK|HW4_CFG38_PKT192_SPS_EN4);
6865 break;
6866 default:
6867 return FALSE;
6868 }
6869
6870 if(bEnable)
6871 {
6872 switch(u32Eng)
6873 {
6874 case 0:
6875 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR1_SEL_SHIFT);
6876 u16value |= HW4_CFG38_PKT192_SPS_EN1;
6877 break;
6878 case 1:
6879 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR2_SEL_SHIFT);
6880 u16value |= HW4_CFG38_PKT192_SPS_EN2;
6881 break;
6882 case 2:
6883 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR3_SEL_SHIFT);
6884 u16value |= HW4_CFG38_PKT192_SPS_EN3;
6885 break;
6886 case 3:
6887 u16value |= (u16CaPvrMode << HW4_CFG38_CA_PVR4_SEL_SHIFT);
6888 u16value |= HW4_CFG38_PKT192_SPS_EN4;
6889 break;
6890 }
6891 }
6892
6893 REG16_W(&_RegCtrl3->CFG3_38, u16value);
6894
6895 return TRUE;
6896
6897 }
6898
6899 //@TODO
6900 #if 1
HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng,MS_BOOL CTR_mode)6901 void HAL_TSP_PVR_SPSConfig(MS_U32 u32Eng, MS_BOOL CTR_mode)
6902 {
6903 switch(u32Eng)
6904 {
6905 case 0: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN1);
6906 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR1_KEY);
6907 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
6908 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
6909 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
6910 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
6911 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
6912 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
6913 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
6914 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
6915 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY1);
6916 break;
6917 case 1: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN2);
6918 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR2_KEY);
6919 /*
6920 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x2222);//PVR SPS key
6921 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x2222);
6922 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x2222);
6923 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x2222);
6924 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x3333);
6925 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x3333);
6926 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x3333);
6927 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x3333);
6928 */
6929 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
6930 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
6931 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
6932 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
6933 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
6934 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
6935 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
6936 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
6937 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY2);
6938 break;
6939 case 2: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN3);
6940 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR3_KEY);
6941 /*
6942 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x4444);//PVR SPS key
6943 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x4444);
6944 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x4444);
6945 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x4444);
6946 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x5555);
6947 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x5555);
6948 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x5555);
6949 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x5555);
6950 */
6951 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
6952 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
6953 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
6954 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
6955 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
6956 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
6957 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
6958 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
6959 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY3);
6960 break;
6961 case 3: REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_PKT192_SPS_EN4);
6962 REG16_MSK_W(&_RegCtrl3->CFG3_43, HW4_CFG43_SRC_AES_PVR_KEY_MASK, HW4_CFG43_SRC_AES_PVR4_KEY);
6963 /*
6964 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x6666);//PVR SPS key
6965 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x6666);
6966 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x6666);
6967 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x6666);
6968 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x7777);
6969 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x7777);
6970 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x7777);
6971 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x7777);
6972 */
6973 REG16_W(&_RegCtrl3->CFG3_60_67[0], 0x0000);//PVR SPS key
6974 REG16_W(&_RegCtrl3->CFG3_60_67[1], 0x0000);
6975 REG16_W(&_RegCtrl3->CFG3_60_67[2], 0x0000);
6976 REG16_W(&_RegCtrl3->CFG3_60_67[3], 0x0000);
6977 REG16_W(&_RegCtrl3->CFG3_60_67[4], 0x1111);
6978 REG16_W(&_RegCtrl3->CFG3_60_67[5], 0x1111);
6979 REG16_W(&_RegCtrl3->CFG3_60_67[6], 0x1111);
6980 REG16_W(&_RegCtrl3->CFG3_60_67[7], 0x1111);
6981 REG16_SET(&_RegCtrl3->CFG3_38,HW4_CFG38_LOAD_SPS_KEY4);
6982 break;
6983 default: printf("Not Support !!\n");
6984 break;
6985 }
6986
6987 if(CTR_mode == TRUE)
6988 {
6989 printf("SPS CTR mode = %p\n",&(_RegCtrl8[u32Eng].CFG8_05));
6990 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_CTR_MODE_SPS_PVR1); //set CTR mode
6991 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[0]), 0x0000); //set counter IV
6992 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[1]), 0x0000);
6993 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[2]), 0x0000);
6994 REG16_W(&(_RegCtrl8[u32Eng].CFG8_00_03[3]), 0x0000);
6995 REG16_W(&(_RegCtrl8[u32Eng].CFG8_04), CFG8_04_CTR_IV_SPS_MAX_1K); //set counter IV max vld
6996 REG16_SET(&(_RegCtrl8[u32Eng].CFG8_05),CFG8_05_LOAD_INIT_CNT_SPS1); //load counter IV
6997 }
6998 }
6999 #endif
7000
7001 // u32GroupId: 0 -> filter0 ~ filter31
7002 // u32GroupId: 1 -> filter32 ~ filter63
7003 // u32GroupId: 2 -> filter64 ~ filter95
7004 // u32GroupId: 3 -> filter96 ~ filter127
7005 // u32GroupId: 4 -> filter128 ~ filter159
7006 // u32GroupId: 5 -> filter160 ~ filter191
7007
7008
HAL_DSCMB_GetStatus(MS_U32 u32PktDmx,MS_U32 u32GroupId,MS_U32 u32PidFltId,MS_U32 * pu32ScmbSts)7009 MS_BOOL HAL_DSCMB_GetStatus(MS_U32 u32PktDmx, MS_U32 u32GroupId, MS_U32 u32PidFltId, MS_U32 *pu32ScmbSts)
7010 {
7011 MS_U16 u16PktDmxSrc;
7012 MS_U16 u16WordId;
7013 MS_U32 u32PIDFltMask = u32PidFltId;
7014
7015 if(u32PidFltId != 0xFFFFFFFF)
7016 {
7017 u32PIDFltMask = (1 << (u32PidFltId & 0x1F));
7018 }
7019
7020 u16PktDmxSrc = _CLR_(REG16_R(&_RegCtrl->reg15b8), TSP_MATCH_PID_SRC_MASK);
7021
7022 switch(u32PktDmx)
7023 {
7024 case 0:
7025 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX0 << TSP_MATCH_PID_SRC_SHIFT);
7026 break;
7027 case 1:
7028 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX1 << TSP_MATCH_PID_SRC_SHIFT);
7029 break;
7030 case 2:
7031 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX2 << TSP_MATCH_PID_SRC_SHIFT);
7032 break;
7033 case 3:
7034 u16PktDmxSrc = _SET_(u16PktDmxSrc, TSP_MATCH_PID_SRC_PKTDMX3 << TSP_MATCH_PID_SRC_SHIFT);
7035 break;
7036 default:
7037 break;
7038 }
7039
7040 REG16_W(&_RegCtrl->reg15b8, u16PktDmxSrc);
7041
7042 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // Set 1 to load match_pid_num
7043
7044 // get status
7045 REG16_W(&_RegCtrl->PVRConfig, _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // freeze
7046
7047 u16WordId = _CLR_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_SEL_MASK);
7048
7049 if (u32GroupId < 6)
7050 {
7051 u16WordId = _SET_(u16WordId, u32GroupId << TSP_MATCH_PID_SEL_SHIFT);
7052 REG16_MSK_W(&_RegCtrl->PVRConfig,TSP_MATCH_PID_SEL_MASK,u16WordId);
7053 }
7054 else
7055 {
7056 printf("[TSP_ERR][%s][%d] Unsupported u32GroupId (%lu)!!!\n",__FUNCTION__, __LINE__, (long unsigned int)u32GroupId);
7057 }
7058
7059 *pu32ScmbSts = _AND_(REG32_R(&_RegCtrl->TsPidScmbStatTsin), u32PIDFltMask);
7060
7061 REG16_W(&_RegCtrl->PVRConfig, _SET_(REG16_R(&_RegCtrl->PVRConfig), TSP_MATCH_PID_LD)); // re-enable
7062
7063 if(u32PIDFltMask != 0xFFFFFFFF)
7064 {
7065 *pu32ScmbSts = ((*pu32ScmbSts > 0) ? 1: 0);
7066 }
7067
7068 return TRUE;
7069 }
7070
7071 // -------------------------------------------------------------
7072 // Merge Stream
7073 // -------------------------------------------------------------
HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SyncByte,MS_BOOL bSet)7074 MS_BOOL HAL_TSP_PktConverter_SetSyncByte(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SyncByte, MS_BOOL bSet)
7075 {
7076 REG16 *SynReg=0;
7077 MS_U16 u16Mask = 0x00FF, u16Sync = 0, u16Shift = 0;
7078
7079 switch(u8Path)
7080 {
7081 case TSP_TSIF0:
7082 SynReg = &(_RegCtrl6->SyncByte_tsif0[u8Idx>>1]);
7083 break;
7084 case TSP_TSIF1:
7085 SynReg = &(_RegCtrl6->SyncByte_tsif1[u8Idx>>1]);
7086 break;
7087 case TSP_TSIF2:
7088 SynReg = &(_RegCtrl6->SyncByte_tsif2[u8Idx>>1]);
7089 break;
7090 case TSP_TSIF3:
7091 SynReg = &(_RegCtrl6->SyncByte_tsif3[u8Idx>>1]);
7092 break;
7093 default:
7094 return FALSE;
7095 }
7096
7097
7098 if(u8Idx & 0x1)
7099 {
7100 u16Shift = 8;
7101 }
7102
7103 if(bSet == TRUE)
7104 {
7105 u16Sync = (MS_U16)(*pu8SyncByte & 0xFF);
7106 REG16_W(SynReg,((REG16_R(SynReg) & ~(u16Mask << u16Shift)) | (u16Sync << u16Shift)));
7107 }
7108 else
7109 {
7110 u16Sync = (REG16_R(SynReg) & (u16Mask << u16Shift)) >> u16Shift;
7111 *pu8SyncByte = (MS_U8)u16Sync;
7112 }
7113
7114 return TRUE;
7115
7116 }
7117
HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path,MS_U8 u8Idx,MS_U8 * pu8SrcId,MS_BOOL bSet)7118 MS_BOOL HAL_TSP_PktConverter_SetSrcId(MS_U8 u8Path, MS_U8 u8Idx, MS_U8 *pu8SrcId, MS_BOOL bSet)
7119 {
7120 REG16 *SrcIdReg =0;
7121 MS_U16 u16SrcId = 0, u16Mask = 0x000F, u16Shift = 0;
7122
7123 switch(u8Path)
7124 {
7125 case TSP_TSIF0:
7126 SrcIdReg = &(_RegCtrl6->SourceId_tsif0[u8Idx>>2]);
7127 break;
7128 case TSP_TSIF1:
7129 SrcIdReg = &(_RegCtrl6->SourceId_tsif1[u8Idx>>2]);
7130 break;
7131 case TSP_TSIF2:
7132 SrcIdReg = &(_RegCtrl6->SourceId_tsif2[u8Idx>>2]);
7133 break;
7134 case TSP_TSIF3:
7135 SrcIdReg = &(_RegCtrl6->SourceId_tsif3[u8Idx>>2]);
7136 break;
7137 default:
7138 return FALSE;
7139 }
7140
7141 switch(u8Idx & 0x3)
7142 {
7143 case 0x1:
7144 u16Shift = 4;
7145 u16SrcId <<= 4;
7146 u16Mask <<= 4;
7147 break;
7148 case 0x2:
7149 u16Shift = 8;
7150 u16SrcId <<= 8;
7151 u16Mask <<= 8;
7152 break;
7153 case 0x3:
7154 u16Shift = 12;
7155 u16SrcId <<= 12;
7156 u16Mask <<= 12;
7157 break;
7158 }
7159
7160 if(bSet == TRUE)
7161 {
7162 u16SrcId = (MS_U16)(*pu8SrcId & 0xFF);
7163 REG16_W(SrcIdReg,((REG16_R(SrcIdReg) & ~(u16Mask << u16Shift)) | (u16SrcId << u16Shift)));
7164 }
7165 else
7166 {
7167 u16SrcId = (REG16_R(SrcIdReg) & (u16Mask << u16Shift)) >> u16Shift;
7168 *pu8SrcId = (MS_U8)u16SrcId;
7169 }
7170
7171 return TRUE;
7172 }
7173
HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path,MS_U8 u8PktHeaderLen)7174 static void HAL_TSP_PktConverter_SetMXLPktHeaderLen(MS_U8 u8Path, MS_U8 u8PktHeaderLen)
7175 {
7176 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7177
7178 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_MXL_PKT_HEADER_MASK)) | ((u8PktHeaderLen << TSP_MXL_PKT_HEADER_SHIFT) & TSP_MXL_PKT_HEADER_MASK)));
7179 }
7180
HAL_TSP_PktConverter_PktMode(MS_U8 u8Path,TSP_HAL_PKT_MODE ePktMode)7181 MS_BOOL HAL_TSP_PktConverter_PktMode(MS_U8 u8Path, TSP_HAL_PKT_MODE ePktMode)
7182 {
7183 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7184
7185 switch(ePktMode)
7186 {
7187 case E_TSP_HAL_PKT_MODE_NORMAL:
7188 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_188Mode));
7189 break;
7190 case E_TSP_HAL_PKT_MODE_CI:
7191 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_CIMode));
7192 break;
7193 case E_TSP_HAL_PKT_MODE_OPEN_CABLE:
7194 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_OpenCableMode));
7195 break;
7196 case E_TSP_HAL_PKT_MODE_ATS:
7197 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_ATSMode));
7198 break;
7199 case E_TSP_HAL_PKT_MODE_MXL_192:
7200 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7201 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,4);
7202 break;
7203 case E_TSP_HAL_PKT_MODE_MXL_196:
7204 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7205 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,8);
7206 break;
7207 case E_TSP_HAL_PKT_MODE_MXL_200:
7208 REG16_W(PktConverterReg,((REG16_R(PktConverterReg) & ~(TSP_PKT_CONVERTER_MODE_MASK)) | TSP_PKT_MxLMode));
7209 HAL_TSP_PktConverter_SetMXLPktHeaderLen(u8Path,12);
7210 break;
7211 default:
7212 printf("[TSP_ERR][%s][%d] Wrong PktConverter Packet Mode!!!\n",__FUNCTION__,__LINE__);
7213 return FALSE;
7214 }
7215
7216 return TRUE;
7217 }
7218
HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path,MS_BOOL bEnable)7219 void HAL_TSP_PktConverter_ForceSync(MS_U8 u8Path, MS_BOOL bEnable)
7220 {
7221 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7222
7223 if(bEnable)
7224 {
7225 REG16_W(PktConverterReg, _SET_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47)); // Set 1 to force sync byte be 0x47
7226 }
7227 else
7228 {
7229 REG16_W(PktConverterReg, _CLR_(REG16_R(PktConverterReg), TSP_PKT_FORCE_SYNC_47));
7230 }
7231 }
7232
HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path,MS_BOOL bEnable)7233 void HAL_TSP_PktConverter_SrcIdFlt(MS_U8 u8Path, MS_BOOL bEnable)
7234 {
7235 REG16 *PktConverterReg = &_RegCtrl6->pkt_converter[u8Path];
7236
7237 if(bEnable)
7238 {
7239 REG16_W(PktConverterReg, _SET_(REG16_R(PktConverterReg), TSP_SRC_ID_FLT_EN)); // Set 1 to enable filter sync byte and path ID match
7240 }
7241 else
7242 {
7243 REG16_W(PktConverterReg, _CLR_(REG16_R(PktConverterReg), TSP_SRC_ID_FLT_EN));
7244 }
7245 }
7246
HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId,MS_U32 u32SrcId)7247 void HAL_TSP_PidFlt_SetSrcId(MS_U32 fltId, MS_U32 u32SrcId)
7248 {
7249 REG_PidFlt *pPidFlt = PPIDFLT1(fltId);
7250 TSP32_IdrW(pPidFlt, ((TSP32_IdrR(pPidFlt) & ~(TSP_PIDFLT_SRCID_MASK)) | ((u32SrcId << TSP_PIDFLT_SRCID_SHIFT) & TSP_PIDFLT_SRCID_MASK)));
7251 }
7252
HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId,MS_U32 u32SrcId)7253 void HAL_TSP_PcrFlt_SetSrcId(MS_U32 pcrFltId, MS_U32 u32SrcId)
7254 {
7255 switch(pcrFltId)
7256 {
7257 case 0:
7258 //src 0
7259 REG16_MSK_W(&_RegCtrl3->CFG3_72,CFG3_72_PIDFLT_PCR_SCR_ID_MASK,(u32SrcId << CFG3_72_PIDFLT_PCR0_SCR_ID_SHIFT));
7260 break;
7261 case 1:
7262 //src 1
7263 REG16_MSK_W(&_RegCtrl3->CFG3_72,CFG3_72_PIDFLT_PCR_SCR_ID_MASK<<CFG3_72_PIDFLT_PCR1_SCR_ID_SHIFT,(u32SrcId << CFG3_72_PIDFLT_PCR1_SCR_ID_SHIFT));
7264
7265 break;
7266 default:
7267 break;
7268 }
7269 }
7270
HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)7271 void HAL_TSP_Reset_TSIF_MergeSetting(MS_U8 u8Path)
7272 {
7273 MS_U8 u8Id;
7274 MS_U8 u8SyncByte;
7275
7276 u8SyncByte = 0x47;
7277 for(u8Id = 0; u8Id < TSP_MERGESTREAM_NUM; u8Id++,u8SyncByte++)
7278 {
7279 HAL_TSP_PktConverter_SetSyncByte(u8Path, u8Id, &u8SyncByte, TRUE);
7280 HAL_TSP_PktConverter_SetSrcId(u8Path, u8Id, &u8Id, TRUE);
7281 }
7282 HAL_TSP_PktConverter_PktMode(u8Path,E_TSP_HAL_PKT_MODE_NORMAL);
7283 }
7284
7285
7286 //-------------------------------------------------------------------------------------------------
7287 // For Debug Table
7288 //-------------------------------------------------------------------------------------------------
7289
HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)7290 TSP_SRC_SEQ HAL_TSP_Debug_Flow2PktDmx_Mapping(TSP_HAL_FLOW eFlow)
7291 {
7292 switch (eFlow)
7293 {
7294 case E_TSP_HAL_FLOW_LIVE0:
7295 return E_TSP_SRC_PKTDMX0;
7296 case E_TSP_HAL_FLOW_LIVE1:
7297 return E_TSP_SRC_PKTDMX2;
7298 case E_TSP_HAL_FLOW_LIVE2:
7299 return E_TSP_SRC_PKTDMX3;
7300 case E_TSP_HAL_FLOW_LIVE3:
7301 return E_TSP_SRC_PKTDMX1;
7302 case E_TSP_HAL_FLOW_FILE0:
7303 return E_TSP_SRC_PKTDMX1;
7304 case E_TSP_HAL_FLOW_FILE1:
7305 return E_TSP_SRC_PKTDMX3;
7306 case E_TSP_HAL_FLOW_FILE2:
7307 return E_TSP_SRC_PKTDMX0;
7308 case E_TSP_HAL_FLOW_FILE3:
7309 return E_TSP_SRC_PKTDMX2;
7310 case E_TSP_HAL_FLOW_MMFI0:
7311 return E_TSP_SRC_MMFI0;
7312 case E_TSP_HAL_FLOW_MMFI1:
7313 return E_TSP_SRC_MMFI1;
7314 default:
7315 printf("[TSP_ERR][%s][%d] UnSupported Debug Flow : %d !!!\n",__FUNCTION__, __LINE__,eFlow);
7316 return E_TSP_SRC_INVALID;
7317 }
7318 }
7319
HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)7320 void HAL_TSP_Debug_LockPktCnt_Src(MS_U32 u32TsIf)
7321 {
7322 MS_U16 u16TSIF = 0;;
7323
7324 switch(u32TsIf)
7325 {
7326 case 0:
7327 u16TSIF = TSIF_SRC_SEL_TSIF0;
7328 break;
7329 case 1:
7330 u16TSIF = TSIF_SRC_SEL_TSIF1;
7331 break;
7332 case 2:
7333 u16TSIF = TSIF_SRC_SEL_TSIF2;
7334 break;
7335 case 3:
7336 u16TSIF = TSIF_SRC_SEL_TSIF3;
7337 break;
7338 default:
7339 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7340 break;
7341 }
7342
7343 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_TSIF_SRC_SEL_MASK,(u16TSIF << CFG5_7F_TSIF_SRC_SEL_SHIFT));
7344 }
7345
HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)7346 void HAL_TSP_Debug_LockPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
7347 {
7348 if(bEn == TRUE)
7349 {
7350 switch(u32TsIf)
7351 {
7352 case 0:
7353 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
7354 break;
7355 case 1:
7356 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
7357 break;
7358 case 2:
7359 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
7360 break;
7361 case 3:
7362 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_3_LOAD);
7363 break;
7364 default:
7365 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7366 break;
7367 }
7368 }
7369 else
7370 {
7371 switch(u32TsIf)
7372 {
7373 case 0:
7374 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_0_LOAD);
7375 break;
7376 case 1:
7377 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_1_LOAD);
7378 break;
7379 case 2:
7380 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_2_LOAD);
7381 break;
7382 case 3:
7383 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_LOCKED_PKT_CNT_3_LOAD);
7384 break;
7385 default:
7386 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7387 break;
7388 }
7389 }
7390
7391 }
7392
HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf,MS_BOOL bLock)7393 MS_U16 HAL_TSP_Debug_LockPktCnt_Get(MS_U32 u32TsIf, MS_BOOL bLock)
7394 {
7395 if(bLock) // 188 mode
7396 {
7397 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
7398 }
7399 else // Non 188 mode
7400 {
7401 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_NON_188_CNT_MODE);
7402 }
7403
7404 return REG16_R(&_RegCtrl5->Locked_PKT_Cnt);
7405 }
7406
HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)7407 void HAL_TSP_Debug_LockPktCnt_Clear(MS_U32 u32Tsif)
7408 {
7409 switch (u32Tsif)
7410 {
7411 case 0 :
7412 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
7413 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_0_CLR);
7414 break;
7415 case 1:
7416 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
7417 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_1_CLR);
7418 break;
7419 case 2:
7420 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
7421 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_2_CLR);
7422 break;
7423 case 3:
7424 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_3_CLR);
7425 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_LOCKED_PKT_CNT_3_CLR);
7426 break;
7427 default :
7428 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
7429 break;
7430 }
7431 }
7432
HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)7433 void HAL_TSP_Debug_ClrSrcSel(TSP_SRC_SEQ eClrSrc)
7434 {
7435 switch (eClrSrc)
7436 {
7437 case E_TSP_SRC_PKTDMX0:
7438 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX0 << CFG5_7F_CLR_SRC_SHIFT);
7439 break;
7440 case E_TSP_SRC_PKTDMX1:
7441 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX1 << CFG5_7F_CLR_SRC_SHIFT);
7442 break;
7443 case E_TSP_SRC_PKTDMX2:
7444 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX2 << CFG5_7F_CLR_SRC_SHIFT);
7445 break;
7446 case E_TSP_SRC_PKTDMX3:
7447 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_PKTDMX3 << CFG5_7F_CLR_SRC_SHIFT);
7448 break;
7449 case E_TSP_SRC_MMFI0:
7450 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI0 << CFG5_7F_CLR_SRC_SHIFT);
7451 break;
7452 case E_TSP_SRC_MMFI1:
7453 REG16_MSK_W(&_RegCtrl5->CFG5_7F, CFG5_7F_CLR_SRC_MASK, CFG5_7F_CLR_SRC_MMFI1 << CFG5_7F_CLR_SRC_SHIFT);
7454 break;
7455 default:
7456 printf("[%s][%s][%d] UnSupported Clear Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,eClrSrc);
7457 break;
7458 }
7459 }
7460
HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)7461 void HAL_TSP_Debug_AvPktCnt_Src(TSP_DST_SEQ eAvType, TSP_SRC_SEQ ePktDmxId)
7462 {
7463 MS_U16 u16AvSrc = 0;
7464
7465 switch(ePktDmxId)
7466 {
7467 case E_TSP_SRC_PKTDMX0:
7468 u16AvSrc = AV_PKT_SRC_PKTDMX0;
7469 break;
7470 case E_TSP_SRC_PKTDMX1:
7471 u16AvSrc = AV_PKT_SRC_PKTDMX1;
7472 break;
7473 case E_TSP_SRC_PKTDMX2:
7474 u16AvSrc = AV_PKT_SRC_PKTDMX2;
7475 break;
7476 case E_TSP_SRC_PKTDMX3:
7477 u16AvSrc = AV_PKT_SRC_PKTDMX3;
7478 break;
7479 case E_TSP_SRC_MMFI0:
7480 u16AvSrc = AV_PKT_SRC_MMFI0;
7481 break;
7482 case E_TSP_SRC_MMFI1:
7483 u16AvSrc = AV_PKT_SRC_MMFI1;
7484 break;
7485 default:
7486 printf("[%s][%s][%d] UnSupported AV Source : %d!\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
7487 break;
7488 }
7489
7490 switch (eAvType)
7491 {
7492 case E_TSP_DST_FIFO_VIDEO :
7493 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_SRC_MASK, u16AvSrc << CFG5_7E_VID_SRC_SHIFT);
7494 break;
7495 case E_TSP_DST_FIFO_VIDEO3D :
7496 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_VID_3D_SRC_MASK, u16AvSrc << CFG5_7E_VID_3D_SRC_SHIFT);
7497 break;
7498 case E_TSP_DST_FIFO_AUDIO :
7499 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDA_SRC_MASK, u16AvSrc << CFG5_7E_AUDA_SRC_SHIFT);
7500 break;
7501 case E_TSP_DST_FIFO_AUDIO2 :
7502 REG16_MSK_W(&_RegCtrl5->CFG5_7E, CFG5_7E_AUDB_SRC_MASK, u16AvSrc << CFG5_7E_AUDB_SRC_SHIFT);
7503 break;
7504 case E_TSP_DST_FIFO_AUDIO3 :
7505 REG16_MSK_W(&_RegCtrl5->CFG5_78, CFG5_78_AUDC_SRC_MASK, u16AvSrc << CFG5_78_AUDC_SRC_SHIFT);
7506 break;
7507 case E_TSP_DST_FIFO_AUDIO4 :
7508 REG16_MSK_W(&_RegCtrl5->CFG5_78, CFG5_78_AUDD_SRC_MASK, u16AvSrc << CFG5_78_AUDD_SRC_SHIFT);
7509 break;
7510 default:
7511 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7512 break;
7513 }
7514 }
7515
HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)7516 void HAL_TSP_Debug_AvPktCnt_Load(TSP_DST_SEQ eAvType, MS_BOOL bEn)
7517 {
7518 if(bEn == TRUE)
7519 {
7520 switch (eAvType)
7521 {
7522 case E_TSP_DST_FIFO_VIDEO :
7523 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
7524 break;
7525 case E_TSP_DST_FIFO_VIDEO3D :
7526 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
7527 break;
7528 case E_TSP_DST_FIFO_AUDIO :
7529 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
7530 break;
7531 case E_TSP_DST_FIFO_AUDIO2 :
7532 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
7533 break;
7534 case E_TSP_DST_FIFO_AUDIO3 :
7535 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADC_PKT_CNT_LOAD);
7536 break;
7537 case E_TSP_DST_FIFO_AUDIO4 :
7538 REG16_SET(&_RegCtrl5->CFG5_7A,CFG5_7A_ADD_PKT_CNT_LOAD);
7539 break;
7540 default :
7541 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7542 break;
7543 }
7544 }
7545 else
7546 {
7547 switch (eAvType)
7548 {
7549 case E_TSP_DST_FIFO_VIDEO :
7550 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V_PKT_CNT_LOAD);
7551 break;
7552 case E_TSP_DST_FIFO_VIDEO3D :
7553 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_V3D_PKT_CNT_LOAD);
7554 break;
7555 case E_TSP_DST_FIFO_AUDIO :
7556 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_A_PKT_CNT_LOAD);
7557 break;
7558 case E_TSP_DST_FIFO_AUDIO2 :
7559 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_AD_PKT_CNT_LOAD);
7560 break;
7561 case E_TSP_DST_FIFO_AUDIO3 :
7562 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_ADC_PKT_CNT_LOAD);
7563 break;
7564 case E_TSP_DST_FIFO_AUDIO4 :
7565 REG16_CLR(&_RegCtrl5->CFG5_7A,CFG5_7A_ADD_PKT_CNT_LOAD);
7566 break;
7567 default :
7568 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7569 break;
7570 }
7571 }
7572 }
7573
HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)7574 MS_U16 HAL_TSP_Debug_AvPktCnt_Get(TSP_DST_SEQ eAvType)
7575 {
7576 switch (eAvType)
7577 {
7578 case E_TSP_DST_FIFO_VIDEO :
7579 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7580 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
7581 case E_TSP_DST_FIFO_VIDEO3D:
7582 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7583 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
7584 case E_TSP_DST_FIFO_AUDIO :
7585 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7586 return REG16_R(&_RegCtrl5->Av_PKT_Cnt);
7587 case E_TSP_DST_FIFO_AUDIO2 :
7588 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_AV_PKT_SRC_SEL);
7589 return REG16_R(&_RegCtrl5->Av_PKT_Cnt1);
7590 default :
7591 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7592 return 0;
7593 }
7594 }
7595
HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)7596 void HAL_TSP_Debug_AvPktCnt_Clear(TSP_DST_SEQ eAvType)
7597 {
7598 switch (eAvType)
7599 {
7600 case E_TSP_DST_FIFO_VIDEO :
7601 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
7602 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V_PKT_CNT_CLR);
7603 break;
7604 case E_TSP_DST_FIFO_VIDEO3D :
7605 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
7606 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_V3D_PKT_CNT_CLR);
7607 break;
7608 case E_TSP_DST_FIFO_AUDIO :
7609 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
7610 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_A_PKT_CNT_CLR);
7611 break;
7612 case E_TSP_DST_FIFO_AUDIO2 :
7613 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
7614 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_AD_PKT_CNT_CLR);
7615 break;
7616 case E_TSP_DST_FIFO_AUDIO3 :
7617 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADC_PKT_CNT_CLR);
7618 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_ADC_PKT_CNT_CLR);
7619 break;
7620 case E_TSP_DST_FIFO_AUDIO4 :
7621 REG16_SET(&_RegCtrl5->CFG5_7C,CFG5_7C_ADD_PKT_CNT_CLR);
7622 REG16_CLR(&_RegCtrl5->CFG5_7C,CFG5_7C_ADD_PKT_CNT_CLR);
7623 break;
7624 default :
7625 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7626 break;
7627 }
7628 }
7629
HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)7630 void HAL_TSP_Debug_DropDisPktCnt_Src(TSP_DST_SEQ eAvType,TSP_SRC_SEQ ePktDmxId)
7631 {
7632 MS_U16 u16AvType = 0;
7633
7634 switch(eAvType)
7635 {
7636 case E_TSP_DST_FIFO_VIDEO:
7637 u16AvType = DIS_DROP_CNT_V;
7638 break;
7639 case E_TSP_DST_FIFO_VIDEO3D:
7640 u16AvType = DIS_DROP_CNT_V3D;
7641 break;
7642 case E_TSP_DST_FIFO_AUDIO:
7643 u16AvType = DIS_DROP_CNT_A;
7644 break;
7645 case E_TSP_DST_FIFO_AUDIO2:
7646 u16AvType = DIS_DROP_CNT_AD;
7647 break;
7648 case E_TSP_DST_FIFO_AUDIO3:
7649 u16AvType = DIS_DROP_CNT_ADC;
7650 break;
7651 case E_TSP_DST_FIFO_AUDIO4:
7652 u16AvType = DIS_DROP_CNT_ADD;
7653 break;
7654 default:
7655 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7656 break;
7657 }
7658
7659 switch(ePktDmxId)
7660 {
7661 case E_TSP_SRC_PKTDMX0:
7662 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL_SHIFT));
7663 break;
7664 case E_TSP_SRC_PKTDMX1:
7665 REG16_MSK_W(&_RegCtrl5->CFG5_7F,CFG5_7F_PIDFLT_SRC_SEL1_MASK,(u16AvType<<CFG5_7F_PIDFLT_SRC_SEL1_SHIFT));
7666 break;
7667 case E_TSP_SRC_PKTDMX2:
7668 REG16_MSK_W(&_RegCtrl5->CFG5_77,CFG5_77_PIDFLT_SRC_SEL2_MASK,(u16AvType<<CFG5_77_PIDFLT_SRC_SEL2_SHIFT));
7669 break;
7670 case E_TSP_SRC_PKTDMX3:
7671 REG16_MSK_W(&_RegCtrl5->CFG5_77,CFG5_77_PIDFLT_SRC_SEL3_MASK,(u16AvType<<CFG5_77_PIDFLT_SRC_SEL3_SHIFT));
7672 break;
7673 case E_TSP_SRC_MMFI0:
7674 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI0_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI0_SHIFT));
7675 break;
7676 case E_TSP_SRC_MMFI1:
7677 REG16_MSK_W(&_RegCtrl5->CFG5_78,CFG5_78_PIDFLT_SRC_SEL_MMFI1_MASK,(u16AvType<<CFG5_78_PIDFLT_SRC_SEL_MMFI1_SHIFT));
7678 break;
7679 default:
7680 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d !\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
7681 break;
7682 }
7683 }
7684
HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)7685 void HAL_TSP_Debug_DropPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn)
7686 {
7687 if(bEn == TRUE)
7688 {
7689 switch (eAvType)
7690 {
7691 case E_TSP_DST_FIFO_VIDEO :
7692 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
7693 break;
7694 case E_TSP_DST_FIFO_VIDEO3D :
7695 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
7696 break;
7697 case E_TSP_DST_FIFO_AUDIO :
7698 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
7699 break;
7700 case E_TSP_DST_FIFO_AUDIO2 :
7701 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
7702 break;
7703 case E_TSP_DST_FIFO_AUDIO3 :
7704 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADC_LOAD);
7705 break;
7706 case E_TSP_DST_FIFO_AUDIO4 :
7707 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADD_LOAD);
7708 break;
7709 default :
7710 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7711 break;
7712 }
7713 }
7714 else
7715 {
7716 switch (eAvType)
7717 {
7718 case E_TSP_DST_FIFO_VIDEO :
7719 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V_LOAD);
7720 break;
7721 case E_TSP_DST_FIFO_VIDEO3D :
7722 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_V3D_LOAD);
7723 break;
7724 case E_TSP_DST_FIFO_AUDIO :
7725 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_A_LOAD);
7726 break;
7727 case E_TSP_DST_FIFO_AUDIO2 :
7728 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_AD_LOAD);
7729 break;
7730 case E_TSP_DST_FIFO_AUDIO3 :
7731 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADC_LOAD);
7732 break;
7733 case E_TSP_DST_FIFO_AUDIO4 :
7734 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DROP_PKT_CNT_ADD_LOAD);
7735 break;
7736 default :
7737 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7738 break;
7739 }
7740 }
7741 }
7742
HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)7743 void HAL_TSP_Debug_DisPktCnt_Load(TSP_DST_SEQ eAvType,MS_BOOL bEn,MS_BOOL bPayload)
7744 {
7745 if(bPayload)
7746 {
7747 REG16_SET(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
7748 }
7749 else
7750 {
7751 REG16_CLR(&_RegCtrl3->CFG3_37,HW4_CFG37_DIS_CNTR_INC_BY_PL);
7752 }
7753
7754 if(bEn == TRUE)
7755 {
7756 switch (eAvType)
7757 {
7758 case E_TSP_DST_FIFO_VIDEO :
7759 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
7760 break;
7761 case E_TSP_DST_FIFO_AUDIO :
7762 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
7763 break;
7764 case E_TSP_DST_FIFO_AUDIO2 :
7765 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
7766 break;
7767 case E_TSP_DST_FIFO_AUDIO3 :
7768 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADC_LOAD);
7769 break;
7770 case E_TSP_DST_FIFO_AUDIO4 :
7771 REG16_SET(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADD_LOAD);
7772 break;
7773 default :
7774 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7775 break;
7776 }
7777 }
7778 else
7779 {
7780 switch (eAvType)
7781 {
7782 case E_TSP_DST_FIFO_VIDEO :
7783 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_V_LOAD);
7784 break;
7785 case E_TSP_DST_FIFO_AUDIO :
7786 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_A_LOAD);
7787 break;
7788 case E_TSP_DST_FIFO_AUDIO2 :
7789 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_AD_LOAD);
7790 break;
7791 case E_TSP_DST_FIFO_AUDIO3 :
7792 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADC_LOAD);
7793 break;
7794 case E_TSP_DST_FIFO_AUDIO4 :
7795 REG16_CLR(&_RegCtrl5->CFG5_7B,CFG5_7B_DIS_PKT_CNT_ADD_LOAD);
7796 break;
7797 default :
7798 printf("[%s][%s][%d] UnSupported AV Type : %d \n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7799 break;
7800 }
7801 }
7802 }
7803
HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId,MS_BOOL bDrop)7804 MS_U16 HAL_TSP_Debug_DropDisPktCnt_Get(TSP_SRC_SEQ ePktDmxId, MS_BOOL bDrop)
7805 {
7806 if(bDrop)
7807 {
7808 REG16_SET(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
7809 }
7810 else
7811 {
7812 REG16_CLR(&_RegCtrl5->CFG5_7F,CFG5_7F_DROP_PKT_MODE);
7813 }
7814
7815 switch (ePktDmxId)
7816 {
7817 case E_TSP_SRC_PKTDMX0:
7818 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_0);
7819 case E_TSP_SRC_PKTDMX1:
7820 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_1);
7821 case E_TSP_SRC_PKTDMX2:
7822 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_2);
7823 case E_TSP_SRC_PKTDMX3:
7824 return REG16_R(&_RegCtrl5->Drop_Dis_PKT_Cnt_3);
7825 case E_TSP_SRC_MMFI0:
7826 return REG16_R(&_RegCtrl5->CFG5_0B);
7827 case E_TSP_SRC_MMFI1:
7828 return REG16_R(&_RegCtrl5->CFG5_0C);
7829 default :
7830 printf("[%s][%s][%d] UnSupported AV FIFO Source : %d\n",__FILE__,__FUNCTION__,__LINE__,ePktDmxId);
7831 return 0;
7832 }
7833 }
7834
HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)7835 void HAL_TSP_Debug_DropPktCnt_Clear(TSP_DST_SEQ eAvType)
7836 {
7837 switch (eAvType)
7838 {
7839 case E_TSP_DST_FIFO_VIDEO :
7840 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
7841 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V_CLR);
7842 break;
7843 case E_TSP_DST_FIFO_VIDEO3D :
7844 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
7845 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_V3D_CLR);
7846 break;
7847 case E_TSP_DST_FIFO_AUDIO :
7848 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
7849 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_A_CLR);
7850 break;
7851 case E_TSP_DST_FIFO_AUDIO2 :
7852 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
7853 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_AD_CLR);
7854 break;
7855 case E_TSP_DST_FIFO_AUDIO3 :
7856 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADC_CLR);
7857 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADC_CLR);
7858 break;
7859 case E_TSP_DST_FIFO_AUDIO4 :
7860 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADD_CLR);
7861 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DROP_PKT_CNT_ADD_CLR);
7862 break;
7863 default :
7864 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7865 break;
7866 }
7867 }
7868
HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)7869 void HAL_TSP_Debug_DisPktCnt_Clear(TSP_DST_SEQ eAvType)
7870 {
7871 switch (eAvType)
7872 {
7873 case E_TSP_DST_FIFO_VIDEO :
7874 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
7875 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_V_CLR);
7876 break;
7877 case E_TSP_DST_FIFO_AUDIO :
7878 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
7879 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_A_CLR);
7880 break;
7881 case E_TSP_DST_FIFO_AUDIO2 :
7882 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
7883 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_AD_CLR);
7884 break;
7885 case E_TSP_DST_FIFO_AUDIO3 :
7886 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
7887 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADC_CLR);
7888 break;
7889 case E_TSP_DST_FIFO_AUDIO4 :
7890 REG16_SET(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
7891 REG16_CLR(&_RegCtrl5->CFG5_7D,CFG5_7D_DIS_PKT_CNT_ADD_CLR);
7892 break;
7893 default :
7894 printf("[%s][%s][%d] UnSupported AV Type : %d !\n",__FILE__,__FUNCTION__,__LINE__,eAvType);
7895 break;
7896 }
7897 }
7898
HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)7899 void HAL_TSP_Debug_ErrPktCnt_Src(MS_U32 u32TsIf)
7900 {
7901 MS_U16 u16TSIF = 0;;
7902
7903 switch(u32TsIf)
7904 {
7905 case 0:
7906 u16TSIF = TSIF_SRC_SEL_TSIF0;
7907 break;
7908 case 1:
7909 u16TSIF = TSIF_SRC_SEL_TSIF1;
7910 break;
7911 case 2:
7912 u16TSIF = TSIF_SRC_SEL_TSIF2;
7913 break;
7914 case 3:
7915 u16TSIF = TSIF_SRC_SEL_TSIF3;
7916 break;
7917 default:
7918 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7919 break;
7920 }
7921
7922 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_ERR_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_ERR_PKT_SRC_SEL_SHIFT));
7923 }
7924
HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)7925 void HAL_TSP_Debug_ErrPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
7926 {
7927 if(bEn == TRUE)
7928 {
7929 switch(u32TsIf)
7930 {
7931 case 0:
7932 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
7933 break;
7934 case 1:
7935 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
7936 break;
7937 case 2:
7938 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
7939 break;
7940 case 3:
7941 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_3_LOAD);
7942 break;
7943 default:
7944 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7945 break;
7946 }
7947 }
7948 else
7949 {
7950 switch(u32TsIf)
7951 {
7952 case 0:
7953 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_0_LOAD);
7954 break;
7955 case 1:
7956 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_1_LOAD);
7957 break;
7958 case 2:
7959 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_2_LOAD);
7960 break;
7961 case 3:
7962 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_ERR_PKT_CNT_3_LOAD);
7963 break;
7964 default:
7965 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
7966 break;
7967 }
7968 }
7969
7970 }
7971
HAL_TSP_Debug_ErrPktCnt_Get(void)7972 MS_U16 HAL_TSP_Debug_ErrPktCnt_Get(void)
7973 {
7974 return REG16_R(&_RegCtrl5->Err_PKT_Cnt);
7975 }
7976
HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)7977 void HAL_TSP_Debug_ErrPktCnt_Clear(MS_U32 u32Tsif)
7978 {
7979 switch (u32Tsif)
7980 {
7981 case 0 :
7982 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
7983 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_0_CLR);
7984 break;
7985 case 1:
7986 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
7987 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_1_CLR);
7988 break;
7989 case 2 :
7990 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
7991 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_2_CLR);
7992 break;
7993 case 3 :
7994 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_3_CLR);
7995 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_ERR_PKT_CNT_3_CLR);
7996 break;
7997
7998 default :
7999 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
8000 break;
8001 }
8002 }
8003
HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)8004 void HAL_TSP_Debug_InputPktCnt_Src(MS_U32 u32TsIf)
8005 {
8006 MS_U16 u16TSIF = 0;;
8007
8008 switch(u32TsIf)
8009 {
8010 case 0:
8011 u16TSIF = TSIF_SRC_SEL_TSIF0;
8012 break;
8013 case 1:
8014 u16TSIF = TSIF_SRC_SEL_TSIF1;
8015 break;
8016 case 2:
8017 u16TSIF = TSIF_SRC_SEL_TSIF2;
8018 break;
8019 case 3:
8020 u16TSIF = TSIF_SRC_SEL_TSIF3;
8021 break;
8022 default:
8023 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8024 break;
8025 }
8026
8027 REG16_MSK_W(&_RegCtrl5->CFG5_70,CFG5_70_INPUT_PKT_SRC_SEL_MASK,(u16TSIF << CFG5_70_INPUT_PKT_SRC_SEL_SHIT));
8028 }
8029
HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)8030 void HAL_TSP_Debug_InputPktCnt_Load(MS_U32 u32TsIf,MS_BOOL bEn)
8031 {
8032 if(bEn == TRUE)
8033 {
8034 switch(u32TsIf)
8035 {
8036 case 0:
8037 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
8038 break;
8039 case 1:
8040 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
8041 break;
8042 case 2:
8043 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
8044 break;
8045 case 3:
8046 REG16_SET(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_3_LOAD);
8047 break;
8048 default:
8049 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8050 break;
8051 }
8052 }
8053 else
8054 {
8055 switch(u32TsIf)
8056 {
8057 case 0:
8058 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_0_LOAD);
8059 break;
8060 case 1:
8061 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_1_LOAD);
8062 break;
8063 case 2:
8064 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_2_LOAD);
8065 break;
8066 case 3:
8067 REG16_CLR(&_RegCtrl5->CFG5_71,CFG5_71_INPUT_PKT_CNT_3_LOAD);
8068 break;
8069 default:
8070 printf("[%s][%s][%d] UnSupported TSIF : %u\n",__FILE__,__FUNCTION__,__LINE__,(unsigned int)u32TsIf);
8071 break;
8072 }
8073 }
8074 }
8075
HAL_TSP_Debug_InputPktCnt_Get(void)8076 MS_U16 HAL_TSP_Debug_InputPktCnt_Get(void)
8077 {
8078 return REG16_R(&_RegCtrl5->Input_PKT_Cnt);
8079 }
8080
HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)8081 void HAL_TSP_Debug_InputPktCnt_Clear(MS_U32 u32Tsif)
8082 {
8083 switch (u32Tsif)
8084 {
8085 case 0 :
8086 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
8087 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_0_CLR);
8088 break;
8089 case 1:
8090 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
8091 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_1_CLR);
8092 break;
8093 case 2 :
8094 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
8095 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_2_CLR);
8096 break;
8097 case 3 :
8098 REG16_SET(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_3_CLR);
8099 REG16_CLR(&_RegCtrl5->CFG5_72,CFG5_72_INPUT_PKT_CNT_3_CLR);
8100 break;
8101
8102 default :
8103 printf("[%s][%s][%d] UnSupported TSIF : %u\n\n",__FILE__,__FUNCTION__,__LINE__, (unsigned int)u32Tsif);
8104 break;
8105 }
8106
8107 }
8108
HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng,MS_U32 u32FQSrc)8109 MS_BOOL HAL_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, MS_U32 u32FQSrc)
8110 {
8111 // not support
8112 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_INFO, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupport feature!\n",__FILE__,__FUNCTION__,__LINE__));
8113 return FALSE;
8114 }
8115
HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)8116 MS_U32 HAL_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng)
8117 {
8118 // not support
8119 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_INFO, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupport feature!\n",__FILE__,__FUNCTION__,__LINE__));
8120 return 0xFF;
8121 }
8122
HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng,MS_BOOL bFltNull)8123 MS_BOOL HAL_TSP_FQ_FLT_NULL_PKT(MS_U32 u32FQEng, MS_BOOL bFltNull)
8124 {
8125 if(KANOU03)
8126 {
8127 if(bFltNull)
8128 {
8129 REG16_SET(&_RegCtrl3->CFG3_2D, CFG3_2D_FILTER_NULL_PKT);
8130 }
8131 else
8132 {
8133 REG16_CLR(&_RegCtrl3->CFG3_2D, CFG3_2D_FILTER_NULL_PKT);
8134 }
8135 return TRUE;
8136 }
8137 else
8138 {
8139 // not support
8140 HAL_TSP_DBGMSG(E_HAL_TSP_DBG_LEVEL_ERR, E_HAL_TSP_DBG_MODEL_ALL, printf("[%s][%s][%d] UnSupport feature!\n",__FILE__,__FUNCTION__,__LINE__));
8141 return FALSE;
8142 }
8143 }
8144
HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType,MS_U8 u8Eng,MS_PHY phyBufStart)8145 void HAL_TSP_FQ_MMFI_MIU_Sel(TSP_HAL_MIU_SEL_TYPE eType, MS_U8 u8Eng, MS_PHY phyBufStart)
8146 {
8147 MS_U8 u8MiuSel = 0;
8148 MS_PHY phyMiuOffsetFileinAddr = 0;
8149 MS_U8 u8Shift = u8Eng * TSP_MIU_SEL_BITS_LEN;
8150
8151 _phy_to_miu_offset(u8MiuSel, phyMiuOffsetFileinAddr, phyBufStart);
8152
8153 switch(eType)
8154 {
8155 case E_TSP_HAL_MIU_SEL_MMFI:
8156 REG16_MSK_W(&_RegCtrl6->CFG6_2C_REG_MIU_SEL_FILEIN_MM, (REG_MIU_SEL_MMFI0_MASK << u8Shift), (u8MiuSel << (REG_MIU_SEL_MMFI0_SHIFT + u8Shift)));
8157 break;
8158 case E_TSP_HAL_MIU_SEL_FQ:
8159 REG16_MSK_W(&_RegCtrl6->CFG6_2E_REG_MIU_PVR_FQ, (REG_MIU_SEL_FIQ0_MASK << u8Shift), (u8MiuSel << (REG_MIU_SEL_FIQ0_SHIFT + u8Shift)));
8160 break;
8161 default:
8162 break;
8163 }
8164 }
8165
8166
8167